2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
47 #include <rte_debug.h>
48 #include <rte_ethdev.h>
50 #include <rte_ether.h>
51 #include <rte_malloc.h>
52 #include <rte_memzone.h>
53 #include <rte_mempool.h>
54 #include <rte_version.h>
55 #include <rte_string_fns.h>
56 #include <rte_alarm.h>
58 #include "nfp_net_pmd.h"
59 #include "nfp_net_logs.h"
60 #include "nfp_net_ctrl.h"
63 static void nfp_net_close(struct rte_eth_dev *dev);
64 static int nfp_net_configure(struct rte_eth_dev *dev);
65 static void nfp_net_dev_interrupt_handler(struct rte_intr_handle *handle,
67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
70 struct rte_eth_dev_info *dev_info);
71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
80 static void nfp_net_rx_queue_release(void *rxq);
81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
82 uint16_t nb_desc, unsigned int socket_id,
83 const struct rte_eth_rxconf *rx_conf,
84 struct rte_mempool *mp);
85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
86 static void nfp_net_tx_queue_release(void *txq);
87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_txconf *tx_conf);
90 static int nfp_net_start(struct rte_eth_dev *dev);
91 static void nfp_net_stats_get(struct rte_eth_dev *dev,
92 struct rte_eth_stats *stats);
93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
94 static void nfp_net_stop(struct rte_eth_dev *dev);
95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
99 * The offset of the queue controller queues in the PCIe Target. These
100 * happen to be at the same offset on the NFP6000 and the NFP3200 so
101 * we use a single macro here.
103 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
105 /* Maximum value which can be added to a queue with one transaction */
106 #define NFP_QCP_MAX_ADD 0x7f
108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
109 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
113 NFP_QCP_READ_PTR = 0,
118 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
119 * @q: Base address for queue structure
120 * @ptr: Add to the Read or Write pointer
121 * @val: Value to add to the queue pointer
123 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
130 if (ptr == NFP_QCP_READ_PTR)
131 off = NFP_QCP_QUEUE_ADD_RPTR;
133 off = NFP_QCP_QUEUE_ADD_WPTR;
135 while (val > NFP_QCP_MAX_ADD) {
136 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
137 val -= NFP_QCP_MAX_ADD;
140 nn_writel(rte_cpu_to_le_32(val), q + off);
144 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
145 * @q: Base address for queue structure
146 * @ptr: Read or Write pointer
148 static inline uint32_t
149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
154 if (ptr == NFP_QCP_READ_PTR)
155 off = NFP_QCP_QUEUE_STS_LO;
157 off = NFP_QCP_QUEUE_STS_HI;
159 val = rte_cpu_to_le_32(nn_readl(q + off));
161 if (ptr == NFP_QCP_READ_PTR)
162 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
164 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
168 * Functions to read/write from/to Config BAR
169 * Performs any endian conversion necessary.
171 static inline uint8_t
172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
174 return nn_readb(hw->ctrl_bar + off);
178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
180 nn_writeb(val, hw->ctrl_bar + off);
183 static inline uint32_t
184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
186 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
192 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
195 static inline uint64_t
196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
198 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
204 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
207 /* Creating memzone for hardware rings. */
208 static const struct rte_memzone *
209 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
210 uint16_t queue_id, uint32_t ring_size, int socket_id)
212 char z_name[RTE_MEMZONE_NAMESIZE];
213 const struct rte_memzone *mz;
215 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
216 dev->driver->pci_drv.name,
217 ring_name, dev->data->port_id, queue_id);
219 mz = rte_memzone_lookup(z_name);
223 return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
228 * Atomically reads link status information from global structure rte_eth_dev.
231 * - Pointer to the structure rte_eth_dev to read from.
232 * - Pointer to the buffer to be saved with the link status.
235 * - On success, zero.
236 * - On failure, negative value.
239 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
240 struct rte_eth_link *link)
242 struct rte_eth_link *dst = link;
243 struct rte_eth_link *src = &dev->data->dev_link;
245 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
246 *(uint64_t *)src) == 0)
253 * Atomically writes the link status information into global
254 * structure rte_eth_dev.
257 * - Pointer to the structure rte_eth_dev to read from.
258 * - Pointer to the buffer to be saved with the link status.
261 * - On success, zero.
262 * - On failure, negative value.
265 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
266 struct rte_eth_link *link)
268 struct rte_eth_link *dst = &dev->data->dev_link;
269 struct rte_eth_link *src = link;
271 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
272 *(uint64_t *)src) == 0)
279 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
283 if (rxq->rxbufs == NULL)
286 for (i = 0; i < rxq->rx_count; i++) {
287 if (rxq->rxbufs[i].mbuf) {
288 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
289 rxq->rxbufs[i].mbuf = NULL;
295 nfp_net_rx_queue_release(void *rx_queue)
297 struct nfp_net_rxq *rxq = rx_queue;
300 nfp_net_rx_queue_release_mbufs(rxq);
301 rte_free(rxq->rxbufs);
307 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
309 nfp_net_rx_queue_release_mbufs(rxq);
316 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
320 if (txq->txbufs == NULL)
323 for (i = 0; i < txq->tx_count; i++) {
324 if (txq->txbufs[i].mbuf) {
325 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
326 txq->txbufs[i].mbuf = NULL;
332 nfp_net_tx_queue_release(void *tx_queue)
334 struct nfp_net_txq *txq = tx_queue;
337 nfp_net_tx_queue_release_mbufs(txq);
338 rte_free(txq->txbufs);
344 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
346 nfp_net_tx_queue_release_mbufs(txq);
354 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
358 struct timespec wait;
360 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
363 if (hw->qcp_cfg == NULL)
364 rte_panic("Bad configuration queue pointer\n");
366 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
369 wait.tv_nsec = 1000000;
371 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
373 /* Poll update field, waiting for NFP to ack the config */
374 for (cnt = 0; ; cnt++) {
375 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
378 if (new & NFP_NET_CFG_UPDATE_ERR) {
379 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x\n", new);
382 if (cnt >= NFP_NET_POLL_TIMEOUT) {
383 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
384 " %dms\n", update, cnt);
385 rte_panic("Exiting\n");
387 nanosleep(&wait, 0); /* waiting for a 1ms */
389 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
394 * Reconfigure the NIC
395 * @nn: device to reconfigure
396 * @ctrl: The value for the ctrl field in the BAR config
397 * @update: The value for the update field in the BAR config
399 * Write the update word to the BAR and ping the reconfig queue. Then poll
400 * until the firmware has acknowledged the update by zeroing the update word.
403 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
407 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
410 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
411 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
415 err = __nfp_net_reconfig(hw, update);
421 * Reconfig errors imply situations where they can be handled.
422 * Otherwise, rte_panic is called inside __nfp_net_reconfig
424 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x\n",
430 * Configure an Ethernet device. This function must be invoked first
431 * before any other function in the Ethernet API. This function can
432 * also be re-invoked when a device is in the stopped state.
435 nfp_net_configure(struct rte_eth_dev *dev)
437 struct rte_eth_conf *dev_conf;
438 struct rte_eth_rxmode *rxmode;
439 struct rte_eth_txmode *txmode;
440 uint32_t new_ctrl = 0;
442 struct nfp_net_hw *hw;
444 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
447 * A DPDK app sends info about how many queues to use and how
448 * those queues need to be configured. This is used by the
449 * DPDK core and it makes sure no more queues than those
450 * advertised by the driver are requested. This function is
451 * called after that internal process
454 PMD_INIT_LOG(DEBUG, "Configure\n");
456 dev_conf = &dev->data->dev_conf;
457 rxmode = &dev_conf->rxmode;
458 txmode = &dev_conf->txmode;
460 /* Checking TX mode */
461 if (txmode->mq_mode) {
462 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported\n");
466 /* Checking RX mode */
467 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
468 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
469 update = NFP_NET_CFG_UPDATE_RSS;
470 new_ctrl = NFP_NET_CFG_CTRL_RSS;
472 PMD_INIT_LOG(INFO, "RSS not supported\n");
477 if (rxmode->split_hdr_size) {
478 PMD_INIT_LOG(INFO, "rxmode does not support split header\n");
482 if (rxmode->hw_ip_checksum) {
483 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
484 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
486 PMD_INIT_LOG(INFO, "RXCSUM not supported\n");
491 if (rxmode->hw_vlan_filter) {
492 PMD_INIT_LOG(INFO, "VLAN filter not supported\n");
496 if (rxmode->hw_vlan_strip) {
497 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
498 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
500 PMD_INIT_LOG(INFO, "hw vlan strip not supported\n");
505 if (rxmode->hw_vlan_extend) {
506 PMD_INIT_LOG(INFO, "VLAN extended not supported\n");
510 /* Supporting VLAN insertion by default */
511 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
512 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
514 if (rxmode->jumbo_frame)
515 /* this is handled in rte_eth_dev_configure */
517 if (rxmode->hw_strip_crc) {
518 PMD_INIT_LOG(INFO, "strip CRC not supported\n");
522 if (rxmode->enable_scatter) {
523 PMD_INIT_LOG(INFO, "Scatter not supported\n");
530 update |= NFP_NET_CFG_UPDATE_GEN;
532 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
533 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
542 nfp_net_enable_queues(struct rte_eth_dev *dev)
544 struct nfp_net_hw *hw;
545 uint64_t enabled_queues = 0;
548 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
550 /* Enabling the required TX queues in the device */
551 for (i = 0; i < dev->data->nb_tx_queues; i++)
552 enabled_queues |= (1 << i);
554 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
558 /* Enabling the required RX queues in the device */
559 for (i = 0; i < dev->data->nb_rx_queues; i++)
560 enabled_queues |= (1 << i);
562 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
566 nfp_net_disable_queues(struct rte_eth_dev *dev)
568 struct nfp_net_hw *hw;
569 uint32_t new_ctrl, update = 0;
571 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
573 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
574 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
576 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
577 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
578 NFP_NET_CFG_UPDATE_MSIX;
580 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
581 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
583 /* If an error when reconfig we avoid to change hw state */
584 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
591 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
595 for (i = 0; i < dev->data->nb_rx_queues; i++) {
596 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
603 nfp_net_params_setup(struct nfp_net_hw *hw)
605 uint32_t *mac_address;
607 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
608 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
610 /* A MAC address is 8 bytes long */
611 mac_address = (uint32_t *)(hw->mac_addr);
613 nn_cfg_writel(hw, NFP_NET_CFG_MACADDR,
614 rte_cpu_to_be_32(*mac_address));
615 nn_cfg_writel(hw, NFP_NET_CFG_MACADDR + 4,
616 rte_cpu_to_be_32(*(mac_address + 4)));
620 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
622 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
626 nfp_net_start(struct rte_eth_dev *dev)
628 uint32_t new_ctrl, update = 0;
629 struct nfp_net_hw *hw;
632 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
634 PMD_INIT_LOG(DEBUG, "Start\n");
636 /* Disabling queues just in case... */
637 nfp_net_disable_queues(dev);
639 /* Writing configuration parameters in the device */
640 nfp_net_params_setup(hw);
642 /* Enabling the required queues in the device */
643 nfp_net_enable_queues(dev);
646 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE | NFP_NET_CFG_UPDATE_MSIX;
647 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
649 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
650 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
652 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
653 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
657 * Allocating rte mbuffs for configured rx queues.
658 * This requires queues being enabled before
660 if (nfp_net_rx_freelist_setup(dev) < 0) {
671 * An error returned by this function should mean the app
672 * exiting and then the system releasing all the memory
673 * allocated even memory coming from hugepages.
675 * The device could be enabled at this point with some queues
676 * ready for getting packets. This is true if the call to
677 * nfp_net_rx_freelist_setup() succeeds for some queues but
678 * fails for subsequent queues.
680 * This should make the app exiting but better if we tell the
683 nfp_net_disable_queues(dev);
688 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
690 nfp_net_stop(struct rte_eth_dev *dev)
694 PMD_INIT_LOG(DEBUG, "Stop\n");
696 nfp_net_disable_queues(dev);
699 for (i = 0; i < dev->data->nb_tx_queues; i++) {
700 nfp_net_reset_tx_queue(
701 (struct nfp_net_txq *)dev->data->tx_queues[i]);
704 for (i = 0; i < dev->data->nb_rx_queues; i++) {
705 nfp_net_reset_rx_queue(
706 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
710 /* Reset and stop device. The device can not be restarted. */
712 nfp_net_close(struct rte_eth_dev *dev)
714 struct nfp_net_hw *hw;
716 PMD_INIT_LOG(DEBUG, "Close\n");
718 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
721 * We assume that the DPDK application is stopping all the
722 * threads/queues before calling the device close function.
727 rte_intr_disable(&dev->pci_dev->intr_handle);
728 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
731 * The ixgbe PMD driver disables the pcie master on the
732 * device. The i40e does not...
737 nfp_net_promisc_enable(struct rte_eth_dev *dev)
739 uint32_t new_ctrl, update = 0;
740 struct nfp_net_hw *hw;
742 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
744 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
746 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
747 PMD_INIT_LOG(INFO, "Promiscuous mode not supported\n");
751 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
752 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
756 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
757 update = NFP_NET_CFG_UPDATE_GEN;
760 * DPDK sets promiscuous mode on just after this call assuming
761 * it can not fail ...
763 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
770 nfp_net_promisc_disable(struct rte_eth_dev *dev)
772 uint32_t new_ctrl, update = 0;
773 struct nfp_net_hw *hw;
775 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
777 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
778 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
782 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
783 update = NFP_NET_CFG_UPDATE_GEN;
786 * DPDK sets promiscuous mode off just before this call
787 * assuming it can not fail ...
789 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
796 * return 0 means link status changed, -1 means not changed
798 * Wait to complete is needed as it can take up to 9 seconds to get the Link
802 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
804 struct nfp_net_hw *hw;
805 struct rte_eth_link link, old;
806 uint32_t nn_link_status;
808 PMD_DRV_LOG(DEBUG, "Link update\n");
810 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
812 memset(&old, 0, sizeof(old));
813 nfp_net_dev_atomic_read_link_status(dev, &old);
815 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
817 memset(&link, 0, sizeof(struct rte_eth_link));
819 if (nn_link_status & NFP_NET_CFG_STS_LINK)
820 link.link_status = 1;
822 link.link_duplex = ETH_LINK_FULL_DUPLEX;
823 /* Other cards can limit the tx and rx rate per VF */
824 link.link_speed = ETH_LINK_SPEED_40G;
826 if (old.link_status != link.link_status) {
827 nfp_net_dev_atomic_write_link_status(dev, &link);
828 if (link.link_status)
829 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
831 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
839 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
842 struct nfp_net_hw *hw;
843 struct rte_eth_stats nfp_dev_stats;
845 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
847 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
849 /* reading per RX ring stats */
850 for (i = 0; i < dev->data->nb_rx_queues; i++) {
851 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
854 nfp_dev_stats.q_ipackets[i] =
855 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
857 nfp_dev_stats.q_ipackets[i] -=
858 hw->eth_stats_base.q_ipackets[i];
860 nfp_dev_stats.q_ibytes[i] =
861 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
863 nfp_dev_stats.q_ibytes[i] -=
864 hw->eth_stats_base.q_ibytes[i];
867 /* reading per TX ring stats */
868 for (i = 0; i < dev->data->nb_tx_queues; i++) {
869 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
872 nfp_dev_stats.q_opackets[i] =
873 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
875 nfp_dev_stats.q_opackets[i] -=
876 hw->eth_stats_base.q_opackets[i];
878 nfp_dev_stats.q_obytes[i] =
879 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
881 nfp_dev_stats.q_obytes[i] -=
882 hw->eth_stats_base.q_obytes[i];
885 nfp_dev_stats.ipackets =
886 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
888 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
890 nfp_dev_stats.ibytes =
891 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
893 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
895 nfp_dev_stats.opackets =
896 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
898 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
900 nfp_dev_stats.obytes =
901 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
903 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
905 nfp_dev_stats.imcasts =
906 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
908 nfp_dev_stats.imcasts -= hw->eth_stats_base.imcasts;
910 /* reading general device stats */
911 nfp_dev_stats.ierrors =
912 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
914 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
916 nfp_dev_stats.oerrors =
917 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
919 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
921 /* Multicast frames received */
922 nfp_dev_stats.imcasts =
923 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
925 nfp_dev_stats.imcasts -= hw->eth_stats_base.imcasts;
927 /* RX ring mbuf allocation failures */
928 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
930 nfp_dev_stats.imissed =
931 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
933 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
936 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
940 nfp_net_stats_reset(struct rte_eth_dev *dev)
943 struct nfp_net_hw *hw;
945 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
948 * hw->eth_stats_base records the per counter starting point.
952 /* reading per RX ring stats */
953 for (i = 0; i < dev->data->nb_rx_queues; i++) {
954 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
957 hw->eth_stats_base.q_ipackets[i] =
958 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
960 hw->eth_stats_base.q_ibytes[i] =
961 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
964 /* reading per TX ring stats */
965 for (i = 0; i < dev->data->nb_tx_queues; i++) {
966 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
969 hw->eth_stats_base.q_opackets[i] =
970 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
972 hw->eth_stats_base.q_obytes[i] =
973 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
976 hw->eth_stats_base.ipackets =
977 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
979 hw->eth_stats_base.ibytes =
980 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
982 hw->eth_stats_base.opackets =
983 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
985 hw->eth_stats_base.obytes =
986 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
988 hw->eth_stats_base.imcasts =
989 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
991 /* reading general device stats */
992 hw->eth_stats_base.ierrors =
993 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
995 hw->eth_stats_base.oerrors =
996 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
998 /* Multicast frames received */
999 hw->eth_stats_base.imcasts =
1000 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
1002 /* RX ring mbuf allocation failures */
1003 dev->data->rx_mbuf_alloc_failed = 0;
1005 hw->eth_stats_base.imissed =
1006 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1010 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1012 struct nfp_net_hw *hw;
1014 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1016 dev_info->driver_name = dev->driver->pci_drv.name;
1017 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1018 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1019 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1020 dev_info->max_rx_pktlen = hw->mtu;
1021 /* Next should change when PF support is implemented */
1022 dev_info->max_mac_addrs = 1;
1024 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1025 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1027 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1028 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1029 DEV_RX_OFFLOAD_UDP_CKSUM |
1030 DEV_RX_OFFLOAD_TCP_CKSUM;
1032 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1033 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1035 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1036 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1037 DEV_RX_OFFLOAD_UDP_CKSUM |
1038 DEV_RX_OFFLOAD_TCP_CKSUM;
1040 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1042 .pthresh = DEFAULT_RX_PTHRESH,
1043 .hthresh = DEFAULT_RX_HTHRESH,
1044 .wthresh = DEFAULT_RX_WTHRESH,
1046 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1050 dev_info->default_txconf = (struct rte_eth_txconf) {
1052 .pthresh = DEFAULT_TX_PTHRESH,
1053 .hthresh = DEFAULT_TX_HTHRESH,
1054 .wthresh = DEFAULT_TX_WTHRESH,
1056 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1057 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1058 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1059 ETH_TXQ_FLAGS_NOOFFLOADS,
1062 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1063 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1066 static const uint32_t *
1067 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1069 static const uint32_t ptypes[] = {
1070 /* refers to nfp_net_set_hash() */
1071 RTE_PTYPE_INNER_L3_IPV4,
1072 RTE_PTYPE_INNER_L3_IPV6,
1073 RTE_PTYPE_INNER_L3_IPV6_EXT,
1074 RTE_PTYPE_INNER_L4_MASK,
1078 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1084 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1086 struct nfp_net_rxq *rxq;
1087 struct nfp_net_rx_desc *rxds;
1091 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1094 PMD_INIT_LOG(ERR, "Bad queue: %u\n", queue_idx);
1098 idx = rxq->rd_p % rxq->rx_count;
1099 rxds = &rxq->rxds[idx];
1104 * Other PMDs are just checking the DD bit in intervals of 4
1105 * descriptors and counting all four if the first has the DD
1106 * bit on. Of course, this is not accurate but can be good for
1107 * perfomance. But ideally that should be done in descriptors
1108 * chunks belonging to the same cache line
1111 while (count < rxq->rx_count) {
1112 rxds = &rxq->rxds[idx];
1113 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1120 if ((idx) == rxq->rx_count)
1128 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1130 struct rte_eth_link link;
1132 memset(&link, 0, sizeof(link));
1133 nfp_net_dev_atomic_read_link_status(dev, &link);
1134 if (link.link_status)
1135 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1136 (int)(dev->data->port_id), (unsigned)link.link_speed,
1137 link.link_duplex == ETH_LINK_FULL_DUPLEX
1138 ? "full-duplex" : "half-duplex");
1140 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1141 (int)(dev->data->port_id));
1143 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1144 dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1145 dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1148 /* Interrupt configuration and handling */
1151 * nfp_net_irq_unmask - Unmask an interrupt
1153 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1154 * clear the ICR for the entry.
1157 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1159 struct nfp_net_hw *hw;
1161 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1163 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1164 /* If MSI-X auto-masking is used, clear the entry */
1166 rte_intr_enable(&dev->pci_dev->intr_handle);
1168 /* Make sure all updates are written before un-masking */
1170 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1171 NFP_NET_CFG_ICR_UNMASKED);
1176 nfp_net_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1180 struct rte_eth_link link;
1181 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1183 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1185 /* get the link status */
1186 memset(&link, 0, sizeof(link));
1187 nfp_net_dev_atomic_read_link_status(dev, &link);
1189 nfp_net_link_update(dev, 0);
1192 if (!link.link_status) {
1193 /* handle it 1 sec later, wait it being stable */
1194 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1195 /* likely to down */
1197 /* handle it 4 sec later, wait it being stable */
1198 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1201 if (rte_eal_alarm_set(timeout * 1000,
1202 nfp_net_dev_interrupt_delayed_handler,
1204 RTE_LOG(ERR, PMD, "Error setting alarm");
1206 nfp_net_irq_unmask(dev);
1211 * Interrupt handler which shall be registered for alarm callback for delayed
1212 * handling specific interrupt to wait for the stable nic state. As the NIC
1213 * interrupt state is not stable for nfp after link is just down, it needs
1214 * to wait 4 seconds to get the stable status.
1216 * @param handle Pointer to interrupt handle.
1217 * @param param The address of parameter (struct rte_eth_dev *)
1222 nfp_net_dev_interrupt_delayed_handler(void *param)
1224 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1226 nfp_net_link_update(dev, 0);
1227 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1229 nfp_net_dev_link_status_print(dev);
1232 nfp_net_irq_unmask(dev);
1236 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1238 struct nfp_net_hw *hw;
1240 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1242 /* check that mtu is within the allowed range */
1243 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1246 /* switch to jumbo mode if needed */
1247 if ((uint32_t)mtu > ETHER_MAX_LEN)
1248 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1250 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1252 /* update max frame size */
1253 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1255 /* writing to configuration space */
1256 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1264 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1265 uint16_t queue_idx, uint16_t nb_desc,
1266 unsigned int socket_id,
1267 const struct rte_eth_rxconf *rx_conf,
1268 struct rte_mempool *mp)
1270 const struct rte_memzone *tz;
1271 struct nfp_net_rxq *rxq;
1272 struct nfp_net_hw *hw;
1274 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276 PMD_INIT_FUNC_TRACE();
1278 /* Validating number of descriptors */
1279 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1280 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1281 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1282 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1287 * Free memory prior to re-allocation if needed. This is the case after
1288 * calling nfp_net_stop
1290 if (dev->data->rx_queues[queue_idx]) {
1291 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1292 dev->data->rx_queues[queue_idx] = NULL;
1295 /* Allocating rx queue data structure */
1296 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1297 RTE_CACHE_LINE_SIZE, socket_id);
1301 /* Hw queues mapping based on firmware confifguration */
1302 rxq->qidx = queue_idx;
1303 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1304 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1305 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1306 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1309 * Tracking mbuf size for detecting a potential mbuf overflow due to
1313 rxq->mbuf_size = rxq->mem_pool->elt_size;
1314 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1315 hw->flbufsz = rxq->mbuf_size;
1317 rxq->rx_count = nb_desc;
1318 rxq->port_id = dev->data->port_id;
1319 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1320 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1322 rxq->drop_en = rx_conf->rx_drop_en;
1325 * Allocate RX ring hardware descriptors. A memzone large enough to
1326 * handle the maximum ring size is allocated in order to allow for
1327 * resizing in later calls to the queue setup function.
1329 tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1330 sizeof(struct nfp_net_rx_desc) *
1331 NFP_NET_MAX_RX_DESC, socket_id);
1334 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1335 nfp_net_rx_queue_release(rxq);
1339 /* Saving physical and virtual addresses for the RX ring */
1340 rxq->dma = (uint64_t)tz->phys_addr;
1341 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1343 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1344 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1345 sizeof(*rxq->rxbufs) * nb_desc,
1346 RTE_CACHE_LINE_SIZE, socket_id);
1347 if (rxq->rxbufs == NULL) {
1348 nfp_net_rx_queue_release(rxq);
1352 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1353 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1355 nfp_net_reset_rx_queue(rxq);
1357 dev->data->rx_queues[queue_idx] = rxq;
1361 * Telling the HW about the physical address of the RX ring and number
1362 * of descriptors in log2 format
1364 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1365 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1371 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1373 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1377 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1380 for (i = 0; i < rxq->rx_count; i++) {
1381 struct nfp_net_rx_desc *rxd;
1382 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1385 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1386 (unsigned)rxq->qidx);
1390 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1392 rxd = &rxq->rxds[i];
1394 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1395 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1397 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1402 /* Make sure all writes are flushed before telling the hardware */
1405 /* Not advertising the whole ring as the firmware gets confused if so */
1406 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1409 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1415 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1416 uint16_t nb_desc, unsigned int socket_id,
1417 const struct rte_eth_txconf *tx_conf)
1419 const struct rte_memzone *tz;
1420 struct nfp_net_txq *txq;
1421 uint16_t tx_free_thresh;
1422 struct nfp_net_hw *hw;
1424 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426 PMD_INIT_FUNC_TRACE();
1428 /* Validating number of descriptors */
1429 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1430 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1431 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1432 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1436 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1437 tx_conf->tx_free_thresh :
1438 DEFAULT_TX_FREE_THRESH);
1440 if (tx_free_thresh > (nb_desc)) {
1442 "tx_free_thresh must be less than the number of TX "
1443 "descriptors. (tx_free_thresh=%u port=%d "
1444 "queue=%d)\n", (unsigned int)tx_free_thresh,
1445 (int)dev->data->port_id, (int)queue_idx);
1450 * Free memory prior to re-allocation if needed. This is the case after
1451 * calling nfp_net_stop
1453 if (dev->data->tx_queues[queue_idx]) {
1454 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1456 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1457 dev->data->tx_queues[queue_idx] = NULL;
1460 /* Allocating tx queue data structure */
1461 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1462 RTE_CACHE_LINE_SIZE, socket_id);
1464 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1469 * Allocate TX ring hardware descriptors. A memzone large enough to
1470 * handle the maximum ring size is allocated in order to allow for
1471 * resizing in later calls to the queue setup function.
1473 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1474 sizeof(struct nfp_net_tx_desc) *
1475 NFP_NET_MAX_TX_DESC, socket_id);
1477 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1478 nfp_net_tx_queue_release(txq);
1482 txq->tx_count = nb_desc;
1484 txq->tx_free_thresh = tx_free_thresh;
1485 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1486 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1487 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1489 /* queue mapping based on firmware configuration */
1490 txq->qidx = queue_idx;
1491 txq->tx_qcidx = queue_idx * hw->stride_tx;
1492 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1494 txq->port_id = dev->data->port_id;
1495 txq->txq_flags = tx_conf->txq_flags;
1497 /* Saving physical and virtual addresses for the TX ring */
1498 txq->dma = (uint64_t)tz->phys_addr;
1499 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1501 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1502 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1503 sizeof(*txq->txbufs) * nb_desc,
1504 RTE_CACHE_LINE_SIZE, socket_id);
1505 if (txq->txbufs == NULL) {
1506 nfp_net_tx_queue_release(txq);
1509 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1510 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1512 nfp_net_reset_tx_queue(txq);
1514 dev->data->tx_queues[queue_idx] = txq;
1518 * Telling the HW about the physical address of the TX ring and number
1519 * of descriptors in log2 format
1521 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1522 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1527 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1529 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1530 struct rte_mbuf *mb)
1533 struct nfp_net_hw *hw = txq->hw;
1535 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1538 ol_flags = mb->ol_flags;
1540 /* IPv6 does not need checksum */
1541 if (ol_flags & PKT_TX_IP_CKSUM)
1542 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1544 switch (ol_flags & PKT_TX_L4_MASK) {
1545 case PKT_TX_UDP_CKSUM:
1546 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1548 case PKT_TX_TCP_CKSUM:
1549 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1553 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1554 txd->flags |= PCIE_DESC_TX_CSUM;
1557 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1559 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1560 struct rte_mbuf *mb)
1562 struct nfp_net_hw *hw = rxq->hw;
1564 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1567 /* If IPv4 and IP checksum error, fail */
1568 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1569 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1570 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1572 /* If neither UDP nor TCP return */
1573 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1574 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1577 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1578 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1579 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1581 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1582 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1583 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1586 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1587 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1590 * nfp_net_set_hash - Set mbuf hash data
1592 * The RSS hash and hash-type are pre-pended to the packet data.
1593 * Extract and decode it and set the mbuf fields.
1596 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1597 struct rte_mbuf *mbuf)
1601 struct nfp_net_hw *hw = rxq->hw;
1603 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1606 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1609 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1610 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1613 * hash type is sharing the same word with input port info
1618 mbuf->hash.rss = hash;
1619 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1621 switch (hash_type) {
1622 case NFP_NET_RSS_IPV4:
1623 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1625 case NFP_NET_RSS_IPV6:
1626 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1628 case NFP_NET_RSS_IPV6_EX:
1629 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1632 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1636 /* nfp_net_check_port - Set mbuf in_port field */
1638 nfp_net_check_port(struct nfp_net_rx_desc *rxd, struct rte_mbuf *mbuf)
1642 if (!(rxd->rxd.flags & PCIE_DESC_RX_INGRESS_PORT)) {
1647 port = rte_be_to_cpu_32(*(uint32_t *)((uint8_t *)mbuf->buf_addr +
1648 mbuf->data_off - 8));
1651 * hash type is sharing the same word with input port info
1655 port = (uint8_t)(port >> 8);
1660 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1662 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1665 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1670 * There are some decissions to take:
1671 * 1) How to check DD RX descriptors bit
1672 * 2) How and when to allocate new mbufs
1674 * Current implementation checks just one single DD bit each loop. As each
1675 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1676 * a single cache line instead. Tests with this change have not shown any
1677 * performance improvement but it requires further investigation. For example,
1678 * depending on which descriptor is next, the number of descriptors could be
1679 * less than 8 for just checking those in the same cache line. This implies
1680 * extra work which could be counterproductive by itself. Indeed, last firmware
1681 * changes are just doing this: writing several descriptors with the DD bit
1682 * for saving PCIe bandwidth and DMA operations from the NFP.
1684 * Mbuf allocation is done when a new packet is received. Then the descriptor
1685 * is automatically linked with the new mbuf and the old one is given to the
1686 * user. The main drawback with this design is mbuf allocation is heavier than
1687 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1688 * cache point of view it does not seem allocating the mbuf early on as we are
1689 * doing now have any benefit at all. Again, tests with this change have not
1690 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1691 * so looking at the implications of this type of allocation should be studied
1696 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1698 struct nfp_net_rxq *rxq;
1699 struct nfp_net_rx_desc *rxds;
1700 struct nfp_net_rx_buff *rxb;
1701 struct nfp_net_hw *hw;
1702 struct rte_mbuf *mb;
1703 struct rte_mbuf *new_mb;
1710 if (unlikely(rxq == NULL)) {
1712 * DPDK just checks the queue is lower than max queues
1713 * enabled. But the queue needs to be configured
1715 RTE_LOG(ERR, PMD, "RX Bad queue\n");
1723 while (avail < nb_pkts) {
1724 idx = rxq->rd_p % rxq->rx_count;
1726 rxb = &rxq->rxbufs[idx];
1727 if (unlikely(rxb == NULL)) {
1728 RTE_LOG(ERR, PMD, "rxb does not exist!\n");
1733 * Memory barrier to ensure that we won't do other
1734 * reads before the DD bit.
1738 rxds = &rxq->rxds[idx];
1739 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1743 * We got a packet. Let's alloc a new mbuff for refilling the
1744 * free descriptor ring as soon as possible
1746 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1747 if (unlikely(new_mb == NULL)) {
1748 RTE_LOG(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1749 "queue_id=%u\n", (unsigned)rxq->port_id,
1750 (unsigned)rxq->qidx);
1751 nfp_net_mbuf_alloc_failed(rxq);
1758 * Grab the mbuff and refill the descriptor with the
1759 * previously allocated mbuff
1764 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1765 rxds->rxd.data_len, rxq->mbuf_size);
1767 /* Size of this segment */
1768 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1769 /* Size of the whole packet. We just support 1 segment */
1770 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1772 if (unlikely((mb->data_len + hw->rx_offset) >
1775 * This should not happen and the user has the
1776 * responsibility of avoiding it. But we have
1777 * to give some info about the error
1780 "mbuf overflow likely due to the RX offset.\n"
1781 "\t\tYour mbuf size should have extra space for"
1782 " RX offset=%u bytes.\n"
1783 "\t\tCurrently you just have %u bytes available"
1784 " but the received packet is %u bytes long",
1786 rxq->mbuf_size - hw->rx_offset,
1791 /* Filling the received mbuff with packet info */
1793 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1795 mb->data_off = RTE_PKTMBUF_HEADROOM +
1796 NFP_DESC_META_LEN(rxds);
1798 /* No scatter mode supported */
1802 /* Checking the RSS flag */
1803 nfp_net_set_hash(rxq, rxds, mb);
1805 /* Checking the checksum flag */
1806 nfp_net_rx_cksum(rxq, rxds, mb);
1808 /* Checking the port flag */
1809 nfp_net_check_port(rxds, mb);
1811 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1812 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1813 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1814 mb->ol_flags |= PKT_RX_VLAN_PKT;
1817 /* Adding the mbuff to the mbuff array passed by the app */
1818 rx_pkts[avail++] = mb;
1820 /* Now resetting and updating the descriptor */
1823 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1825 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1826 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1834 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1835 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1837 nb_hold += rxq->nb_rx_hold;
1840 * FL descriptors needs to be written before incrementing the
1841 * FL queue WR pointer
1844 if (nb_hold > rxq->rx_free_thresh) {
1845 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1846 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1847 (unsigned)nb_hold, (unsigned)avail);
1848 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1851 rxq->nb_rx_hold = nb_hold;
1857 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1859 * @txq: TX queue to work with
1860 * Returns number of descriptors freed
1863 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1868 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1869 " status\n", txq->qidx);
1871 /* Work out how many packets have been sent */
1872 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1874 if (qcp_rd_p == txq->qcp_rd_p) {
1875 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1876 "packets (%u, %u)\n", txq->qidx,
1877 qcp_rd_p, txq->qcp_rd_p);
1881 if (qcp_rd_p > txq->qcp_rd_p)
1882 todo = qcp_rd_p - txq->qcp_rd_p;
1884 todo = qcp_rd_p + txq->tx_count - txq->qcp_rd_p;
1886 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->qcp_rd_p: %u, qcp->rd_p: %u\n",
1887 qcp_rd_p, txq->qcp_rd_p, txq->rd_p);
1892 txq->qcp_rd_p += todo;
1893 txq->qcp_rd_p %= txq->tx_count;
1899 /* Leaving always free descriptors for avoiding wrapping confusion */
1900 #define NFP_FREE_TX_DESC(t) (t->tx_count - (t->wr_p - t->rd_p) - 8)
1903 * nfp_net_txq_full - Check if the TX queue free descriptors
1904 * is below tx_free_threshold
1906 * @txq: TX queue to check
1908 * This function uses the host copy* of read/write pointers
1911 int nfp_net_txq_full(struct nfp_net_txq *txq)
1913 return NFP_FREE_TX_DESC(txq) < txq->tx_free_thresh;
1917 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1919 struct nfp_net_txq *txq;
1920 struct nfp_net_hw *hw;
1921 struct nfp_net_tx_desc *txds;
1922 struct rte_mbuf *pkt;
1924 int pkt_size, dma_size;
1925 uint16_t free_descs, issued_descs;
1926 struct rte_mbuf **lmbuf;
1931 txds = &txq->txds[txq->tail];
1933 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
1934 txq->qidx, txq->tail, nb_pkts);
1936 if ((NFP_FREE_TX_DESC(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
1937 nfp_net_tx_free_bufs(txq);
1939 free_descs = (uint16_t)NFP_FREE_TX_DESC(txq);
1940 if (unlikely(free_descs == 0))
1947 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
1948 txq->qidx, nb_pkts);
1949 /* Sending packets */
1950 while ((i < nb_pkts) && free_descs) {
1951 /* Grabbing the mbuf linked to the current descriptor */
1952 lmbuf = &txq->txbufs[txq->tail].mbuf;
1953 /* Warming the cache for releasing the mbuf later on */
1954 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
1956 pkt = *(tx_pkts + i);
1958 if (unlikely((pkt->nb_segs > 1) &&
1959 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
1960 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set\n");
1961 rte_panic("Multisegment packet unsupported\n");
1964 /* Checking if we have enough descriptors */
1965 if (unlikely(pkt->nb_segs > free_descs))
1969 * Checksum and VLAN flags just in the first descriptor for a
1970 * multisegment packet
1972 nfp_net_tx_cksum(txq, txds, pkt);
1974 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
1975 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
1976 txds->flags |= PCIE_DESC_TX_VLAN;
1977 txds->vlan = pkt->vlan_tci;
1980 if (pkt->ol_flags & PKT_TX_TCP_SEG)
1981 rte_panic("TSO is not supported\n");
1984 * mbuf data_len is the data in one segment and pkt_len data
1985 * in the whole packet. When the packet is just one segment,
1986 * then data_len = pkt_len
1988 pkt_size = pkt->pkt_len;
1991 /* Releasing mbuf which was prefetched above */
1993 rte_pktmbuf_free_seg(*lmbuf);
1995 dma_size = pkt->data_len;
1996 dma_addr = rte_mbuf_data_dma_addr(pkt);
1997 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
1998 "%" PRIx64 "\n", dma_addr);
2000 /* Filling descriptors fields */
2001 txds->dma_len = dma_size;
2002 txds->data_len = pkt->pkt_len;
2003 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2004 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2005 ASSERT(free_descs > 0);
2009 * Linking mbuf with descriptor for being released
2010 * next time descriptor is used
2016 if (unlikely(txq->tail == txq->tx_count)) /* wrapping?*/
2019 pkt_size -= dma_size;
2022 txds->offset_eop |= PCIE_DESC_TX_EOP;
2024 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2027 /* Referencing next free TX descriptor */
2028 txds = &txq->txds[txq->tail];
2035 /* Increment write pointers. Force memory write before we let HW know */
2037 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2043 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2045 uint32_t new_ctrl, update;
2046 struct nfp_net_hw *hw;
2048 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2052 (mask & ETH_VLAN_FILTER_OFFLOAD))
2053 RTE_LOG(INFO, PMD, "Not support for ETH_VLAN_FILTER_OFFLOAD or"
2054 " ETH_VLAN_FILTER_EXTEND");
2056 /* Enable vlan strip if it is not configured yet */
2057 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2058 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2059 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2061 /* Disable vlan strip just if it is configured */
2062 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2063 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2064 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2069 update = NFP_NET_CFG_UPDATE_GEN;
2071 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2074 hw->ctrl = new_ctrl;
2077 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2079 nfp_net_reta_update(struct rte_eth_dev *dev,
2080 struct rte_eth_rss_reta_entry64 *reta_conf,
2083 uint32_t reta, mask;
2087 struct nfp_net_hw *hw =
2088 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2090 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2093 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2094 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2095 "(%d) doesn't match the number hardware can supported "
2096 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2101 * Update Redirection Table. There are 128 8bit-entries which can be
2102 * manage as 32 32bit-entries
2104 for (i = 0; i < reta_size; i += 4) {
2105 /* Handling 4 RSS entries per loop */
2106 idx = i / RTE_RETA_GROUP_SIZE;
2107 shift = i % RTE_RETA_GROUP_SIZE;
2108 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2114 /* If all 4 entries were set, don't need read RETA register */
2116 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2118 for (j = 0; j < 4; j++) {
2119 if (!(mask & (0x1 << j)))
2122 /* Clearing the entry bits */
2123 reta &= ~(0xFF << (8 * j));
2124 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2126 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2129 update = NFP_NET_CFG_UPDATE_RSS;
2131 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2137 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2139 nfp_net_reta_query(struct rte_eth_dev *dev,
2140 struct rte_eth_rss_reta_entry64 *reta_conf,
2146 struct nfp_net_hw *hw;
2148 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2153 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2154 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2155 "(%d) doesn't match the number hardware can supported "
2156 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2161 * Reading Redirection Table. There are 128 8bit-entries which can be
2162 * manage as 32 32bit-entries
2164 for (i = 0; i < reta_size; i += 4) {
2165 /* Handling 4 RSS entries per loop */
2166 idx = i / RTE_RETA_GROUP_SIZE;
2167 shift = i % RTE_RETA_GROUP_SIZE;
2168 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2173 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2174 for (j = 0; j < 4; j++) {
2175 if (!(mask & (0x1 << j)))
2177 reta_conf->reta[shift + j] =
2178 (uint8_t)((reta >> (8 * j)) & 0xF);
2185 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2186 struct rte_eth_rss_conf *rss_conf)
2189 uint32_t cfg_rss_ctrl = 0;
2193 struct nfp_net_hw *hw;
2195 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2197 rss_hf = rss_conf->rss_hf;
2199 /* Checking if RSS is enabled */
2200 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2201 if (rss_hf != 0) { /* Enable RSS? */
2202 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2205 return 0; /* Nothing to do */
2208 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2209 RTE_LOG(ERR, PMD, "hash key too long\n");
2213 if (rss_hf & ETH_RSS_IPV4)
2214 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2215 NFP_NET_CFG_RSS_IPV4_TCP |
2216 NFP_NET_CFG_RSS_IPV4_UDP;
2218 if (rss_hf & ETH_RSS_IPV6)
2219 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2220 NFP_NET_CFG_RSS_IPV6_TCP |
2221 NFP_NET_CFG_RSS_IPV6_UDP;
2223 /* configuring where to apply the RSS hash */
2224 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2226 /* Writing the key byte a byte */
2227 for (i = 0; i < rss_conf->rss_key_len; i++) {
2228 memcpy(&key, &rss_conf->rss_key[i], 1);
2229 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2232 /* Writing the key size */
2233 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2235 update = NFP_NET_CFG_UPDATE_RSS;
2237 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2244 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2245 struct rte_eth_rss_conf *rss_conf)
2248 uint32_t cfg_rss_ctrl;
2251 struct nfp_net_hw *hw;
2253 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2255 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2258 rss_hf = rss_conf->rss_hf;
2259 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2261 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2262 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2264 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2265 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2267 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2268 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2270 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2271 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2273 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2274 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2276 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2277 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2279 /* Reading the key size */
2280 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2282 /* Reading the key byte a byte */
2283 for (i = 0; i < rss_conf->rss_key_len; i++) {
2284 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2285 memcpy(&rss_conf->rss_key[i], &key, 1);
2291 /* Initialise and register driver with DPDK Application */
2292 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2293 .dev_configure = nfp_net_configure,
2294 .dev_start = nfp_net_start,
2295 .dev_stop = nfp_net_stop,
2296 .dev_close = nfp_net_close,
2297 .promiscuous_enable = nfp_net_promisc_enable,
2298 .promiscuous_disable = nfp_net_promisc_disable,
2299 .link_update = nfp_net_link_update,
2300 .stats_get = nfp_net_stats_get,
2301 .stats_reset = nfp_net_stats_reset,
2302 .dev_infos_get = nfp_net_infos_get,
2303 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2304 .mtu_set = nfp_net_dev_mtu_set,
2305 .vlan_offload_set = nfp_net_vlan_offload_set,
2306 .reta_update = nfp_net_reta_update,
2307 .reta_query = nfp_net_reta_query,
2308 .rss_hash_update = nfp_net_rss_hash_update,
2309 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2310 .rx_queue_setup = nfp_net_rx_queue_setup,
2311 .rx_queue_release = nfp_net_rx_queue_release,
2312 .rx_queue_count = nfp_net_rx_queue_count,
2313 .tx_queue_setup = nfp_net_tx_queue_setup,
2314 .tx_queue_release = nfp_net_tx_queue_release,
2318 nfp_net_init(struct rte_eth_dev *eth_dev)
2320 struct rte_pci_device *pci_dev;
2321 struct nfp_net_hw *hw;
2323 uint32_t tx_bar_off, rx_bar_off;
2327 PMD_INIT_FUNC_TRACE();
2329 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2331 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2332 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2333 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2335 /* For secondary processes, the primary has done all the work */
2336 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2339 pci_dev = eth_dev->pci_dev;
2340 hw->device_id = pci_dev->id.device_id;
2341 hw->vendor_id = pci_dev->id.vendor_id;
2342 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2343 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2345 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u\n",
2346 pci_dev->id.vendor_id, pci_dev->id.device_id,
2347 pci_dev->addr.domain, pci_dev->addr.bus,
2348 pci_dev->addr.devid, pci_dev->addr.function);
2350 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2351 if (hw->ctrl_bar == NULL) {
2353 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2356 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2357 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2359 /* Work out where in the BAR the queues start. */
2360 switch (pci_dev->id.device_id) {
2361 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2362 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2363 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2364 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2365 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2368 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2372 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x\n", tx_bar_off);
2373 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x\n", rx_bar_off);
2375 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2376 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2378 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p\n",
2379 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2381 nfp_net_cfg_queue_setup(hw);
2383 /* Get some of the read-only fields from the config BAR */
2384 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2385 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2386 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2387 hw->mtu = hw->max_mtu;
2389 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2390 hw->rx_offset = NFP_NET_RX_OFFSET;
2392 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2394 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d\n",
2395 hw->ver, hw->max_mtu);
2396 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s\n", hw->cap,
2397 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2398 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2399 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2400 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2401 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2402 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2403 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2404 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2405 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2407 pci_dev = eth_dev->pci_dev;
2410 hw->stride_rx = stride;
2411 hw->stride_tx = stride;
2413 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u\n",
2414 hw->max_rx_queues, hw->max_tx_queues);
2416 /* Allocating memory for mac addr */
2417 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2418 if (eth_dev->data->mac_addrs == NULL) {
2419 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2423 /* Using random mac addresses for VFs */
2424 eth_random_addr(&hw->mac_addr[0]);
2426 /* Copying mac address to DPDK eth_dev struct */
2427 ether_addr_copy(ð_dev->data->mac_addrs[0],
2428 (struct ether_addr *)hw->mac_addr);
2430 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2431 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2432 eth_dev->data->port_id, pci_dev->id.vendor_id,
2433 pci_dev->id.device_id,
2434 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2435 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2437 /* Registering LSC interrupt handler */
2438 rte_intr_callback_register(&pci_dev->intr_handle,
2439 nfp_net_dev_interrupt_handler,
2442 /* enable uio intr after callback register */
2443 rte_intr_enable(&pci_dev->intr_handle);
2445 /* Telling the firmware about the LSC interrupt entry */
2446 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2448 /* Recording current stats counters values */
2449 nfp_net_stats_reset(eth_dev);
2454 static struct rte_pci_id pci_id_nfp_net_map[] = {
2456 .vendor_id = PCI_VENDOR_ID_NETRONOME,
2457 .device_id = PCI_DEVICE_ID_NFP6000_PF_NIC,
2458 .subsystem_vendor_id = PCI_ANY_ID,
2459 .subsystem_device_id = PCI_ANY_ID,
2462 .vendor_id = PCI_VENDOR_ID_NETRONOME,
2463 .device_id = PCI_DEVICE_ID_NFP6000_VF_NIC,
2464 .subsystem_vendor_id = PCI_ANY_ID,
2465 .subsystem_device_id = PCI_ANY_ID,
2472 static struct eth_driver rte_nfp_net_pmd = {
2474 .name = "rte_nfp_net_pmd",
2475 .id_table = pci_id_nfp_net_map,
2476 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2478 .eth_dev_init = nfp_net_init,
2479 .dev_private_size = sizeof(struct nfp_net_adapter),
2483 nfp_net_pmd_init(const char *name __rte_unused,
2484 const char *params __rte_unused)
2486 PMD_INIT_FUNC_TRACE();
2487 PMD_INIT_LOG(INFO, "librte_pmd_nfp_net version %s\n",
2488 NFP_NET_PMD_VERSION);
2490 rte_eth_driver_register(&rte_nfp_net_pmd);
2494 static struct rte_driver rte_nfp_net_driver = {
2496 .init = nfp_net_pmd_init,
2499 PMD_REGISTER_DRIVER(rte_nfp_net_driver);
2503 * c-file-style: "Linux"
2504 * indent-tabs-mode: t