2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
47 #include <rte_debug.h>
48 #include <rte_ethdev.h>
50 #include <rte_ether.h>
51 #include <rte_malloc.h>
52 #include <rte_memzone.h>
53 #include <rte_mempool.h>
54 #include <rte_version.h>
55 #include <rte_string_fns.h>
56 #include <rte_alarm.h>
57 #include <rte_spinlock.h>
59 #include "nfp_net_pmd.h"
60 #include "nfp_net_logs.h"
61 #include "nfp_net_ctrl.h"
64 static void nfp_net_close(struct rte_eth_dev *dev);
65 static int nfp_net_configure(struct rte_eth_dev *dev);
66 static void nfp_net_dev_interrupt_handler(struct rte_intr_handle *handle,
68 static void nfp_net_dev_interrupt_delayed_handler(void *param);
69 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
70 static void nfp_net_infos_get(struct rte_eth_dev *dev,
71 struct rte_eth_dev_info *dev_info);
72 static int nfp_net_init(struct rte_eth_dev *eth_dev);
73 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
74 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
75 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
76 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
77 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
79 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
81 static void nfp_net_rx_queue_release(void *rxq);
82 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
83 uint16_t nb_desc, unsigned int socket_id,
84 const struct rte_eth_rxconf *rx_conf,
85 struct rte_mempool *mp);
86 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
87 static void nfp_net_tx_queue_release(void *txq);
88 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
89 uint16_t nb_desc, unsigned int socket_id,
90 const struct rte_eth_txconf *tx_conf);
91 static int nfp_net_start(struct rte_eth_dev *dev);
92 static void nfp_net_stats_get(struct rte_eth_dev *dev,
93 struct rte_eth_stats *stats);
94 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
95 static void nfp_net_stop(struct rte_eth_dev *dev);
96 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
100 * The offset of the queue controller queues in the PCIe Target. These
101 * happen to be at the same offset on the NFP6000 and the NFP3200 so
102 * we use a single macro here.
104 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
106 /* Maximum value which can be added to a queue with one transaction */
107 #define NFP_QCP_MAX_ADD 0x7f
109 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
110 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
112 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
114 NFP_QCP_READ_PTR = 0,
119 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
120 * @q: Base address for queue structure
121 * @ptr: Add to the Read or Write pointer
122 * @val: Value to add to the queue pointer
124 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
127 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
131 if (ptr == NFP_QCP_READ_PTR)
132 off = NFP_QCP_QUEUE_ADD_RPTR;
134 off = NFP_QCP_QUEUE_ADD_WPTR;
136 while (val > NFP_QCP_MAX_ADD) {
137 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
138 val -= NFP_QCP_MAX_ADD;
141 nn_writel(rte_cpu_to_le_32(val), q + off);
145 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
146 * @q: Base address for queue structure
147 * @ptr: Read or Write pointer
149 static inline uint32_t
150 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
155 if (ptr == NFP_QCP_READ_PTR)
156 off = NFP_QCP_QUEUE_STS_LO;
158 off = NFP_QCP_QUEUE_STS_HI;
160 val = rte_cpu_to_le_32(nn_readl(q + off));
162 if (ptr == NFP_QCP_READ_PTR)
163 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
165 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
169 * Functions to read/write from/to Config BAR
170 * Performs any endian conversion necessary.
172 static inline uint8_t
173 nn_cfg_readb(struct nfp_net_hw *hw, int off)
175 return nn_readb(hw->ctrl_bar + off);
179 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
181 nn_writeb(val, hw->ctrl_bar + off);
184 static inline uint32_t
185 nn_cfg_readl(struct nfp_net_hw *hw, int off)
187 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
191 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
193 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
196 static inline uint64_t
197 nn_cfg_readq(struct nfp_net_hw *hw, int off)
199 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
203 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
205 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
208 /* Creating memzone for hardware rings. */
209 static const struct rte_memzone *
210 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
211 uint16_t queue_id, uint32_t ring_size, int socket_id)
213 char z_name[RTE_MEMZONE_NAMESIZE];
214 const struct rte_memzone *mz;
216 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
217 dev->driver->pci_drv.driver.name,
218 ring_name, dev->data->port_id, queue_id);
220 mz = rte_memzone_lookup(z_name);
224 return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
229 * Atomically reads link status information from global structure rte_eth_dev.
232 * - Pointer to the structure rte_eth_dev to read from.
233 * - Pointer to the buffer to be saved with the link status.
236 * - On success, zero.
237 * - On failure, negative value.
240 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
241 struct rte_eth_link *link)
243 struct rte_eth_link *dst = link;
244 struct rte_eth_link *src = &dev->data->dev_link;
246 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
247 *(uint64_t *)src) == 0)
254 * Atomically writes the link status information into global
255 * structure rte_eth_dev.
258 * - Pointer to the structure rte_eth_dev to read from.
259 * - Pointer to the buffer to be saved with the link status.
262 * - On success, zero.
263 * - On failure, negative value.
266 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
267 struct rte_eth_link *link)
269 struct rte_eth_link *dst = &dev->data->dev_link;
270 struct rte_eth_link *src = link;
272 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
273 *(uint64_t *)src) == 0)
280 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
284 if (rxq->rxbufs == NULL)
287 for (i = 0; i < rxq->rx_count; i++) {
288 if (rxq->rxbufs[i].mbuf) {
289 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
290 rxq->rxbufs[i].mbuf = NULL;
296 nfp_net_rx_queue_release(void *rx_queue)
298 struct nfp_net_rxq *rxq = rx_queue;
301 nfp_net_rx_queue_release_mbufs(rxq);
302 rte_free(rxq->rxbufs);
308 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
310 nfp_net_rx_queue_release_mbufs(rxq);
316 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
320 if (txq->txbufs == NULL)
323 for (i = 0; i < txq->tx_count; i++) {
324 if (txq->txbufs[i].mbuf) {
325 rte_pktmbuf_free(txq->txbufs[i].mbuf);
326 txq->txbufs[i].mbuf = NULL;
332 nfp_net_tx_queue_release(void *tx_queue)
334 struct nfp_net_txq *txq = tx_queue;
337 nfp_net_tx_queue_release_mbufs(txq);
338 rte_free(txq->txbufs);
344 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
346 nfp_net_tx_queue_release_mbufs(txq);
352 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
356 struct timespec wait;
358 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
361 if (hw->qcp_cfg == NULL)
362 rte_panic("Bad configuration queue pointer\n");
364 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
367 wait.tv_nsec = 1000000;
369 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
371 /* Poll update field, waiting for NFP to ack the config */
372 for (cnt = 0; ; cnt++) {
373 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
376 if (new & NFP_NET_CFG_UPDATE_ERR) {
377 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
380 if (cnt >= NFP_NET_POLL_TIMEOUT) {
381 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
382 " %dms", update, cnt);
383 rte_panic("Exiting\n");
385 nanosleep(&wait, 0); /* waiting for a 1ms */
387 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
392 * Reconfigure the NIC
393 * @nn: device to reconfigure
394 * @ctrl: The value for the ctrl field in the BAR config
395 * @update: The value for the update field in the BAR config
397 * Write the update word to the BAR and ping the reconfig queue. Then poll
398 * until the firmware has acknowledged the update by zeroing the update word.
401 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
405 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
408 rte_spinlock_lock(&hw->reconfig_lock);
410 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
411 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
415 err = __nfp_net_reconfig(hw, update);
417 rte_spinlock_unlock(&hw->reconfig_lock);
423 * Reconfig errors imply situations where they can be handled.
424 * Otherwise, rte_panic is called inside __nfp_net_reconfig
426 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
432 * Configure an Ethernet device. This function must be invoked first
433 * before any other function in the Ethernet API. This function can
434 * also be re-invoked when a device is in the stopped state.
437 nfp_net_configure(struct rte_eth_dev *dev)
439 struct rte_eth_conf *dev_conf;
440 struct rte_eth_rxmode *rxmode;
441 struct rte_eth_txmode *txmode;
442 uint32_t new_ctrl = 0;
444 struct nfp_net_hw *hw;
446 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
449 * A DPDK app sends info about how many queues to use and how
450 * those queues need to be configured. This is used by the
451 * DPDK core and it makes sure no more queues than those
452 * advertised by the driver are requested. This function is
453 * called after that internal process
456 PMD_INIT_LOG(DEBUG, "Configure");
458 dev_conf = &dev->data->dev_conf;
459 rxmode = &dev_conf->rxmode;
460 txmode = &dev_conf->txmode;
462 /* Checking TX mode */
463 if (txmode->mq_mode) {
464 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
468 /* Checking RX mode */
469 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
470 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
471 update = NFP_NET_CFG_UPDATE_RSS;
472 new_ctrl = NFP_NET_CFG_CTRL_RSS;
474 PMD_INIT_LOG(INFO, "RSS not supported");
479 if (rxmode->split_hdr_size) {
480 PMD_INIT_LOG(INFO, "rxmode does not support split header");
484 if (rxmode->hw_ip_checksum) {
485 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
486 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
488 PMD_INIT_LOG(INFO, "RXCSUM not supported");
493 if (rxmode->hw_vlan_filter) {
494 PMD_INIT_LOG(INFO, "VLAN filter not supported");
498 if (rxmode->hw_vlan_strip) {
499 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
500 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
502 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
507 if (rxmode->hw_vlan_extend) {
508 PMD_INIT_LOG(INFO, "VLAN extended not supported");
512 /* Supporting VLAN insertion by default */
513 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
514 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
516 if (rxmode->jumbo_frame)
517 /* this is handled in rte_eth_dev_configure */
519 if (rxmode->hw_strip_crc) {
520 PMD_INIT_LOG(INFO, "strip CRC not supported");
524 if (rxmode->enable_scatter) {
525 PMD_INIT_LOG(INFO, "Scatter not supported");
532 update |= NFP_NET_CFG_UPDATE_GEN;
534 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
535 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
544 nfp_net_enable_queues(struct rte_eth_dev *dev)
546 struct nfp_net_hw *hw;
547 uint64_t enabled_queues = 0;
550 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
552 /* Enabling the required TX queues in the device */
553 for (i = 0; i < dev->data->nb_tx_queues; i++)
554 enabled_queues |= (1 << i);
556 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
560 /* Enabling the required RX queues in the device */
561 for (i = 0; i < dev->data->nb_rx_queues; i++)
562 enabled_queues |= (1 << i);
564 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
568 nfp_net_disable_queues(struct rte_eth_dev *dev)
570 struct nfp_net_hw *hw;
571 uint32_t new_ctrl, update = 0;
573 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
575 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
576 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
578 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
579 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
580 NFP_NET_CFG_UPDATE_MSIX;
582 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
583 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
585 /* If an error when reconfig we avoid to change hw state */
586 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
593 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
597 for (i = 0; i < dev->data->nb_rx_queues; i++) {
598 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
605 nfp_net_params_setup(struct nfp_net_hw *hw)
607 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
608 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
612 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
614 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
617 static void nfp_net_read_mac(struct nfp_net_hw *hw)
621 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
622 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
624 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
625 memcpy(&hw->mac_addr[4], &tmp, 2);
629 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
630 struct rte_intr_handle *intr_handle)
632 struct nfp_net_hw *hw;
635 if (!intr_handle->intr_vec) {
636 intr_handle->intr_vec =
637 rte_zmalloc("intr_vec",
638 dev->data->nb_rx_queues * sizeof(int), 0);
639 if (!intr_handle->intr_vec) {
640 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
641 " intr_vec", dev->data->nb_rx_queues);
646 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
648 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
649 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
650 /* UIO just supports one queue and no LSC*/
651 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
653 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
654 for (i = 0; i < dev->data->nb_rx_queues; i++)
656 * The first msix vector is reserved for non
659 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
662 /* Avoiding TX interrupts */
663 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
668 nfp_net_start(struct rte_eth_dev *dev)
670 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
671 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
672 uint32_t new_ctrl, update = 0;
673 struct nfp_net_hw *hw;
674 uint32_t intr_vector;
677 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
679 PMD_INIT_LOG(DEBUG, "Start");
681 /* Disabling queues just in case... */
682 nfp_net_disable_queues(dev);
684 /* Writing configuration parameters in the device */
685 nfp_net_params_setup(hw);
687 /* Enabling the required queues in the device */
688 nfp_net_enable_queues(dev);
690 /* check and configure queue intr-vector mapping */
691 if (dev->data->dev_conf.intr_conf.rxq != 0) {
692 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
694 * Better not to share LSC with RX interrupts.
695 * Unregistering LSC interrupt handler
697 rte_intr_callback_unregister(&pci_dev->intr_handle,
698 nfp_net_dev_interrupt_handler, (void *)dev);
700 if (dev->data->nb_rx_queues > 1) {
701 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
702 "supports 1 queue with UIO");
706 intr_vector = dev->data->nb_rx_queues;
707 if (rte_intr_efd_enable(intr_handle, intr_vector))
711 if (rte_intr_dp_is_en(intr_handle))
712 nfp_configure_rx_interrupt(dev, intr_handle);
714 rte_intr_enable(intr_handle);
717 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
718 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
720 /* Just configuring queues interrupts when necessary */
721 if (rte_intr_dp_is_en(intr_handle))
722 update |= NFP_NET_CFG_UPDATE_MSIX;
724 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
725 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
727 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
728 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
732 * Allocating rte mbuffs for configured rx queues.
733 * This requires queues being enabled before
735 if (nfp_net_rx_freelist_setup(dev) < 0) {
746 * An error returned by this function should mean the app
747 * exiting and then the system releasing all the memory
748 * allocated even memory coming from hugepages.
750 * The device could be enabled at this point with some queues
751 * ready for getting packets. This is true if the call to
752 * nfp_net_rx_freelist_setup() succeeds for some queues but
753 * fails for subsequent queues.
755 * This should make the app exiting but better if we tell the
758 nfp_net_disable_queues(dev);
763 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
765 nfp_net_stop(struct rte_eth_dev *dev)
769 PMD_INIT_LOG(DEBUG, "Stop");
771 nfp_net_disable_queues(dev);
774 for (i = 0; i < dev->data->nb_tx_queues; i++) {
775 nfp_net_reset_tx_queue(
776 (struct nfp_net_txq *)dev->data->tx_queues[i]);
779 for (i = 0; i < dev->data->nb_rx_queues; i++) {
780 nfp_net_reset_rx_queue(
781 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
785 /* Reset and stop device. The device can not be restarted. */
787 nfp_net_close(struct rte_eth_dev *dev)
789 struct nfp_net_hw *hw;
790 struct rte_pci_device *pci_dev;
792 PMD_INIT_LOG(DEBUG, "Close");
794 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
795 pci_dev = RTE_DEV_TO_PCI(dev->device);
798 * We assume that the DPDK application is stopping all the
799 * threads/queues before calling the device close function.
804 rte_intr_disable(&pci_dev->intr_handle);
805 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
807 /* unregister callback func from eal lib */
808 rte_intr_callback_unregister(&pci_dev->intr_handle,
809 nfp_net_dev_interrupt_handler,
813 * The ixgbe PMD driver disables the pcie master on the
814 * device. The i40e does not...
819 nfp_net_promisc_enable(struct rte_eth_dev *dev)
821 uint32_t new_ctrl, update = 0;
822 struct nfp_net_hw *hw;
824 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
826 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
828 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
829 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
833 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
834 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
838 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
839 update = NFP_NET_CFG_UPDATE_GEN;
842 * DPDK sets promiscuous mode on just after this call assuming
843 * it can not fail ...
845 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
852 nfp_net_promisc_disable(struct rte_eth_dev *dev)
854 uint32_t new_ctrl, update = 0;
855 struct nfp_net_hw *hw;
857 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
859 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
860 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
864 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
865 update = NFP_NET_CFG_UPDATE_GEN;
868 * DPDK sets promiscuous mode off just before this call
869 * assuming it can not fail ...
871 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
878 * return 0 means link status changed, -1 means not changed
880 * Wait to complete is needed as it can take up to 9 seconds to get the Link
884 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
886 struct nfp_net_hw *hw;
887 struct rte_eth_link link, old;
888 uint32_t nn_link_status;
890 static const uint32_t ls_to_ethtool[] = {
891 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
892 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
893 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
894 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
895 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
896 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
897 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
898 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
901 PMD_DRV_LOG(DEBUG, "Link update\n");
903 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
905 memset(&old, 0, sizeof(old));
906 nfp_net_dev_atomic_read_link_status(dev, &old);
908 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
910 memset(&link, 0, sizeof(struct rte_eth_link));
912 if (nn_link_status & NFP_NET_CFG_STS_LINK)
913 link.link_status = ETH_LINK_UP;
915 link.link_duplex = ETH_LINK_FULL_DUPLEX;
917 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
918 NFP_NET_CFG_STS_LINK_RATE_MASK;
920 if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
921 ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
922 (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
923 /* We really do not know the speed wil old firmware */
924 link.link_speed = ETH_SPEED_NUM_NONE;
926 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
927 link.link_speed = ETH_SPEED_NUM_NONE;
929 link.link_speed = ls_to_ethtool[nn_link_status];
932 if (old.link_status != link.link_status) {
933 nfp_net_dev_atomic_write_link_status(dev, &link);
934 if (link.link_status)
935 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
937 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
945 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
948 struct nfp_net_hw *hw;
949 struct rte_eth_stats nfp_dev_stats;
951 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
953 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
955 /* reading per RX ring stats */
956 for (i = 0; i < dev->data->nb_rx_queues; i++) {
957 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
960 nfp_dev_stats.q_ipackets[i] =
961 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
963 nfp_dev_stats.q_ipackets[i] -=
964 hw->eth_stats_base.q_ipackets[i];
966 nfp_dev_stats.q_ibytes[i] =
967 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
969 nfp_dev_stats.q_ibytes[i] -=
970 hw->eth_stats_base.q_ibytes[i];
973 /* reading per TX ring stats */
974 for (i = 0; i < dev->data->nb_tx_queues; i++) {
975 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
978 nfp_dev_stats.q_opackets[i] =
979 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
981 nfp_dev_stats.q_opackets[i] -=
982 hw->eth_stats_base.q_opackets[i];
984 nfp_dev_stats.q_obytes[i] =
985 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
987 nfp_dev_stats.q_obytes[i] -=
988 hw->eth_stats_base.q_obytes[i];
991 nfp_dev_stats.ipackets =
992 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
994 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
996 nfp_dev_stats.ibytes =
997 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
999 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1001 nfp_dev_stats.opackets =
1002 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1004 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1006 nfp_dev_stats.obytes =
1007 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1009 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1011 /* reading general device stats */
1012 nfp_dev_stats.ierrors =
1013 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1015 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1017 nfp_dev_stats.oerrors =
1018 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1020 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1022 /* RX ring mbuf allocation failures */
1023 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1025 nfp_dev_stats.imissed =
1026 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1028 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1031 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1035 nfp_net_stats_reset(struct rte_eth_dev *dev)
1038 struct nfp_net_hw *hw;
1040 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043 * hw->eth_stats_base records the per counter starting point.
1044 * Lets update it now
1047 /* reading per RX ring stats */
1048 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1049 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1052 hw->eth_stats_base.q_ipackets[i] =
1053 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1055 hw->eth_stats_base.q_ibytes[i] =
1056 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1059 /* reading per TX ring stats */
1060 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1061 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1064 hw->eth_stats_base.q_opackets[i] =
1065 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1067 hw->eth_stats_base.q_obytes[i] =
1068 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1071 hw->eth_stats_base.ipackets =
1072 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1074 hw->eth_stats_base.ibytes =
1075 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1077 hw->eth_stats_base.opackets =
1078 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1080 hw->eth_stats_base.obytes =
1081 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1083 /* reading general device stats */
1084 hw->eth_stats_base.ierrors =
1085 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1087 hw->eth_stats_base.oerrors =
1088 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1090 /* RX ring mbuf allocation failures */
1091 dev->data->rx_mbuf_alloc_failed = 0;
1093 hw->eth_stats_base.imissed =
1094 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1098 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1100 struct nfp_net_hw *hw;
1102 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1104 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1105 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1106 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1107 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1108 dev_info->max_rx_pktlen = hw->mtu;
1109 /* Next should change when PF support is implemented */
1110 dev_info->max_mac_addrs = 1;
1112 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1113 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1115 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1116 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1117 DEV_RX_OFFLOAD_UDP_CKSUM |
1118 DEV_RX_OFFLOAD_TCP_CKSUM;
1120 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1121 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1123 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1124 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1125 DEV_TX_OFFLOAD_UDP_CKSUM |
1126 DEV_TX_OFFLOAD_TCP_CKSUM;
1128 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1130 .pthresh = DEFAULT_RX_PTHRESH,
1131 .hthresh = DEFAULT_RX_HTHRESH,
1132 .wthresh = DEFAULT_RX_WTHRESH,
1134 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1138 dev_info->default_txconf = (struct rte_eth_txconf) {
1140 .pthresh = DEFAULT_TX_PTHRESH,
1141 .hthresh = DEFAULT_TX_HTHRESH,
1142 .wthresh = DEFAULT_TX_WTHRESH,
1144 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1145 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1146 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1147 ETH_TXQ_FLAGS_NOOFFLOADS,
1150 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1151 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1153 dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1154 ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1155 ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1157 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1158 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1161 static const uint32_t *
1162 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1164 static const uint32_t ptypes[] = {
1165 /* refers to nfp_net_set_hash() */
1166 RTE_PTYPE_INNER_L3_IPV4,
1167 RTE_PTYPE_INNER_L3_IPV6,
1168 RTE_PTYPE_INNER_L3_IPV6_EXT,
1169 RTE_PTYPE_INNER_L4_MASK,
1173 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1179 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1181 struct nfp_net_rxq *rxq;
1182 struct nfp_net_rx_desc *rxds;
1186 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1193 * Other PMDs are just checking the DD bit in intervals of 4
1194 * descriptors and counting all four if the first has the DD
1195 * bit on. Of course, this is not accurate but can be good for
1196 * perfomance. But ideally that should be done in descriptors
1197 * chunks belonging to the same cache line
1200 while (count < rxq->rx_count) {
1201 rxds = &rxq->rxds[idx];
1202 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1209 if ((idx) == rxq->rx_count)
1217 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1219 struct rte_pci_device *pci_dev;
1220 struct nfp_net_hw *hw;
1223 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224 pci_dev = RTE_DEV_TO_PCI(dev->device);
1226 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1229 /* Make sure all updates are written before un-masking */
1231 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1232 NFP_NET_CFG_ICR_UNMASKED);
1237 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1239 struct rte_pci_device *pci_dev;
1240 struct nfp_net_hw *hw;
1243 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1244 pci_dev = RTE_DEV_TO_PCI(dev->device);
1246 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1249 /* Make sure all updates are written before un-masking */
1251 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1256 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1258 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1259 struct rte_eth_link link;
1261 memset(&link, 0, sizeof(link));
1262 nfp_net_dev_atomic_read_link_status(dev, &link);
1263 if (link.link_status)
1264 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1265 (int)(dev->data->port_id), (unsigned)link.link_speed,
1266 link.link_duplex == ETH_LINK_FULL_DUPLEX
1267 ? "full-duplex" : "half-duplex");
1269 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1270 (int)(dev->data->port_id));
1272 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1273 pci_dev->addr.domain, pci_dev->addr.bus,
1274 pci_dev->addr.devid, pci_dev->addr.function);
1277 /* Interrupt configuration and handling */
1280 * nfp_net_irq_unmask - Unmask an interrupt
1282 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1283 * clear the ICR for the entry.
1286 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1288 struct nfp_net_hw *hw;
1289 struct rte_pci_device *pci_dev;
1291 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1292 pci_dev = RTE_DEV_TO_PCI(dev->device);
1294 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1295 /* If MSI-X auto-masking is used, clear the entry */
1297 rte_intr_enable(&pci_dev->intr_handle);
1299 /* Make sure all updates are written before un-masking */
1301 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1302 NFP_NET_CFG_ICR_UNMASKED);
1307 nfp_net_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1311 struct rte_eth_link link;
1312 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1314 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1316 /* get the link status */
1317 memset(&link, 0, sizeof(link));
1318 nfp_net_dev_atomic_read_link_status(dev, &link);
1320 nfp_net_link_update(dev, 0);
1323 if (!link.link_status) {
1324 /* handle it 1 sec later, wait it being stable */
1325 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1326 /* likely to down */
1328 /* handle it 4 sec later, wait it being stable */
1329 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1332 if (rte_eal_alarm_set(timeout * 1000,
1333 nfp_net_dev_interrupt_delayed_handler,
1335 RTE_LOG(ERR, PMD, "Error setting alarm");
1337 nfp_net_irq_unmask(dev);
1342 * Interrupt handler which shall be registered for alarm callback for delayed
1343 * handling specific interrupt to wait for the stable nic state. As the NIC
1344 * interrupt state is not stable for nfp after link is just down, it needs
1345 * to wait 4 seconds to get the stable status.
1347 * @param handle Pointer to interrupt handle.
1348 * @param param The address of parameter (struct rte_eth_dev *)
1353 nfp_net_dev_interrupt_delayed_handler(void *param)
1355 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1357 nfp_net_link_update(dev, 0);
1358 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1360 nfp_net_dev_link_status_print(dev);
1363 nfp_net_irq_unmask(dev);
1367 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1369 struct nfp_net_hw *hw;
1371 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1373 /* check that mtu is within the allowed range */
1374 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1377 /* switch to jumbo mode if needed */
1378 if ((uint32_t)mtu > ETHER_MAX_LEN)
1379 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1381 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1383 /* update max frame size */
1384 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1386 /* writing to configuration space */
1387 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1395 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1396 uint16_t queue_idx, uint16_t nb_desc,
1397 unsigned int socket_id,
1398 const struct rte_eth_rxconf *rx_conf,
1399 struct rte_mempool *mp)
1401 const struct rte_memzone *tz;
1402 struct nfp_net_rxq *rxq;
1403 struct nfp_net_hw *hw;
1405 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1407 PMD_INIT_FUNC_TRACE();
1409 /* Validating number of descriptors */
1410 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1411 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1412 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1413 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1418 * Free memory prior to re-allocation if needed. This is the case after
1419 * calling nfp_net_stop
1421 if (dev->data->rx_queues[queue_idx]) {
1422 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1423 dev->data->rx_queues[queue_idx] = NULL;
1426 /* Allocating rx queue data structure */
1427 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1428 RTE_CACHE_LINE_SIZE, socket_id);
1432 /* Hw queues mapping based on firmware confifguration */
1433 rxq->qidx = queue_idx;
1434 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1435 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1436 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1437 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1440 * Tracking mbuf size for detecting a potential mbuf overflow due to
1444 rxq->mbuf_size = rxq->mem_pool->elt_size;
1445 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1446 hw->flbufsz = rxq->mbuf_size;
1448 rxq->rx_count = nb_desc;
1449 rxq->port_id = dev->data->port_id;
1450 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1451 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1453 rxq->drop_en = rx_conf->rx_drop_en;
1456 * Allocate RX ring hardware descriptors. A memzone large enough to
1457 * handle the maximum ring size is allocated in order to allow for
1458 * resizing in later calls to the queue setup function.
1460 tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1461 sizeof(struct nfp_net_rx_desc) *
1462 NFP_NET_MAX_RX_DESC, socket_id);
1465 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1466 nfp_net_rx_queue_release(rxq);
1470 /* Saving physical and virtual addresses for the RX ring */
1471 rxq->dma = (uint64_t)tz->phys_addr;
1472 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1474 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1475 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1476 sizeof(*rxq->rxbufs) * nb_desc,
1477 RTE_CACHE_LINE_SIZE, socket_id);
1478 if (rxq->rxbufs == NULL) {
1479 nfp_net_rx_queue_release(rxq);
1483 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1484 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1486 nfp_net_reset_rx_queue(rxq);
1488 dev->data->rx_queues[queue_idx] = rxq;
1492 * Telling the HW about the physical address of the RX ring and number
1493 * of descriptors in log2 format
1495 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1496 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1502 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1504 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1508 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1511 for (i = 0; i < rxq->rx_count; i++) {
1512 struct nfp_net_rx_desc *rxd;
1513 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1516 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1517 (unsigned)rxq->qidx);
1521 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1523 rxd = &rxq->rxds[i];
1525 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1526 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1528 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1531 /* Make sure all writes are flushed before telling the hardware */
1534 /* Not advertising the whole ring as the firmware gets confused if so */
1535 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1538 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1544 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1545 uint16_t nb_desc, unsigned int socket_id,
1546 const struct rte_eth_txconf *tx_conf)
1548 const struct rte_memzone *tz;
1549 struct nfp_net_txq *txq;
1550 uint16_t tx_free_thresh;
1551 struct nfp_net_hw *hw;
1553 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555 PMD_INIT_FUNC_TRACE();
1557 /* Validating number of descriptors */
1558 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1559 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1560 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1561 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1565 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1566 tx_conf->tx_free_thresh :
1567 DEFAULT_TX_FREE_THRESH);
1569 if (tx_free_thresh > (nb_desc)) {
1571 "tx_free_thresh must be less than the number of TX "
1572 "descriptors. (tx_free_thresh=%u port=%d "
1573 "queue=%d)\n", (unsigned int)tx_free_thresh,
1574 (int)dev->data->port_id, (int)queue_idx);
1579 * Free memory prior to re-allocation if needed. This is the case after
1580 * calling nfp_net_stop
1582 if (dev->data->tx_queues[queue_idx]) {
1583 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1585 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1586 dev->data->tx_queues[queue_idx] = NULL;
1589 /* Allocating tx queue data structure */
1590 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1591 RTE_CACHE_LINE_SIZE, socket_id);
1593 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1598 * Allocate TX ring hardware descriptors. A memzone large enough to
1599 * handle the maximum ring size is allocated in order to allow for
1600 * resizing in later calls to the queue setup function.
1602 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1603 sizeof(struct nfp_net_tx_desc) *
1604 NFP_NET_MAX_TX_DESC, socket_id);
1606 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1607 nfp_net_tx_queue_release(txq);
1611 txq->tx_count = nb_desc;
1612 txq->tx_free_thresh = tx_free_thresh;
1613 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1614 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1615 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1617 /* queue mapping based on firmware configuration */
1618 txq->qidx = queue_idx;
1619 txq->tx_qcidx = queue_idx * hw->stride_tx;
1620 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1622 txq->port_id = dev->data->port_id;
1623 txq->txq_flags = tx_conf->txq_flags;
1625 /* Saving physical and virtual addresses for the TX ring */
1626 txq->dma = (uint64_t)tz->phys_addr;
1627 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1629 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1630 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1631 sizeof(*txq->txbufs) * nb_desc,
1632 RTE_CACHE_LINE_SIZE, socket_id);
1633 if (txq->txbufs == NULL) {
1634 nfp_net_tx_queue_release(txq);
1637 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1638 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1640 nfp_net_reset_tx_queue(txq);
1642 dev->data->tx_queues[queue_idx] = txq;
1646 * Telling the HW about the physical address of the TX ring and number
1647 * of descriptors in log2 format
1649 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1650 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1655 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1657 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1658 struct rte_mbuf *mb)
1661 struct nfp_net_hw *hw = txq->hw;
1663 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1666 ol_flags = mb->ol_flags;
1668 if (!(ol_flags & PKT_TX_TCP_SEG))
1671 txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1672 txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1673 txd->flags = PCIE_DESC_TX_LSO;
1682 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1684 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1685 struct rte_mbuf *mb)
1688 struct nfp_net_hw *hw = txq->hw;
1690 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1693 ol_flags = mb->ol_flags;
1695 /* IPv6 does not need checksum */
1696 if (ol_flags & PKT_TX_IP_CKSUM)
1697 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1699 switch (ol_flags & PKT_TX_L4_MASK) {
1700 case PKT_TX_UDP_CKSUM:
1701 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1703 case PKT_TX_TCP_CKSUM:
1704 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1708 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1709 txd->flags |= PCIE_DESC_TX_CSUM;
1712 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1714 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1715 struct rte_mbuf *mb)
1717 struct nfp_net_hw *hw = rxq->hw;
1719 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1722 /* If IPv4 and IP checksum error, fail */
1723 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1724 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1725 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1727 /* If neither UDP nor TCP return */
1728 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1729 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1732 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1733 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1734 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1736 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1737 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1738 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1741 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1742 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1745 * nfp_net_set_hash - Set mbuf hash data
1747 * The RSS hash and hash-type are pre-pended to the packet data.
1748 * Extract and decode it and set the mbuf fields.
1751 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1752 struct rte_mbuf *mbuf)
1756 struct nfp_net_hw *hw = rxq->hw;
1758 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1761 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1764 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1765 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1767 mbuf->hash.rss = hash;
1768 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1770 switch (hash_type) {
1771 case NFP_NET_RSS_IPV4:
1772 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1774 case NFP_NET_RSS_IPV6:
1775 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1777 case NFP_NET_RSS_IPV6_EX:
1778 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1781 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1786 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1788 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1791 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1796 * There are some decissions to take:
1797 * 1) How to check DD RX descriptors bit
1798 * 2) How and when to allocate new mbufs
1800 * Current implementation checks just one single DD bit each loop. As each
1801 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1802 * a single cache line instead. Tests with this change have not shown any
1803 * performance improvement but it requires further investigation. For example,
1804 * depending on which descriptor is next, the number of descriptors could be
1805 * less than 8 for just checking those in the same cache line. This implies
1806 * extra work which could be counterproductive by itself. Indeed, last firmware
1807 * changes are just doing this: writing several descriptors with the DD bit
1808 * for saving PCIe bandwidth and DMA operations from the NFP.
1810 * Mbuf allocation is done when a new packet is received. Then the descriptor
1811 * is automatically linked with the new mbuf and the old one is given to the
1812 * user. The main drawback with this design is mbuf allocation is heavier than
1813 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1814 * cache point of view it does not seem allocating the mbuf early on as we are
1815 * doing now have any benefit at all. Again, tests with this change have not
1816 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1817 * so looking at the implications of this type of allocation should be studied
1822 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1824 struct nfp_net_rxq *rxq;
1825 struct nfp_net_rx_desc *rxds;
1826 struct nfp_net_rx_buff *rxb;
1827 struct nfp_net_hw *hw;
1828 struct rte_mbuf *mb;
1829 struct rte_mbuf *new_mb;
1835 if (unlikely(rxq == NULL)) {
1837 * DPDK just checks the queue is lower than max queues
1838 * enabled. But the queue needs to be configured
1840 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1848 while (avail < nb_pkts) {
1849 rxb = &rxq->rxbufs[rxq->rd_p];
1850 if (unlikely(rxb == NULL)) {
1851 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1856 * Memory barrier to ensure that we won't do other
1857 * reads before the DD bit.
1861 rxds = &rxq->rxds[rxq->rd_p];
1862 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1866 * We got a packet. Let's alloc a new mbuff for refilling the
1867 * free descriptor ring as soon as possible
1869 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1870 if (unlikely(new_mb == NULL)) {
1871 RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1872 "queue_id=%u\n", (unsigned)rxq->port_id,
1873 (unsigned)rxq->qidx);
1874 nfp_net_mbuf_alloc_failed(rxq);
1881 * Grab the mbuff and refill the descriptor with the
1882 * previously allocated mbuff
1887 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1888 rxds->rxd.data_len, rxq->mbuf_size);
1890 /* Size of this segment */
1891 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1892 /* Size of the whole packet. We just support 1 segment */
1893 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1895 if (unlikely((mb->data_len + hw->rx_offset) >
1898 * This should not happen and the user has the
1899 * responsibility of avoiding it. But we have
1900 * to give some info about the error
1902 RTE_LOG_DP(ERR, PMD,
1903 "mbuf overflow likely due to the RX offset.\n"
1904 "\t\tYour mbuf size should have extra space for"
1905 " RX offset=%u bytes.\n"
1906 "\t\tCurrently you just have %u bytes available"
1907 " but the received packet is %u bytes long",
1909 rxq->mbuf_size - hw->rx_offset,
1914 /* Filling the received mbuff with packet info */
1916 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1918 mb->data_off = RTE_PKTMBUF_HEADROOM +
1919 NFP_DESC_META_LEN(rxds);
1921 /* No scatter mode supported */
1925 /* Checking the RSS flag */
1926 nfp_net_set_hash(rxq, rxds, mb);
1928 /* Checking the checksum flag */
1929 nfp_net_rx_cksum(rxq, rxds, mb);
1931 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1932 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1933 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1934 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1937 /* Adding the mbuff to the mbuff array passed by the app */
1938 rx_pkts[avail++] = mb;
1940 /* Now resetting and updating the descriptor */
1943 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1945 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1946 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1949 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
1956 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1957 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1959 nb_hold += rxq->nb_rx_hold;
1962 * FL descriptors needs to be written before incrementing the
1963 * FL queue WR pointer
1966 if (nb_hold > rxq->rx_free_thresh) {
1967 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1968 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1969 (unsigned)nb_hold, (unsigned)avail);
1970 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1973 rxq->nb_rx_hold = nb_hold;
1979 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1981 * @txq: TX queue to work with
1982 * Returns number of descriptors freed
1985 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1990 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1991 " status\n", txq->qidx);
1993 /* Work out how many packets have been sent */
1994 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1996 if (qcp_rd_p == txq->rd_p) {
1997 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1998 "packets (%u, %u)\n", txq->qidx,
1999 qcp_rd_p, txq->rd_p);
2003 if (qcp_rd_p > txq->rd_p)
2004 todo = qcp_rd_p - txq->rd_p;
2006 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2008 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2009 qcp_rd_p, txq->rd_p, txq->rd_p);
2015 if (unlikely(txq->rd_p >= txq->tx_count))
2016 txq->rd_p -= txq->tx_count;
2021 /* Leaving always free descriptors for avoiding wrapping confusion */
2023 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2025 if (txq->wr_p >= txq->rd_p)
2026 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2028 return txq->rd_p - txq->wr_p - 8;
2032 * nfp_net_txq_full - Check if the TX queue free descriptors
2033 * is below tx_free_threshold
2035 * @txq: TX queue to check
2037 * This function uses the host copy* of read/write pointers
2040 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2042 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2046 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2048 struct nfp_net_txq *txq;
2049 struct nfp_net_hw *hw;
2050 struct nfp_net_tx_desc *txds, txd;
2051 struct rte_mbuf *pkt;
2053 int pkt_size, dma_size;
2054 uint16_t free_descs, issued_descs;
2055 struct rte_mbuf **lmbuf;
2060 txds = &txq->txds[txq->wr_p];
2062 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2063 txq->qidx, txq->wr_p, nb_pkts);
2065 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2066 nfp_net_tx_free_bufs(txq);
2068 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2069 if (unlikely(free_descs == 0))
2076 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2077 txq->qidx, nb_pkts);
2078 /* Sending packets */
2079 while ((i < nb_pkts) && free_descs) {
2080 /* Grabbing the mbuf linked to the current descriptor */
2081 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2082 /* Warming the cache for releasing the mbuf later on */
2083 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2085 pkt = *(tx_pkts + i);
2087 if (unlikely((pkt->nb_segs > 1) &&
2088 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2089 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2090 rte_panic("Multisegment packet unsupported\n");
2093 /* Checking if we have enough descriptors */
2094 if (unlikely(pkt->nb_segs > free_descs))
2098 * Checksum and VLAN flags just in the first descriptor for a
2099 * multisegment packet, but TSO info needs to be in all of them.
2101 txd.data_len = pkt->pkt_len;
2102 nfp_net_tx_tso(txq, &txd, pkt);
2103 nfp_net_tx_cksum(txq, &txd, pkt);
2105 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2106 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2107 txd.flags |= PCIE_DESC_TX_VLAN;
2108 txd.vlan = pkt->vlan_tci;
2112 * mbuf data_len is the data in one segment and pkt_len data
2113 * in the whole packet. When the packet is just one segment,
2114 * then data_len = pkt_len
2116 pkt_size = pkt->pkt_len;
2118 /* Releasing mbuf which was prefetched above */
2120 rte_pktmbuf_free(*lmbuf);
2122 * Linking mbuf with descriptor for being released
2123 * next time descriptor is used
2128 /* Copying TSO, VLAN and cksum info */
2130 dma_size = pkt->data_len;
2131 dma_addr = rte_mbuf_data_dma_addr(pkt);
2132 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2133 "%" PRIx64 "\n", dma_addr);
2135 /* Filling descriptors fields */
2136 txds->dma_len = dma_size;
2137 txds->data_len = txd.data_len;
2138 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2139 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2140 ASSERT(free_descs > 0);
2144 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2147 pkt_size -= dma_size;
2150 txds->offset_eop |= PCIE_DESC_TX_EOP;
2152 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2155 /* Referencing next free TX descriptor */
2156 txds = &txq->txds[txq->wr_p];
2163 /* Increment write pointers. Force memory write before we let HW know */
2165 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2171 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2173 uint32_t new_ctrl, update;
2174 struct nfp_net_hw *hw;
2176 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2179 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2180 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2181 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2182 " ETH_VLAN_EXTEND_OFFLOAD");
2184 /* Enable vlan strip if it is not configured yet */
2185 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2186 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2187 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2189 /* Disable vlan strip just if it is configured */
2190 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2191 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2192 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2197 update = NFP_NET_CFG_UPDATE_GEN;
2199 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2202 hw->ctrl = new_ctrl;
2205 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2207 nfp_net_reta_update(struct rte_eth_dev *dev,
2208 struct rte_eth_rss_reta_entry64 *reta_conf,
2211 uint32_t reta, mask;
2215 struct nfp_net_hw *hw =
2216 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2218 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2221 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2222 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2223 "(%d) doesn't match the number hardware can supported "
2224 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2229 * Update Redirection Table. There are 128 8bit-entries which can be
2230 * manage as 32 32bit-entries
2232 for (i = 0; i < reta_size; i += 4) {
2233 /* Handling 4 RSS entries per loop */
2234 idx = i / RTE_RETA_GROUP_SIZE;
2235 shift = i % RTE_RETA_GROUP_SIZE;
2236 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2242 /* If all 4 entries were set, don't need read RETA register */
2244 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2246 for (j = 0; j < 4; j++) {
2247 if (!(mask & (0x1 << j)))
2250 /* Clearing the entry bits */
2251 reta &= ~(0xFF << (8 * j));
2252 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2254 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2257 update = NFP_NET_CFG_UPDATE_RSS;
2259 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2265 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2267 nfp_net_reta_query(struct rte_eth_dev *dev,
2268 struct rte_eth_rss_reta_entry64 *reta_conf,
2274 struct nfp_net_hw *hw;
2276 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2278 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2281 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2282 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2283 "(%d) doesn't match the number hardware can supported "
2284 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2289 * Reading Redirection Table. There are 128 8bit-entries which can be
2290 * manage as 32 32bit-entries
2292 for (i = 0; i < reta_size; i += 4) {
2293 /* Handling 4 RSS entries per loop */
2294 idx = i / RTE_RETA_GROUP_SIZE;
2295 shift = i % RTE_RETA_GROUP_SIZE;
2296 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2301 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2302 for (j = 0; j < 4; j++) {
2303 if (!(mask & (0x1 << j)))
2305 reta_conf->reta[shift + j] =
2306 (uint8_t)((reta >> (8 * j)) & 0xF);
2313 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2314 struct rte_eth_rss_conf *rss_conf)
2317 uint32_t cfg_rss_ctrl = 0;
2321 struct nfp_net_hw *hw;
2323 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2325 rss_hf = rss_conf->rss_hf;
2327 /* Checking if RSS is enabled */
2328 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2329 if (rss_hf != 0) { /* Enable RSS? */
2330 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2333 return 0; /* Nothing to do */
2336 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2337 RTE_LOG(ERR, PMD, "hash key too long\n");
2341 if (rss_hf & ETH_RSS_IPV4)
2342 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2343 NFP_NET_CFG_RSS_IPV4_TCP |
2344 NFP_NET_CFG_RSS_IPV4_UDP;
2346 if (rss_hf & ETH_RSS_IPV6)
2347 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2348 NFP_NET_CFG_RSS_IPV6_TCP |
2349 NFP_NET_CFG_RSS_IPV6_UDP;
2351 /* configuring where to apply the RSS hash */
2352 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2354 /* Writing the key byte a byte */
2355 for (i = 0; i < rss_conf->rss_key_len; i++) {
2356 memcpy(&key, &rss_conf->rss_key[i], 1);
2357 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2360 /* Writing the key size */
2361 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2363 update = NFP_NET_CFG_UPDATE_RSS;
2365 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2372 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2373 struct rte_eth_rss_conf *rss_conf)
2376 uint32_t cfg_rss_ctrl;
2379 struct nfp_net_hw *hw;
2381 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2383 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2386 rss_hf = rss_conf->rss_hf;
2387 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2389 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2390 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2392 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2393 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2395 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2396 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2398 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2399 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2401 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2402 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2404 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2405 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2407 /* Reading the key size */
2408 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2410 /* Reading the key byte a byte */
2411 for (i = 0; i < rss_conf->rss_key_len; i++) {
2412 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2413 memcpy(&rss_conf->rss_key[i], &key, 1);
2419 /* Initialise and register driver with DPDK Application */
2420 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2421 .dev_configure = nfp_net_configure,
2422 .dev_start = nfp_net_start,
2423 .dev_stop = nfp_net_stop,
2424 .dev_close = nfp_net_close,
2425 .promiscuous_enable = nfp_net_promisc_enable,
2426 .promiscuous_disable = nfp_net_promisc_disable,
2427 .link_update = nfp_net_link_update,
2428 .stats_get = nfp_net_stats_get,
2429 .stats_reset = nfp_net_stats_reset,
2430 .dev_infos_get = nfp_net_infos_get,
2431 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2432 .mtu_set = nfp_net_dev_mtu_set,
2433 .vlan_offload_set = nfp_net_vlan_offload_set,
2434 .reta_update = nfp_net_reta_update,
2435 .reta_query = nfp_net_reta_query,
2436 .rss_hash_update = nfp_net_rss_hash_update,
2437 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2438 .rx_queue_setup = nfp_net_rx_queue_setup,
2439 .rx_queue_release = nfp_net_rx_queue_release,
2440 .rx_queue_count = nfp_net_rx_queue_count,
2441 .tx_queue_setup = nfp_net_tx_queue_setup,
2442 .tx_queue_release = nfp_net_tx_queue_release,
2443 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2444 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2448 nfp_net_init(struct rte_eth_dev *eth_dev)
2450 struct rte_pci_device *pci_dev;
2451 struct nfp_net_hw *hw;
2453 uint32_t tx_bar_off, rx_bar_off;
2457 PMD_INIT_FUNC_TRACE();
2459 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2461 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2462 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2463 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2465 /* For secondary processes, the primary has done all the work */
2466 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2469 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2470 rte_eth_copy_pci_info(eth_dev, pci_dev);
2471 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2473 hw->device_id = pci_dev->id.device_id;
2474 hw->vendor_id = pci_dev->id.vendor_id;
2475 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2476 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2478 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2479 pci_dev->id.vendor_id, pci_dev->id.device_id,
2480 pci_dev->addr.domain, pci_dev->addr.bus,
2481 pci_dev->addr.devid, pci_dev->addr.function);
2483 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2484 if (hw->ctrl_bar == NULL) {
2486 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2489 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2490 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2492 /* Work out where in the BAR the queues start. */
2493 switch (pci_dev->id.device_id) {
2494 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2495 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2496 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2497 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2498 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2501 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2505 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x", tx_bar_off);
2506 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x", rx_bar_off);
2508 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2509 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2511 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2512 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2514 nfp_net_cfg_queue_setup(hw);
2516 /* Get some of the read-only fields from the config BAR */
2517 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2518 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2519 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2520 hw->mtu = hw->max_mtu;
2522 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2523 hw->rx_offset = NFP_NET_RX_OFFSET;
2525 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2527 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2528 hw->ver, hw->max_mtu);
2529 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
2530 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2531 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2532 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2533 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2534 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2535 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2536 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2537 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2538 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2542 hw->stride_rx = stride;
2543 hw->stride_tx = stride;
2545 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2546 hw->max_rx_queues, hw->max_tx_queues);
2548 /* Initializing spinlock for reconfigs */
2549 rte_spinlock_init(&hw->reconfig_lock);
2551 /* Allocating memory for mac addr */
2552 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2553 if (eth_dev->data->mac_addrs == NULL) {
2554 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2558 nfp_net_read_mac(hw);
2560 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr))
2561 /* Using random mac addresses for VFs */
2562 eth_random_addr(&hw->mac_addr[0]);
2564 /* Copying mac address to DPDK eth_dev struct */
2565 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2566 ð_dev->data->mac_addrs[0]);
2568 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2569 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2570 eth_dev->data->port_id, pci_dev->id.vendor_id,
2571 pci_dev->id.device_id,
2572 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2573 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2575 /* Registering LSC interrupt handler */
2576 rte_intr_callback_register(&pci_dev->intr_handle,
2577 nfp_net_dev_interrupt_handler,
2580 /* Telling the firmware about the LSC interrupt entry */
2581 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2583 /* Recording current stats counters values */
2584 nfp_net_stats_reset(eth_dev);
2589 static const struct rte_pci_id pci_id_nfp_net_map[] = {
2591 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2592 PCI_DEVICE_ID_NFP6000_PF_NIC)
2595 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2596 PCI_DEVICE_ID_NFP6000_VF_NIC)
2603 static struct eth_driver rte_nfp_net_pmd = {
2605 .id_table = pci_id_nfp_net_map,
2606 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2607 .probe = rte_eth_dev_pci_probe,
2608 .remove = rte_eth_dev_pci_remove,
2610 .eth_dev_init = nfp_net_init,
2611 .dev_private_size = sizeof(struct nfp_net_adapter),
2614 RTE_PMD_REGISTER_PCI(net_nfp, rte_nfp_net_pmd.pci_drv);
2615 RTE_PMD_REGISTER_PCI_TABLE(net_nfp, pci_id_nfp_net_map);
2616 RTE_PMD_REGISTER_KMOD_DEP(net_nfp, "* igb_uio | uio_pci_generic | vfio");
2620 * c-file-style: "Linux"
2621 * indent-tabs-mode: t