1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
9 * vim:shiftwidth=8:noexpandtab
11 * @file dpdk/pmd/nfp_net.c
13 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
19 #include <rte_debug.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
23 #include <rte_ether.h>
24 #include <rte_malloc.h>
25 #include <rte_memzone.h>
26 #include <rte_mempool.h>
27 #include <rte_version.h>
28 #include <rte_string_fns.h>
29 #include <rte_alarm.h>
30 #include <rte_spinlock.h>
31 #include <rte_service_component.h>
33 #include "eal_firmware.h"
35 #include "nfpcore/nfp_cpp.h"
36 #include "nfpcore/nfp_nffw.h"
37 #include "nfpcore/nfp_hwinfo.h"
38 #include "nfpcore/nfp_mip.h"
39 #include "nfpcore/nfp_rtsym.h"
40 #include "nfpcore/nfp_nsp.h"
42 #include "nfp_net_pmd.h"
43 #include "nfp_net_logs.h"
44 #include "nfp_net_ctrl.h"
46 #include <sys/types.h>
47 #include <sys/socket.h>
51 #include <sys/ioctl.h>
55 static int nfp_net_close(struct rte_eth_dev *dev);
56 static int nfp_net_configure(struct rte_eth_dev *dev);
57 static void nfp_net_dev_interrupt_handler(void *param);
58 static void nfp_net_dev_interrupt_delayed_handler(void *param);
59 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
60 static int nfp_net_infos_get(struct rte_eth_dev *dev,
61 struct rte_eth_dev_info *dev_info);
62 static int nfp_net_init(struct rte_eth_dev *eth_dev);
63 static int nfp_pf_init(struct rte_pci_device *pci_dev);
64 static int nfp_pf_secondary_init(struct rte_pci_device *pci_dev);
65 static int nfp_pci_uninit(struct rte_eth_dev *eth_dev);
66 static int nfp_init_phyports(struct nfp_pf_dev *pf_dev);
67 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
68 static int nfp_net_promisc_enable(struct rte_eth_dev *dev);
69 static int nfp_net_promisc_disable(struct rte_eth_dev *dev);
70 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
71 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
73 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
75 static void nfp_net_rx_queue_release(void *rxq);
76 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
77 uint16_t nb_desc, unsigned int socket_id,
78 const struct rte_eth_rxconf *rx_conf,
79 struct rte_mempool *mp);
80 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
81 static void nfp_net_tx_queue_release(void *txq);
82 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
83 uint16_t nb_desc, unsigned int socket_id,
84 const struct rte_eth_txconf *tx_conf);
85 static int nfp_net_start(struct rte_eth_dev *dev);
86 static int nfp_net_stats_get(struct rte_eth_dev *dev,
87 struct rte_eth_stats *stats);
88 static int nfp_net_stats_reset(struct rte_eth_dev *dev);
89 static int nfp_net_stop(struct rte_eth_dev *dev);
90 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
93 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
94 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
95 struct rte_eth_rss_conf *rss_conf);
96 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
97 struct rte_eth_rss_reta_entry64 *reta_conf,
99 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
100 struct rte_eth_rss_conf *rss_conf);
101 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
102 struct rte_ether_addr *mac_addr);
103 static int32_t nfp_cpp_bridge_service_func(void *args);
104 static void nfp_register_cpp_service(struct nfp_cpp *cpp);
105 static int nfp_fw_setup(struct rte_pci_device *dev,
107 struct nfp_eth_table *nfp_eth_table,
108 struct nfp_hwinfo *hwinfo);
111 /* The offset of the queue controller queues in the PCIe Target */
112 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
114 /* Maximum value which can be added to a queue with one transaction */
115 #define NFP_QCP_MAX_ADD 0x7f
117 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
118 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
120 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
122 NFP_QCP_READ_PTR = 0,
127 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
128 * @q: Base address for queue structure
129 * @ptr: Add to the Read or Write pointer
130 * @val: Value to add to the queue pointer
132 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
135 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
139 if (ptr == NFP_QCP_READ_PTR)
140 off = NFP_QCP_QUEUE_ADD_RPTR;
142 off = NFP_QCP_QUEUE_ADD_WPTR;
144 while (val > NFP_QCP_MAX_ADD) {
145 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
146 val -= NFP_QCP_MAX_ADD;
149 nn_writel(rte_cpu_to_le_32(val), q + off);
153 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
154 * @q: Base address for queue structure
155 * @ptr: Read or Write pointer
157 static inline uint32_t
158 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
163 if (ptr == NFP_QCP_READ_PTR)
164 off = NFP_QCP_QUEUE_STS_LO;
166 off = NFP_QCP_QUEUE_STS_HI;
168 val = rte_cpu_to_le_32(nn_readl(q + off));
170 if (ptr == NFP_QCP_READ_PTR)
171 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
173 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
177 * Functions to read/write from/to Config BAR
178 * Performs any endian conversion necessary.
180 static inline uint8_t
181 nn_cfg_readb(struct nfp_net_hw *hw, int off)
183 return nn_readb(hw->ctrl_bar + off);
187 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
189 nn_writeb(val, hw->ctrl_bar + off);
192 static inline uint32_t
193 nn_cfg_readl(struct nfp_net_hw *hw, int off)
195 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
199 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
201 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
204 static inline uint64_t
205 nn_cfg_readq(struct nfp_net_hw *hw, int off)
207 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
211 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
213 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
217 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
221 if (rxq->rxbufs == NULL)
224 for (i = 0; i < rxq->rx_count; i++) {
225 if (rxq->rxbufs[i].mbuf) {
226 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
227 rxq->rxbufs[i].mbuf = NULL;
233 nfp_net_rx_queue_release(void *rx_queue)
235 struct nfp_net_rxq *rxq = rx_queue;
238 nfp_net_rx_queue_release_mbufs(rxq);
239 rte_free(rxq->rxbufs);
245 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
247 nfp_net_rx_queue_release_mbufs(rxq);
253 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
257 if (txq->txbufs == NULL)
260 for (i = 0; i < txq->tx_count; i++) {
261 if (txq->txbufs[i].mbuf) {
262 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
263 txq->txbufs[i].mbuf = NULL;
269 nfp_net_tx_queue_release(void *tx_queue)
271 struct nfp_net_txq *txq = tx_queue;
274 nfp_net_tx_queue_release_mbufs(txq);
275 rte_free(txq->txbufs);
281 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
283 nfp_net_tx_queue_release_mbufs(txq);
289 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
293 struct timespec wait;
295 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
298 if (hw->qcp_cfg == NULL)
299 rte_panic("Bad configuration queue pointer\n");
301 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
304 wait.tv_nsec = 1000000;
306 PMD_DRV_LOG(DEBUG, "Polling for update ack...");
308 /* Poll update field, waiting for NFP to ack the config */
309 for (cnt = 0; ; cnt++) {
310 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
313 if (new & NFP_NET_CFG_UPDATE_ERR) {
314 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
317 if (cnt >= NFP_NET_POLL_TIMEOUT) {
318 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
319 " %dms", update, cnt);
320 rte_panic("Exiting\n");
322 nanosleep(&wait, 0); /* waiting for a 1ms */
324 PMD_DRV_LOG(DEBUG, "Ack DONE");
329 * Reconfigure the NIC
330 * @nn: device to reconfigure
331 * @ctrl: The value for the ctrl field in the BAR config
332 * @update: The value for the update field in the BAR config
334 * Write the update word to the BAR and ping the reconfig queue. Then poll
335 * until the firmware has acknowledged the update by zeroing the update word.
338 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
342 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
345 rte_spinlock_lock(&hw->reconfig_lock);
347 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
348 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
352 err = __nfp_net_reconfig(hw, update);
354 rte_spinlock_unlock(&hw->reconfig_lock);
360 * Reconfig errors imply situations where they can be handled.
361 * Otherwise, rte_panic is called inside __nfp_net_reconfig
363 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
369 * Configure an Ethernet device. This function must be invoked first
370 * before any other function in the Ethernet API. This function can
371 * also be re-invoked when a device is in the stopped state.
374 nfp_net_configure(struct rte_eth_dev *dev)
376 struct rte_eth_conf *dev_conf;
377 struct rte_eth_rxmode *rxmode;
378 struct rte_eth_txmode *txmode;
379 struct nfp_net_hw *hw;
381 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
384 * A DPDK app sends info about how many queues to use and how
385 * those queues need to be configured. This is used by the
386 * DPDK core and it makes sure no more queues than those
387 * advertised by the driver are requested. This function is
388 * called after that internal process
391 PMD_INIT_LOG(DEBUG, "Configure");
393 dev_conf = &dev->data->dev_conf;
394 rxmode = &dev_conf->rxmode;
395 txmode = &dev_conf->txmode;
397 if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
398 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
400 /* Checking TX mode */
401 if (txmode->mq_mode) {
402 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
406 /* Checking RX mode */
407 if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
408 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
409 PMD_INIT_LOG(INFO, "RSS not supported");
417 nfp_net_enable_queues(struct rte_eth_dev *dev)
419 struct nfp_net_hw *hw;
420 uint64_t enabled_queues = 0;
423 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
425 /* Enabling the required TX queues in the device */
426 for (i = 0; i < dev->data->nb_tx_queues; i++)
427 enabled_queues |= (1 << i);
429 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
433 /* Enabling the required RX queues in the device */
434 for (i = 0; i < dev->data->nb_rx_queues; i++)
435 enabled_queues |= (1 << i);
437 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
441 nfp_net_disable_queues(struct rte_eth_dev *dev)
443 struct nfp_net_hw *hw;
444 uint32_t new_ctrl, update = 0;
446 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
448 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
449 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
451 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
452 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
453 NFP_NET_CFG_UPDATE_MSIX;
455 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
456 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
458 /* If an error when reconfig we avoid to change hw state */
459 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
466 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
470 for (i = 0; i < dev->data->nb_rx_queues; i++) {
471 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
478 nfp_net_params_setup(struct nfp_net_hw *hw)
480 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
481 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
485 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
487 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
490 #define ETH_ADDR_LEN 6
493 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
497 for (i = 0; i < ETH_ADDR_LEN; i++)
502 nfp_net_pf_read_mac(struct nfp_pf_dev *pf_dev, int port)
504 struct nfp_eth_table *nfp_eth_table;
505 struct nfp_net_hw *hw = NULL;
507 /* Grab a pointer to the correct physical port */
508 hw = pf_dev->ports[port];
510 nfp_eth_table = nfp_eth_read_ports(pf_dev->cpp);
512 nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
513 (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
520 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
524 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
525 memcpy(&hw->mac_addr[0], &tmp, 4);
527 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
528 memcpy(&hw->mac_addr[4], &tmp, 2);
532 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
534 uint32_t mac0 = *(uint32_t *)mac;
537 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
540 mac1 = *(uint16_t *)mac;
541 nn_writew(rte_cpu_to_be_16(mac1),
542 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
546 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
548 struct nfp_net_hw *hw;
549 uint32_t update, ctrl;
551 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
552 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
553 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
554 PMD_INIT_LOG(INFO, "MAC address unable to change when"
559 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
560 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
563 /* Writing new MAC to the specific port BAR address */
564 nfp_net_write_mac(hw, (uint8_t *)mac_addr);
566 /* Signal the NIC about the change */
567 update = NFP_NET_CFG_UPDATE_MACADDR;
569 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
570 (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
571 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
572 if (nfp_net_reconfig(hw, ctrl, update) < 0) {
573 PMD_INIT_LOG(INFO, "MAC address update failed");
580 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
581 struct rte_intr_handle *intr_handle)
583 struct nfp_net_hw *hw;
586 if (!intr_handle->intr_vec) {
587 intr_handle->intr_vec =
588 rte_zmalloc("intr_vec",
589 dev->data->nb_rx_queues * sizeof(int), 0);
590 if (!intr_handle->intr_vec) {
591 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
592 " intr_vec", dev->data->nb_rx_queues);
597 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
599 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
600 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
601 /* UIO just supports one queue and no LSC*/
602 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
603 intr_handle->intr_vec[0] = 0;
605 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
606 for (i = 0; i < dev->data->nb_rx_queues; i++) {
608 * The first msix vector is reserved for non
611 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
612 intr_handle->intr_vec[i] = i + 1;
613 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
614 intr_handle->intr_vec[i]);
618 /* Avoiding TX interrupts */
619 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
624 nfp_check_offloads(struct rte_eth_dev *dev)
626 struct nfp_net_hw *hw;
627 struct rte_eth_conf *dev_conf;
628 struct rte_eth_rxmode *rxmode;
629 struct rte_eth_txmode *txmode;
632 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
634 dev_conf = &dev->data->dev_conf;
635 rxmode = &dev_conf->rxmode;
636 txmode = &dev_conf->txmode;
638 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
639 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
640 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
643 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
644 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
645 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
648 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
649 hw->mtu = rxmode->max_rx_pkt_len;
651 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
652 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
655 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
656 ctrl |= NFP_NET_CFG_CTRL_L2BC;
659 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
660 ctrl |= NFP_NET_CFG_CTRL_L2MC;
662 /* TX checksum offload */
663 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
664 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
665 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
666 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
669 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
670 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
671 ctrl |= NFP_NET_CFG_CTRL_LSO;
673 ctrl |= NFP_NET_CFG_CTRL_LSO2;
677 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
678 ctrl |= NFP_NET_CFG_CTRL_GATHER;
684 nfp_net_start(struct rte_eth_dev *dev)
686 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
687 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
688 uint32_t new_ctrl, update = 0;
689 struct nfp_net_hw *hw;
690 struct nfp_pf_dev *pf_dev;
691 struct rte_eth_conf *dev_conf;
692 struct rte_eth_rxmode *rxmode;
693 uint32_t intr_vector;
696 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
697 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(dev->data->dev_private);
699 PMD_INIT_LOG(DEBUG, "Start");
701 /* Disabling queues just in case... */
702 nfp_net_disable_queues(dev);
704 /* Enabling the required queues in the device */
705 nfp_net_enable_queues(dev);
707 /* check and configure queue intr-vector mapping */
708 if (dev->data->dev_conf.intr_conf.rxq != 0) {
709 if (pf_dev->multiport) {
710 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
711 "with NFP multiport PF");
714 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
716 * Better not to share LSC with RX interrupts.
717 * Unregistering LSC interrupt handler
719 rte_intr_callback_unregister(&pci_dev->intr_handle,
720 nfp_net_dev_interrupt_handler, (void *)dev);
722 if (dev->data->nb_rx_queues > 1) {
723 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
724 "supports 1 queue with UIO");
728 intr_vector = dev->data->nb_rx_queues;
729 if (rte_intr_efd_enable(intr_handle, intr_vector))
732 nfp_configure_rx_interrupt(dev, intr_handle);
733 update = NFP_NET_CFG_UPDATE_MSIX;
736 rte_intr_enable(intr_handle);
738 new_ctrl = nfp_check_offloads(dev);
740 /* Writing configuration parameters in the device */
741 nfp_net_params_setup(hw);
743 dev_conf = &dev->data->dev_conf;
744 rxmode = &dev_conf->rxmode;
746 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
747 nfp_net_rss_config_default(dev);
748 update |= NFP_NET_CFG_UPDATE_RSS;
749 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
753 new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
755 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
757 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
758 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
760 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
761 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
765 * Allocating rte mbufs for configured rx queues.
766 * This requires queues being enabled before
768 if (nfp_net_rx_freelist_setup(dev) < 0) {
773 if (hw->is_phyport) {
774 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
775 /* Configure the physical port up */
776 nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 1);
778 nfp_eth_set_configured(dev->process_private,
788 * An error returned by this function should mean the app
789 * exiting and then the system releasing all the memory
790 * allocated even memory coming from hugepages.
792 * The device could be enabled at this point with some queues
793 * ready for getting packets. This is true if the call to
794 * nfp_net_rx_freelist_setup() succeeds for some queues but
795 * fails for subsequent queues.
797 * This should make the app exiting but better if we tell the
800 nfp_net_disable_queues(dev);
805 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
807 nfp_net_stop(struct rte_eth_dev *dev)
810 struct nfp_net_hw *hw;
812 PMD_INIT_LOG(DEBUG, "Stop");
814 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
816 nfp_net_disable_queues(dev);
819 for (i = 0; i < dev->data->nb_tx_queues; i++) {
820 nfp_net_reset_tx_queue(
821 (struct nfp_net_txq *)dev->data->tx_queues[i]);
824 for (i = 0; i < dev->data->nb_rx_queues; i++) {
825 nfp_net_reset_rx_queue(
826 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
829 if (hw->is_phyport) {
830 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
831 /* Configure the physical port down */
832 nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 0);
834 nfp_eth_set_configured(dev->process_private,
841 /* Set the link up. */
843 nfp_net_set_link_up(struct rte_eth_dev *dev)
845 struct nfp_net_hw *hw;
847 PMD_DRV_LOG(DEBUG, "Set link up");
849 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
854 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
855 /* Configure the physical port down */
856 return nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 1);
858 return nfp_eth_set_configured(dev->process_private,
862 /* Set the link down. */
864 nfp_net_set_link_down(struct rte_eth_dev *dev)
866 struct nfp_net_hw *hw;
868 PMD_DRV_LOG(DEBUG, "Set link down");
870 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
875 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
876 /* Configure the physical port down */
877 return nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 0);
879 return nfp_eth_set_configured(dev->process_private,
883 /* Reset and stop device. The device can not be restarted. */
885 nfp_net_close(struct rte_eth_dev *dev)
887 struct nfp_net_hw *hw;
888 struct rte_pci_device *pci_dev;
891 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
894 PMD_INIT_LOG(DEBUG, "Close");
896 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
897 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
900 * We assume that the DPDK application is stopping all the
901 * threads/queues before calling the device close function.
904 nfp_net_disable_queues(dev);
907 for (i = 0; i < dev->data->nb_tx_queues; i++) {
908 nfp_net_reset_tx_queue(
909 (struct nfp_net_txq *)dev->data->tx_queues[i]);
912 for (i = 0; i < dev->data->nb_rx_queues; i++) {
913 nfp_net_reset_rx_queue(
914 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
917 /* Only free PF resources after all physical ports have been closed */
918 if (pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC ||
919 pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC) {
920 struct nfp_pf_dev *pf_dev;
921 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(dev->data->dev_private);
923 /* Mark this port as unused and free device priv resources*/
924 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
925 pf_dev->ports[hw->idx] = NULL;
926 rte_eth_dev_release_port(dev);
928 for (i = 0; i < pf_dev->total_phyports; i++) {
929 /* Check to see if ports are still in use */
930 if (pf_dev->ports[i])
934 /* Now it is safe to free all PF resources */
935 PMD_INIT_LOG(INFO, "Freeing PF resources");
936 nfp_cpp_area_free(pf_dev->ctrl_area);
937 nfp_cpp_area_free(pf_dev->hwqueues_area);
938 free(pf_dev->hwinfo);
939 free(pf_dev->sym_tbl);
940 nfp_cpp_free(pf_dev->cpp);
944 rte_intr_disable(&pci_dev->intr_handle);
946 /* unregister callback func from eal lib */
947 rte_intr_callback_unregister(&pci_dev->intr_handle,
948 nfp_net_dev_interrupt_handler,
952 * The ixgbe PMD driver disables the pcie master on the
953 * device. The i40e does not...
960 nfp_net_promisc_enable(struct rte_eth_dev *dev)
962 uint32_t new_ctrl, update = 0;
963 struct nfp_net_hw *hw;
966 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
968 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
970 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
971 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
975 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
976 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
980 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
981 update = NFP_NET_CFG_UPDATE_GEN;
984 * DPDK sets promiscuous mode on just after this call assuming
985 * it can not fail ...
987 ret = nfp_net_reconfig(hw, new_ctrl, update);
997 nfp_net_promisc_disable(struct rte_eth_dev *dev)
999 uint32_t new_ctrl, update = 0;
1000 struct nfp_net_hw *hw;
1003 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1005 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
1006 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
1010 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
1011 update = NFP_NET_CFG_UPDATE_GEN;
1014 * DPDK sets promiscuous mode off just before this call
1015 * assuming it can not fail ...
1017 ret = nfp_net_reconfig(hw, new_ctrl, update);
1021 hw->ctrl = new_ctrl;
1027 * return 0 means link status changed, -1 means not changed
1029 * Wait to complete is needed as it can take up to 9 seconds to get the Link
1033 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1035 struct nfp_net_hw *hw;
1036 struct rte_eth_link link;
1037 uint32_t nn_link_status;
1040 static const uint32_t ls_to_ethtool[] = {
1041 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
1042 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
1043 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
1044 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
1045 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
1046 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
1047 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
1048 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
1051 PMD_DRV_LOG(DEBUG, "Link update");
1053 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1055 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1057 memset(&link, 0, sizeof(struct rte_eth_link));
1059 if (nn_link_status & NFP_NET_CFG_STS_LINK)
1060 link.link_status = ETH_LINK_UP;
1062 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1064 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1065 NFP_NET_CFG_STS_LINK_RATE_MASK;
1067 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1068 link.link_speed = ETH_SPEED_NUM_NONE;
1070 link.link_speed = ls_to_ethtool[nn_link_status];
1072 ret = rte_eth_linkstatus_set(dev, &link);
1074 if (link.link_status)
1075 PMD_DRV_LOG(INFO, "NIC Link is Up");
1077 PMD_DRV_LOG(INFO, "NIC Link is Down");
1083 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1086 struct nfp_net_hw *hw;
1087 struct rte_eth_stats nfp_dev_stats;
1089 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1091 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1093 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1095 /* reading per RX ring stats */
1096 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1097 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1100 nfp_dev_stats.q_ipackets[i] =
1101 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1103 nfp_dev_stats.q_ipackets[i] -=
1104 hw->eth_stats_base.q_ipackets[i];
1106 nfp_dev_stats.q_ibytes[i] =
1107 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1109 nfp_dev_stats.q_ibytes[i] -=
1110 hw->eth_stats_base.q_ibytes[i];
1113 /* reading per TX ring stats */
1114 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1115 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1118 nfp_dev_stats.q_opackets[i] =
1119 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1121 nfp_dev_stats.q_opackets[i] -=
1122 hw->eth_stats_base.q_opackets[i];
1124 nfp_dev_stats.q_obytes[i] =
1125 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1127 nfp_dev_stats.q_obytes[i] -=
1128 hw->eth_stats_base.q_obytes[i];
1131 nfp_dev_stats.ipackets =
1132 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1134 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1136 nfp_dev_stats.ibytes =
1137 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1139 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1141 nfp_dev_stats.opackets =
1142 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1144 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1146 nfp_dev_stats.obytes =
1147 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1149 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1151 /* reading general device stats */
1152 nfp_dev_stats.ierrors =
1153 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1155 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1157 nfp_dev_stats.oerrors =
1158 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1160 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1162 /* RX ring mbuf allocation failures */
1163 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1165 nfp_dev_stats.imissed =
1166 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1168 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1171 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1178 nfp_net_stats_reset(struct rte_eth_dev *dev)
1181 struct nfp_net_hw *hw;
1183 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1186 * hw->eth_stats_base records the per counter starting point.
1187 * Lets update it now
1190 /* reading per RX ring stats */
1191 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1192 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1195 hw->eth_stats_base.q_ipackets[i] =
1196 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1198 hw->eth_stats_base.q_ibytes[i] =
1199 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1202 /* reading per TX ring stats */
1203 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1204 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1207 hw->eth_stats_base.q_opackets[i] =
1208 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1210 hw->eth_stats_base.q_obytes[i] =
1211 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1214 hw->eth_stats_base.ipackets =
1215 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1217 hw->eth_stats_base.ibytes =
1218 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1220 hw->eth_stats_base.opackets =
1221 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1223 hw->eth_stats_base.obytes =
1224 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1226 /* reading general device stats */
1227 hw->eth_stats_base.ierrors =
1228 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1230 hw->eth_stats_base.oerrors =
1231 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1233 /* RX ring mbuf allocation failures */
1234 dev->data->rx_mbuf_alloc_failed = 0;
1236 hw->eth_stats_base.imissed =
1237 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1243 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1245 struct nfp_net_hw *hw;
1247 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1249 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1250 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1251 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1252 dev_info->max_rx_pktlen = hw->max_mtu;
1253 /* Next should change when PF support is implemented */
1254 dev_info->max_mac_addrs = 1;
1256 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1257 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1259 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1260 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1261 DEV_RX_OFFLOAD_UDP_CKSUM |
1262 DEV_RX_OFFLOAD_TCP_CKSUM;
1264 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1265 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1267 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1268 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1269 DEV_TX_OFFLOAD_UDP_CKSUM |
1270 DEV_TX_OFFLOAD_TCP_CKSUM;
1272 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1273 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1275 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1276 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1278 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1280 .pthresh = DEFAULT_RX_PTHRESH,
1281 .hthresh = DEFAULT_RX_HTHRESH,
1282 .wthresh = DEFAULT_RX_WTHRESH,
1284 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1288 dev_info->default_txconf = (struct rte_eth_txconf) {
1290 .pthresh = DEFAULT_TX_PTHRESH,
1291 .hthresh = DEFAULT_TX_HTHRESH,
1292 .wthresh = DEFAULT_TX_WTHRESH,
1294 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1295 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1298 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1299 .nb_max = NFP_NET_MAX_RX_DESC,
1300 .nb_min = NFP_NET_MIN_RX_DESC,
1301 .nb_align = NFP_ALIGN_RING_DESC,
1304 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1305 .nb_max = NFP_NET_MAX_TX_DESC,
1306 .nb_min = NFP_NET_MIN_TX_DESC,
1307 .nb_align = NFP_ALIGN_RING_DESC,
1308 .nb_seg_max = NFP_TX_MAX_SEG,
1309 .nb_mtu_seg_max = NFP_TX_MAX_MTU_SEG,
1312 /* All NFP devices support jumbo frames */
1313 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1315 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
1316 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_RSS_HASH;
1318 dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1319 ETH_RSS_NONFRAG_IPV4_TCP |
1320 ETH_RSS_NONFRAG_IPV4_UDP |
1322 ETH_RSS_NONFRAG_IPV6_TCP |
1323 ETH_RSS_NONFRAG_IPV6_UDP;
1325 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1326 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1329 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1330 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1331 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1336 static const uint32_t *
1337 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1339 static const uint32_t ptypes[] = {
1340 /* refers to nfp_net_set_hash() */
1341 RTE_PTYPE_INNER_L3_IPV4,
1342 RTE_PTYPE_INNER_L3_IPV6,
1343 RTE_PTYPE_INNER_L3_IPV6_EXT,
1344 RTE_PTYPE_INNER_L4_MASK,
1348 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1354 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1356 struct nfp_net_rxq *rxq;
1357 struct nfp_net_rx_desc *rxds;
1361 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1368 * Other PMDs are just checking the DD bit in intervals of 4
1369 * descriptors and counting all four if the first has the DD
1370 * bit on. Of course, this is not accurate but can be good for
1371 * performance. But ideally that should be done in descriptors
1372 * chunks belonging to the same cache line
1375 while (count < rxq->rx_count) {
1376 rxds = &rxq->rxds[idx];
1377 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1384 if ((idx) == rxq->rx_count)
1392 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1394 struct rte_pci_device *pci_dev;
1395 struct nfp_net_hw *hw;
1398 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1399 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1401 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1404 /* Make sure all updates are written before un-masking */
1406 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1407 NFP_NET_CFG_ICR_UNMASKED);
1412 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1414 struct rte_pci_device *pci_dev;
1415 struct nfp_net_hw *hw;
1418 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1421 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1424 /* Make sure all updates are written before un-masking */
1426 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1431 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1433 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1434 struct rte_eth_link link;
1436 rte_eth_linkstatus_get(dev, &link);
1437 if (link.link_status)
1438 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1439 dev->data->port_id, link.link_speed,
1440 link.link_duplex == ETH_LINK_FULL_DUPLEX
1441 ? "full-duplex" : "half-duplex");
1443 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1444 dev->data->port_id);
1446 PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
1447 pci_dev->addr.domain, pci_dev->addr.bus,
1448 pci_dev->addr.devid, pci_dev->addr.function);
1451 /* Interrupt configuration and handling */
1454 * nfp_net_irq_unmask - Unmask an interrupt
1456 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1457 * clear the ICR for the entry.
1460 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1462 struct nfp_net_hw *hw;
1463 struct rte_pci_device *pci_dev;
1465 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1466 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1468 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1469 /* If MSI-X auto-masking is used, clear the entry */
1471 rte_intr_ack(&pci_dev->intr_handle);
1473 /* Make sure all updates are written before un-masking */
1475 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1476 NFP_NET_CFG_ICR_UNMASKED);
1481 nfp_net_dev_interrupt_handler(void *param)
1484 struct rte_eth_link link;
1485 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1487 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1489 rte_eth_linkstatus_get(dev, &link);
1491 nfp_net_link_update(dev, 0);
1494 if (!link.link_status) {
1495 /* handle it 1 sec later, wait it being stable */
1496 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1497 /* likely to down */
1499 /* handle it 4 sec later, wait it being stable */
1500 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1503 if (rte_eal_alarm_set(timeout * 1000,
1504 nfp_net_dev_interrupt_delayed_handler,
1506 PMD_INIT_LOG(ERR, "Error setting alarm");
1508 nfp_net_irq_unmask(dev);
1513 * Interrupt handler which shall be registered for alarm callback for delayed
1514 * handling specific interrupt to wait for the stable nic state. As the NIC
1515 * interrupt state is not stable for nfp after link is just down, it needs
1516 * to wait 4 seconds to get the stable status.
1518 * @param handle Pointer to interrupt handle.
1519 * @param param The address of parameter (struct rte_eth_dev *)
1524 nfp_net_dev_interrupt_delayed_handler(void *param)
1526 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1528 nfp_net_link_update(dev, 0);
1529 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1531 nfp_net_dev_link_status_print(dev);
1534 nfp_net_irq_unmask(dev);
1538 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1540 struct nfp_net_hw *hw;
1542 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1544 /* check that mtu is within the allowed range */
1545 if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1548 /* mtu setting is forbidden if port is started */
1549 if (dev->data->dev_started) {
1550 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1551 dev->data->port_id);
1555 /* switch to jumbo mode if needed */
1556 if ((uint32_t)mtu > RTE_ETHER_MTU)
1557 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1559 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1561 /* update max frame size */
1562 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1564 /* writing to configuration space */
1565 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1573 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1574 uint16_t queue_idx, uint16_t nb_desc,
1575 unsigned int socket_id,
1576 const struct rte_eth_rxconf *rx_conf,
1577 struct rte_mempool *mp)
1579 const struct rte_memzone *tz;
1580 struct nfp_net_rxq *rxq;
1581 struct nfp_net_hw *hw;
1582 uint32_t rx_desc_sz;
1584 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586 PMD_INIT_FUNC_TRACE();
1588 /* Validating number of descriptors */
1589 rx_desc_sz = nb_desc * sizeof(struct nfp_net_rx_desc);
1590 if (rx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1591 nb_desc > NFP_NET_MAX_RX_DESC ||
1592 nb_desc < NFP_NET_MIN_RX_DESC) {
1593 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1598 * Free memory prior to re-allocation if needed. This is the case after
1599 * calling nfp_net_stop
1601 if (dev->data->rx_queues[queue_idx]) {
1602 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1603 dev->data->rx_queues[queue_idx] = NULL;
1606 /* Allocating rx queue data structure */
1607 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1608 RTE_CACHE_LINE_SIZE, socket_id);
1612 /* Hw queues mapping based on firmware configuration */
1613 rxq->qidx = queue_idx;
1614 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1615 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1616 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1617 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1620 * Tracking mbuf size for detecting a potential mbuf overflow due to
1624 rxq->mbuf_size = rxq->mem_pool->elt_size;
1625 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1626 hw->flbufsz = rxq->mbuf_size;
1628 rxq->rx_count = nb_desc;
1629 rxq->port_id = dev->data->port_id;
1630 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1631 rxq->drop_en = rx_conf->rx_drop_en;
1634 * Allocate RX ring hardware descriptors. A memzone large enough to
1635 * handle the maximum ring size is allocated in order to allow for
1636 * resizing in later calls to the queue setup function.
1638 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1639 sizeof(struct nfp_net_rx_desc) *
1640 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1644 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1645 nfp_net_rx_queue_release(rxq);
1649 /* Saving physical and virtual addresses for the RX ring */
1650 rxq->dma = (uint64_t)tz->iova;
1651 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1653 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1654 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1655 sizeof(*rxq->rxbufs) * nb_desc,
1656 RTE_CACHE_LINE_SIZE, socket_id);
1657 if (rxq->rxbufs == NULL) {
1658 nfp_net_rx_queue_release(rxq);
1662 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1663 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1665 nfp_net_reset_rx_queue(rxq);
1667 dev->data->rx_queues[queue_idx] = rxq;
1671 * Telling the HW about the physical address of the RX ring and number
1672 * of descriptors in log2 format
1674 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1675 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1681 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1683 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1687 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1690 for (i = 0; i < rxq->rx_count; i++) {
1691 struct nfp_net_rx_desc *rxd;
1692 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1695 PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1696 (unsigned)rxq->qidx);
1700 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1702 rxd = &rxq->rxds[i];
1704 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1705 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1707 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1710 /* Make sure all writes are flushed before telling the hardware */
1713 /* Not advertising the whole ring as the firmware gets confused if so */
1714 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1717 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1723 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1724 uint16_t nb_desc, unsigned int socket_id,
1725 const struct rte_eth_txconf *tx_conf)
1727 const struct rte_memzone *tz;
1728 struct nfp_net_txq *txq;
1729 uint16_t tx_free_thresh;
1730 struct nfp_net_hw *hw;
1731 uint32_t tx_desc_sz;
1733 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1735 PMD_INIT_FUNC_TRACE();
1737 /* Validating number of descriptors */
1738 tx_desc_sz = nb_desc * sizeof(struct nfp_net_tx_desc);
1739 if (tx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1740 nb_desc > NFP_NET_MAX_TX_DESC ||
1741 nb_desc < NFP_NET_MIN_TX_DESC) {
1742 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1746 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1747 tx_conf->tx_free_thresh :
1748 DEFAULT_TX_FREE_THRESH);
1750 if (tx_free_thresh > (nb_desc)) {
1752 "tx_free_thresh must be less than the number of TX "
1753 "descriptors. (tx_free_thresh=%u port=%d "
1754 "queue=%d)", (unsigned int)tx_free_thresh,
1755 dev->data->port_id, (int)queue_idx);
1760 * Free memory prior to re-allocation if needed. This is the case after
1761 * calling nfp_net_stop
1763 if (dev->data->tx_queues[queue_idx]) {
1764 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1766 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1767 dev->data->tx_queues[queue_idx] = NULL;
1770 /* Allocating tx queue data structure */
1771 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1772 RTE_CACHE_LINE_SIZE, socket_id);
1774 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1779 * Allocate TX ring hardware descriptors. A memzone large enough to
1780 * handle the maximum ring size is allocated in order to allow for
1781 * resizing in later calls to the queue setup function.
1783 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1784 sizeof(struct nfp_net_tx_desc) *
1785 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1788 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1789 nfp_net_tx_queue_release(txq);
1793 txq->tx_count = nb_desc;
1794 txq->tx_free_thresh = tx_free_thresh;
1795 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1796 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1797 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1799 /* queue mapping based on firmware configuration */
1800 txq->qidx = queue_idx;
1801 txq->tx_qcidx = queue_idx * hw->stride_tx;
1802 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1804 txq->port_id = dev->data->port_id;
1806 /* Saving physical and virtual addresses for the TX ring */
1807 txq->dma = (uint64_t)tz->iova;
1808 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1810 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1811 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1812 sizeof(*txq->txbufs) * nb_desc,
1813 RTE_CACHE_LINE_SIZE, socket_id);
1814 if (txq->txbufs == NULL) {
1815 nfp_net_tx_queue_release(txq);
1818 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1819 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1821 nfp_net_reset_tx_queue(txq);
1823 dev->data->tx_queues[queue_idx] = txq;
1827 * Telling the HW about the physical address of the TX ring and number
1828 * of descriptors in log2 format
1830 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1831 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1836 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1838 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1839 struct rte_mbuf *mb)
1842 struct nfp_net_hw *hw = txq->hw;
1844 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1847 ol_flags = mb->ol_flags;
1849 if (!(ol_flags & PKT_TX_TCP_SEG))
1852 txd->l3_offset = mb->l2_len;
1853 txd->l4_offset = mb->l2_len + mb->l3_len;
1854 txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1855 txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1856 txd->flags = PCIE_DESC_TX_LSO;
1863 txd->lso_hdrlen = 0;
1867 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1869 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1870 struct rte_mbuf *mb)
1873 struct nfp_net_hw *hw = txq->hw;
1875 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1878 ol_flags = mb->ol_flags;
1880 /* IPv6 does not need checksum */
1881 if (ol_flags & PKT_TX_IP_CKSUM)
1882 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1884 switch (ol_flags & PKT_TX_L4_MASK) {
1885 case PKT_TX_UDP_CKSUM:
1886 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1888 case PKT_TX_TCP_CKSUM:
1889 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1893 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1894 txd->flags |= PCIE_DESC_TX_CSUM;
1897 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1899 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1900 struct rte_mbuf *mb)
1902 struct nfp_net_hw *hw = rxq->hw;
1904 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1907 /* If IPv4 and IP checksum error, fail */
1908 if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1909 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1910 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1912 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1914 /* If neither UDP nor TCP return */
1915 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1916 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1919 if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1920 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1922 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1925 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1926 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1928 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1931 * nfp_net_set_hash - Set mbuf hash data
1933 * The RSS hash and hash-type are pre-pended to the packet data.
1934 * Extract and decode it and set the mbuf fields.
1937 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1938 struct rte_mbuf *mbuf)
1940 struct nfp_net_hw *hw = rxq->hw;
1941 uint8_t *meta_offset;
1944 uint32_t hash_type = 0;
1946 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1949 /* this is true for new firmwares */
1950 if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1951 (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1952 NFP_DESC_META_LEN(rxd))) {
1955 * <---- 32 bit ----->
1960 * ====================
1963 * Field type word contains up to 8 4bit field types
1964 * A 4bit field type refers to a data field word
1965 * A data field word can have several 4bit field types
1967 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1968 meta_offset -= NFP_DESC_META_LEN(rxd);
1969 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1971 /* NFP PMD just supports metadata for hashing */
1972 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1973 case NFP_NET_META_HASH:
1974 /* next field type is about the hash type */
1975 meta_info >>= NFP_NET_META_FIELD_SIZE;
1976 /* hash value is in the data field */
1977 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1978 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1981 /* Unsupported metadata can be a performance issue */
1985 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1988 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1989 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1992 mbuf->hash.rss = hash;
1993 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1995 switch (hash_type) {
1996 case NFP_NET_RSS_IPV4:
1997 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1999 case NFP_NET_RSS_IPV6:
2000 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
2002 case NFP_NET_RSS_IPV6_EX:
2003 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2005 case NFP_NET_RSS_IPV4_TCP:
2006 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2008 case NFP_NET_RSS_IPV6_TCP:
2009 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2011 case NFP_NET_RSS_IPV4_UDP:
2012 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2014 case NFP_NET_RSS_IPV6_UDP:
2015 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2018 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
2023 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
2025 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
2028 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
2033 * There are some decisions to take:
2034 * 1) How to check DD RX descriptors bit
2035 * 2) How and when to allocate new mbufs
2037 * Current implementation checks just one single DD bit each loop. As each
2038 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
2039 * a single cache line instead. Tests with this change have not shown any
2040 * performance improvement but it requires further investigation. For example,
2041 * depending on which descriptor is next, the number of descriptors could be
2042 * less than 8 for just checking those in the same cache line. This implies
2043 * extra work which could be counterproductive by itself. Indeed, last firmware
2044 * changes are just doing this: writing several descriptors with the DD bit
2045 * for saving PCIe bandwidth and DMA operations from the NFP.
2047 * Mbuf allocation is done when a new packet is received. Then the descriptor
2048 * is automatically linked with the new mbuf and the old one is given to the
2049 * user. The main drawback with this design is mbuf allocation is heavier than
2050 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
2051 * cache point of view it does not seem allocating the mbuf early on as we are
2052 * doing now have any benefit at all. Again, tests with this change have not
2053 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2054 * so looking at the implications of this type of allocation should be studied
2059 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2061 struct nfp_net_rxq *rxq;
2062 struct nfp_net_rx_desc *rxds;
2063 struct nfp_net_rx_buff *rxb;
2064 struct nfp_net_hw *hw;
2065 struct rte_mbuf *mb;
2066 struct rte_mbuf *new_mb;
2072 if (unlikely(rxq == NULL)) {
2074 * DPDK just checks the queue is lower than max queues
2075 * enabled. But the queue needs to be configured
2077 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2085 while (avail < nb_pkts) {
2086 rxb = &rxq->rxbufs[rxq->rd_p];
2087 if (unlikely(rxb == NULL)) {
2088 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2092 rxds = &rxq->rxds[rxq->rd_p];
2093 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2097 * Memory barrier to ensure that we won't do other
2098 * reads before the DD bit.
2103 * We got a packet. Let's alloc a new mbuf for refilling the
2104 * free descriptor ring as soon as possible
2106 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2107 if (unlikely(new_mb == NULL)) {
2108 RTE_LOG_DP(DEBUG, PMD,
2109 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2110 rxq->port_id, (unsigned int)rxq->qidx);
2111 nfp_net_mbuf_alloc_failed(rxq);
2118 * Grab the mbuf and refill the descriptor with the
2119 * previously allocated mbuf
2124 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2125 rxds->rxd.data_len, rxq->mbuf_size);
2127 /* Size of this segment */
2128 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2129 /* Size of the whole packet. We just support 1 segment */
2130 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2132 if (unlikely((mb->data_len + hw->rx_offset) >
2135 * This should not happen and the user has the
2136 * responsibility of avoiding it. But we have
2137 * to give some info about the error
2139 RTE_LOG_DP(ERR, PMD,
2140 "mbuf overflow likely due to the RX offset.\n"
2141 "\t\tYour mbuf size should have extra space for"
2142 " RX offset=%u bytes.\n"
2143 "\t\tCurrently you just have %u bytes available"
2144 " but the received packet is %u bytes long",
2146 rxq->mbuf_size - hw->rx_offset,
2151 /* Filling the received mbuf with packet info */
2153 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2155 mb->data_off = RTE_PKTMBUF_HEADROOM +
2156 NFP_DESC_META_LEN(rxds);
2158 /* No scatter mode supported */
2162 mb->port = rxq->port_id;
2164 /* Checking the RSS flag */
2165 nfp_net_set_hash(rxq, rxds, mb);
2167 /* Checking the checksum flag */
2168 nfp_net_rx_cksum(rxq, rxds, mb);
2170 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2171 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2172 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2173 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2176 /* Adding the mbuf to the mbuf array passed by the app */
2177 rx_pkts[avail++] = mb;
2179 /* Now resetting and updating the descriptor */
2182 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2184 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2185 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2188 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2195 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received",
2196 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2198 nb_hold += rxq->nb_rx_hold;
2201 * FL descriptors needs to be written before incrementing the
2202 * FL queue WR pointer
2205 if (nb_hold > rxq->rx_free_thresh) {
2206 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2207 rxq->port_id, (unsigned int)rxq->qidx,
2208 (unsigned)nb_hold, (unsigned)avail);
2209 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2212 rxq->nb_rx_hold = nb_hold;
2218 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2220 * @txq: TX queue to work with
2221 * Returns number of descriptors freed
2224 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2229 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2230 " status", txq->qidx);
2232 /* Work out how many packets have been sent */
2233 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2235 if (qcp_rd_p == txq->rd_p) {
2236 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2237 "packets (%u, %u)", txq->qidx,
2238 qcp_rd_p, txq->rd_p);
2242 if (qcp_rd_p > txq->rd_p)
2243 todo = qcp_rd_p - txq->rd_p;
2245 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2247 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2248 qcp_rd_p, txq->rd_p, txq->rd_p);
2254 if (unlikely(txq->rd_p >= txq->tx_count))
2255 txq->rd_p -= txq->tx_count;
2260 /* Leaving always free descriptors for avoiding wrapping confusion */
2262 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2264 if (txq->wr_p >= txq->rd_p)
2265 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2267 return txq->rd_p - txq->wr_p - 8;
2271 * nfp_net_txq_full - Check if the TX queue free descriptors
2272 * is below tx_free_threshold
2274 * @txq: TX queue to check
2276 * This function uses the host copy* of read/write pointers
2279 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2281 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2285 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2287 struct nfp_net_txq *txq;
2288 struct nfp_net_hw *hw;
2289 struct nfp_net_tx_desc *txds, txd;
2290 struct rte_mbuf *pkt;
2292 int pkt_size, dma_size;
2293 uint16_t free_descs, issued_descs;
2294 struct rte_mbuf **lmbuf;
2299 txds = &txq->txds[txq->wr_p];
2301 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2302 txq->qidx, txq->wr_p, nb_pkts);
2304 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2305 nfp_net_tx_free_bufs(txq);
2307 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2308 if (unlikely(free_descs == 0))
2315 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2316 txq->qidx, nb_pkts);
2317 /* Sending packets */
2318 while ((i < nb_pkts) && free_descs) {
2319 /* Grabbing the mbuf linked to the current descriptor */
2320 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2321 /* Warming the cache for releasing the mbuf later on */
2322 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2324 pkt = *(tx_pkts + i);
2326 if (unlikely((pkt->nb_segs > 1) &&
2327 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2328 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2329 rte_panic("Multisegment packet unsupported\n");
2332 /* Checking if we have enough descriptors */
2333 if (unlikely(pkt->nb_segs > free_descs))
2337 * Checksum and VLAN flags just in the first descriptor for a
2338 * multisegment packet, but TSO info needs to be in all of them.
2340 txd.data_len = pkt->pkt_len;
2341 nfp_net_tx_tso(txq, &txd, pkt);
2342 nfp_net_tx_cksum(txq, &txd, pkt);
2344 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2345 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2346 txd.flags |= PCIE_DESC_TX_VLAN;
2347 txd.vlan = pkt->vlan_tci;
2351 * mbuf data_len is the data in one segment and pkt_len data
2352 * in the whole packet. When the packet is just one segment,
2353 * then data_len = pkt_len
2355 pkt_size = pkt->pkt_len;
2358 /* Copying TSO, VLAN and cksum info */
2361 /* Releasing mbuf used by this descriptor previously*/
2363 rte_pktmbuf_free_seg(*lmbuf);
2366 * Linking mbuf with descriptor for being released
2367 * next time descriptor is used
2371 dma_size = pkt->data_len;
2372 dma_addr = rte_mbuf_data_iova(pkt);
2373 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2374 "%" PRIx64 "", dma_addr);
2376 /* Filling descriptors fields */
2377 txds->dma_len = dma_size;
2378 txds->data_len = txd.data_len;
2379 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2380 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2381 ASSERT(free_descs > 0);
2385 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2388 pkt_size -= dma_size;
2391 * Making the EOP, packets with just one segment
2394 if (likely(!pkt_size))
2395 txds->offset_eop = PCIE_DESC_TX_EOP;
2397 txds->offset_eop = 0;
2400 /* Referencing next free TX descriptor */
2401 txds = &txq->txds[txq->wr_p];
2402 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2409 /* Increment write pointers. Force memory write before we let HW know */
2411 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2417 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2419 uint32_t new_ctrl, update;
2420 struct nfp_net_hw *hw;
2423 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2426 /* Enable vlan strip if it is not configured yet */
2427 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2428 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2429 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2431 /* Disable vlan strip just if it is configured */
2432 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2433 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2434 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2439 update = NFP_NET_CFG_UPDATE_GEN;
2441 ret = nfp_net_reconfig(hw, new_ctrl, update);
2443 hw->ctrl = new_ctrl;
2449 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2450 struct rte_eth_rss_reta_entry64 *reta_conf,
2453 uint32_t reta, mask;
2456 struct nfp_net_hw *hw =
2457 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2460 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2461 "(%d) doesn't match the number hardware can supported "
2462 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2467 * Update Redirection Table. There are 128 8bit-entries which can be
2468 * manage as 32 32bit-entries
2470 for (i = 0; i < reta_size; i += 4) {
2471 /* Handling 4 RSS entries per loop */
2472 idx = i / RTE_RETA_GROUP_SIZE;
2473 shift = i % RTE_RETA_GROUP_SIZE;
2474 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2480 /* If all 4 entries were set, don't need read RETA register */
2482 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2484 for (j = 0; j < 4; j++) {
2485 if (!(mask & (0x1 << j)))
2488 /* Clearing the entry bits */
2489 reta &= ~(0xFF << (8 * j));
2490 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2492 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2498 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2500 nfp_net_reta_update(struct rte_eth_dev *dev,
2501 struct rte_eth_rss_reta_entry64 *reta_conf,
2504 struct nfp_net_hw *hw =
2505 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2509 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2512 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2516 update = NFP_NET_CFG_UPDATE_RSS;
2518 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2524 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2526 nfp_net_reta_query(struct rte_eth_dev *dev,
2527 struct rte_eth_rss_reta_entry64 *reta_conf,
2533 struct nfp_net_hw *hw;
2535 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2540 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2541 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2542 "(%d) doesn't match the number hardware can supported "
2543 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2548 * Reading Redirection Table. There are 128 8bit-entries which can be
2549 * manage as 32 32bit-entries
2551 for (i = 0; i < reta_size; i += 4) {
2552 /* Handling 4 RSS entries per loop */
2553 idx = i / RTE_RETA_GROUP_SIZE;
2554 shift = i % RTE_RETA_GROUP_SIZE;
2555 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2560 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2562 for (j = 0; j < 4; j++) {
2563 if (!(mask & (0x1 << j)))
2565 reta_conf[idx].reta[shift + j] =
2566 (uint8_t)((reta >> (8 * j)) & 0xF);
2573 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2574 struct rte_eth_rss_conf *rss_conf)
2576 struct nfp_net_hw *hw;
2578 uint32_t cfg_rss_ctrl = 0;
2582 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584 /* Writing the key byte a byte */
2585 for (i = 0; i < rss_conf->rss_key_len; i++) {
2586 memcpy(&key, &rss_conf->rss_key[i], 1);
2587 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2590 rss_hf = rss_conf->rss_hf;
2592 if (rss_hf & ETH_RSS_IPV4)
2593 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2595 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2596 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2598 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2599 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2601 if (rss_hf & ETH_RSS_IPV6)
2602 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2604 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2605 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2607 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2608 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2610 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2611 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2613 /* configuring where to apply the RSS hash */
2614 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2616 /* Writing the key size */
2617 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2623 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2624 struct rte_eth_rss_conf *rss_conf)
2628 struct nfp_net_hw *hw;
2630 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632 rss_hf = rss_conf->rss_hf;
2634 /* Checking if RSS is enabled */
2635 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2636 if (rss_hf != 0) { /* Enable RSS? */
2637 PMD_DRV_LOG(ERR, "RSS unsupported");
2640 return 0; /* Nothing to do */
2643 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2644 PMD_DRV_LOG(ERR, "hash key too long");
2648 nfp_net_rss_hash_write(dev, rss_conf);
2650 update = NFP_NET_CFG_UPDATE_RSS;
2652 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2659 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2660 struct rte_eth_rss_conf *rss_conf)
2663 uint32_t cfg_rss_ctrl;
2666 struct nfp_net_hw *hw;
2668 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2670 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2673 rss_hf = rss_conf->rss_hf;
2674 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2676 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2677 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2679 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2680 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2682 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2683 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2685 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2686 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2688 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2689 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2691 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2692 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2694 /* Propagate current RSS hash functions to caller */
2695 rss_conf->rss_hf = rss_hf;
2697 /* Reading the key size */
2698 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2700 /* Reading the key byte a byte */
2701 for (i = 0; i < rss_conf->rss_key_len; i++) {
2702 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2703 memcpy(&rss_conf->rss_key[i], &key, 1);
2710 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2712 struct rte_eth_conf *dev_conf;
2713 struct rte_eth_rss_conf rss_conf;
2714 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2715 uint16_t rx_queues = dev->data->nb_rx_queues;
2719 PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2722 nfp_reta_conf[0].mask = ~0x0;
2723 nfp_reta_conf[1].mask = ~0x0;
2726 for (i = 0; i < 0x40; i += 8) {
2727 for (j = i; j < (i + 8); j++) {
2728 nfp_reta_conf[0].reta[j] = queue;
2729 nfp_reta_conf[1].reta[j] = queue++;
2733 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2737 dev_conf = &dev->data->dev_conf;
2739 PMD_DRV_LOG(INFO, "wrong rss conf");
2742 rss_conf = dev_conf->rx_adv_conf.rss_conf;
2744 ret = nfp_net_rss_hash_write(dev, &rss_conf);
2750 /* Initialise and register driver with DPDK Application */
2751 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2752 .dev_configure = nfp_net_configure,
2753 .dev_start = nfp_net_start,
2754 .dev_stop = nfp_net_stop,
2755 .dev_set_link_up = nfp_net_set_link_up,
2756 .dev_set_link_down = nfp_net_set_link_down,
2757 .dev_close = nfp_net_close,
2758 .promiscuous_enable = nfp_net_promisc_enable,
2759 .promiscuous_disable = nfp_net_promisc_disable,
2760 .link_update = nfp_net_link_update,
2761 .stats_get = nfp_net_stats_get,
2762 .stats_reset = nfp_net_stats_reset,
2763 .dev_infos_get = nfp_net_infos_get,
2764 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2765 .mtu_set = nfp_net_dev_mtu_set,
2766 .mac_addr_set = nfp_set_mac_addr,
2767 .vlan_offload_set = nfp_net_vlan_offload_set,
2768 .reta_update = nfp_net_reta_update,
2769 .reta_query = nfp_net_reta_query,
2770 .rss_hash_update = nfp_net_rss_hash_update,
2771 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2772 .rx_queue_setup = nfp_net_rx_queue_setup,
2773 .rx_queue_release = nfp_net_rx_queue_release,
2774 .tx_queue_setup = nfp_net_tx_queue_setup,
2775 .tx_queue_release = nfp_net_tx_queue_release,
2776 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2777 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2782 nfp_net_init(struct rte_eth_dev *eth_dev)
2784 struct rte_pci_device *pci_dev;
2785 struct nfp_pf_dev *pf_dev;
2786 struct nfp_net_hw *hw;
2788 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2794 PMD_INIT_FUNC_TRACE();
2796 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2798 /* Use backpointer here to the PF of this eth_dev */
2799 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(eth_dev->data->dev_private);
2801 /* NFP can not handle DMA addresses requiring more than 40 bits */
2802 if (rte_mem_check_dma_mask(40)) {
2803 RTE_LOG(ERR, PMD, "device %s can not be used:",
2804 pci_dev->device.name);
2805 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2809 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2810 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2811 port = ((struct nfp_net_hw *)eth_dev->data->dev_private)->idx;
2812 if (port < 0 || port > 7) {
2813 PMD_DRV_LOG(ERR, "Port value is wrong");
2817 /* Use PF array of physical ports to get pointer to
2818 * this specific port
2820 hw = pf_dev->ports[port];
2822 PMD_INIT_LOG(DEBUG, "Working with physical port number: %d, "
2823 "NFP internal port number: %d",
2827 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2830 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2831 eth_dev->rx_queue_count = nfp_net_rx_queue_count;
2832 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2833 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2835 /* For secondary processes, the primary has done all the work */
2836 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2839 rte_eth_copy_pci_info(eth_dev, pci_dev);
2841 hw->device_id = pci_dev->id.device_id;
2842 hw->vendor_id = pci_dev->id.vendor_id;
2843 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2844 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2846 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2847 pci_dev->id.vendor_id, pci_dev->id.device_id,
2848 pci_dev->addr.domain, pci_dev->addr.bus,
2849 pci_dev->addr.devid, pci_dev->addr.function);
2851 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2852 if (hw->ctrl_bar == NULL) {
2854 "hw->ctrl_bar is NULL. BAR0 not configured");
2858 if (hw->is_phyport) {
2860 hw->ctrl_bar = pf_dev->ctrl_bar;
2862 if (!pf_dev->ctrl_bar)
2864 /* Use port offset in pf ctrl_bar for this
2867 hw->ctrl_bar = pf_dev->ctrl_bar +
2868 (port * NFP_PF_CSR_SLICE_SIZE);
2872 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2874 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2875 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2877 /* Work out where in the BAR the queues start. */
2878 switch (pci_dev->id.device_id) {
2879 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2880 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2881 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2882 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2883 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2884 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2885 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2888 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2890 goto dev_err_ctrl_map;
2893 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2894 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2896 if (hw->is_phyport) {
2897 hw->tx_bar = pf_dev->hw_queues + tx_bar_off;
2898 hw->rx_bar = pf_dev->hw_queues + rx_bar_off;
2899 eth_dev->data->dev_private = hw;
2901 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2903 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2907 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2908 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2910 nfp_net_cfg_queue_setup(hw);
2912 /* Get some of the read-only fields from the config BAR */
2913 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2914 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2915 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2916 hw->mtu = RTE_ETHER_MTU;
2918 /* VLAN insertion is incompatible with LSOv2 */
2919 if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2920 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2922 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2923 hw->rx_offset = NFP_NET_RX_OFFSET;
2925 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2927 PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2928 NFD_CFG_MAJOR_VERSION_of(hw->ver),
2929 NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2931 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2932 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2933 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2934 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2935 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2936 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2937 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2938 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2939 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2940 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2941 hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR " : "",
2942 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2943 hw->cap & NFP_NET_CFG_CTRL_LSO2 ? "TSOv2 " : "",
2944 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "",
2945 hw->cap & NFP_NET_CFG_CTRL_RSS2 ? "RSSv2 " : "");
2949 hw->stride_rx = stride;
2950 hw->stride_tx = stride;
2952 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2953 hw->max_rx_queues, hw->max_tx_queues);
2955 /* Initializing spinlock for reconfigs */
2956 rte_spinlock_init(&hw->reconfig_lock);
2958 /* Allocating memory for mac addr */
2959 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2960 RTE_ETHER_ADDR_LEN, 0);
2961 if (eth_dev->data->mac_addrs == NULL) {
2962 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2964 goto dev_err_queues_map;
2967 if (hw->is_phyport) {
2968 nfp_net_pf_read_mac(pf_dev, port);
2969 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2971 nfp_net_vf_read_mac(hw);
2974 if (!rte_is_valid_assigned_ether_addr(
2975 (struct rte_ether_addr *)&hw->mac_addr)) {
2976 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2978 /* Using random mac addresses for VFs */
2979 rte_eth_random_addr(&hw->mac_addr[0]);
2980 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2983 /* Copying mac address to DPDK eth_dev struct */
2984 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2985 ð_dev->data->mac_addrs[0]);
2987 if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2988 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2990 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2992 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2993 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2994 eth_dev->data->port_id, pci_dev->id.vendor_id,
2995 pci_dev->id.device_id,
2996 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2997 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2999 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3000 /* Registering LSC interrupt handler */
3001 rte_intr_callback_register(&pci_dev->intr_handle,
3002 nfp_net_dev_interrupt_handler,
3004 /* Telling the firmware about the LSC interrupt entry */
3005 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
3006 /* Recording current stats counters values */
3007 nfp_net_stats_reset(eth_dev);
3013 nfp_cpp_area_free(hw->hwqueues_area);
3015 nfp_cpp_area_free(hw->ctrl_area);
3020 #define NFP_CPP_MEMIO_BOUNDARY (1 << 20)
3023 * Serving a write request to NFP from host programs. The request
3024 * sends the write size and the CPP target. The bridge makes use
3025 * of CPP interface handler configured by the PMD setup.
3028 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3030 struct nfp_cpp_area *area;
3031 off_t offset, nfp_offset;
3032 uint32_t cpp_id, pos, len;
3033 uint32_t tmpbuf[16];
3034 size_t count, curlen, totlen = 0;
3037 PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3038 sizeof(off_t), sizeof(size_t));
3040 /* Reading the count param */
3041 err = recv(sockfd, &count, sizeof(off_t), 0);
3042 if (err != sizeof(off_t))
3047 /* Reading the offset param */
3048 err = recv(sockfd, &offset, sizeof(off_t), 0);
3049 if (err != sizeof(off_t))
3052 /* Obtain target's CPP ID and offset in target */
3053 cpp_id = (offset >> 40) << 8;
3054 nfp_offset = offset & ((1ull << 40) - 1);
3056 PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3058 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3059 cpp_id, nfp_offset);
3061 /* Adjust length if not aligned */
3062 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3063 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3064 curlen = NFP_CPP_MEMIO_BOUNDARY -
3065 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3069 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3070 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3071 nfp_offset, curlen);
3073 RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3077 /* mapping the target */
3078 err = nfp_cpp_area_acquire(area);
3080 RTE_LOG(ERR, PMD, "area acquire failed\n");
3081 nfp_cpp_area_free(area);
3085 for (pos = 0; pos < curlen; pos += len) {
3087 if (len > sizeof(tmpbuf))
3088 len = sizeof(tmpbuf);
3090 PMD_CPP_LOG(DEBUG, "%s: Receive %u of %zu\n", __func__,
3092 err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3093 if (err != (int)len) {
3095 "%s: error when receiving, %d of %zu\n",
3096 __func__, err, count);
3097 nfp_cpp_area_release(area);
3098 nfp_cpp_area_free(area);
3101 err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3103 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3104 nfp_cpp_area_release(area);
3105 nfp_cpp_area_free(area);
3112 nfp_cpp_area_release(area);
3113 nfp_cpp_area_free(area);
3116 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3117 NFP_CPP_MEMIO_BOUNDARY : count;
3124 * Serving a read request to NFP from host programs. The request
3125 * sends the read size and the CPP target. The bridge makes use
3126 * of CPP interface handler configured by the PMD setup. The read
3127 * data is sent to the requester using the same socket.
3130 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3132 struct nfp_cpp_area *area;
3133 off_t offset, nfp_offset;
3134 uint32_t cpp_id, pos, len;
3135 uint32_t tmpbuf[16];
3136 size_t count, curlen, totlen = 0;
3139 PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3140 sizeof(off_t), sizeof(size_t));
3142 /* Reading the count param */
3143 err = recv(sockfd, &count, sizeof(off_t), 0);
3144 if (err != sizeof(off_t))
3149 /* Reading the offset param */
3150 err = recv(sockfd, &offset, sizeof(off_t), 0);
3151 if (err != sizeof(off_t))
3154 /* Obtain target's CPP ID and offset in target */
3155 cpp_id = (offset >> 40) << 8;
3156 nfp_offset = offset & ((1ull << 40) - 1);
3158 PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3160 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3161 cpp_id, nfp_offset);
3163 /* Adjust length if not aligned */
3164 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3165 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3166 curlen = NFP_CPP_MEMIO_BOUNDARY -
3167 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3171 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3172 nfp_offset, curlen);
3174 RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3178 err = nfp_cpp_area_acquire(area);
3180 RTE_LOG(ERR, PMD, "area acquire failed\n");
3181 nfp_cpp_area_free(area);
3185 for (pos = 0; pos < curlen; pos += len) {
3187 if (len > sizeof(tmpbuf))
3188 len = sizeof(tmpbuf);
3190 err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3192 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3193 nfp_cpp_area_release(area);
3194 nfp_cpp_area_free(area);
3197 PMD_CPP_LOG(DEBUG, "%s: sending %u of %zu\n", __func__,
3200 err = send(sockfd, tmpbuf, len, 0);
3201 if (err != (int)len) {
3203 "%s: error when sending: %d of %zu\n",
3204 __func__, err, count);
3205 nfp_cpp_area_release(area);
3206 nfp_cpp_area_free(area);
3213 nfp_cpp_area_release(area);
3214 nfp_cpp_area_free(area);
3217 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3218 NFP_CPP_MEMIO_BOUNDARY : count;
3223 #define NFP_IOCTL 'n'
3224 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3226 * Serving a ioctl command from host NFP tools. This usually goes to
3227 * a kernel driver char driver but it is not available when the PF is
3228 * bound to the PMD. Currently just one ioctl command is served and it
3229 * does not require any CPP access at all.
3232 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3234 uint32_t cmd, ident_size, tmp;
3237 /* Reading now the IOCTL command */
3238 err = recv(sockfd, &cmd, 4, 0);
3240 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3244 /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3245 if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3246 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3250 err = recv(sockfd, &ident_size, 4, 0);
3252 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3256 tmp = nfp_cpp_model(cpp);
3258 PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3260 err = send(sockfd, &tmp, 4, 0);
3262 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3266 tmp = cpp->interface;
3268 PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3270 err = send(sockfd, &tmp, 4, 0);
3272 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3279 #define NFP_BRIDGE_OP_READ 20
3280 #define NFP_BRIDGE_OP_WRITE 30
3281 #define NFP_BRIDGE_OP_IOCTL 40
3284 * This is the code to be executed by a service core. The CPP bridge interface
3285 * is based on a unix socket and requests usually received by a kernel char
3286 * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3287 * can be executed with a wrapper library and LD_LIBRARY being completely
3288 * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3292 nfp_cpp_bridge_service_func(void *args)
3294 struct sockaddr address;
3295 struct nfp_cpp *cpp = args;
3296 int sockfd, datafd, op, ret;
3298 unlink("/tmp/nfp_cpp");
3299 sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3301 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3306 memset(&address, 0, sizeof(struct sockaddr));
3308 address.sa_family = AF_UNIX;
3309 strcpy(address.sa_data, "/tmp/nfp_cpp");
3311 ret = bind(sockfd, (const struct sockaddr *)&address,
3312 sizeof(struct sockaddr));
3314 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3320 ret = listen(sockfd, 20);
3322 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3329 datafd = accept(sockfd, NULL, NULL);
3331 RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3333 RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3339 ret = recv(datafd, &op, 4, 0);
3341 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3346 PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3348 if (op == NFP_BRIDGE_OP_READ)
3349 nfp_cpp_bridge_serve_read(datafd, cpp);
3351 if (op == NFP_BRIDGE_OP_WRITE)
3352 nfp_cpp_bridge_serve_write(datafd, cpp);
3354 if (op == NFP_BRIDGE_OP_IOCTL)
3355 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3367 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
3370 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3372 struct nfp_cpp *cpp = nsp->cpp;
3378 /* Looking for firmware file in order of priority */
3380 /* First try to find a firmware image specific for this device */
3381 snprintf(serial, sizeof(serial),
3382 "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3383 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3384 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3385 cpp->interface & 0xff);
3387 snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3389 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3390 if (rte_firmware_read(fw_name, &fw_buf, &fsize) == 0)
3393 /* Then try the PCI name */
3394 snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3396 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3397 if (rte_firmware_read(fw_name, &fw_buf, &fsize) == 0)
3400 /* Finally try the card type and media */
3401 snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3402 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3403 if (rte_firmware_read(fw_name, &fw_buf, &fsize) < 0) {
3404 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3409 PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %zu",
3412 PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3413 nfp_nsp_load_fw(nsp, fw_buf, fsize);
3414 PMD_DRV_LOG(INFO, "Done");
3421 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3422 struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3424 struct nfp_nsp *nsp;
3425 const char *nfp_fw_model;
3426 char card_desc[100];
3429 nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3432 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3434 PMD_DRV_LOG(ERR, "firmware model NOT found");
3438 if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3439 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3440 nfp_eth_table->count);
3444 PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3445 nfp_eth_table->count);
3447 PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3449 snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3450 nfp_fw_model, nfp_eth_table->count,
3451 nfp_eth_table->ports[0].speed / 1000);
3453 nsp = nfp_nsp_open(cpp);
3455 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3459 nfp_nsp_device_soft_reset(nsp);
3460 err = nfp_fw_upload(dev, nsp, card_desc);
3466 static int nfp_init_phyports(struct nfp_pf_dev *pf_dev)
3468 struct nfp_net_hw *hw;
3469 struct rte_eth_dev *eth_dev;
3470 struct nfp_eth_table *nfp_eth_table = NULL;
3474 nfp_eth_table = nfp_eth_read_ports(pf_dev->cpp);
3475 if (!nfp_eth_table) {
3476 PMD_INIT_LOG(ERR, "Error reading NFP ethernet table");
3481 /* Loop through all physical ports on PF */
3482 for (i = 0; i < pf_dev->total_phyports; i++) {
3483 const unsigned int numa_node = rte_socket_id();
3484 char port_name[RTE_ETH_NAME_MAX_LEN];
3486 snprintf(port_name, sizeof(port_name), "%s_port%d",
3487 pf_dev->pci_dev->device.name, i);
3489 /* Allocate a eth_dev for this phyport */
3490 eth_dev = rte_eth_dev_allocate(port_name);
3496 /* Allocate memory for this phyport */
3497 eth_dev->data->dev_private =
3498 rte_zmalloc_socket(port_name, sizeof(struct nfp_net_hw),
3499 RTE_CACHE_LINE_SIZE, numa_node);
3500 if (!eth_dev->data->dev_private) {
3502 rte_eth_dev_release_port(eth_dev);
3506 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3508 /* Add this device to the PF's array of physical ports */
3509 pf_dev->ports[i] = hw;
3511 hw->pf_dev = pf_dev;
3512 hw->cpp = pf_dev->cpp;
3513 hw->eth_dev = eth_dev;
3515 hw->nfp_idx = nfp_eth_table->ports[i].index;
3516 hw->is_phyport = true;
3518 eth_dev->device = &pf_dev->pci_dev->device;
3520 /* ctrl/tx/rx BAR mappings and remaining init happens in
3523 ret = nfp_net_init(eth_dev);
3530 rte_eth_dev_probing_finish(eth_dev);
3532 } /* End loop, all ports on this PF */
3534 goto eth_table_cleanup;
3537 for (i = 0; i < pf_dev->total_phyports; i++) {
3538 if (pf_dev->ports[i] && pf_dev->ports[i]->eth_dev) {
3539 struct rte_eth_dev *tmp_dev;
3540 tmp_dev = pf_dev->ports[i]->eth_dev;
3541 rte_eth_dev_release_port(tmp_dev);
3542 pf_dev->ports[i] = NULL;
3546 free(nfp_eth_table);
3551 static void nfp_register_cpp_service(struct nfp_cpp *cpp)
3553 uint32_t *cpp_service_id = NULL;
3554 struct rte_service_spec service;
3556 memset(&service, 0, sizeof(struct rte_service_spec));
3557 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3558 service.callback = nfp_cpp_bridge_service_func;
3559 service.callback_userdata = (void *)cpp;
3561 if (rte_service_component_register(&service,
3563 RTE_LOG(WARNING, PMD, "NFP CPP bridge service register() failed");
3565 RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3568 static int nfp_pf_init(struct rte_pci_device *pci_dev)
3570 struct nfp_pf_dev *pf_dev = NULL;
3571 struct nfp_cpp *cpp;
3572 struct nfp_hwinfo *hwinfo;
3573 struct nfp_rtsym_table *sym_tbl;
3574 struct nfp_eth_table *nfp_eth_table = NULL;
3575 char name[RTE_ETH_NAME_MAX_LEN];
3584 * When device bound to UIO, the device could be used, by mistake,
3585 * by two DPDK apps, and the UIO driver does not avoid it. This
3586 * could lead to a serious problem when configuring the NFP CPP
3587 * interface. Here we avoid this telling to the CPP init code to
3588 * use a lock file if UIO is being used.
3590 if (pci_dev->kdrv == RTE_PCI_KDRV_VFIO)
3591 cpp = nfp_cpp_from_device_name(pci_dev, 0);
3593 cpp = nfp_cpp_from_device_name(pci_dev, 1);
3596 PMD_INIT_LOG(ERR, "A CPP handle can not be obtained");
3601 hwinfo = nfp_hwinfo_read(cpp);
3603 PMD_INIT_LOG(ERR, "Error reading hwinfo table");
3608 nfp_eth_table = nfp_eth_read_ports(cpp);
3609 if (!nfp_eth_table) {
3610 PMD_INIT_LOG(ERR, "Error reading NFP ethernet table");
3612 goto hwinfo_cleanup;
3615 if (nfp_fw_setup(pci_dev, cpp, nfp_eth_table, hwinfo)) {
3616 PMD_INIT_LOG(ERR, "Error when uploading firmware");
3618 goto eth_table_cleanup;
3621 /* Now the symbol table should be there */
3622 sym_tbl = nfp_rtsym_table_read(cpp);
3624 PMD_INIT_LOG(ERR, "Something is wrong with the firmware"
3627 goto eth_table_cleanup;
3630 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3631 if (total_ports != (int)nfp_eth_table->count) {
3632 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3634 goto sym_tbl_cleanup;
3637 PMD_INIT_LOG(INFO, "Total physical ports: %d", total_ports);
3639 if (total_ports <= 0 || total_ports > 8) {
3640 PMD_INIT_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3642 goto sym_tbl_cleanup;
3644 /* Allocate memory for the PF "device" */
3645 snprintf(name, sizeof(name), "nfp_pf%d", 0);
3646 pf_dev = rte_zmalloc(name, sizeof(*pf_dev), 0);
3649 goto sym_tbl_cleanup;
3652 /* Populate the newly created PF device */
3654 pf_dev->hwinfo = hwinfo;
3655 pf_dev->sym_tbl = sym_tbl;
3656 pf_dev->total_phyports = total_ports;
3658 if (total_ports > 1)
3659 pf_dev->multiport = true;
3661 pf_dev->pci_dev = pci_dev;
3663 /* Map the symbol table */
3664 pf_dev->ctrl_bar = nfp_rtsym_map(pf_dev->sym_tbl, "_pf0_net_bar0",
3665 pf_dev->total_phyports * 32768,
3666 &pf_dev->ctrl_area);
3667 if (!pf_dev->ctrl_bar) {
3668 PMD_INIT_LOG(ERR, "nfp_rtsym_map fails for _pf0_net_ctrl_bar");
3673 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", pf_dev->ctrl_bar);
3675 /* configure access to tx/rx vNIC BARs */
3676 pf_dev->hw_queues = nfp_cpp_map_area(pf_dev->cpp, 0, 0,
3678 NFP_QCP_QUEUE_AREA_SZ,
3679 &pf_dev->hwqueues_area);
3680 if (!pf_dev->hw_queues) {
3681 PMD_INIT_LOG(ERR, "nfp_rtsym_map fails for net.qc");
3683 goto ctrl_area_cleanup;
3686 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p", pf_dev->hw_queues);
3688 /* Initialize and prep physical ports now
3689 * This will loop through all physical ports
3691 ret = nfp_init_phyports(pf_dev);
3693 PMD_INIT_LOG(ERR, "Could not create physical ports");
3694 goto hwqueues_cleanup;
3697 /* register the CPP bridge service here for primary use */
3698 nfp_register_cpp_service(pf_dev->cpp);
3703 nfp_cpp_area_free(pf_dev->hwqueues_area);
3705 nfp_cpp_area_free(pf_dev->ctrl_area);
3711 free(nfp_eth_table);
3719 * When attaching to the NFP4000/6000 PF on a secondary process there
3720 * is no need to initialize the PF again. Only minimal work is required
3723 static int nfp_pf_secondary_init(struct rte_pci_device *pci_dev)
3725 struct nfp_cpp *cpp;
3726 struct nfp_rtsym_table *sym_tbl;
3735 * When device bound to UIO, the device could be used, by mistake,
3736 * by two DPDK apps, and the UIO driver does not avoid it. This
3737 * could lead to a serious problem when configuring the NFP CPP
3738 * interface. Here we avoid this telling to the CPP init code to
3739 * use a lock file if UIO is being used.
3741 if (pci_dev->kdrv == RTE_PCI_KDRV_VFIO)
3742 cpp = nfp_cpp_from_device_name(pci_dev, 0);
3744 cpp = nfp_cpp_from_device_name(pci_dev, 1);
3747 PMD_INIT_LOG(ERR, "A CPP handle can not be obtained");
3752 * We don't have access to the PF created in the primary process
3753 * here so we have to read the number of ports from firmware
3755 sym_tbl = nfp_rtsym_table_read(cpp);
3757 PMD_INIT_LOG(ERR, "Something is wrong with the firmware"
3762 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3764 for (i = 0; i < total_ports; i++) {
3765 struct rte_eth_dev *eth_dev;
3766 char port_name[RTE_ETH_NAME_MAX_LEN];
3768 snprintf(port_name, sizeof(port_name), "%s_port%d",
3769 pci_dev->device.name, i);
3771 PMD_DRV_LOG(DEBUG, "Secondary attaching to port %s",
3773 eth_dev = rte_eth_dev_attach_secondary(port_name);
3776 "secondary process attach failed, "
3777 "ethdev doesn't exist");
3780 eth_dev->process_private = cpp;
3781 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
3782 eth_dev->rx_queue_count = nfp_net_rx_queue_count;
3783 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
3784 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
3785 rte_eth_dev_probing_finish(eth_dev);
3788 /* Register the CPP bridge service for the secondary too */
3789 nfp_register_cpp_service(cpp);
3794 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3795 struct rte_pci_device *dev)
3797 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3798 return nfp_pf_init(dev);
3800 return nfp_pf_secondary_init(dev);
3803 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3805 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3806 PCI_DEVICE_ID_NFP4000_PF_NIC)
3809 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3810 PCI_DEVICE_ID_NFP6000_PF_NIC)
3817 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3819 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3820 PCI_DEVICE_ID_NFP6000_VF_NIC)
3827 static int nfp_pci_uninit(struct rte_eth_dev *eth_dev)
3829 struct rte_pci_device *pci_dev;
3832 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3834 if (pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC ||
3835 pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC) {
3836 /* Free up all physical ports under PF */
3837 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3838 rte_eth_dev_close(port_id);
3840 * Ports can be closed and freed but hotplugging is not
3841 * currently supported
3846 /* VF cleanup, just free private port data */
3847 return nfp_net_close(eth_dev);
3850 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3851 struct rte_pci_device *pci_dev)
3853 return rte_eth_dev_pci_generic_probe(pci_dev,
3854 sizeof(struct nfp_net_adapter), nfp_net_init);
3857 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3859 return rte_eth_dev_pci_generic_remove(pci_dev, nfp_pci_uninit);
3862 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3863 .id_table = pci_id_nfp_pf_net_map,
3864 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3865 .probe = nfp_pf_pci_probe,
3866 .remove = eth_nfp_pci_remove,
3869 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3870 .id_table = pci_id_nfp_vf_net_map,
3871 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3872 .probe = eth_nfp_pci_probe,
3873 .remove = eth_nfp_pci_remove,
3876 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3877 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3878 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3879 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3880 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3881 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3882 RTE_LOG_REGISTER_SUFFIX(nfp_logtype_init, init, NOTICE);
3883 RTE_LOG_REGISTER_SUFFIX(nfp_logtype_driver, driver, NOTICE);
3886 * c-file-style: "Linux"
3887 * indent-tabs-mode: t