2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev_driver.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
58 #include "nfpcore/nfp_cpp.h"
59 #include "nfpcore/nfp_nffw.h"
60 #include "nfpcore/nfp_hwinfo.h"
61 #include "nfpcore/nfp_mip.h"
62 #include "nfpcore/nfp_rtsym.h"
63 #include "nfpcore/nfp_nsp.h"
65 #include "nfp_net_pmd.h"
66 #include "nfp_net_logs.h"
67 #include "nfp_net_ctrl.h"
70 static void nfp_net_close(struct rte_eth_dev *dev);
71 static int nfp_net_configure(struct rte_eth_dev *dev);
72 static void nfp_net_dev_interrupt_handler(void *param);
73 static void nfp_net_dev_interrupt_delayed_handler(void *param);
74 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
75 static void nfp_net_infos_get(struct rte_eth_dev *dev,
76 struct rte_eth_dev_info *dev_info);
77 static int nfp_net_init(struct rte_eth_dev *eth_dev);
78 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
79 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
80 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
81 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
82 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
84 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
86 static void nfp_net_rx_queue_release(void *rxq);
87 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_rxconf *rx_conf,
90 struct rte_mempool *mp);
91 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
92 static void nfp_net_tx_queue_release(void *txq);
93 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
94 uint16_t nb_desc, unsigned int socket_id,
95 const struct rte_eth_txconf *tx_conf);
96 static int nfp_net_start(struct rte_eth_dev *dev);
97 static int nfp_net_stats_get(struct rte_eth_dev *dev,
98 struct rte_eth_stats *stats);
99 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
100 static void nfp_net_stop(struct rte_eth_dev *dev);
101 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
104 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
105 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
106 struct rte_eth_rss_conf *rss_conf);
107 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
108 struct rte_eth_rss_reta_entry64 *reta_conf,
110 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
111 struct rte_eth_rss_conf *rss_conf);
112 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
113 struct ether_addr *mac_addr);
115 /* The offset of the queue controller queues in the PCIe Target */
116 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
118 /* Maximum value which can be added to a queue with one transaction */
119 #define NFP_QCP_MAX_ADD 0x7f
121 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
122 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
124 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
126 NFP_QCP_READ_PTR = 0,
131 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
132 * @q: Base address for queue structure
133 * @ptr: Add to the Read or Write pointer
134 * @val: Value to add to the queue pointer
136 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
139 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
143 if (ptr == NFP_QCP_READ_PTR)
144 off = NFP_QCP_QUEUE_ADD_RPTR;
146 off = NFP_QCP_QUEUE_ADD_WPTR;
148 while (val > NFP_QCP_MAX_ADD) {
149 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
150 val -= NFP_QCP_MAX_ADD;
153 nn_writel(rte_cpu_to_le_32(val), q + off);
157 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
158 * @q: Base address for queue structure
159 * @ptr: Read or Write pointer
161 static inline uint32_t
162 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
167 if (ptr == NFP_QCP_READ_PTR)
168 off = NFP_QCP_QUEUE_STS_LO;
170 off = NFP_QCP_QUEUE_STS_HI;
172 val = rte_cpu_to_le_32(nn_readl(q + off));
174 if (ptr == NFP_QCP_READ_PTR)
175 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
177 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
181 * Functions to read/write from/to Config BAR
182 * Performs any endian conversion necessary.
184 static inline uint8_t
185 nn_cfg_readb(struct nfp_net_hw *hw, int off)
187 return nn_readb(hw->ctrl_bar + off);
191 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
193 nn_writeb(val, hw->ctrl_bar + off);
196 static inline uint32_t
197 nn_cfg_readl(struct nfp_net_hw *hw, int off)
199 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
203 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
205 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
208 static inline uint64_t
209 nn_cfg_readq(struct nfp_net_hw *hw, int off)
211 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
215 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
217 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
221 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
225 if (rxq->rxbufs == NULL)
228 for (i = 0; i < rxq->rx_count; i++) {
229 if (rxq->rxbufs[i].mbuf) {
230 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
231 rxq->rxbufs[i].mbuf = NULL;
237 nfp_net_rx_queue_release(void *rx_queue)
239 struct nfp_net_rxq *rxq = rx_queue;
242 nfp_net_rx_queue_release_mbufs(rxq);
243 rte_free(rxq->rxbufs);
249 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
251 nfp_net_rx_queue_release_mbufs(rxq);
257 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
261 if (txq->txbufs == NULL)
264 for (i = 0; i < txq->tx_count; i++) {
265 if (txq->txbufs[i].mbuf) {
266 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
267 txq->txbufs[i].mbuf = NULL;
273 nfp_net_tx_queue_release(void *tx_queue)
275 struct nfp_net_txq *txq = tx_queue;
278 nfp_net_tx_queue_release_mbufs(txq);
279 rte_free(txq->txbufs);
285 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
287 nfp_net_tx_queue_release_mbufs(txq);
293 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
297 struct timespec wait;
299 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
302 if (hw->qcp_cfg == NULL)
303 rte_panic("Bad configuration queue pointer\n");
305 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
308 wait.tv_nsec = 1000000;
310 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
312 /* Poll update field, waiting for NFP to ack the config */
313 for (cnt = 0; ; cnt++) {
314 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
317 if (new & NFP_NET_CFG_UPDATE_ERR) {
318 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
321 if (cnt >= NFP_NET_POLL_TIMEOUT) {
322 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
323 " %dms", update, cnt);
324 rte_panic("Exiting\n");
326 nanosleep(&wait, 0); /* waiting for a 1ms */
328 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
333 * Reconfigure the NIC
334 * @nn: device to reconfigure
335 * @ctrl: The value for the ctrl field in the BAR config
336 * @update: The value for the update field in the BAR config
338 * Write the update word to the BAR and ping the reconfig queue. Then poll
339 * until the firmware has acknowledged the update by zeroing the update word.
342 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
346 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
349 rte_spinlock_lock(&hw->reconfig_lock);
351 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
352 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
356 err = __nfp_net_reconfig(hw, update);
358 rte_spinlock_unlock(&hw->reconfig_lock);
364 * Reconfig errors imply situations where they can be handled.
365 * Otherwise, rte_panic is called inside __nfp_net_reconfig
367 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
373 * Configure an Ethernet device. This function must be invoked first
374 * before any other function in the Ethernet API. This function can
375 * also be re-invoked when a device is in the stopped state.
378 nfp_net_configure(struct rte_eth_dev *dev)
380 struct rte_eth_conf *dev_conf;
381 struct rte_eth_rxmode *rxmode;
382 struct rte_eth_txmode *txmode;
383 struct nfp_net_hw *hw;
385 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
388 * A DPDK app sends info about how many queues to use and how
389 * those queues need to be configured. This is used by the
390 * DPDK core and it makes sure no more queues than those
391 * advertised by the driver are requested. This function is
392 * called after that internal process
395 PMD_INIT_LOG(DEBUG, "Configure");
397 dev_conf = &dev->data->dev_conf;
398 rxmode = &dev_conf->rxmode;
399 txmode = &dev_conf->txmode;
401 /* Checking TX mode */
402 if (txmode->mq_mode) {
403 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
407 /* Checking RX mode */
408 if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
409 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
410 PMD_INIT_LOG(INFO, "RSS not supported");
414 /* Checking RX offloads */
415 if (rxmode->offloads & DEV_RX_OFFLOAD_HEADER_SPLIT) {
416 PMD_INIT_LOG(INFO, "rxmode does not support split header");
420 if ((rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) &&
421 !(hw->cap & NFP_NET_CFG_CTRL_RXCSUM))
422 PMD_INIT_LOG(INFO, "RXCSUM not supported");
424 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
425 PMD_INIT_LOG(INFO, "VLAN filter not supported");
429 if ((rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) &&
430 !(hw->cap & NFP_NET_CFG_CTRL_RXVLAN)) {
431 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
435 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
436 PMD_INIT_LOG(INFO, "VLAN extended not supported");
440 if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
441 PMD_INIT_LOG(INFO, "LRO not supported");
445 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP) {
446 PMD_INIT_LOG(INFO, "QINQ STRIP not supported");
450 if (rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) {
451 PMD_INIT_LOG(INFO, "Outer IP checksum not supported");
455 if (rxmode->offloads & DEV_RX_OFFLOAD_MACSEC_STRIP) {
456 PMD_INIT_LOG(INFO, "MACSEC strip not supported");
460 if (rxmode->offloads & DEV_RX_OFFLOAD_MACSEC_STRIP) {
461 PMD_INIT_LOG(INFO, "MACSEC strip not supported");
465 if (!(rxmode->offloads & DEV_RX_OFFLOAD_CRC_STRIP))
466 PMD_INIT_LOG(INFO, "HW does strip CRC. No configurable!");
468 if ((rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) &&
469 !(hw->cap & NFP_NET_CFG_CTRL_SCATTER)) {
470 PMD_INIT_LOG(INFO, "Scatter not supported");
474 if (rxmode->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
475 PMD_INIT_LOG(INFO, "timestamp offfload not supported");
479 if (rxmode->offloads & DEV_RX_OFFLOAD_SECURITY) {
480 PMD_INIT_LOG(INFO, "security offload not supported");
484 /* checking TX offloads */
485 if ((txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT) &&
486 !(hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
487 PMD_INIT_LOG(INFO, "vlan insert offload not supported");
491 if ((txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) &&
492 !(hw->cap & NFP_NET_CFG_CTRL_TXCSUM)) {
493 PMD_INIT_LOG(INFO, "TX checksum offload not supported");
497 if (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) {
498 PMD_INIT_LOG(INFO, "TX SCTP checksum offload not supported");
502 if ((txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) &&
503 !(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)) {
504 PMD_INIT_LOG(INFO, "TSO TCP offload not supported");
508 if (txmode->offloads & DEV_TX_OFFLOAD_UDP_TSO) {
509 PMD_INIT_LOG(INFO, "TSO UDP offload not supported");
513 if (txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) {
514 PMD_INIT_LOG(INFO, "TX outer checksum offload not supported");
518 if (txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT) {
519 PMD_INIT_LOG(INFO, "QINQ insert offload not supported");
523 if (txmode->offloads & DEV_TX_OFFLOAD_VXLAN_TNL_TSO ||
524 txmode->offloads & DEV_TX_OFFLOAD_GRE_TNL_TSO ||
525 txmode->offloads & DEV_TX_OFFLOAD_IPIP_TNL_TSO ||
526 txmode->offloads & DEV_TX_OFFLOAD_GENEVE_TNL_TSO) {
527 PMD_INIT_LOG(INFO, "tunneling offload not supported");
531 if (txmode->offloads & DEV_TX_OFFLOAD_MACSEC_INSERT) {
532 PMD_INIT_LOG(INFO, "TX MACSEC offload not supported");
536 if (txmode->offloads & DEV_TX_OFFLOAD_MT_LOCKFREE) {
537 PMD_INIT_LOG(INFO, "multiqueue lockfree not supported");
541 if ((txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) &&
542 !(hw->cap & NFP_NET_CFG_CTRL_GATHER)) {
543 PMD_INIT_LOG(INFO, "TX multisegs not supported");
547 if (txmode->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
548 PMD_INIT_LOG(INFO, "mbuf fast-free not supported");
552 if (txmode->offloads & DEV_TX_OFFLOAD_SECURITY) {
553 PMD_INIT_LOG(INFO, "TX security offload not supported");
561 nfp_net_enable_queues(struct rte_eth_dev *dev)
563 struct nfp_net_hw *hw;
564 uint64_t enabled_queues = 0;
567 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
569 /* Enabling the required TX queues in the device */
570 for (i = 0; i < dev->data->nb_tx_queues; i++)
571 enabled_queues |= (1 << i);
573 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
577 /* Enabling the required RX queues in the device */
578 for (i = 0; i < dev->data->nb_rx_queues; i++)
579 enabled_queues |= (1 << i);
581 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
585 nfp_net_disable_queues(struct rte_eth_dev *dev)
587 struct nfp_net_hw *hw;
588 uint32_t new_ctrl, update = 0;
590 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
592 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
593 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
595 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
596 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
597 NFP_NET_CFG_UPDATE_MSIX;
599 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
600 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
602 /* If an error when reconfig we avoid to change hw state */
603 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
610 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
614 for (i = 0; i < dev->data->nb_rx_queues; i++) {
615 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
622 nfp_net_params_setup(struct nfp_net_hw *hw)
624 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
625 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
629 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
631 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
634 #define ETH_ADDR_LEN 6
637 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
641 for (i = 0; i < ETH_ADDR_LEN; i++)
646 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
648 struct nfp_eth_table *nfp_eth_table;
650 nfp_eth_table = nfp_eth_read_ports(hw->cpp);
652 * hw points to port0 private data. We need hw now pointing to
656 nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
657 (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
664 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
668 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
669 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
671 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
672 memcpy(&hw->mac_addr[4], &tmp, 2);
676 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
678 uint32_t mac0 = *(uint32_t *)mac;
681 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
684 mac1 = *(uint16_t *)mac;
685 nn_writew(rte_cpu_to_be_16(mac1),
686 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
690 nfp_set_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
692 struct nfp_net_hw *hw;
693 uint32_t update, ctrl;
695 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
696 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
697 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
698 PMD_INIT_LOG(INFO, "MAC address unable to change when"
703 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
704 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
707 /* Writing new MAC to the specific port BAR address */
708 nfp_net_write_mac(hw, (uint8_t *)mac_addr);
710 /* Signal the NIC about the change */
711 update = NFP_NET_CFG_UPDATE_MACADDR;
712 ctrl = hw->ctrl | NFP_NET_CFG_CTRL_LIVE_ADDR;
713 if (nfp_net_reconfig(hw, ctrl, update) < 0) {
714 PMD_INIT_LOG(INFO, "MAC address update failed");
721 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
722 struct rte_intr_handle *intr_handle)
724 struct nfp_net_hw *hw;
727 if (!intr_handle->intr_vec) {
728 intr_handle->intr_vec =
729 rte_zmalloc("intr_vec",
730 dev->data->nb_rx_queues * sizeof(int), 0);
731 if (!intr_handle->intr_vec) {
732 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
733 " intr_vec", dev->data->nb_rx_queues);
738 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
740 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
741 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
742 /* UIO just supports one queue and no LSC*/
743 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
744 intr_handle->intr_vec[0] = 0;
746 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
747 for (i = 0; i < dev->data->nb_rx_queues; i++) {
749 * The first msix vector is reserved for non
752 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
753 intr_handle->intr_vec[i] = i + 1;
754 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
755 intr_handle->intr_vec[i]);
759 /* Avoiding TX interrupts */
760 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
765 nfp_check_offloads(struct rte_eth_dev *dev)
767 struct nfp_net_hw *hw;
768 struct rte_eth_conf *dev_conf;
769 struct rte_eth_rxmode *rxmode;
770 struct rte_eth_txmode *txmode;
773 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
775 dev_conf = &dev->data->dev_conf;
776 rxmode = &dev_conf->rxmode;
777 txmode = &dev_conf->txmode;
779 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
780 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
781 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
784 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
785 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
786 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
789 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
790 hw->mtu = rxmode->max_rx_pkt_len;
792 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
793 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
796 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
797 ctrl |= NFP_NET_CFG_CTRL_L2BC;
800 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
801 ctrl |= NFP_NET_CFG_CTRL_L2MC;
803 /* TX checksum offload */
804 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
805 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
806 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
807 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
810 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
811 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
812 ctrl |= NFP_NET_CFG_CTRL_LSO;
814 ctrl |= NFP_NET_CFG_CTRL_LSO2;
818 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
819 ctrl |= NFP_NET_CFG_CTRL_GATHER;
825 nfp_net_start(struct rte_eth_dev *dev)
827 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
828 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
829 uint32_t new_ctrl, update = 0;
830 struct nfp_net_hw *hw;
831 struct rte_eth_conf *dev_conf;
832 struct rte_eth_rxmode *rxmode;
833 uint32_t intr_vector;
836 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
838 PMD_INIT_LOG(DEBUG, "Start");
840 /* Disabling queues just in case... */
841 nfp_net_disable_queues(dev);
843 /* Enabling the required queues in the device */
844 nfp_net_enable_queues(dev);
846 /* check and configure queue intr-vector mapping */
847 if (dev->data->dev_conf.intr_conf.rxq != 0) {
848 if (hw->pf_multiport_enabled) {
849 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
850 "with NFP multiport PF");
853 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
855 * Better not to share LSC with RX interrupts.
856 * Unregistering LSC interrupt handler
858 rte_intr_callback_unregister(&pci_dev->intr_handle,
859 nfp_net_dev_interrupt_handler, (void *)dev);
861 if (dev->data->nb_rx_queues > 1) {
862 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
863 "supports 1 queue with UIO");
867 intr_vector = dev->data->nb_rx_queues;
868 if (rte_intr_efd_enable(intr_handle, intr_vector))
871 nfp_configure_rx_interrupt(dev, intr_handle);
872 update = NFP_NET_CFG_UPDATE_MSIX;
875 rte_intr_enable(intr_handle);
877 new_ctrl = nfp_check_offloads(dev);
879 /* Writing configuration parameters in the device */
880 nfp_net_params_setup(hw);
882 dev_conf = &dev->data->dev_conf;
883 rxmode = &dev_conf->rxmode;
885 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
886 nfp_net_rss_config_default(dev);
887 update |= NFP_NET_CFG_UPDATE_RSS;
888 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
892 new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
894 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
896 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
897 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
899 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
900 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
904 * Allocating rte mbuffs for configured rx queues.
905 * This requires queues being enabled before
907 if (nfp_net_rx_freelist_setup(dev) < 0) {
913 /* Configure the physical port up */
914 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
922 * An error returned by this function should mean the app
923 * exiting and then the system releasing all the memory
924 * allocated even memory coming from hugepages.
926 * The device could be enabled at this point with some queues
927 * ready for getting packets. This is true if the call to
928 * nfp_net_rx_freelist_setup() succeeds for some queues but
929 * fails for subsequent queues.
931 * This should make the app exiting but better if we tell the
934 nfp_net_disable_queues(dev);
939 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
941 nfp_net_stop(struct rte_eth_dev *dev)
944 struct nfp_net_hw *hw;
946 PMD_INIT_LOG(DEBUG, "Stop");
948 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
950 nfp_net_disable_queues(dev);
953 for (i = 0; i < dev->data->nb_tx_queues; i++) {
954 nfp_net_reset_tx_queue(
955 (struct nfp_net_txq *)dev->data->tx_queues[i]);
958 for (i = 0; i < dev->data->nb_rx_queues; i++) {
959 nfp_net_reset_rx_queue(
960 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
964 /* Configure the physical port down */
965 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
968 /* Reset and stop device. The device can not be restarted. */
970 nfp_net_close(struct rte_eth_dev *dev)
972 struct nfp_net_hw *hw;
973 struct rte_pci_device *pci_dev;
976 PMD_INIT_LOG(DEBUG, "Close");
978 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
979 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
982 * We assume that the DPDK application is stopping all the
983 * threads/queues before calling the device close function.
986 nfp_net_disable_queues(dev);
989 for (i = 0; i < dev->data->nb_tx_queues; i++) {
990 nfp_net_reset_tx_queue(
991 (struct nfp_net_txq *)dev->data->tx_queues[i]);
994 for (i = 0; i < dev->data->nb_rx_queues; i++) {
995 nfp_net_reset_rx_queue(
996 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
999 rte_intr_disable(&pci_dev->intr_handle);
1000 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
1002 /* unregister callback func from eal lib */
1003 rte_intr_callback_unregister(&pci_dev->intr_handle,
1004 nfp_net_dev_interrupt_handler,
1008 * The ixgbe PMD driver disables the pcie master on the
1009 * device. The i40e does not...
1014 nfp_net_promisc_enable(struct rte_eth_dev *dev)
1016 uint32_t new_ctrl, update = 0;
1017 struct nfp_net_hw *hw;
1019 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
1021 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1023 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
1024 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
1028 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
1029 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
1033 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
1034 update = NFP_NET_CFG_UPDATE_GEN;
1037 * DPDK sets promiscuous mode on just after this call assuming
1038 * it can not fail ...
1040 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
1043 hw->ctrl = new_ctrl;
1047 nfp_net_promisc_disable(struct rte_eth_dev *dev)
1049 uint32_t new_ctrl, update = 0;
1050 struct nfp_net_hw *hw;
1052 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1054 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
1055 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
1059 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
1060 update = NFP_NET_CFG_UPDATE_GEN;
1063 * DPDK sets promiscuous mode off just before this call
1064 * assuming it can not fail ...
1066 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
1069 hw->ctrl = new_ctrl;
1073 * return 0 means link status changed, -1 means not changed
1075 * Wait to complete is needed as it can take up to 9 seconds to get the Link
1079 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1081 struct nfp_net_hw *hw;
1082 struct rte_eth_link link;
1083 uint32_t nn_link_status;
1086 static const uint32_t ls_to_ethtool[] = {
1087 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
1088 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
1089 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
1090 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
1091 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
1092 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
1093 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
1094 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
1097 PMD_DRV_LOG(DEBUG, "Link update\n");
1099 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1101 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1103 memset(&link, 0, sizeof(struct rte_eth_link));
1105 if (nn_link_status & NFP_NET_CFG_STS_LINK)
1106 link.link_status = ETH_LINK_UP;
1108 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1110 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1111 NFP_NET_CFG_STS_LINK_RATE_MASK;
1113 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1114 link.link_speed = ETH_SPEED_NUM_NONE;
1116 link.link_speed = ls_to_ethtool[nn_link_status];
1118 ret = rte_eth_linkstatus_set(dev, &link);
1120 if (link.link_status)
1121 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
1123 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
1129 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1132 struct nfp_net_hw *hw;
1133 struct rte_eth_stats nfp_dev_stats;
1135 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1137 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1139 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1141 /* reading per RX ring stats */
1142 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1143 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1146 nfp_dev_stats.q_ipackets[i] =
1147 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1149 nfp_dev_stats.q_ipackets[i] -=
1150 hw->eth_stats_base.q_ipackets[i];
1152 nfp_dev_stats.q_ibytes[i] =
1153 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1155 nfp_dev_stats.q_ibytes[i] -=
1156 hw->eth_stats_base.q_ibytes[i];
1159 /* reading per TX ring stats */
1160 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1161 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1164 nfp_dev_stats.q_opackets[i] =
1165 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1167 nfp_dev_stats.q_opackets[i] -=
1168 hw->eth_stats_base.q_opackets[i];
1170 nfp_dev_stats.q_obytes[i] =
1171 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1173 nfp_dev_stats.q_obytes[i] -=
1174 hw->eth_stats_base.q_obytes[i];
1177 nfp_dev_stats.ipackets =
1178 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1180 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1182 nfp_dev_stats.ibytes =
1183 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1185 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1187 nfp_dev_stats.opackets =
1188 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1190 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1192 nfp_dev_stats.obytes =
1193 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1195 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1197 /* reading general device stats */
1198 nfp_dev_stats.ierrors =
1199 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1201 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1203 nfp_dev_stats.oerrors =
1204 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1206 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1208 /* RX ring mbuf allocation failures */
1209 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1211 nfp_dev_stats.imissed =
1212 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1214 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1217 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1224 nfp_net_stats_reset(struct rte_eth_dev *dev)
1227 struct nfp_net_hw *hw;
1229 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1232 * hw->eth_stats_base records the per counter starting point.
1233 * Lets update it now
1236 /* reading per RX ring stats */
1237 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1238 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1241 hw->eth_stats_base.q_ipackets[i] =
1242 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1244 hw->eth_stats_base.q_ibytes[i] =
1245 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1248 /* reading per TX ring stats */
1249 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1250 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1253 hw->eth_stats_base.q_opackets[i] =
1254 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1256 hw->eth_stats_base.q_obytes[i] =
1257 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1260 hw->eth_stats_base.ipackets =
1261 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1263 hw->eth_stats_base.ibytes =
1264 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1266 hw->eth_stats_base.opackets =
1267 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1269 hw->eth_stats_base.obytes =
1270 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1272 /* reading general device stats */
1273 hw->eth_stats_base.ierrors =
1274 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1276 hw->eth_stats_base.oerrors =
1277 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1279 /* RX ring mbuf allocation failures */
1280 dev->data->rx_mbuf_alloc_failed = 0;
1282 hw->eth_stats_base.imissed =
1283 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1287 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1289 struct nfp_net_hw *hw;
1291 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1293 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1294 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1295 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1296 dev_info->max_rx_pktlen = hw->max_mtu;
1297 /* Next should change when PF support is implemented */
1298 dev_info->max_mac_addrs = 1;
1300 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1301 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1303 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1304 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1305 DEV_RX_OFFLOAD_UDP_CKSUM |
1306 DEV_RX_OFFLOAD_TCP_CKSUM;
1308 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1310 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1311 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1313 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1314 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1315 DEV_TX_OFFLOAD_UDP_CKSUM |
1316 DEV_TX_OFFLOAD_TCP_CKSUM;
1318 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1319 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1321 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1322 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1324 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1326 .pthresh = DEFAULT_RX_PTHRESH,
1327 .hthresh = DEFAULT_RX_HTHRESH,
1328 .wthresh = DEFAULT_RX_WTHRESH,
1330 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1334 dev_info->default_txconf = (struct rte_eth_txconf) {
1336 .pthresh = DEFAULT_TX_PTHRESH,
1337 .hthresh = DEFAULT_TX_HTHRESH,
1338 .wthresh = DEFAULT_TX_WTHRESH,
1340 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1341 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1344 dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1345 ETH_RSS_NONFRAG_IPV4_UDP |
1346 ETH_RSS_NONFRAG_IPV6_TCP |
1347 ETH_RSS_NONFRAG_IPV6_UDP;
1349 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1350 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1352 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1353 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1354 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1357 static const uint32_t *
1358 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1360 static const uint32_t ptypes[] = {
1361 /* refers to nfp_net_set_hash() */
1362 RTE_PTYPE_INNER_L3_IPV4,
1363 RTE_PTYPE_INNER_L3_IPV6,
1364 RTE_PTYPE_INNER_L3_IPV6_EXT,
1365 RTE_PTYPE_INNER_L4_MASK,
1369 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1375 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1377 struct nfp_net_rxq *rxq;
1378 struct nfp_net_rx_desc *rxds;
1382 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1389 * Other PMDs are just checking the DD bit in intervals of 4
1390 * descriptors and counting all four if the first has the DD
1391 * bit on. Of course, this is not accurate but can be good for
1392 * performance. But ideally that should be done in descriptors
1393 * chunks belonging to the same cache line
1396 while (count < rxq->rx_count) {
1397 rxds = &rxq->rxds[idx];
1398 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1405 if ((idx) == rxq->rx_count)
1413 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1415 struct rte_pci_device *pci_dev;
1416 struct nfp_net_hw *hw;
1419 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1420 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1422 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1425 /* Make sure all updates are written before un-masking */
1427 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1428 NFP_NET_CFG_ICR_UNMASKED);
1433 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1435 struct rte_pci_device *pci_dev;
1436 struct nfp_net_hw *hw;
1439 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1440 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1442 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1445 /* Make sure all updates are written before un-masking */
1447 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1452 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1454 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1455 struct rte_eth_link link;
1457 rte_eth_linkstatus_get(dev, &link);
1458 if (link.link_status)
1459 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1460 dev->data->port_id, link.link_speed,
1461 link.link_duplex == ETH_LINK_FULL_DUPLEX
1462 ? "full-duplex" : "half-duplex");
1464 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1465 dev->data->port_id);
1467 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1468 pci_dev->addr.domain, pci_dev->addr.bus,
1469 pci_dev->addr.devid, pci_dev->addr.function);
1472 /* Interrupt configuration and handling */
1475 * nfp_net_irq_unmask - Unmask an interrupt
1477 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1478 * clear the ICR for the entry.
1481 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1483 struct nfp_net_hw *hw;
1484 struct rte_pci_device *pci_dev;
1486 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1487 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1489 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1490 /* If MSI-X auto-masking is used, clear the entry */
1492 rte_intr_enable(&pci_dev->intr_handle);
1494 /* Make sure all updates are written before un-masking */
1496 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1497 NFP_NET_CFG_ICR_UNMASKED);
1502 nfp_net_dev_interrupt_handler(void *param)
1505 struct rte_eth_link link;
1506 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1508 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1510 rte_eth_linkstatus_get(dev, &link);
1512 nfp_net_link_update(dev, 0);
1515 if (!link.link_status) {
1516 /* handle it 1 sec later, wait it being stable */
1517 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1518 /* likely to down */
1520 /* handle it 4 sec later, wait it being stable */
1521 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1524 if (rte_eal_alarm_set(timeout * 1000,
1525 nfp_net_dev_interrupt_delayed_handler,
1527 RTE_LOG(ERR, PMD, "Error setting alarm");
1529 nfp_net_irq_unmask(dev);
1534 * Interrupt handler which shall be registered for alarm callback for delayed
1535 * handling specific interrupt to wait for the stable nic state. As the NIC
1536 * interrupt state is not stable for nfp after link is just down, it needs
1537 * to wait 4 seconds to get the stable status.
1539 * @param handle Pointer to interrupt handle.
1540 * @param param The address of parameter (struct rte_eth_dev *)
1545 nfp_net_dev_interrupt_delayed_handler(void *param)
1547 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1549 nfp_net_link_update(dev, 0);
1550 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1552 nfp_net_dev_link_status_print(dev);
1555 nfp_net_irq_unmask(dev);
1559 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1561 struct nfp_net_hw *hw;
1563 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1565 /* check that mtu is within the allowed range */
1566 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1569 /* mtu setting is forbidden if port is started */
1570 if (dev->data->dev_started) {
1571 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1572 dev->data->port_id);
1576 /* switch to jumbo mode if needed */
1577 if ((uint32_t)mtu > ETHER_MAX_LEN)
1578 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1580 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1582 /* update max frame size */
1583 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1585 /* writing to configuration space */
1586 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1594 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1595 uint16_t queue_idx, uint16_t nb_desc,
1596 unsigned int socket_id,
1597 const struct rte_eth_rxconf *rx_conf,
1598 struct rte_mempool *mp)
1600 const struct rte_memzone *tz;
1601 struct nfp_net_rxq *rxq;
1602 struct nfp_net_hw *hw;
1603 struct rte_eth_conf *dev_conf;
1604 struct rte_eth_rxmode *rxmode;
1606 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608 PMD_INIT_FUNC_TRACE();
1610 /* Validating number of descriptors */
1611 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1612 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1613 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1614 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1618 dev_conf = &dev->data->dev_conf;
1619 rxmode = &dev_conf->rxmode;
1621 if (rx_conf->offloads != rxmode->offloads) {
1622 RTE_LOG(ERR, PMD, "queue %u rx offloads not as port offloads\n",
1624 RTE_LOG(ERR, PMD, "\tport: %" PRIx64 "\n", rxmode->offloads);
1625 RTE_LOG(ERR, PMD, "\tqueue: %" PRIx64 "\n", rx_conf->offloads);
1630 * Free memory prior to re-allocation if needed. This is the case after
1631 * calling nfp_net_stop
1633 if (dev->data->rx_queues[queue_idx]) {
1634 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1635 dev->data->rx_queues[queue_idx] = NULL;
1638 /* Allocating rx queue data structure */
1639 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1640 RTE_CACHE_LINE_SIZE, socket_id);
1644 /* Hw queues mapping based on firmware confifguration */
1645 rxq->qidx = queue_idx;
1646 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1647 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1648 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1649 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1652 * Tracking mbuf size for detecting a potential mbuf overflow due to
1656 rxq->mbuf_size = rxq->mem_pool->elt_size;
1657 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1658 hw->flbufsz = rxq->mbuf_size;
1660 rxq->rx_count = nb_desc;
1661 rxq->port_id = dev->data->port_id;
1662 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1663 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1665 rxq->drop_en = rx_conf->rx_drop_en;
1668 * Allocate RX ring hardware descriptors. A memzone large enough to
1669 * handle the maximum ring size is allocated in order to allow for
1670 * resizing in later calls to the queue setup function.
1672 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1673 sizeof(struct nfp_net_rx_desc) *
1674 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1678 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1679 nfp_net_rx_queue_release(rxq);
1683 /* Saving physical and virtual addresses for the RX ring */
1684 rxq->dma = (uint64_t)tz->iova;
1685 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1687 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1688 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1689 sizeof(*rxq->rxbufs) * nb_desc,
1690 RTE_CACHE_LINE_SIZE, socket_id);
1691 if (rxq->rxbufs == NULL) {
1692 nfp_net_rx_queue_release(rxq);
1696 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1697 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1699 nfp_net_reset_rx_queue(rxq);
1701 dev->data->rx_queues[queue_idx] = rxq;
1705 * Telling the HW about the physical address of the RX ring and number
1706 * of descriptors in log2 format
1708 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1709 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1715 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1717 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1721 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1724 for (i = 0; i < rxq->rx_count; i++) {
1725 struct nfp_net_rx_desc *rxd;
1726 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1729 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1730 (unsigned)rxq->qidx);
1734 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1736 rxd = &rxq->rxds[i];
1738 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1739 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1741 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1744 /* Make sure all writes are flushed before telling the hardware */
1747 /* Not advertising the whole ring as the firmware gets confused if so */
1748 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1751 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1757 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1758 uint16_t nb_desc, unsigned int socket_id,
1759 const struct rte_eth_txconf *tx_conf)
1761 const struct rte_memzone *tz;
1762 struct nfp_net_txq *txq;
1763 uint16_t tx_free_thresh;
1764 struct nfp_net_hw *hw;
1765 struct rte_eth_conf *dev_conf;
1766 struct rte_eth_txmode *txmode;
1768 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770 PMD_INIT_FUNC_TRACE();
1772 /* Validating number of descriptors */
1773 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1774 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1775 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1776 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1780 dev_conf = &dev->data->dev_conf;
1781 txmode = &dev_conf->txmode;
1783 if (tx_conf->offloads != txmode->offloads) {
1784 RTE_LOG(ERR, PMD, "queue %u tx offloads not as port offloads",
1789 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1790 tx_conf->tx_free_thresh :
1791 DEFAULT_TX_FREE_THRESH);
1793 if (tx_free_thresh > (nb_desc)) {
1795 "tx_free_thresh must be less than the number of TX "
1796 "descriptors. (tx_free_thresh=%u port=%d "
1797 "queue=%d)\n", (unsigned int)tx_free_thresh,
1798 dev->data->port_id, (int)queue_idx);
1803 * Free memory prior to re-allocation if needed. This is the case after
1804 * calling nfp_net_stop
1806 if (dev->data->tx_queues[queue_idx]) {
1807 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1809 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1810 dev->data->tx_queues[queue_idx] = NULL;
1813 /* Allocating tx queue data structure */
1814 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1815 RTE_CACHE_LINE_SIZE, socket_id);
1817 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1822 * Allocate TX ring hardware descriptors. A memzone large enough to
1823 * handle the maximum ring size is allocated in order to allow for
1824 * resizing in later calls to the queue setup function.
1826 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1827 sizeof(struct nfp_net_tx_desc) *
1828 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1831 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1832 nfp_net_tx_queue_release(txq);
1836 txq->tx_count = nb_desc;
1837 txq->tx_free_thresh = tx_free_thresh;
1838 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1839 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1840 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1842 /* queue mapping based on firmware configuration */
1843 txq->qidx = queue_idx;
1844 txq->tx_qcidx = queue_idx * hw->stride_tx;
1845 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1847 txq->port_id = dev->data->port_id;
1849 /* Saving physical and virtual addresses for the TX ring */
1850 txq->dma = (uint64_t)tz->iova;
1851 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1853 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1854 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1855 sizeof(*txq->txbufs) * nb_desc,
1856 RTE_CACHE_LINE_SIZE, socket_id);
1857 if (txq->txbufs == NULL) {
1858 nfp_net_tx_queue_release(txq);
1861 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1862 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1864 nfp_net_reset_tx_queue(txq);
1866 dev->data->tx_queues[queue_idx] = txq;
1870 * Telling the HW about the physical address of the TX ring and number
1871 * of descriptors in log2 format
1873 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1874 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1879 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1881 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1882 struct rte_mbuf *mb)
1885 struct nfp_net_hw *hw = txq->hw;
1887 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1890 ol_flags = mb->ol_flags;
1892 if (!(ol_flags & PKT_TX_TCP_SEG))
1895 txd->l3_offset = mb->l2_len;
1896 txd->l4_offset = mb->l2_len + mb->l3_len;
1897 txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1898 txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1899 txd->flags = PCIE_DESC_TX_LSO;
1906 txd->lso_hdrlen = 0;
1910 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1912 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1913 struct rte_mbuf *mb)
1916 struct nfp_net_hw *hw = txq->hw;
1918 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1921 ol_flags = mb->ol_flags;
1923 /* IPv6 does not need checksum */
1924 if (ol_flags & PKT_TX_IP_CKSUM)
1925 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1927 switch (ol_flags & PKT_TX_L4_MASK) {
1928 case PKT_TX_UDP_CKSUM:
1929 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1931 case PKT_TX_TCP_CKSUM:
1932 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1936 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1937 txd->flags |= PCIE_DESC_TX_CSUM;
1940 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1942 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1943 struct rte_mbuf *mb)
1945 struct nfp_net_hw *hw = rxq->hw;
1947 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1950 /* If IPv4 and IP checksum error, fail */
1951 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1952 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1953 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1955 /* If neither UDP nor TCP return */
1956 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1957 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1960 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1961 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1962 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1964 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1965 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1966 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1969 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1970 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1972 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1975 * nfp_net_set_hash - Set mbuf hash data
1977 * The RSS hash and hash-type are pre-pended to the packet data.
1978 * Extract and decode it and set the mbuf fields.
1981 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1982 struct rte_mbuf *mbuf)
1984 struct nfp_net_hw *hw = rxq->hw;
1985 uint8_t *meta_offset;
1988 uint32_t hash_type = 0;
1990 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1993 /* this is true for new firmwares */
1994 if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1995 (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1996 NFP_DESC_META_LEN(rxd))) {
1999 * <---- 32 bit ----->
2004 * ====================
2007 * Field type word contains up to 8 4bit field types
2008 * A 4bit field type refers to a data field word
2009 * A data field word can have several 4bit field types
2011 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
2012 meta_offset -= NFP_DESC_META_LEN(rxd);
2013 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
2015 /* NFP PMD just supports metadata for hashing */
2016 switch (meta_info & NFP_NET_META_FIELD_MASK) {
2017 case NFP_NET_META_HASH:
2018 /* next field type is about the hash type */
2019 meta_info >>= NFP_NET_META_FIELD_SIZE;
2020 /* hash value is in the data field */
2021 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
2022 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
2025 /* Unsupported metadata can be a performance issue */
2029 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
2032 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
2033 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
2036 mbuf->hash.rss = hash;
2037 mbuf->ol_flags |= PKT_RX_RSS_HASH;
2039 switch (hash_type) {
2040 case NFP_NET_RSS_IPV4:
2041 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
2043 case NFP_NET_RSS_IPV6:
2044 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
2046 case NFP_NET_RSS_IPV6_EX:
2047 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2050 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
2055 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
2057 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
2060 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
2065 * There are some decissions to take:
2066 * 1) How to check DD RX descriptors bit
2067 * 2) How and when to allocate new mbufs
2069 * Current implementation checks just one single DD bit each loop. As each
2070 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
2071 * a single cache line instead. Tests with this change have not shown any
2072 * performance improvement but it requires further investigation. For example,
2073 * depending on which descriptor is next, the number of descriptors could be
2074 * less than 8 for just checking those in the same cache line. This implies
2075 * extra work which could be counterproductive by itself. Indeed, last firmware
2076 * changes are just doing this: writing several descriptors with the DD bit
2077 * for saving PCIe bandwidth and DMA operations from the NFP.
2079 * Mbuf allocation is done when a new packet is received. Then the descriptor
2080 * is automatically linked with the new mbuf and the old one is given to the
2081 * user. The main drawback with this design is mbuf allocation is heavier than
2082 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
2083 * cache point of view it does not seem allocating the mbuf early on as we are
2084 * doing now have any benefit at all. Again, tests with this change have not
2085 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2086 * so looking at the implications of this type of allocation should be studied
2091 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2093 struct nfp_net_rxq *rxq;
2094 struct nfp_net_rx_desc *rxds;
2095 struct nfp_net_rx_buff *rxb;
2096 struct nfp_net_hw *hw;
2097 struct rte_mbuf *mb;
2098 struct rte_mbuf *new_mb;
2104 if (unlikely(rxq == NULL)) {
2106 * DPDK just checks the queue is lower than max queues
2107 * enabled. But the queue needs to be configured
2109 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2117 while (avail < nb_pkts) {
2118 rxb = &rxq->rxbufs[rxq->rd_p];
2119 if (unlikely(rxb == NULL)) {
2120 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2124 rxds = &rxq->rxds[rxq->rd_p];
2125 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2129 * Memory barrier to ensure that we won't do other
2130 * reads before the DD bit.
2135 * We got a packet. Let's alloc a new mbuff for refilling the
2136 * free descriptor ring as soon as possible
2138 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2139 if (unlikely(new_mb == NULL)) {
2140 RTE_LOG_DP(DEBUG, PMD,
2141 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2142 rxq->port_id, (unsigned int)rxq->qidx);
2143 nfp_net_mbuf_alloc_failed(rxq);
2150 * Grab the mbuff and refill the descriptor with the
2151 * previously allocated mbuff
2156 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
2157 rxds->rxd.data_len, rxq->mbuf_size);
2159 /* Size of this segment */
2160 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2161 /* Size of the whole packet. We just support 1 segment */
2162 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2164 if (unlikely((mb->data_len + hw->rx_offset) >
2167 * This should not happen and the user has the
2168 * responsibility of avoiding it. But we have
2169 * to give some info about the error
2171 RTE_LOG_DP(ERR, PMD,
2172 "mbuf overflow likely due to the RX offset.\n"
2173 "\t\tYour mbuf size should have extra space for"
2174 " RX offset=%u bytes.\n"
2175 "\t\tCurrently you just have %u bytes available"
2176 " but the received packet is %u bytes long",
2178 rxq->mbuf_size - hw->rx_offset,
2183 /* Filling the received mbuff with packet info */
2185 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2187 mb->data_off = RTE_PKTMBUF_HEADROOM +
2188 NFP_DESC_META_LEN(rxds);
2190 /* No scatter mode supported */
2194 mb->port = rxq->port_id;
2196 /* Checking the RSS flag */
2197 nfp_net_set_hash(rxq, rxds, mb);
2199 /* Checking the checksum flag */
2200 nfp_net_rx_cksum(rxq, rxds, mb);
2202 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2203 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2204 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2205 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2208 /* Adding the mbuff to the mbuff array passed by the app */
2209 rx_pkts[avail++] = mb;
2211 /* Now resetting and updating the descriptor */
2214 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2216 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2217 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2220 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2227 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
2228 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2230 nb_hold += rxq->nb_rx_hold;
2233 * FL descriptors needs to be written before incrementing the
2234 * FL queue WR pointer
2237 if (nb_hold > rxq->rx_free_thresh) {
2238 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2239 rxq->port_id, (unsigned int)rxq->qidx,
2240 (unsigned)nb_hold, (unsigned)avail);
2241 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2244 rxq->nb_rx_hold = nb_hold;
2250 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2252 * @txq: TX queue to work with
2253 * Returns number of descriptors freed
2256 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2261 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2262 " status\n", txq->qidx);
2264 /* Work out how many packets have been sent */
2265 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2267 if (qcp_rd_p == txq->rd_p) {
2268 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2269 "packets (%u, %u)\n", txq->qidx,
2270 qcp_rd_p, txq->rd_p);
2274 if (qcp_rd_p > txq->rd_p)
2275 todo = qcp_rd_p - txq->rd_p;
2277 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2279 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2280 qcp_rd_p, txq->rd_p, txq->rd_p);
2286 if (unlikely(txq->rd_p >= txq->tx_count))
2287 txq->rd_p -= txq->tx_count;
2292 /* Leaving always free descriptors for avoiding wrapping confusion */
2294 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2296 if (txq->wr_p >= txq->rd_p)
2297 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2299 return txq->rd_p - txq->wr_p - 8;
2303 * nfp_net_txq_full - Check if the TX queue free descriptors
2304 * is below tx_free_threshold
2306 * @txq: TX queue to check
2308 * This function uses the host copy* of read/write pointers
2311 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2313 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2317 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2319 struct nfp_net_txq *txq;
2320 struct nfp_net_hw *hw;
2321 struct nfp_net_tx_desc *txds, txd;
2322 struct rte_mbuf *pkt;
2324 int pkt_size, dma_size;
2325 uint16_t free_descs, issued_descs;
2326 struct rte_mbuf **lmbuf;
2331 txds = &txq->txds[txq->wr_p];
2333 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2334 txq->qidx, txq->wr_p, nb_pkts);
2336 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2337 nfp_net_tx_free_bufs(txq);
2339 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2340 if (unlikely(free_descs == 0))
2347 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2348 txq->qidx, nb_pkts);
2349 /* Sending packets */
2350 while ((i < nb_pkts) && free_descs) {
2351 /* Grabbing the mbuf linked to the current descriptor */
2352 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2353 /* Warming the cache for releasing the mbuf later on */
2354 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2356 pkt = *(tx_pkts + i);
2358 if (unlikely((pkt->nb_segs > 1) &&
2359 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2360 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2361 rte_panic("Multisegment packet unsupported\n");
2364 /* Checking if we have enough descriptors */
2365 if (unlikely(pkt->nb_segs > free_descs))
2369 * Checksum and VLAN flags just in the first descriptor for a
2370 * multisegment packet, but TSO info needs to be in all of them.
2372 txd.data_len = pkt->pkt_len;
2373 nfp_net_tx_tso(txq, &txd, pkt);
2374 nfp_net_tx_cksum(txq, &txd, pkt);
2376 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2377 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2378 txd.flags |= PCIE_DESC_TX_VLAN;
2379 txd.vlan = pkt->vlan_tci;
2383 * mbuf data_len is the data in one segment and pkt_len data
2384 * in the whole packet. When the packet is just one segment,
2385 * then data_len = pkt_len
2387 pkt_size = pkt->pkt_len;
2390 /* Copying TSO, VLAN and cksum info */
2393 /* Releasing mbuf used by this descriptor previously*/
2395 rte_pktmbuf_free_seg(*lmbuf);
2398 * Linking mbuf with descriptor for being released
2399 * next time descriptor is used
2403 dma_size = pkt->data_len;
2404 dma_addr = rte_mbuf_data_iova(pkt);
2405 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2406 "%" PRIx64 "\n", dma_addr);
2408 /* Filling descriptors fields */
2409 txds->dma_len = dma_size;
2410 txds->data_len = txd.data_len;
2411 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2412 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2413 ASSERT(free_descs > 0);
2417 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2420 pkt_size -= dma_size;
2423 txds->offset_eop |= PCIE_DESC_TX_EOP;
2425 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2428 /* Referencing next free TX descriptor */
2429 txds = &txq->txds[txq->wr_p];
2430 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2437 /* Increment write pointers. Force memory write before we let HW know */
2439 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2445 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2447 uint32_t new_ctrl, update;
2448 struct nfp_net_hw *hw;
2451 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2454 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2455 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2456 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2457 " ETH_VLAN_EXTEND_OFFLOAD");
2459 /* Enable vlan strip if it is not configured yet */
2460 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2461 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2462 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2464 /* Disable vlan strip just if it is configured */
2465 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2466 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2467 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2472 update = NFP_NET_CFG_UPDATE_GEN;
2474 ret = nfp_net_reconfig(hw, new_ctrl, update);
2476 hw->ctrl = new_ctrl;
2482 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2483 struct rte_eth_rss_reta_entry64 *reta_conf,
2486 uint32_t reta, mask;
2489 struct nfp_net_hw *hw =
2490 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2493 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2494 "(%d) doesn't match the number hardware can supported "
2495 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2500 * Update Redirection Table. There are 128 8bit-entries which can be
2501 * manage as 32 32bit-entries
2503 for (i = 0; i < reta_size; i += 4) {
2504 /* Handling 4 RSS entries per loop */
2505 idx = i / RTE_RETA_GROUP_SIZE;
2506 shift = i % RTE_RETA_GROUP_SIZE;
2507 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2513 /* If all 4 entries were set, don't need read RETA register */
2515 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2517 for (j = 0; j < 4; j++) {
2518 if (!(mask & (0x1 << j)))
2521 /* Clearing the entry bits */
2522 reta &= ~(0xFF << (8 * j));
2523 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2525 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2531 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2533 nfp_net_reta_update(struct rte_eth_dev *dev,
2534 struct rte_eth_rss_reta_entry64 *reta_conf,
2537 struct nfp_net_hw *hw =
2538 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2542 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2545 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2549 update = NFP_NET_CFG_UPDATE_RSS;
2551 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2557 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2559 nfp_net_reta_query(struct rte_eth_dev *dev,
2560 struct rte_eth_rss_reta_entry64 *reta_conf,
2566 struct nfp_net_hw *hw;
2568 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2573 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2574 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2575 "(%d) doesn't match the number hardware can supported "
2576 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2581 * Reading Redirection Table. There are 128 8bit-entries which can be
2582 * manage as 32 32bit-entries
2584 for (i = 0; i < reta_size; i += 4) {
2585 /* Handling 4 RSS entries per loop */
2586 idx = i / RTE_RETA_GROUP_SIZE;
2587 shift = i % RTE_RETA_GROUP_SIZE;
2588 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2593 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2595 for (j = 0; j < 4; j++) {
2596 if (!(mask & (0x1 << j)))
2598 reta_conf->reta[shift + j] =
2599 (uint8_t)((reta >> (8 * j)) & 0xF);
2606 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2607 struct rte_eth_rss_conf *rss_conf)
2609 struct nfp_net_hw *hw;
2611 uint32_t cfg_rss_ctrl = 0;
2615 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2617 /* Writing the key byte a byte */
2618 for (i = 0; i < rss_conf->rss_key_len; i++) {
2619 memcpy(&key, &rss_conf->rss_key[i], 1);
2620 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2623 rss_hf = rss_conf->rss_hf;
2625 if (rss_hf & ETH_RSS_IPV4)
2626 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2627 NFP_NET_CFG_RSS_IPV4_TCP |
2628 NFP_NET_CFG_RSS_IPV4_UDP;
2630 if (rss_hf & ETH_RSS_IPV6)
2631 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2632 NFP_NET_CFG_RSS_IPV6_TCP |
2633 NFP_NET_CFG_RSS_IPV6_UDP;
2635 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2636 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2638 /* configuring where to apply the RSS hash */
2639 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2641 /* Writing the key size */
2642 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2648 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2649 struct rte_eth_rss_conf *rss_conf)
2653 struct nfp_net_hw *hw;
2655 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2657 rss_hf = rss_conf->rss_hf;
2659 /* Checking if RSS is enabled */
2660 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2661 if (rss_hf != 0) { /* Enable RSS? */
2662 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2665 return 0; /* Nothing to do */
2668 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2669 RTE_LOG(ERR, PMD, "hash key too long\n");
2673 nfp_net_rss_hash_write(dev, rss_conf);
2675 update = NFP_NET_CFG_UPDATE_RSS;
2677 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2684 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2685 struct rte_eth_rss_conf *rss_conf)
2688 uint32_t cfg_rss_ctrl;
2691 struct nfp_net_hw *hw;
2693 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2695 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2698 rss_hf = rss_conf->rss_hf;
2699 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2701 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2702 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2704 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2705 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2707 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2708 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2710 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2711 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2713 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2714 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2716 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2717 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2719 /* Reading the key size */
2720 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2722 /* Reading the key byte a byte */
2723 for (i = 0; i < rss_conf->rss_key_len; i++) {
2724 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2725 memcpy(&rss_conf->rss_key[i], &key, 1);
2732 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2734 struct rte_eth_conf *dev_conf;
2735 struct rte_eth_rss_conf rss_conf;
2736 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2737 uint16_t rx_queues = dev->data->nb_rx_queues;
2741 RTE_LOG(INFO, PMD, "setting default RSS conf for %u queues\n",
2744 nfp_reta_conf[0].mask = ~0x0;
2745 nfp_reta_conf[1].mask = ~0x0;
2748 for (i = 0; i < 0x40; i += 8) {
2749 for (j = i; j < (i + 8); j++) {
2750 nfp_reta_conf[0].reta[j] = queue;
2751 nfp_reta_conf[1].reta[j] = queue++;
2755 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2759 dev_conf = &dev->data->dev_conf;
2761 RTE_LOG(INFO, PMD, "wrong rss conf");
2764 rss_conf = dev_conf->rx_adv_conf.rss_conf;
2766 ret = nfp_net_rss_hash_write(dev, &rss_conf);
2772 /* Initialise and register driver with DPDK Application */
2773 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2774 .dev_configure = nfp_net_configure,
2775 .dev_start = nfp_net_start,
2776 .dev_stop = nfp_net_stop,
2777 .dev_close = nfp_net_close,
2778 .promiscuous_enable = nfp_net_promisc_enable,
2779 .promiscuous_disable = nfp_net_promisc_disable,
2780 .link_update = nfp_net_link_update,
2781 .stats_get = nfp_net_stats_get,
2782 .stats_reset = nfp_net_stats_reset,
2783 .dev_infos_get = nfp_net_infos_get,
2784 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2785 .mtu_set = nfp_net_dev_mtu_set,
2786 .mac_addr_set = nfp_set_mac_addr,
2787 .vlan_offload_set = nfp_net_vlan_offload_set,
2788 .reta_update = nfp_net_reta_update,
2789 .reta_query = nfp_net_reta_query,
2790 .rss_hash_update = nfp_net_rss_hash_update,
2791 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2792 .rx_queue_setup = nfp_net_rx_queue_setup,
2793 .rx_queue_release = nfp_net_rx_queue_release,
2794 .rx_queue_count = nfp_net_rx_queue_count,
2795 .tx_queue_setup = nfp_net_tx_queue_setup,
2796 .tx_queue_release = nfp_net_tx_queue_release,
2797 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2798 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2802 * All eth_dev created got its private data, but before nfp_net_init, that
2803 * private data is referencing private data for all the PF ports. This is due
2804 * to how the vNIC bars are mapped based on first port, so all ports need info
2805 * about port 0 private data. Inside nfp_net_init the private data pointer is
2806 * changed to the right address for each port once the bars have been mapped.
2808 * This functions helps to find out which port and therefore which offset
2809 * inside the private data array to use.
2812 get_pf_port_number(char *name)
2814 char *pf_str = name;
2817 while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2822 * This should not happen at all and it would mean major
2823 * implementation fault.
2825 rte_panic("nfp_net: problem with pf device name\n");
2827 /* Expecting _portX with X within [0,7] */
2830 return (int)strtol(pf_str, NULL, 10);
2834 nfp_net_init(struct rte_eth_dev *eth_dev)
2836 struct rte_pci_device *pci_dev;
2837 struct nfp_net_hw *hw, *hwport0;
2839 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2845 PMD_INIT_FUNC_TRACE();
2847 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2849 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2850 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2851 port = get_pf_port_number(eth_dev->data->name);
2852 if (port < 0 || port > 7) {
2853 RTE_LOG(ERR, PMD, "Port value is wrong\n");
2857 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2859 /* This points to port 0 private data */
2860 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2862 /* This points to the specific port private data */
2863 hw = &hwport0[port];
2865 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2869 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2870 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2871 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2873 /* For secondary processes, the primary has done all the work */
2874 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2877 rte_eth_copy_pci_info(eth_dev, pci_dev);
2879 hw->device_id = pci_dev->id.device_id;
2880 hw->vendor_id = pci_dev->id.vendor_id;
2881 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2882 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2884 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2885 pci_dev->id.vendor_id, pci_dev->id.device_id,
2886 pci_dev->addr.domain, pci_dev->addr.bus,
2887 pci_dev->addr.devid, pci_dev->addr.function);
2889 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2890 if (hw->ctrl_bar == NULL) {
2892 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2896 if (hw->is_pf && port == 0) {
2897 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2898 hw->total_ports * 32768,
2900 if (!hw->ctrl_bar) {
2901 printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar\n");
2905 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2909 if (!hwport0->ctrl_bar)
2912 /* address based on port0 offset */
2913 hw->ctrl_bar = hwport0->ctrl_bar +
2914 (port * NFP_PF_CSR_SLICE_SIZE);
2917 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2919 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2920 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2922 /* Work out where in the BAR the queues start. */
2923 switch (pci_dev->id.device_id) {
2924 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2925 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2926 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2927 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2928 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2929 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2930 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2933 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2935 goto dev_err_ctrl_map;
2938 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2939 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2941 if (hw->is_pf && port == 0) {
2942 /* configure access to tx/rx vNIC BARs */
2943 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2945 NFP_QCP_QUEUE_AREA_SZ,
2946 &hw->hwqueues_area);
2948 if (!hwport0->hw_queues) {
2949 printf("nfp_rtsym_map fails for net.qc\n");
2951 goto dev_err_ctrl_map;
2954 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p\n",
2955 hwport0->hw_queues);
2959 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2960 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2961 eth_dev->data->dev_private = hw;
2963 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2965 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2969 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2970 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2972 nfp_net_cfg_queue_setup(hw);
2974 /* Get some of the read-only fields from the config BAR */
2975 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2976 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2977 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2978 hw->mtu = ETHER_MTU;
2980 /* VLAN insertion is incompatible with LSOv2 */
2981 if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2982 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2984 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2985 hw->rx_offset = NFP_NET_RX_OFFSET;
2987 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2989 PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2990 NFD_CFG_MAJOR_VERSION_of(hw->ver),
2991 NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2993 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2994 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2995 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2996 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2997 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2998 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2999 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
3000 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
3001 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
3002 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
3003 hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR " : "",
3004 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
3005 hw->cap & NFP_NET_CFG_CTRL_LSO2 ? "TSOv2 " : "",
3006 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "",
3007 hw->cap & NFP_NET_CFG_CTRL_RSS2 ? "RSSv2 " : "");
3011 hw->stride_rx = stride;
3012 hw->stride_tx = stride;
3014 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
3015 hw->max_rx_queues, hw->max_tx_queues);
3017 /* Initializing spinlock for reconfigs */
3018 rte_spinlock_init(&hw->reconfig_lock);
3020 /* Allocating memory for mac addr */
3021 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
3022 if (eth_dev->data->mac_addrs == NULL) {
3023 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
3025 goto dev_err_queues_map;
3029 nfp_net_pf_read_mac(hwport0, port);
3030 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
3032 nfp_net_vf_read_mac(hw);
3035 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
3036 PMD_INIT_LOG(INFO, "Using random mac address for port %d\n",
3038 /* Using random mac addresses for VFs */
3039 eth_random_addr(&hw->mac_addr[0]);
3040 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
3043 /* Copying mac address to DPDK eth_dev struct */
3044 ether_addr_copy((struct ether_addr *)hw->mac_addr,
3045 ð_dev->data->mac_addrs[0]);
3047 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
3048 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
3049 eth_dev->data->port_id, pci_dev->id.vendor_id,
3050 pci_dev->id.device_id,
3051 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
3052 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
3054 /* Registering LSC interrupt handler */
3055 rte_intr_callback_register(&pci_dev->intr_handle,
3056 nfp_net_dev_interrupt_handler,
3059 /* Telling the firmware about the LSC interrupt entry */
3060 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
3062 /* Recording current stats counters values */
3063 nfp_net_stats_reset(eth_dev);
3068 nfp_cpp_area_free(hw->hwqueues_area);
3070 nfp_cpp_area_free(hw->ctrl_area);
3076 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3077 struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3078 int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3080 struct rte_eth_dev *eth_dev;
3081 struct nfp_net_hw *hw;
3085 port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3090 sprintf(port_name, "%s_port%d", dev->device.name, port);
3092 sprintf(port_name, "%s", dev->device.name);
3094 eth_dev = rte_eth_dev_allocate(port_name);
3099 *priv = rte_zmalloc(port_name,
3100 sizeof(struct nfp_net_adapter) * ports,
3101 RTE_CACHE_LINE_SIZE);
3103 rte_eth_dev_release_port(eth_dev);
3108 eth_dev->data->dev_private = *priv;
3111 * dev_private pointing to port0 dev_private because we need
3112 * to configure vNIC bars based on port0 at nfp_net_init.
3113 * Then dev_private is adjusted per port.
3115 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3117 hw->hwinfo = hwinfo;
3118 hw->sym_tbl = sym_tbl;
3119 hw->pf_port_idx = phys_port;
3122 hw->pf_multiport_enabled = 1;
3124 hw->total_ports = ports;
3126 eth_dev->device = &dev->device;
3127 rte_eth_copy_pci_info(eth_dev, dev);
3129 ret = nfp_net_init(eth_dev);
3132 rte_eth_dev_release_port(eth_dev);
3134 rte_free(port_name);
3139 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
3142 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3144 struct nfp_cpp *cpp = nsp->cpp;
3149 struct stat file_stat;
3152 /* Looking for firmware file in order of priority */
3154 /* First try to find a firmware image specific for this device */
3155 sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3156 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3157 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3158 cpp->interface & 0xff);
3160 sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial);
3162 RTE_LOG(DEBUG, PMD, "Trying with fw file: %s\n", fw_name);
3163 fw_f = open(fw_name, O_RDONLY);
3167 /* Then try the PCI name */
3168 sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name);
3170 RTE_LOG(DEBUG, PMD, "Trying with fw file: %s\n", fw_name);
3171 fw_f = open(fw_name, O_RDONLY);
3175 /* Finally try the card type and media */
3176 sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card);
3177 RTE_LOG(DEBUG, PMD, "Trying with fw file: %s\n", fw_name);
3178 fw_f = open(fw_name, O_RDONLY);
3180 RTE_LOG(INFO, PMD, "Firmware file %s not found.", fw_name);
3185 if (fstat(fw_f, &file_stat) < 0) {
3186 RTE_LOG(INFO, PMD, "Firmware file %s size is unknown", fw_name);
3191 fsize = file_stat.st_size;
3192 RTE_LOG(INFO, PMD, "Firmware file found at %s with size: %" PRIu64 "\n",
3193 fw_name, (uint64_t)fsize);
3195 fw_buf = malloc((size_t)fsize);
3197 RTE_LOG(INFO, PMD, "malloc failed for fw buffer");
3201 memset(fw_buf, 0, fsize);
3203 bytes = read(fw_f, fw_buf, fsize);
3204 if (bytes != fsize) {
3205 RTE_LOG(INFO, PMD, "Reading fw to buffer failed.\n"
3206 "Just %" PRIu64 " of %" PRIu64 " bytes read",
3207 (uint64_t)bytes, (uint64_t)fsize);
3213 RTE_LOG(INFO, PMD, "Uploading the firmware ...");
3214 nfp_nsp_load_fw(nsp, fw_buf, bytes);
3215 RTE_LOG(INFO, PMD, "Done");
3224 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3225 struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3227 struct nfp_nsp *nsp;
3228 const char *nfp_fw_model;
3229 char card_desc[100];
3232 nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3235 RTE_LOG(INFO, PMD, "firmware model found: %s\n", nfp_fw_model);
3237 RTE_LOG(ERR, PMD, "firmware model NOT found\n");
3241 if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3242 RTE_LOG(ERR, PMD, "NFP ethernet table reports wrong ports: %u\n",
3243 nfp_eth_table->count);
3247 RTE_LOG(INFO, PMD, "NFP ethernet port table reports %u ports\n",
3248 nfp_eth_table->count);
3250 RTE_LOG(INFO, PMD, "Port speed: %u\n", nfp_eth_table->ports[0].speed);
3252 sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model,
3253 nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000);
3255 nsp = nfp_nsp_open(cpp);
3257 RTE_LOG(ERR, PMD, "NFP error when obtaining NSP handle\n");
3261 nfp_nsp_device_soft_reset(nsp);
3262 err = nfp_fw_upload(dev, nsp, card_desc);
3268 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3269 struct rte_pci_device *dev)
3271 struct nfp_cpp *cpp;
3272 struct nfp_hwinfo *hwinfo;
3273 struct nfp_rtsym_table *sym_tbl;
3274 struct nfp_eth_table *nfp_eth_table = NULL;
3284 cpp = nfp_cpp_from_device_name(dev->device.name);
3286 RTE_LOG(ERR, PMD, "A CPP handle can not be obtained");
3291 hwinfo = nfp_hwinfo_read(cpp);
3293 RTE_LOG(ERR, PMD, "Error reading hwinfo table");
3297 nfp_eth_table = nfp_eth_read_ports(cpp);
3298 if (!nfp_eth_table) {
3299 RTE_LOG(ERR, PMD, "Error reading NFP ethernet table\n");
3303 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3304 RTE_LOG(INFO, PMD, "Error when uploading firmware\n");
3309 /* Now the symbol table should be there */
3310 sym_tbl = nfp_rtsym_table_read(cpp);
3312 RTE_LOG(ERR, PMD, "Something is wrong with the firmware"
3318 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3319 if (total_ports != (int)nfp_eth_table->count) {
3320 RTE_LOG(ERR, PMD, "Inconsistent number of ports\n");
3324 PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
3326 if (total_ports <= 0 || total_ports > 8) {
3327 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
3332 for (i = 0; i < total_ports; i++) {
3333 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3334 nfp_eth_table->ports[i].index,
3341 free(nfp_eth_table);
3345 int nfp_logtype_init;
3346 int nfp_logtype_driver;
3348 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3350 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3351 PCI_DEVICE_ID_NFP4000_PF_NIC)
3354 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3355 PCI_DEVICE_ID_NFP6000_PF_NIC)
3362 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3364 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3365 PCI_DEVICE_ID_NFP6000_VF_NIC)
3372 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3373 struct rte_pci_device *pci_dev)
3375 return rte_eth_dev_pci_generic_probe(pci_dev,
3376 sizeof(struct nfp_net_adapter), nfp_net_init);
3379 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3381 struct rte_eth_dev *eth_dev;
3382 struct nfp_net_hw *hw, *hwport0;
3385 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3386 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3387 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3388 port = get_pf_port_number(eth_dev->data->name);
3390 * hotplug is not possible with multiport PF although freeing
3391 * data structures can be done for first port.
3395 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3396 hw = &hwport0[port];
3397 nfp_cpp_area_free(hw->ctrl_area);
3398 nfp_cpp_area_free(hw->hwqueues_area);
3401 nfp_cpp_free(hw->cpp);
3403 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3405 /* hotplug is not possible with multiport PF */
3406 if (hw->pf_multiport_enabled)
3408 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3411 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3412 .id_table = pci_id_nfp_pf_net_map,
3413 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3414 .probe = nfp_pf_pci_probe,
3415 .remove = eth_nfp_pci_remove,
3418 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3419 .id_table = pci_id_nfp_vf_net_map,
3420 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3421 .probe = eth_nfp_pci_probe,
3422 .remove = eth_nfp_pci_remove,
3425 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3426 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3427 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3428 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3429 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3430 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3432 RTE_INIT(nfp_init_log);
3436 nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3437 if (nfp_logtype_init >= 0)
3438 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3439 nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3440 if (nfp_logtype_driver >= 0)
3441 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3445 * c-file-style: "Linux"
3446 * indent-tabs-mode: t