2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
58 #include "nfp_net_pmd.h"
59 #include "nfp_net_logs.h"
60 #include "nfp_net_ctrl.h"
63 static void nfp_net_close(struct rte_eth_dev *dev);
64 static int nfp_net_configure(struct rte_eth_dev *dev);
65 static void nfp_net_dev_interrupt_handler(void *param);
66 static void nfp_net_dev_interrupt_delayed_handler(void *param);
67 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
68 static void nfp_net_infos_get(struct rte_eth_dev *dev,
69 struct rte_eth_dev_info *dev_info);
70 static int nfp_net_init(struct rte_eth_dev *eth_dev);
71 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
72 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
73 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
74 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
75 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
77 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
79 static void nfp_net_rx_queue_release(void *rxq);
80 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
81 uint16_t nb_desc, unsigned int socket_id,
82 const struct rte_eth_rxconf *rx_conf,
83 struct rte_mempool *mp);
84 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
85 static void nfp_net_tx_queue_release(void *txq);
86 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
87 uint16_t nb_desc, unsigned int socket_id,
88 const struct rte_eth_txconf *tx_conf);
89 static int nfp_net_start(struct rte_eth_dev *dev);
90 static void nfp_net_stats_get(struct rte_eth_dev *dev,
91 struct rte_eth_stats *stats);
92 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
93 static void nfp_net_stop(struct rte_eth_dev *dev);
94 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
98 * The offset of the queue controller queues in the PCIe Target. These
99 * happen to be at the same offset on the NFP6000 and the NFP3200 so
100 * we use a single macro here.
102 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
104 /* Maximum value which can be added to a queue with one transaction */
105 #define NFP_QCP_MAX_ADD 0x7f
107 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
108 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
110 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
112 NFP_QCP_READ_PTR = 0,
117 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
118 * @q: Base address for queue structure
119 * @ptr: Add to the Read or Write pointer
120 * @val: Value to add to the queue pointer
122 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
125 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
129 if (ptr == NFP_QCP_READ_PTR)
130 off = NFP_QCP_QUEUE_ADD_RPTR;
132 off = NFP_QCP_QUEUE_ADD_WPTR;
134 while (val > NFP_QCP_MAX_ADD) {
135 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
136 val -= NFP_QCP_MAX_ADD;
139 nn_writel(rte_cpu_to_le_32(val), q + off);
143 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
144 * @q: Base address for queue structure
145 * @ptr: Read or Write pointer
147 static inline uint32_t
148 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
153 if (ptr == NFP_QCP_READ_PTR)
154 off = NFP_QCP_QUEUE_STS_LO;
156 off = NFP_QCP_QUEUE_STS_HI;
158 val = rte_cpu_to_le_32(nn_readl(q + off));
160 if (ptr == NFP_QCP_READ_PTR)
161 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
163 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
167 * Functions to read/write from/to Config BAR
168 * Performs any endian conversion necessary.
170 static inline uint8_t
171 nn_cfg_readb(struct nfp_net_hw *hw, int off)
173 return nn_readb(hw->ctrl_bar + off);
177 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
179 nn_writeb(val, hw->ctrl_bar + off);
182 static inline uint32_t
183 nn_cfg_readl(struct nfp_net_hw *hw, int off)
185 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
189 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
191 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
194 static inline uint64_t
195 nn_cfg_readq(struct nfp_net_hw *hw, int off)
197 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
201 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
203 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
207 * Atomically reads link status information from global structure rte_eth_dev.
210 * - Pointer to the structure rte_eth_dev to read from.
211 * - Pointer to the buffer to be saved with the link status.
214 * - On success, zero.
215 * - On failure, negative value.
218 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
219 struct rte_eth_link *link)
221 struct rte_eth_link *dst = link;
222 struct rte_eth_link *src = &dev->data->dev_link;
224 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
225 *(uint64_t *)src) == 0)
232 * Atomically writes the link status information into global
233 * structure rte_eth_dev.
236 * - Pointer to the structure rte_eth_dev to read from.
237 * - Pointer to the buffer to be saved with the link status.
240 * - On success, zero.
241 * - On failure, negative value.
244 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
245 struct rte_eth_link *link)
247 struct rte_eth_link *dst = &dev->data->dev_link;
248 struct rte_eth_link *src = link;
250 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
251 *(uint64_t *)src) == 0)
258 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
262 if (rxq->rxbufs == NULL)
265 for (i = 0; i < rxq->rx_count; i++) {
266 if (rxq->rxbufs[i].mbuf) {
267 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
268 rxq->rxbufs[i].mbuf = NULL;
274 nfp_net_rx_queue_release(void *rx_queue)
276 struct nfp_net_rxq *rxq = rx_queue;
279 nfp_net_rx_queue_release_mbufs(rxq);
280 rte_free(rxq->rxbufs);
286 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
288 nfp_net_rx_queue_release_mbufs(rxq);
294 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
298 if (txq->txbufs == NULL)
301 for (i = 0; i < txq->tx_count; i++) {
302 if (txq->txbufs[i].mbuf) {
303 rte_pktmbuf_free(txq->txbufs[i].mbuf);
304 txq->txbufs[i].mbuf = NULL;
310 nfp_net_tx_queue_release(void *tx_queue)
312 struct nfp_net_txq *txq = tx_queue;
315 nfp_net_tx_queue_release_mbufs(txq);
316 rte_free(txq->txbufs);
322 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
324 nfp_net_tx_queue_release_mbufs(txq);
330 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
334 struct timespec wait;
336 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
339 if (hw->qcp_cfg == NULL)
340 rte_panic("Bad configuration queue pointer\n");
342 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
345 wait.tv_nsec = 1000000;
347 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
349 /* Poll update field, waiting for NFP to ack the config */
350 for (cnt = 0; ; cnt++) {
351 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
354 if (new & NFP_NET_CFG_UPDATE_ERR) {
355 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
358 if (cnt >= NFP_NET_POLL_TIMEOUT) {
359 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
360 " %dms", update, cnt);
361 rte_panic("Exiting\n");
363 nanosleep(&wait, 0); /* waiting for a 1ms */
365 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
370 * Reconfigure the NIC
371 * @nn: device to reconfigure
372 * @ctrl: The value for the ctrl field in the BAR config
373 * @update: The value for the update field in the BAR config
375 * Write the update word to the BAR and ping the reconfig queue. Then poll
376 * until the firmware has acknowledged the update by zeroing the update word.
379 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
383 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
386 rte_spinlock_lock(&hw->reconfig_lock);
388 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
389 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
393 err = __nfp_net_reconfig(hw, update);
395 rte_spinlock_unlock(&hw->reconfig_lock);
401 * Reconfig errors imply situations where they can be handled.
402 * Otherwise, rte_panic is called inside __nfp_net_reconfig
404 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
410 * Configure an Ethernet device. This function must be invoked first
411 * before any other function in the Ethernet API. This function can
412 * also be re-invoked when a device is in the stopped state.
415 nfp_net_configure(struct rte_eth_dev *dev)
417 struct rte_eth_conf *dev_conf;
418 struct rte_eth_rxmode *rxmode;
419 struct rte_eth_txmode *txmode;
420 uint32_t new_ctrl = 0;
422 struct nfp_net_hw *hw;
424 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
427 * A DPDK app sends info about how many queues to use and how
428 * those queues need to be configured. This is used by the
429 * DPDK core and it makes sure no more queues than those
430 * advertised by the driver are requested. This function is
431 * called after that internal process
434 PMD_INIT_LOG(DEBUG, "Configure");
436 dev_conf = &dev->data->dev_conf;
437 rxmode = &dev_conf->rxmode;
438 txmode = &dev_conf->txmode;
440 /* Checking TX mode */
441 if (txmode->mq_mode) {
442 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
446 /* Checking RX mode */
447 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
448 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
449 update = NFP_NET_CFG_UPDATE_RSS;
450 new_ctrl = NFP_NET_CFG_CTRL_RSS;
452 PMD_INIT_LOG(INFO, "RSS not supported");
457 if (rxmode->split_hdr_size) {
458 PMD_INIT_LOG(INFO, "rxmode does not support split header");
462 if (rxmode->hw_ip_checksum) {
463 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
464 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
466 PMD_INIT_LOG(INFO, "RXCSUM not supported");
471 if (rxmode->hw_vlan_filter) {
472 PMD_INIT_LOG(INFO, "VLAN filter not supported");
476 if (rxmode->hw_vlan_strip) {
477 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
478 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
480 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
485 if (rxmode->hw_vlan_extend) {
486 PMD_INIT_LOG(INFO, "VLAN extended not supported");
490 /* Supporting VLAN insertion by default */
491 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
492 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
494 if (rxmode->jumbo_frame)
495 /* this is handled in rte_eth_dev_configure */
497 if (rxmode->hw_strip_crc) {
498 PMD_INIT_LOG(INFO, "strip CRC not supported");
502 if (rxmode->enable_scatter) {
503 PMD_INIT_LOG(INFO, "Scatter not supported");
510 update |= NFP_NET_CFG_UPDATE_GEN;
512 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
513 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
522 nfp_net_enable_queues(struct rte_eth_dev *dev)
524 struct nfp_net_hw *hw;
525 uint64_t enabled_queues = 0;
528 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
530 /* Enabling the required TX queues in the device */
531 for (i = 0; i < dev->data->nb_tx_queues; i++)
532 enabled_queues |= (1 << i);
534 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
538 /* Enabling the required RX queues in the device */
539 for (i = 0; i < dev->data->nb_rx_queues; i++)
540 enabled_queues |= (1 << i);
542 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
546 nfp_net_disable_queues(struct rte_eth_dev *dev)
548 struct nfp_net_hw *hw;
549 uint32_t new_ctrl, update = 0;
551 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
553 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
554 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
556 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
557 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
558 NFP_NET_CFG_UPDATE_MSIX;
560 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
561 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
563 /* If an error when reconfig we avoid to change hw state */
564 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
571 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
575 for (i = 0; i < dev->data->nb_rx_queues; i++) {
576 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
583 nfp_net_params_setup(struct nfp_net_hw *hw)
585 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
586 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
590 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
592 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
595 static void nfp_net_read_mac(struct nfp_net_hw *hw)
599 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
600 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
602 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
603 memcpy(&hw->mac_addr[4], &tmp, 2);
607 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
609 uint32_t mac0 = *(uint32_t *)mac;
612 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
615 mac1 = *(uint16_t *)mac;
616 nn_writew(rte_cpu_to_be_16(mac1),
617 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
621 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
622 struct rte_intr_handle *intr_handle)
624 struct nfp_net_hw *hw;
627 if (!intr_handle->intr_vec) {
628 intr_handle->intr_vec =
629 rte_zmalloc("intr_vec",
630 dev->data->nb_rx_queues * sizeof(int), 0);
631 if (!intr_handle->intr_vec) {
632 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
633 " intr_vec", dev->data->nb_rx_queues);
638 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
640 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
641 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
642 /* UIO just supports one queue and no LSC*/
643 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
644 intr_handle->intr_vec[0] = 0;
646 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
647 for (i = 0; i < dev->data->nb_rx_queues; i++) {
649 * The first msix vector is reserved for non
652 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
653 intr_handle->intr_vec[i] = i + 1;
654 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
655 intr_handle->intr_vec[i]);
659 /* Avoiding TX interrupts */
660 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
665 nfp_net_start(struct rte_eth_dev *dev)
667 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
668 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
669 uint32_t new_ctrl, update = 0;
670 struct nfp_net_hw *hw;
671 uint32_t intr_vector;
674 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
676 PMD_INIT_LOG(DEBUG, "Start");
678 /* Disabling queues just in case... */
679 nfp_net_disable_queues(dev);
681 /* Writing configuration parameters in the device */
682 nfp_net_params_setup(hw);
684 /* Enabling the required queues in the device */
685 nfp_net_enable_queues(dev);
687 /* check and configure queue intr-vector mapping */
688 if (dev->data->dev_conf.intr_conf.rxq != 0) {
689 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
691 * Better not to share LSC with RX interrupts.
692 * Unregistering LSC interrupt handler
694 rte_intr_callback_unregister(&pci_dev->intr_handle,
695 nfp_net_dev_interrupt_handler, (void *)dev);
697 if (dev->data->nb_rx_queues > 1) {
698 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
699 "supports 1 queue with UIO");
703 intr_vector = dev->data->nb_rx_queues;
704 if (rte_intr_efd_enable(intr_handle, intr_vector))
707 nfp_configure_rx_interrupt(dev, intr_handle);
708 update = NFP_NET_CFG_UPDATE_MSIX;
711 rte_intr_enable(intr_handle);
714 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
716 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
718 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
719 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
721 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
722 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
726 * Allocating rte mbuffs for configured rx queues.
727 * This requires queues being enabled before
729 if (nfp_net_rx_freelist_setup(dev) < 0) {
740 * An error returned by this function should mean the app
741 * exiting and then the system releasing all the memory
742 * allocated even memory coming from hugepages.
744 * The device could be enabled at this point with some queues
745 * ready for getting packets. This is true if the call to
746 * nfp_net_rx_freelist_setup() succeeds for some queues but
747 * fails for subsequent queues.
749 * This should make the app exiting but better if we tell the
752 nfp_net_disable_queues(dev);
757 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
759 nfp_net_stop(struct rte_eth_dev *dev)
763 PMD_INIT_LOG(DEBUG, "Stop");
765 nfp_net_disable_queues(dev);
768 for (i = 0; i < dev->data->nb_tx_queues; i++) {
769 nfp_net_reset_tx_queue(
770 (struct nfp_net_txq *)dev->data->tx_queues[i]);
773 for (i = 0; i < dev->data->nb_rx_queues; i++) {
774 nfp_net_reset_rx_queue(
775 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
779 /* Reset and stop device. The device can not be restarted. */
781 nfp_net_close(struct rte_eth_dev *dev)
783 struct nfp_net_hw *hw;
784 struct rte_pci_device *pci_dev;
786 PMD_INIT_LOG(DEBUG, "Close");
788 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
789 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
792 * We assume that the DPDK application is stopping all the
793 * threads/queues before calling the device close function.
798 rte_intr_disable(&pci_dev->intr_handle);
799 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
801 /* unregister callback func from eal lib */
802 rte_intr_callback_unregister(&pci_dev->intr_handle,
803 nfp_net_dev_interrupt_handler,
807 * The ixgbe PMD driver disables the pcie master on the
808 * device. The i40e does not...
813 nfp_net_promisc_enable(struct rte_eth_dev *dev)
815 uint32_t new_ctrl, update = 0;
816 struct nfp_net_hw *hw;
818 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
820 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
822 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
823 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
827 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
828 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
832 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
833 update = NFP_NET_CFG_UPDATE_GEN;
836 * DPDK sets promiscuous mode on just after this call assuming
837 * it can not fail ...
839 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
846 nfp_net_promisc_disable(struct rte_eth_dev *dev)
848 uint32_t new_ctrl, update = 0;
849 struct nfp_net_hw *hw;
851 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
853 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
854 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
858 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
859 update = NFP_NET_CFG_UPDATE_GEN;
862 * DPDK sets promiscuous mode off just before this call
863 * assuming it can not fail ...
865 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
872 * return 0 means link status changed, -1 means not changed
874 * Wait to complete is needed as it can take up to 9 seconds to get the Link
878 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
880 struct nfp_net_hw *hw;
881 struct rte_eth_link link, old;
882 uint32_t nn_link_status;
884 static const uint32_t ls_to_ethtool[] = {
885 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
886 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
887 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
888 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
889 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
890 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
891 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
892 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
895 PMD_DRV_LOG(DEBUG, "Link update\n");
897 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
899 memset(&old, 0, sizeof(old));
900 nfp_net_dev_atomic_read_link_status(dev, &old);
902 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
904 memset(&link, 0, sizeof(struct rte_eth_link));
906 if (nn_link_status & NFP_NET_CFG_STS_LINK)
907 link.link_status = ETH_LINK_UP;
909 link.link_duplex = ETH_LINK_FULL_DUPLEX;
911 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
912 NFP_NET_CFG_STS_LINK_RATE_MASK;
914 if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
915 ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
916 (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
917 /* We really do not know the speed wil old firmware */
918 link.link_speed = ETH_SPEED_NUM_NONE;
920 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
921 link.link_speed = ETH_SPEED_NUM_NONE;
923 link.link_speed = ls_to_ethtool[nn_link_status];
926 if (old.link_status != link.link_status) {
927 nfp_net_dev_atomic_write_link_status(dev, &link);
928 if (link.link_status)
929 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
931 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
939 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
942 struct nfp_net_hw *hw;
943 struct rte_eth_stats nfp_dev_stats;
945 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
947 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
949 /* reading per RX ring stats */
950 for (i = 0; i < dev->data->nb_rx_queues; i++) {
951 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
954 nfp_dev_stats.q_ipackets[i] =
955 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
957 nfp_dev_stats.q_ipackets[i] -=
958 hw->eth_stats_base.q_ipackets[i];
960 nfp_dev_stats.q_ibytes[i] =
961 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
963 nfp_dev_stats.q_ibytes[i] -=
964 hw->eth_stats_base.q_ibytes[i];
967 /* reading per TX ring stats */
968 for (i = 0; i < dev->data->nb_tx_queues; i++) {
969 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
972 nfp_dev_stats.q_opackets[i] =
973 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
975 nfp_dev_stats.q_opackets[i] -=
976 hw->eth_stats_base.q_opackets[i];
978 nfp_dev_stats.q_obytes[i] =
979 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
981 nfp_dev_stats.q_obytes[i] -=
982 hw->eth_stats_base.q_obytes[i];
985 nfp_dev_stats.ipackets =
986 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
988 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
990 nfp_dev_stats.ibytes =
991 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
993 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
995 nfp_dev_stats.opackets =
996 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
998 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1000 nfp_dev_stats.obytes =
1001 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1003 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1005 /* reading general device stats */
1006 nfp_dev_stats.ierrors =
1007 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1009 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1011 nfp_dev_stats.oerrors =
1012 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1014 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1016 /* RX ring mbuf allocation failures */
1017 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1019 nfp_dev_stats.imissed =
1020 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1022 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1025 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1029 nfp_net_stats_reset(struct rte_eth_dev *dev)
1032 struct nfp_net_hw *hw;
1034 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037 * hw->eth_stats_base records the per counter starting point.
1038 * Lets update it now
1041 /* reading per RX ring stats */
1042 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1043 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1046 hw->eth_stats_base.q_ipackets[i] =
1047 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1049 hw->eth_stats_base.q_ibytes[i] =
1050 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1053 /* reading per TX ring stats */
1054 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1055 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1058 hw->eth_stats_base.q_opackets[i] =
1059 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1061 hw->eth_stats_base.q_obytes[i] =
1062 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1065 hw->eth_stats_base.ipackets =
1066 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1068 hw->eth_stats_base.ibytes =
1069 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1071 hw->eth_stats_base.opackets =
1072 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1074 hw->eth_stats_base.obytes =
1075 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1077 /* reading general device stats */
1078 hw->eth_stats_base.ierrors =
1079 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1081 hw->eth_stats_base.oerrors =
1082 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1084 /* RX ring mbuf allocation failures */
1085 dev->data->rx_mbuf_alloc_failed = 0;
1087 hw->eth_stats_base.imissed =
1088 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1092 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1094 struct nfp_net_hw *hw;
1096 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1098 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1099 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1100 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1101 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1102 dev_info->max_rx_pktlen = hw->mtu;
1103 /* Next should change when PF support is implemented */
1104 dev_info->max_mac_addrs = 1;
1106 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1107 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1109 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1110 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1111 DEV_RX_OFFLOAD_UDP_CKSUM |
1112 DEV_RX_OFFLOAD_TCP_CKSUM;
1114 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1115 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1117 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1118 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1119 DEV_TX_OFFLOAD_UDP_CKSUM |
1120 DEV_TX_OFFLOAD_TCP_CKSUM;
1122 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1124 .pthresh = DEFAULT_RX_PTHRESH,
1125 .hthresh = DEFAULT_RX_HTHRESH,
1126 .wthresh = DEFAULT_RX_WTHRESH,
1128 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1132 dev_info->default_txconf = (struct rte_eth_txconf) {
1134 .pthresh = DEFAULT_TX_PTHRESH,
1135 .hthresh = DEFAULT_TX_HTHRESH,
1136 .wthresh = DEFAULT_TX_WTHRESH,
1138 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1139 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1140 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1141 ETH_TXQ_FLAGS_NOOFFLOADS,
1144 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1145 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1147 dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1148 ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1149 ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1151 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1152 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1155 static const uint32_t *
1156 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1158 static const uint32_t ptypes[] = {
1159 /* refers to nfp_net_set_hash() */
1160 RTE_PTYPE_INNER_L3_IPV4,
1161 RTE_PTYPE_INNER_L3_IPV6,
1162 RTE_PTYPE_INNER_L3_IPV6_EXT,
1163 RTE_PTYPE_INNER_L4_MASK,
1167 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1173 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1175 struct nfp_net_rxq *rxq;
1176 struct nfp_net_rx_desc *rxds;
1180 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1187 * Other PMDs are just checking the DD bit in intervals of 4
1188 * descriptors and counting all four if the first has the DD
1189 * bit on. Of course, this is not accurate but can be good for
1190 * performance. But ideally that should be done in descriptors
1191 * chunks belonging to the same cache line
1194 while (count < rxq->rx_count) {
1195 rxds = &rxq->rxds[idx];
1196 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1203 if ((idx) == rxq->rx_count)
1211 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1213 struct rte_pci_device *pci_dev;
1214 struct nfp_net_hw *hw;
1217 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1220 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1223 /* Make sure all updates are written before un-masking */
1225 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1226 NFP_NET_CFG_ICR_UNMASKED);
1231 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1233 struct rte_pci_device *pci_dev;
1234 struct nfp_net_hw *hw;
1237 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1238 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1240 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1243 /* Make sure all updates are written before un-masking */
1245 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1250 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1252 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1253 struct rte_eth_link link;
1255 memset(&link, 0, sizeof(link));
1256 nfp_net_dev_atomic_read_link_status(dev, &link);
1257 if (link.link_status)
1258 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1259 (int)(dev->data->port_id), (unsigned)link.link_speed,
1260 link.link_duplex == ETH_LINK_FULL_DUPLEX
1261 ? "full-duplex" : "half-duplex");
1263 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1264 (int)(dev->data->port_id));
1266 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1267 pci_dev->addr.domain, pci_dev->addr.bus,
1268 pci_dev->addr.devid, pci_dev->addr.function);
1271 /* Interrupt configuration and handling */
1274 * nfp_net_irq_unmask - Unmask an interrupt
1276 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1277 * clear the ICR for the entry.
1280 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1282 struct nfp_net_hw *hw;
1283 struct rte_pci_device *pci_dev;
1285 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1286 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1288 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1289 /* If MSI-X auto-masking is used, clear the entry */
1291 rte_intr_enable(&pci_dev->intr_handle);
1293 /* Make sure all updates are written before un-masking */
1295 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1296 NFP_NET_CFG_ICR_UNMASKED);
1301 nfp_net_dev_interrupt_handler(void *param)
1304 struct rte_eth_link link;
1305 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1307 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1309 /* get the link status */
1310 memset(&link, 0, sizeof(link));
1311 nfp_net_dev_atomic_read_link_status(dev, &link);
1313 nfp_net_link_update(dev, 0);
1316 if (!link.link_status) {
1317 /* handle it 1 sec later, wait it being stable */
1318 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1319 /* likely to down */
1321 /* handle it 4 sec later, wait it being stable */
1322 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1325 if (rte_eal_alarm_set(timeout * 1000,
1326 nfp_net_dev_interrupt_delayed_handler,
1328 RTE_LOG(ERR, PMD, "Error setting alarm");
1330 nfp_net_irq_unmask(dev);
1335 * Interrupt handler which shall be registered for alarm callback for delayed
1336 * handling specific interrupt to wait for the stable nic state. As the NIC
1337 * interrupt state is not stable for nfp after link is just down, it needs
1338 * to wait 4 seconds to get the stable status.
1340 * @param handle Pointer to interrupt handle.
1341 * @param param The address of parameter (struct rte_eth_dev *)
1346 nfp_net_dev_interrupt_delayed_handler(void *param)
1348 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1350 nfp_net_link_update(dev, 0);
1351 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1353 nfp_net_dev_link_status_print(dev);
1356 nfp_net_irq_unmask(dev);
1360 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1362 struct nfp_net_hw *hw;
1364 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1366 /* check that mtu is within the allowed range */
1367 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1370 /* switch to jumbo mode if needed */
1371 if ((uint32_t)mtu > ETHER_MAX_LEN)
1372 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1374 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1376 /* update max frame size */
1377 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1379 /* writing to configuration space */
1380 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1388 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1389 uint16_t queue_idx, uint16_t nb_desc,
1390 unsigned int socket_id,
1391 const struct rte_eth_rxconf *rx_conf,
1392 struct rte_mempool *mp)
1394 const struct rte_memzone *tz;
1395 struct nfp_net_rxq *rxq;
1396 struct nfp_net_hw *hw;
1398 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400 PMD_INIT_FUNC_TRACE();
1402 /* Validating number of descriptors */
1403 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1404 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1405 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1406 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1411 * Free memory prior to re-allocation if needed. This is the case after
1412 * calling nfp_net_stop
1414 if (dev->data->rx_queues[queue_idx]) {
1415 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1416 dev->data->rx_queues[queue_idx] = NULL;
1419 /* Allocating rx queue data structure */
1420 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1421 RTE_CACHE_LINE_SIZE, socket_id);
1425 /* Hw queues mapping based on firmware confifguration */
1426 rxq->qidx = queue_idx;
1427 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1428 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1429 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1430 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1433 * Tracking mbuf size for detecting a potential mbuf overflow due to
1437 rxq->mbuf_size = rxq->mem_pool->elt_size;
1438 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1439 hw->flbufsz = rxq->mbuf_size;
1441 rxq->rx_count = nb_desc;
1442 rxq->port_id = dev->data->port_id;
1443 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1444 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1446 rxq->drop_en = rx_conf->rx_drop_en;
1449 * Allocate RX ring hardware descriptors. A memzone large enough to
1450 * handle the maximum ring size is allocated in order to allow for
1451 * resizing in later calls to the queue setup function.
1453 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1454 sizeof(struct nfp_net_rx_desc) *
1455 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1459 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1460 nfp_net_rx_queue_release(rxq);
1464 /* Saving physical and virtual addresses for the RX ring */
1465 rxq->dma = (uint64_t)tz->phys_addr;
1466 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1468 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1469 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1470 sizeof(*rxq->rxbufs) * nb_desc,
1471 RTE_CACHE_LINE_SIZE, socket_id);
1472 if (rxq->rxbufs == NULL) {
1473 nfp_net_rx_queue_release(rxq);
1477 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1478 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1480 nfp_net_reset_rx_queue(rxq);
1482 dev->data->rx_queues[queue_idx] = rxq;
1486 * Telling the HW about the physical address of the RX ring and number
1487 * of descriptors in log2 format
1489 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1490 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1496 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1498 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1502 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1505 for (i = 0; i < rxq->rx_count; i++) {
1506 struct nfp_net_rx_desc *rxd;
1507 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1510 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1511 (unsigned)rxq->qidx);
1515 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1517 rxd = &rxq->rxds[i];
1519 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1520 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1522 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1525 /* Make sure all writes are flushed before telling the hardware */
1528 /* Not advertising the whole ring as the firmware gets confused if so */
1529 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1532 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1538 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1539 uint16_t nb_desc, unsigned int socket_id,
1540 const struct rte_eth_txconf *tx_conf)
1542 const struct rte_memzone *tz;
1543 struct nfp_net_txq *txq;
1544 uint16_t tx_free_thresh;
1545 struct nfp_net_hw *hw;
1547 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1549 PMD_INIT_FUNC_TRACE();
1551 /* Validating number of descriptors */
1552 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1553 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1554 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1555 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1559 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1560 tx_conf->tx_free_thresh :
1561 DEFAULT_TX_FREE_THRESH);
1563 if (tx_free_thresh > (nb_desc)) {
1565 "tx_free_thresh must be less than the number of TX "
1566 "descriptors. (tx_free_thresh=%u port=%d "
1567 "queue=%d)\n", (unsigned int)tx_free_thresh,
1568 (int)dev->data->port_id, (int)queue_idx);
1573 * Free memory prior to re-allocation if needed. This is the case after
1574 * calling nfp_net_stop
1576 if (dev->data->tx_queues[queue_idx]) {
1577 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1579 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1580 dev->data->tx_queues[queue_idx] = NULL;
1583 /* Allocating tx queue data structure */
1584 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1585 RTE_CACHE_LINE_SIZE, socket_id);
1587 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1592 * Allocate TX ring hardware descriptors. A memzone large enough to
1593 * handle the maximum ring size is allocated in order to allow for
1594 * resizing in later calls to the queue setup function.
1596 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1597 sizeof(struct nfp_net_tx_desc) *
1598 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1601 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1602 nfp_net_tx_queue_release(txq);
1606 txq->tx_count = nb_desc;
1607 txq->tx_free_thresh = tx_free_thresh;
1608 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1609 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1610 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1612 /* queue mapping based on firmware configuration */
1613 txq->qidx = queue_idx;
1614 txq->tx_qcidx = queue_idx * hw->stride_tx;
1615 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1617 txq->port_id = dev->data->port_id;
1618 txq->txq_flags = tx_conf->txq_flags;
1620 /* Saving physical and virtual addresses for the TX ring */
1621 txq->dma = (uint64_t)tz->phys_addr;
1622 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1624 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1625 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1626 sizeof(*txq->txbufs) * nb_desc,
1627 RTE_CACHE_LINE_SIZE, socket_id);
1628 if (txq->txbufs == NULL) {
1629 nfp_net_tx_queue_release(txq);
1632 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1633 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1635 nfp_net_reset_tx_queue(txq);
1637 dev->data->tx_queues[queue_idx] = txq;
1641 * Telling the HW about the physical address of the TX ring and number
1642 * of descriptors in log2 format
1644 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1645 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1650 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1652 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1653 struct rte_mbuf *mb)
1656 struct nfp_net_hw *hw = txq->hw;
1658 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1661 ol_flags = mb->ol_flags;
1663 if (!(ol_flags & PKT_TX_TCP_SEG))
1666 txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1667 txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1668 txd->flags = PCIE_DESC_TX_LSO;
1677 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1679 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1680 struct rte_mbuf *mb)
1683 struct nfp_net_hw *hw = txq->hw;
1685 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1688 ol_flags = mb->ol_flags;
1690 /* IPv6 does not need checksum */
1691 if (ol_flags & PKT_TX_IP_CKSUM)
1692 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1694 switch (ol_flags & PKT_TX_L4_MASK) {
1695 case PKT_TX_UDP_CKSUM:
1696 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1698 case PKT_TX_TCP_CKSUM:
1699 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1703 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1704 txd->flags |= PCIE_DESC_TX_CSUM;
1707 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1709 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1710 struct rte_mbuf *mb)
1712 struct nfp_net_hw *hw = rxq->hw;
1714 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1717 /* If IPv4 and IP checksum error, fail */
1718 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1719 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1720 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1722 /* If neither UDP nor TCP return */
1723 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1724 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1727 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1728 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1729 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1731 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1732 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1733 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1736 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1737 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1740 * nfp_net_set_hash - Set mbuf hash data
1742 * The RSS hash and hash-type are pre-pended to the packet data.
1743 * Extract and decode it and set the mbuf fields.
1746 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1747 struct rte_mbuf *mbuf)
1751 struct nfp_net_hw *hw = rxq->hw;
1753 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1756 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1759 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1760 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1762 mbuf->hash.rss = hash;
1763 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1765 switch (hash_type) {
1766 case NFP_NET_RSS_IPV4:
1767 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1769 case NFP_NET_RSS_IPV6:
1770 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1772 case NFP_NET_RSS_IPV6_EX:
1773 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1776 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1781 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1783 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1786 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1791 * There are some decissions to take:
1792 * 1) How to check DD RX descriptors bit
1793 * 2) How and when to allocate new mbufs
1795 * Current implementation checks just one single DD bit each loop. As each
1796 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1797 * a single cache line instead. Tests with this change have not shown any
1798 * performance improvement but it requires further investigation. For example,
1799 * depending on which descriptor is next, the number of descriptors could be
1800 * less than 8 for just checking those in the same cache line. This implies
1801 * extra work which could be counterproductive by itself. Indeed, last firmware
1802 * changes are just doing this: writing several descriptors with the DD bit
1803 * for saving PCIe bandwidth and DMA operations from the NFP.
1805 * Mbuf allocation is done when a new packet is received. Then the descriptor
1806 * is automatically linked with the new mbuf and the old one is given to the
1807 * user. The main drawback with this design is mbuf allocation is heavier than
1808 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1809 * cache point of view it does not seem allocating the mbuf early on as we are
1810 * doing now have any benefit at all. Again, tests with this change have not
1811 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1812 * so looking at the implications of this type of allocation should be studied
1817 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1819 struct nfp_net_rxq *rxq;
1820 struct nfp_net_rx_desc *rxds;
1821 struct nfp_net_rx_buff *rxb;
1822 struct nfp_net_hw *hw;
1823 struct rte_mbuf *mb;
1824 struct rte_mbuf *new_mb;
1830 if (unlikely(rxq == NULL)) {
1832 * DPDK just checks the queue is lower than max queues
1833 * enabled. But the queue needs to be configured
1835 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1843 while (avail < nb_pkts) {
1844 rxb = &rxq->rxbufs[rxq->rd_p];
1845 if (unlikely(rxb == NULL)) {
1846 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1851 * Memory barrier to ensure that we won't do other
1852 * reads before the DD bit.
1856 rxds = &rxq->rxds[rxq->rd_p];
1857 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1861 * We got a packet. Let's alloc a new mbuff for refilling the
1862 * free descriptor ring as soon as possible
1864 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1865 if (unlikely(new_mb == NULL)) {
1866 RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1867 "queue_id=%u\n", (unsigned)rxq->port_id,
1868 (unsigned)rxq->qidx);
1869 nfp_net_mbuf_alloc_failed(rxq);
1876 * Grab the mbuff and refill the descriptor with the
1877 * previously allocated mbuff
1882 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1883 rxds->rxd.data_len, rxq->mbuf_size);
1885 /* Size of this segment */
1886 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1887 /* Size of the whole packet. We just support 1 segment */
1888 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1890 if (unlikely((mb->data_len + hw->rx_offset) >
1893 * This should not happen and the user has the
1894 * responsibility of avoiding it. But we have
1895 * to give some info about the error
1897 RTE_LOG_DP(ERR, PMD,
1898 "mbuf overflow likely due to the RX offset.\n"
1899 "\t\tYour mbuf size should have extra space for"
1900 " RX offset=%u bytes.\n"
1901 "\t\tCurrently you just have %u bytes available"
1902 " but the received packet is %u bytes long",
1904 rxq->mbuf_size - hw->rx_offset,
1909 /* Filling the received mbuff with packet info */
1911 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1913 mb->data_off = RTE_PKTMBUF_HEADROOM +
1914 NFP_DESC_META_LEN(rxds);
1916 /* No scatter mode supported */
1920 /* Checking the RSS flag */
1921 nfp_net_set_hash(rxq, rxds, mb);
1923 /* Checking the checksum flag */
1924 nfp_net_rx_cksum(rxq, rxds, mb);
1926 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1927 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1928 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1929 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1932 /* Adding the mbuff to the mbuff array passed by the app */
1933 rx_pkts[avail++] = mb;
1935 /* Now resetting and updating the descriptor */
1938 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1940 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1941 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1944 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
1951 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1952 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1954 nb_hold += rxq->nb_rx_hold;
1957 * FL descriptors needs to be written before incrementing the
1958 * FL queue WR pointer
1961 if (nb_hold > rxq->rx_free_thresh) {
1962 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1963 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1964 (unsigned)nb_hold, (unsigned)avail);
1965 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1968 rxq->nb_rx_hold = nb_hold;
1974 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1976 * @txq: TX queue to work with
1977 * Returns number of descriptors freed
1980 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1985 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1986 " status\n", txq->qidx);
1988 /* Work out how many packets have been sent */
1989 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1991 if (qcp_rd_p == txq->rd_p) {
1992 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1993 "packets (%u, %u)\n", txq->qidx,
1994 qcp_rd_p, txq->rd_p);
1998 if (qcp_rd_p > txq->rd_p)
1999 todo = qcp_rd_p - txq->rd_p;
2001 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2003 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2004 qcp_rd_p, txq->rd_p, txq->rd_p);
2010 if (unlikely(txq->rd_p >= txq->tx_count))
2011 txq->rd_p -= txq->tx_count;
2016 /* Leaving always free descriptors for avoiding wrapping confusion */
2018 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2020 if (txq->wr_p >= txq->rd_p)
2021 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2023 return txq->rd_p - txq->wr_p - 8;
2027 * nfp_net_txq_full - Check if the TX queue free descriptors
2028 * is below tx_free_threshold
2030 * @txq: TX queue to check
2032 * This function uses the host copy* of read/write pointers
2035 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2037 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2041 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2043 struct nfp_net_txq *txq;
2044 struct nfp_net_hw *hw;
2045 struct nfp_net_tx_desc *txds, txd;
2046 struct rte_mbuf *pkt;
2048 int pkt_size, dma_size;
2049 uint16_t free_descs, issued_descs;
2050 struct rte_mbuf **lmbuf;
2055 txds = &txq->txds[txq->wr_p];
2057 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2058 txq->qidx, txq->wr_p, nb_pkts);
2060 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2061 nfp_net_tx_free_bufs(txq);
2063 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2064 if (unlikely(free_descs == 0))
2071 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2072 txq->qidx, nb_pkts);
2073 /* Sending packets */
2074 while ((i < nb_pkts) && free_descs) {
2075 /* Grabbing the mbuf linked to the current descriptor */
2076 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2077 /* Warming the cache for releasing the mbuf later on */
2078 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2080 pkt = *(tx_pkts + i);
2082 if (unlikely((pkt->nb_segs > 1) &&
2083 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2084 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2085 rte_panic("Multisegment packet unsupported\n");
2088 /* Checking if we have enough descriptors */
2089 if (unlikely(pkt->nb_segs > free_descs))
2093 * Checksum and VLAN flags just in the first descriptor for a
2094 * multisegment packet, but TSO info needs to be in all of them.
2096 txd.data_len = pkt->pkt_len;
2097 nfp_net_tx_tso(txq, &txd, pkt);
2098 nfp_net_tx_cksum(txq, &txd, pkt);
2100 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2101 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2102 txd.flags |= PCIE_DESC_TX_VLAN;
2103 txd.vlan = pkt->vlan_tci;
2107 * mbuf data_len is the data in one segment and pkt_len data
2108 * in the whole packet. When the packet is just one segment,
2109 * then data_len = pkt_len
2111 pkt_size = pkt->pkt_len;
2114 /* Copying TSO, VLAN and cksum info */
2117 /* Releasing mbuf used by this descriptor previously*/
2119 rte_pktmbuf_free_seg(*lmbuf);
2122 * Linking mbuf with descriptor for being released
2123 * next time descriptor is used
2127 dma_size = pkt->data_len;
2128 dma_addr = rte_mbuf_data_dma_addr(pkt);
2129 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2130 "%" PRIx64 "\n", dma_addr);
2132 /* Filling descriptors fields */
2133 txds->dma_len = dma_size;
2134 txds->data_len = txd.data_len;
2135 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2136 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2137 ASSERT(free_descs > 0);
2141 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2144 pkt_size -= dma_size;
2147 txds->offset_eop |= PCIE_DESC_TX_EOP;
2149 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2152 /* Referencing next free TX descriptor */
2153 txds = &txq->txds[txq->wr_p];
2154 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2161 /* Increment write pointers. Force memory write before we let HW know */
2163 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2169 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2171 uint32_t new_ctrl, update;
2172 struct nfp_net_hw *hw;
2174 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2178 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2179 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2180 " ETH_VLAN_EXTEND_OFFLOAD");
2182 /* Enable vlan strip if it is not configured yet */
2183 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2184 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2185 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2187 /* Disable vlan strip just if it is configured */
2188 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2189 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2190 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2195 update = NFP_NET_CFG_UPDATE_GEN;
2197 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2200 hw->ctrl = new_ctrl;
2203 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2205 nfp_net_reta_update(struct rte_eth_dev *dev,
2206 struct rte_eth_rss_reta_entry64 *reta_conf,
2209 uint32_t reta, mask;
2213 struct nfp_net_hw *hw =
2214 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2219 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2220 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2221 "(%d) doesn't match the number hardware can supported "
2222 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2227 * Update Redirection Table. There are 128 8bit-entries which can be
2228 * manage as 32 32bit-entries
2230 for (i = 0; i < reta_size; i += 4) {
2231 /* Handling 4 RSS entries per loop */
2232 idx = i / RTE_RETA_GROUP_SIZE;
2233 shift = i % RTE_RETA_GROUP_SIZE;
2234 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2240 /* If all 4 entries were set, don't need read RETA register */
2242 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2244 for (j = 0; j < 4; j++) {
2245 if (!(mask & (0x1 << j)))
2248 /* Clearing the entry bits */
2249 reta &= ~(0xFF << (8 * j));
2250 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2252 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2256 update = NFP_NET_CFG_UPDATE_RSS;
2258 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2264 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2266 nfp_net_reta_query(struct rte_eth_dev *dev,
2267 struct rte_eth_rss_reta_entry64 *reta_conf,
2273 struct nfp_net_hw *hw;
2275 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2280 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2281 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2282 "(%d) doesn't match the number hardware can supported "
2283 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2288 * Reading Redirection Table. There are 128 8bit-entries which can be
2289 * manage as 32 32bit-entries
2291 for (i = 0; i < reta_size; i += 4) {
2292 /* Handling 4 RSS entries per loop */
2293 idx = i / RTE_RETA_GROUP_SIZE;
2294 shift = i % RTE_RETA_GROUP_SIZE;
2295 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2300 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2302 for (j = 0; j < 4; j++) {
2303 if (!(mask & (0x1 << j)))
2305 reta_conf->reta[shift + j] =
2306 (uint8_t)((reta >> (8 * j)) & 0xF);
2313 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2314 struct rte_eth_rss_conf *rss_conf)
2317 uint32_t cfg_rss_ctrl = 0;
2321 struct nfp_net_hw *hw;
2323 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2325 rss_hf = rss_conf->rss_hf;
2327 /* Checking if RSS is enabled */
2328 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2329 if (rss_hf != 0) { /* Enable RSS? */
2330 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2333 return 0; /* Nothing to do */
2336 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2337 RTE_LOG(ERR, PMD, "hash key too long\n");
2341 if (rss_hf & ETH_RSS_IPV4)
2342 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2343 NFP_NET_CFG_RSS_IPV4_TCP |
2344 NFP_NET_CFG_RSS_IPV4_UDP;
2346 if (rss_hf & ETH_RSS_IPV6)
2347 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2348 NFP_NET_CFG_RSS_IPV6_TCP |
2349 NFP_NET_CFG_RSS_IPV6_UDP;
2351 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2352 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2354 /* configuring where to apply the RSS hash */
2355 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2357 /* Writing the key byte a byte */
2358 for (i = 0; i < rss_conf->rss_key_len; i++) {
2359 memcpy(&key, &rss_conf->rss_key[i], 1);
2360 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2363 /* Writing the key size */
2364 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2366 update = NFP_NET_CFG_UPDATE_RSS;
2368 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2375 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2376 struct rte_eth_rss_conf *rss_conf)
2379 uint32_t cfg_rss_ctrl;
2382 struct nfp_net_hw *hw;
2384 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2386 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2389 rss_hf = rss_conf->rss_hf;
2390 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2392 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2393 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2395 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2396 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2398 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2399 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2401 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2402 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2404 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2405 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2407 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2408 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2410 /* Reading the key size */
2411 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2413 /* Reading the key byte a byte */
2414 for (i = 0; i < rss_conf->rss_key_len; i++) {
2415 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2416 memcpy(&rss_conf->rss_key[i], &key, 1);
2422 /* Initialise and register driver with DPDK Application */
2423 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2424 .dev_configure = nfp_net_configure,
2425 .dev_start = nfp_net_start,
2426 .dev_stop = nfp_net_stop,
2427 .dev_close = nfp_net_close,
2428 .promiscuous_enable = nfp_net_promisc_enable,
2429 .promiscuous_disable = nfp_net_promisc_disable,
2430 .link_update = nfp_net_link_update,
2431 .stats_get = nfp_net_stats_get,
2432 .stats_reset = nfp_net_stats_reset,
2433 .dev_infos_get = nfp_net_infos_get,
2434 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2435 .mtu_set = nfp_net_dev_mtu_set,
2436 .vlan_offload_set = nfp_net_vlan_offload_set,
2437 .reta_update = nfp_net_reta_update,
2438 .reta_query = nfp_net_reta_query,
2439 .rss_hash_update = nfp_net_rss_hash_update,
2440 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2441 .rx_queue_setup = nfp_net_rx_queue_setup,
2442 .rx_queue_release = nfp_net_rx_queue_release,
2443 .rx_queue_count = nfp_net_rx_queue_count,
2444 .tx_queue_setup = nfp_net_tx_queue_setup,
2445 .tx_queue_release = nfp_net_tx_queue_release,
2446 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2447 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2451 nfp_net_init(struct rte_eth_dev *eth_dev)
2453 struct rte_pci_device *pci_dev;
2454 struct nfp_net_hw *hw;
2456 uint32_t tx_bar_off, rx_bar_off;
2460 PMD_INIT_FUNC_TRACE();
2462 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2464 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2465 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2466 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2468 /* For secondary processes, the primary has done all the work */
2469 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2472 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2473 rte_eth_copy_pci_info(eth_dev, pci_dev);
2474 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2476 hw->device_id = pci_dev->id.device_id;
2477 hw->vendor_id = pci_dev->id.vendor_id;
2478 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2479 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2481 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2482 pci_dev->id.vendor_id, pci_dev->id.device_id,
2483 pci_dev->addr.domain, pci_dev->addr.bus,
2484 pci_dev->addr.devid, pci_dev->addr.function);
2486 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2487 if (hw->ctrl_bar == NULL) {
2489 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2492 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2493 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2495 /* Work out where in the BAR the queues start. */
2496 switch (pci_dev->id.device_id) {
2497 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2498 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2499 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2500 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2501 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2504 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2508 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x", tx_bar_off);
2509 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x", rx_bar_off);
2511 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2512 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2514 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2515 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2517 nfp_net_cfg_queue_setup(hw);
2519 /* Get some of the read-only fields from the config BAR */
2520 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2521 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2522 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2523 hw->mtu = hw->max_mtu;
2525 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2526 hw->rx_offset = NFP_NET_RX_OFFSET;
2528 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2530 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2531 hw->ver, hw->max_mtu);
2532 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
2533 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2534 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2535 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2536 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2537 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2538 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2539 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2540 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2541 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2545 hw->stride_rx = stride;
2546 hw->stride_tx = stride;
2548 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2549 hw->max_rx_queues, hw->max_tx_queues);
2551 /* Initializing spinlock for reconfigs */
2552 rte_spinlock_init(&hw->reconfig_lock);
2554 /* Allocating memory for mac addr */
2555 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2556 if (eth_dev->data->mac_addrs == NULL) {
2557 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2561 nfp_net_read_mac(hw);
2563 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2564 /* Using random mac addresses for VFs */
2565 eth_random_addr(&hw->mac_addr[0]);
2566 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2569 /* Copying mac address to DPDK eth_dev struct */
2570 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2571 ð_dev->data->mac_addrs[0]);
2573 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2574 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2575 eth_dev->data->port_id, pci_dev->id.vendor_id,
2576 pci_dev->id.device_id,
2577 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2578 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2580 /* Registering LSC interrupt handler */
2581 rte_intr_callback_register(&pci_dev->intr_handle,
2582 nfp_net_dev_interrupt_handler,
2585 /* Telling the firmware about the LSC interrupt entry */
2586 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2588 /* Recording current stats counters values */
2589 nfp_net_stats_reset(eth_dev);
2594 static const struct rte_pci_id pci_id_nfp_net_map[] = {
2596 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2597 PCI_DEVICE_ID_NFP6000_PF_NIC)
2600 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2601 PCI_DEVICE_ID_NFP6000_VF_NIC)
2608 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2609 struct rte_pci_device *pci_dev)
2611 return rte_eth_dev_pci_generic_probe(pci_dev,
2612 sizeof(struct nfp_net_adapter), nfp_net_init);
2615 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
2617 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2620 static struct rte_pci_driver rte_nfp_net_pmd = {
2621 .id_table = pci_id_nfp_net_map,
2622 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2623 .probe = eth_nfp_pci_probe,
2624 .remove = eth_nfp_pci_remove,
2627 RTE_PMD_REGISTER_PCI(net_nfp, rte_nfp_net_pmd);
2628 RTE_PMD_REGISTER_PCI_TABLE(net_nfp, pci_id_nfp_net_map);
2629 RTE_PMD_REGISTER_KMOD_DEP(net_nfp, "* igb_uio | uio_pci_generic | vfio-pci");
2633 * c-file-style: "Linux"
2634 * indent-tabs-mode: t