2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev_driver.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
58 #include "nfpcore/nfp_cpp.h"
59 #include "nfpcore/nfp_nffw.h"
60 #include "nfpcore/nfp_hwinfo.h"
61 #include "nfpcore/nfp_mip.h"
62 #include "nfpcore/nfp_rtsym.h"
63 #include "nfpcore/nfp_nsp.h"
65 #include "nfp_net_pmd.h"
66 #include "nfp_net_logs.h"
67 #include "nfp_net_ctrl.h"
70 static void nfp_net_close(struct rte_eth_dev *dev);
71 static int nfp_net_configure(struct rte_eth_dev *dev);
72 static void nfp_net_dev_interrupt_handler(void *param);
73 static void nfp_net_dev_interrupt_delayed_handler(void *param);
74 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
75 static void nfp_net_infos_get(struct rte_eth_dev *dev,
76 struct rte_eth_dev_info *dev_info);
77 static int nfp_net_init(struct rte_eth_dev *eth_dev);
78 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
79 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
80 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
81 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
82 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
84 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
86 static void nfp_net_rx_queue_release(void *rxq);
87 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_rxconf *rx_conf,
90 struct rte_mempool *mp);
91 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
92 static void nfp_net_tx_queue_release(void *txq);
93 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
94 uint16_t nb_desc, unsigned int socket_id,
95 const struct rte_eth_txconf *tx_conf);
96 static int nfp_net_start(struct rte_eth_dev *dev);
97 static int nfp_net_stats_get(struct rte_eth_dev *dev,
98 struct rte_eth_stats *stats);
99 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
100 static void nfp_net_stop(struct rte_eth_dev *dev);
101 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
104 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
105 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
106 struct rte_eth_rss_conf *rss_conf);
107 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
108 struct rte_eth_rss_reta_entry64 *reta_conf,
110 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
111 struct rte_eth_rss_conf *rss_conf);
113 /* The offset of the queue controller queues in the PCIe Target */
114 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
116 /* Maximum value which can be added to a queue with one transaction */
117 #define NFP_QCP_MAX_ADD 0x7f
119 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
120 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
122 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
124 NFP_QCP_READ_PTR = 0,
129 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
130 * @q: Base address for queue structure
131 * @ptr: Add to the Read or Write pointer
132 * @val: Value to add to the queue pointer
134 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
137 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
141 if (ptr == NFP_QCP_READ_PTR)
142 off = NFP_QCP_QUEUE_ADD_RPTR;
144 off = NFP_QCP_QUEUE_ADD_WPTR;
146 while (val > NFP_QCP_MAX_ADD) {
147 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
148 val -= NFP_QCP_MAX_ADD;
151 nn_writel(rte_cpu_to_le_32(val), q + off);
155 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
156 * @q: Base address for queue structure
157 * @ptr: Read or Write pointer
159 static inline uint32_t
160 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
165 if (ptr == NFP_QCP_READ_PTR)
166 off = NFP_QCP_QUEUE_STS_LO;
168 off = NFP_QCP_QUEUE_STS_HI;
170 val = rte_cpu_to_le_32(nn_readl(q + off));
172 if (ptr == NFP_QCP_READ_PTR)
173 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
175 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
179 * Functions to read/write from/to Config BAR
180 * Performs any endian conversion necessary.
182 static inline uint8_t
183 nn_cfg_readb(struct nfp_net_hw *hw, int off)
185 return nn_readb(hw->ctrl_bar + off);
189 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
191 nn_writeb(val, hw->ctrl_bar + off);
194 static inline uint32_t
195 nn_cfg_readl(struct nfp_net_hw *hw, int off)
197 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
201 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
203 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
206 static inline uint64_t
207 nn_cfg_readq(struct nfp_net_hw *hw, int off)
209 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
213 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
215 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
219 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
223 if (rxq->rxbufs == NULL)
226 for (i = 0; i < rxq->rx_count; i++) {
227 if (rxq->rxbufs[i].mbuf) {
228 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
229 rxq->rxbufs[i].mbuf = NULL;
235 nfp_net_rx_queue_release(void *rx_queue)
237 struct nfp_net_rxq *rxq = rx_queue;
240 nfp_net_rx_queue_release_mbufs(rxq);
241 rte_free(rxq->rxbufs);
247 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
249 nfp_net_rx_queue_release_mbufs(rxq);
255 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
259 if (txq->txbufs == NULL)
262 for (i = 0; i < txq->tx_count; i++) {
263 if (txq->txbufs[i].mbuf) {
264 rte_pktmbuf_free(txq->txbufs[i].mbuf);
265 txq->txbufs[i].mbuf = NULL;
271 nfp_net_tx_queue_release(void *tx_queue)
273 struct nfp_net_txq *txq = tx_queue;
276 nfp_net_tx_queue_release_mbufs(txq);
277 rte_free(txq->txbufs);
283 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
285 nfp_net_tx_queue_release_mbufs(txq);
291 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
295 struct timespec wait;
297 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
300 if (hw->qcp_cfg == NULL)
301 rte_panic("Bad configuration queue pointer\n");
303 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
306 wait.tv_nsec = 1000000;
308 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
310 /* Poll update field, waiting for NFP to ack the config */
311 for (cnt = 0; ; cnt++) {
312 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
315 if (new & NFP_NET_CFG_UPDATE_ERR) {
316 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
319 if (cnt >= NFP_NET_POLL_TIMEOUT) {
320 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
321 " %dms", update, cnt);
322 rte_panic("Exiting\n");
324 nanosleep(&wait, 0); /* waiting for a 1ms */
326 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
331 * Reconfigure the NIC
332 * @nn: device to reconfigure
333 * @ctrl: The value for the ctrl field in the BAR config
334 * @update: The value for the update field in the BAR config
336 * Write the update word to the BAR and ping the reconfig queue. Then poll
337 * until the firmware has acknowledged the update by zeroing the update word.
340 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
344 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
347 rte_spinlock_lock(&hw->reconfig_lock);
349 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
350 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
354 err = __nfp_net_reconfig(hw, update);
356 rte_spinlock_unlock(&hw->reconfig_lock);
362 * Reconfig errors imply situations where they can be handled.
363 * Otherwise, rte_panic is called inside __nfp_net_reconfig
365 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
371 * Configure an Ethernet device. This function must be invoked first
372 * before any other function in the Ethernet API. This function can
373 * also be re-invoked when a device is in the stopped state.
376 nfp_net_configure(struct rte_eth_dev *dev)
378 struct rte_eth_conf *dev_conf;
379 struct rte_eth_rxmode *rxmode;
380 struct rte_eth_txmode *txmode;
381 struct nfp_net_hw *hw;
383 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
386 * A DPDK app sends info about how many queues to use and how
387 * those queues need to be configured. This is used by the
388 * DPDK core and it makes sure no more queues than those
389 * advertised by the driver are requested. This function is
390 * called after that internal process
393 PMD_INIT_LOG(DEBUG, "Configure");
395 dev_conf = &dev->data->dev_conf;
396 rxmode = &dev_conf->rxmode;
397 txmode = &dev_conf->txmode;
399 /* Checking TX mode */
400 if (txmode->mq_mode) {
401 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
405 /* Checking RX mode */
406 if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
407 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
408 PMD_INIT_LOG(INFO, "RSS not supported");
412 /* Checking RX offloads */
413 if (rxmode->offloads & DEV_RX_OFFLOAD_HEADER_SPLIT) {
414 PMD_INIT_LOG(INFO, "rxmode does not support split header");
418 if ((rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) &&
419 !(hw->cap & NFP_NET_CFG_CTRL_RXCSUM))
420 PMD_INIT_LOG(INFO, "RXCSUM not supported");
422 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
423 PMD_INIT_LOG(INFO, "VLAN filter not supported");
427 if ((rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) &&
428 !(hw->cap & NFP_NET_CFG_CTRL_RXVLAN)) {
429 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
433 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
434 PMD_INIT_LOG(INFO, "VLAN extended not supported");
438 if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
439 PMD_INIT_LOG(INFO, "LRO not supported");
443 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP) {
444 PMD_INIT_LOG(INFO, "QINQ STRIP not supported");
448 if (rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) {
449 PMD_INIT_LOG(INFO, "Outer IP checksum not supported");
453 if (rxmode->offloads & DEV_RX_OFFLOAD_MACSEC_STRIP) {
454 PMD_INIT_LOG(INFO, "MACSEC strip not supported");
458 if (rxmode->offloads & DEV_RX_OFFLOAD_MACSEC_STRIP) {
459 PMD_INIT_LOG(INFO, "MACSEC strip not supported");
463 if (!(rxmode->offloads & DEV_RX_OFFLOAD_CRC_STRIP))
464 PMD_INIT_LOG(INFO, "HW does strip CRC. No configurable!");
466 if ((rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) &&
467 !(hw->cap & NFP_NET_CFG_CTRL_SCATTER)) {
468 PMD_INIT_LOG(INFO, "Scatter not supported");
472 if (rxmode->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
473 PMD_INIT_LOG(INFO, "timestamp offfload not supported");
477 if (rxmode->offloads & DEV_RX_OFFLOAD_SECURITY) {
478 PMD_INIT_LOG(INFO, "security offload not supported");
482 /* checking TX offloads */
483 if ((txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT) &&
484 !(hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
485 PMD_INIT_LOG(INFO, "vlan insert offload not supported");
489 if ((txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) &&
490 !(hw->cap & NFP_NET_CFG_CTRL_TXCSUM)) {
491 PMD_INIT_LOG(INFO, "TX checksum offload not supported");
495 if (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) {
496 PMD_INIT_LOG(INFO, "TX SCTP checksum offload not supported");
500 if ((txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) &&
501 !(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)) {
502 PMD_INIT_LOG(INFO, "TSO TCP offload not supported");
506 if (txmode->offloads & DEV_TX_OFFLOAD_UDP_TSO) {
507 PMD_INIT_LOG(INFO, "TSO UDP offload not supported");
511 if (txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) {
512 PMD_INIT_LOG(INFO, "TX outer checksum offload not supported");
516 if (txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT) {
517 PMD_INIT_LOG(INFO, "QINQ insert offload not supported");
521 if (txmode->offloads & DEV_TX_OFFLOAD_VXLAN_TNL_TSO ||
522 txmode->offloads & DEV_TX_OFFLOAD_GRE_TNL_TSO ||
523 txmode->offloads & DEV_TX_OFFLOAD_IPIP_TNL_TSO ||
524 txmode->offloads & DEV_TX_OFFLOAD_GENEVE_TNL_TSO) {
525 PMD_INIT_LOG(INFO, "tunneling offload not supported");
529 if (txmode->offloads & DEV_TX_OFFLOAD_MACSEC_INSERT) {
530 PMD_INIT_LOG(INFO, "TX MACSEC offload not supported");
534 if (txmode->offloads & DEV_TX_OFFLOAD_MT_LOCKFREE) {
535 PMD_INIT_LOG(INFO, "multiqueue lockfree not supported");
539 if ((txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) &&
540 !(hw->cap & NFP_NET_CFG_CTRL_GATHER)) {
541 PMD_INIT_LOG(INFO, "TX multisegs not supported");
545 if (txmode->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
546 PMD_INIT_LOG(INFO, "mbuf fast-free not supported");
550 if (txmode->offloads & DEV_TX_OFFLOAD_SECURITY) {
551 PMD_INIT_LOG(INFO, "TX security offload not supported");
559 nfp_net_enable_queues(struct rte_eth_dev *dev)
561 struct nfp_net_hw *hw;
562 uint64_t enabled_queues = 0;
565 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
567 /* Enabling the required TX queues in the device */
568 for (i = 0; i < dev->data->nb_tx_queues; i++)
569 enabled_queues |= (1 << i);
571 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
575 /* Enabling the required RX queues in the device */
576 for (i = 0; i < dev->data->nb_rx_queues; i++)
577 enabled_queues |= (1 << i);
579 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
583 nfp_net_disable_queues(struct rte_eth_dev *dev)
585 struct nfp_net_hw *hw;
586 uint32_t new_ctrl, update = 0;
588 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
590 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
591 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
593 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
594 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
595 NFP_NET_CFG_UPDATE_MSIX;
597 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
598 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
600 /* If an error when reconfig we avoid to change hw state */
601 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
608 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
612 for (i = 0; i < dev->data->nb_rx_queues; i++) {
613 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
620 nfp_net_params_setup(struct nfp_net_hw *hw)
622 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
623 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
627 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
629 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
632 #define ETH_ADDR_LEN 6
635 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
639 for (i = 0; i < ETH_ADDR_LEN; i++)
644 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
646 struct nfp_eth_table *nfp_eth_table;
648 nfp_eth_table = nfp_eth_read_ports(hw->cpp);
650 * hw points to port0 private data. We need hw now pointing to
654 nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
655 (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
662 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
666 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
667 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
669 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
670 memcpy(&hw->mac_addr[4], &tmp, 2);
674 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
676 uint32_t mac0 = *(uint32_t *)mac;
679 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
682 mac1 = *(uint16_t *)mac;
683 nn_writew(rte_cpu_to_be_16(mac1),
684 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
688 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
689 struct rte_intr_handle *intr_handle)
691 struct nfp_net_hw *hw;
694 if (!intr_handle->intr_vec) {
695 intr_handle->intr_vec =
696 rte_zmalloc("intr_vec",
697 dev->data->nb_rx_queues * sizeof(int), 0);
698 if (!intr_handle->intr_vec) {
699 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
700 " intr_vec", dev->data->nb_rx_queues);
705 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
707 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
708 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
709 /* UIO just supports one queue and no LSC*/
710 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
711 intr_handle->intr_vec[0] = 0;
713 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
714 for (i = 0; i < dev->data->nb_rx_queues; i++) {
716 * The first msix vector is reserved for non
719 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
720 intr_handle->intr_vec[i] = i + 1;
721 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
722 intr_handle->intr_vec[i]);
726 /* Avoiding TX interrupts */
727 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
732 nfp_check_offloads(struct rte_eth_dev *dev)
734 struct nfp_net_hw *hw;
735 struct rte_eth_conf *dev_conf;
736 struct rte_eth_rxmode *rxmode;
737 struct rte_eth_txmode *txmode;
740 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
742 dev_conf = &dev->data->dev_conf;
743 rxmode = &dev_conf->rxmode;
744 txmode = &dev_conf->txmode;
746 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
747 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
748 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
751 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
752 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
753 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
756 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
757 hw->mtu = rxmode->max_rx_pkt_len;
759 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
760 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
763 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
764 ctrl |= NFP_NET_CFG_CTRL_L2BC;
767 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
768 ctrl |= NFP_NET_CFG_CTRL_L2MC;
770 /* TX checksum offload */
771 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
772 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
773 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
774 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
777 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
778 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
779 ctrl |= NFP_NET_CFG_CTRL_LSO;
781 ctrl |= NFP_NET_CFG_CTRL_LSO2;
785 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
786 ctrl |= NFP_NET_CFG_CTRL_GATHER;
792 nfp_net_start(struct rte_eth_dev *dev)
794 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
795 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
796 uint32_t new_ctrl, update = 0;
797 struct nfp_net_hw *hw;
798 struct rte_eth_conf *dev_conf;
799 struct rte_eth_rxmode *rxmode;
800 uint32_t intr_vector;
803 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
805 PMD_INIT_LOG(DEBUG, "Start");
807 /* Disabling queues just in case... */
808 nfp_net_disable_queues(dev);
810 /* Enabling the required queues in the device */
811 nfp_net_enable_queues(dev);
813 /* check and configure queue intr-vector mapping */
814 if (dev->data->dev_conf.intr_conf.rxq != 0) {
815 if (hw->pf_multiport_enabled) {
816 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
817 "with NFP multiport PF");
820 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
822 * Better not to share LSC with RX interrupts.
823 * Unregistering LSC interrupt handler
825 rte_intr_callback_unregister(&pci_dev->intr_handle,
826 nfp_net_dev_interrupt_handler, (void *)dev);
828 if (dev->data->nb_rx_queues > 1) {
829 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
830 "supports 1 queue with UIO");
834 intr_vector = dev->data->nb_rx_queues;
835 if (rte_intr_efd_enable(intr_handle, intr_vector))
838 nfp_configure_rx_interrupt(dev, intr_handle);
839 update = NFP_NET_CFG_UPDATE_MSIX;
842 rte_intr_enable(intr_handle);
844 new_ctrl = nfp_check_offloads(dev);
846 /* Writing configuration parameters in the device */
847 nfp_net_params_setup(hw);
849 dev_conf = &dev->data->dev_conf;
850 rxmode = &dev_conf->rxmode;
852 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
853 nfp_net_rss_config_default(dev);
854 update |= NFP_NET_CFG_UPDATE_RSS;
855 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
859 new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
861 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
863 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
864 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
866 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
867 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
871 * Allocating rte mbuffs for configured rx queues.
872 * This requires queues being enabled before
874 if (nfp_net_rx_freelist_setup(dev) < 0) {
880 /* Configure the physical port up */
881 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
889 * An error returned by this function should mean the app
890 * exiting and then the system releasing all the memory
891 * allocated even memory coming from hugepages.
893 * The device could be enabled at this point with some queues
894 * ready for getting packets. This is true if the call to
895 * nfp_net_rx_freelist_setup() succeeds for some queues but
896 * fails for subsequent queues.
898 * This should make the app exiting but better if we tell the
901 nfp_net_disable_queues(dev);
906 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
908 nfp_net_stop(struct rte_eth_dev *dev)
911 struct nfp_net_hw *hw;
913 PMD_INIT_LOG(DEBUG, "Stop");
915 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
917 nfp_net_disable_queues(dev);
920 for (i = 0; i < dev->data->nb_tx_queues; i++) {
921 nfp_net_reset_tx_queue(
922 (struct nfp_net_txq *)dev->data->tx_queues[i]);
925 for (i = 0; i < dev->data->nb_rx_queues; i++) {
926 nfp_net_reset_rx_queue(
927 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
931 /* Configure the physical port down */
932 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
935 /* Reset and stop device. The device can not be restarted. */
937 nfp_net_close(struct rte_eth_dev *dev)
939 struct nfp_net_hw *hw;
940 struct rte_pci_device *pci_dev;
943 PMD_INIT_LOG(DEBUG, "Close");
945 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
946 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
949 * We assume that the DPDK application is stopping all the
950 * threads/queues before calling the device close function.
953 nfp_net_disable_queues(dev);
956 for (i = 0; i < dev->data->nb_tx_queues; i++) {
957 nfp_net_reset_tx_queue(
958 (struct nfp_net_txq *)dev->data->tx_queues[i]);
961 for (i = 0; i < dev->data->nb_rx_queues; i++) {
962 nfp_net_reset_rx_queue(
963 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
966 rte_intr_disable(&pci_dev->intr_handle);
967 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
969 /* unregister callback func from eal lib */
970 rte_intr_callback_unregister(&pci_dev->intr_handle,
971 nfp_net_dev_interrupt_handler,
975 * The ixgbe PMD driver disables the pcie master on the
976 * device. The i40e does not...
981 nfp_net_promisc_enable(struct rte_eth_dev *dev)
983 uint32_t new_ctrl, update = 0;
984 struct nfp_net_hw *hw;
986 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
988 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
990 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
991 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
995 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
996 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
1000 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
1001 update = NFP_NET_CFG_UPDATE_GEN;
1004 * DPDK sets promiscuous mode on just after this call assuming
1005 * it can not fail ...
1007 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
1010 hw->ctrl = new_ctrl;
1014 nfp_net_promisc_disable(struct rte_eth_dev *dev)
1016 uint32_t new_ctrl, update = 0;
1017 struct nfp_net_hw *hw;
1019 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1021 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
1022 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
1026 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
1027 update = NFP_NET_CFG_UPDATE_GEN;
1030 * DPDK sets promiscuous mode off just before this call
1031 * assuming it can not fail ...
1033 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
1036 hw->ctrl = new_ctrl;
1040 * return 0 means link status changed, -1 means not changed
1042 * Wait to complete is needed as it can take up to 9 seconds to get the Link
1046 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1048 struct nfp_net_hw *hw;
1049 struct rte_eth_link link;
1050 uint32_t nn_link_status;
1053 static const uint32_t ls_to_ethtool[] = {
1054 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
1055 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
1056 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
1057 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
1058 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
1059 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
1060 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
1061 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
1064 PMD_DRV_LOG(DEBUG, "Link update\n");
1066 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1068 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1070 memset(&link, 0, sizeof(struct rte_eth_link));
1072 if (nn_link_status & NFP_NET_CFG_STS_LINK)
1073 link.link_status = ETH_LINK_UP;
1075 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1077 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1078 NFP_NET_CFG_STS_LINK_RATE_MASK;
1080 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1081 link.link_speed = ETH_SPEED_NUM_NONE;
1083 link.link_speed = ls_to_ethtool[nn_link_status];
1085 ret = rte_eth_linkstatus_set(dev, &link);
1087 if (link.link_status)
1088 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
1090 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
1096 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1099 struct nfp_net_hw *hw;
1100 struct rte_eth_stats nfp_dev_stats;
1102 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1104 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1106 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1108 /* reading per RX ring stats */
1109 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1110 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1113 nfp_dev_stats.q_ipackets[i] =
1114 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1116 nfp_dev_stats.q_ipackets[i] -=
1117 hw->eth_stats_base.q_ipackets[i];
1119 nfp_dev_stats.q_ibytes[i] =
1120 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1122 nfp_dev_stats.q_ibytes[i] -=
1123 hw->eth_stats_base.q_ibytes[i];
1126 /* reading per TX ring stats */
1127 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1128 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1131 nfp_dev_stats.q_opackets[i] =
1132 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1134 nfp_dev_stats.q_opackets[i] -=
1135 hw->eth_stats_base.q_opackets[i];
1137 nfp_dev_stats.q_obytes[i] =
1138 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1140 nfp_dev_stats.q_obytes[i] -=
1141 hw->eth_stats_base.q_obytes[i];
1144 nfp_dev_stats.ipackets =
1145 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1147 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1149 nfp_dev_stats.ibytes =
1150 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1152 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1154 nfp_dev_stats.opackets =
1155 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1157 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1159 nfp_dev_stats.obytes =
1160 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1162 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1164 /* reading general device stats */
1165 nfp_dev_stats.ierrors =
1166 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1168 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1170 nfp_dev_stats.oerrors =
1171 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1173 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1175 /* RX ring mbuf allocation failures */
1176 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1178 nfp_dev_stats.imissed =
1179 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1181 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1184 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1191 nfp_net_stats_reset(struct rte_eth_dev *dev)
1194 struct nfp_net_hw *hw;
1196 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1199 * hw->eth_stats_base records the per counter starting point.
1200 * Lets update it now
1203 /* reading per RX ring stats */
1204 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1205 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1208 hw->eth_stats_base.q_ipackets[i] =
1209 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1211 hw->eth_stats_base.q_ibytes[i] =
1212 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1215 /* reading per TX ring stats */
1216 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1217 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1220 hw->eth_stats_base.q_opackets[i] =
1221 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1223 hw->eth_stats_base.q_obytes[i] =
1224 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1227 hw->eth_stats_base.ipackets =
1228 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1230 hw->eth_stats_base.ibytes =
1231 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1233 hw->eth_stats_base.opackets =
1234 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1236 hw->eth_stats_base.obytes =
1237 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1239 /* reading general device stats */
1240 hw->eth_stats_base.ierrors =
1241 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1243 hw->eth_stats_base.oerrors =
1244 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1246 /* RX ring mbuf allocation failures */
1247 dev->data->rx_mbuf_alloc_failed = 0;
1249 hw->eth_stats_base.imissed =
1250 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1254 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1256 struct nfp_net_hw *hw;
1258 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1260 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1261 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1262 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1263 dev_info->max_rx_pktlen = hw->max_mtu;
1264 /* Next should change when PF support is implemented */
1265 dev_info->max_mac_addrs = 1;
1267 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1268 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1270 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1271 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1272 DEV_RX_OFFLOAD_UDP_CKSUM |
1273 DEV_RX_OFFLOAD_TCP_CKSUM;
1275 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1277 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1278 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1280 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1281 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1282 DEV_TX_OFFLOAD_UDP_CKSUM |
1283 DEV_TX_OFFLOAD_TCP_CKSUM;
1285 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1286 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1288 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1289 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1291 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1293 .pthresh = DEFAULT_RX_PTHRESH,
1294 .hthresh = DEFAULT_RX_HTHRESH,
1295 .wthresh = DEFAULT_RX_WTHRESH,
1297 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1301 dev_info->default_txconf = (struct rte_eth_txconf) {
1303 .pthresh = DEFAULT_TX_PTHRESH,
1304 .hthresh = DEFAULT_TX_HTHRESH,
1305 .wthresh = DEFAULT_TX_WTHRESH,
1307 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1308 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1311 dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1312 ETH_RSS_NONFRAG_IPV4_UDP |
1313 ETH_RSS_NONFRAG_IPV6_TCP |
1314 ETH_RSS_NONFRAG_IPV6_UDP;
1316 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1317 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1319 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1320 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1321 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1324 static const uint32_t *
1325 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1327 static const uint32_t ptypes[] = {
1328 /* refers to nfp_net_set_hash() */
1329 RTE_PTYPE_INNER_L3_IPV4,
1330 RTE_PTYPE_INNER_L3_IPV6,
1331 RTE_PTYPE_INNER_L3_IPV6_EXT,
1332 RTE_PTYPE_INNER_L4_MASK,
1336 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1342 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1344 struct nfp_net_rxq *rxq;
1345 struct nfp_net_rx_desc *rxds;
1349 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1356 * Other PMDs are just checking the DD bit in intervals of 4
1357 * descriptors and counting all four if the first has the DD
1358 * bit on. Of course, this is not accurate but can be good for
1359 * performance. But ideally that should be done in descriptors
1360 * chunks belonging to the same cache line
1363 while (count < rxq->rx_count) {
1364 rxds = &rxq->rxds[idx];
1365 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1372 if ((idx) == rxq->rx_count)
1380 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1382 struct rte_pci_device *pci_dev;
1383 struct nfp_net_hw *hw;
1386 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1387 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1389 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1392 /* Make sure all updates are written before un-masking */
1394 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1395 NFP_NET_CFG_ICR_UNMASKED);
1400 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1402 struct rte_pci_device *pci_dev;
1403 struct nfp_net_hw *hw;
1406 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1407 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1409 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1412 /* Make sure all updates are written before un-masking */
1414 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1419 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1421 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1422 struct rte_eth_link link;
1424 rte_eth_linkstatus_get(dev, &link);
1425 if (link.link_status)
1426 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1427 dev->data->port_id, link.link_speed,
1428 link.link_duplex == ETH_LINK_FULL_DUPLEX
1429 ? "full-duplex" : "half-duplex");
1431 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1432 dev->data->port_id);
1434 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1435 pci_dev->addr.domain, pci_dev->addr.bus,
1436 pci_dev->addr.devid, pci_dev->addr.function);
1439 /* Interrupt configuration and handling */
1442 * nfp_net_irq_unmask - Unmask an interrupt
1444 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1445 * clear the ICR for the entry.
1448 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1450 struct nfp_net_hw *hw;
1451 struct rte_pci_device *pci_dev;
1453 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1454 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1456 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1457 /* If MSI-X auto-masking is used, clear the entry */
1459 rte_intr_enable(&pci_dev->intr_handle);
1461 /* Make sure all updates are written before un-masking */
1463 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1464 NFP_NET_CFG_ICR_UNMASKED);
1469 nfp_net_dev_interrupt_handler(void *param)
1472 struct rte_eth_link link;
1473 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1475 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1477 rte_eth_linkstatus_get(dev, &link);
1479 nfp_net_link_update(dev, 0);
1482 if (!link.link_status) {
1483 /* handle it 1 sec later, wait it being stable */
1484 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1485 /* likely to down */
1487 /* handle it 4 sec later, wait it being stable */
1488 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1491 if (rte_eal_alarm_set(timeout * 1000,
1492 nfp_net_dev_interrupt_delayed_handler,
1494 RTE_LOG(ERR, PMD, "Error setting alarm");
1496 nfp_net_irq_unmask(dev);
1501 * Interrupt handler which shall be registered for alarm callback for delayed
1502 * handling specific interrupt to wait for the stable nic state. As the NIC
1503 * interrupt state is not stable for nfp after link is just down, it needs
1504 * to wait 4 seconds to get the stable status.
1506 * @param handle Pointer to interrupt handle.
1507 * @param param The address of parameter (struct rte_eth_dev *)
1512 nfp_net_dev_interrupt_delayed_handler(void *param)
1514 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1516 nfp_net_link_update(dev, 0);
1517 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1519 nfp_net_dev_link_status_print(dev);
1522 nfp_net_irq_unmask(dev);
1526 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1528 struct nfp_net_hw *hw;
1530 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1532 /* check that mtu is within the allowed range */
1533 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1536 /* mtu setting is forbidden if port is started */
1537 if (dev->data->dev_started) {
1538 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1539 dev->data->port_id);
1543 /* switch to jumbo mode if needed */
1544 if ((uint32_t)mtu > ETHER_MAX_LEN)
1545 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1547 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1549 /* update max frame size */
1550 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1552 /* writing to configuration space */
1553 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1561 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1562 uint16_t queue_idx, uint16_t nb_desc,
1563 unsigned int socket_id,
1564 const struct rte_eth_rxconf *rx_conf,
1565 struct rte_mempool *mp)
1567 const struct rte_memzone *tz;
1568 struct nfp_net_rxq *rxq;
1569 struct nfp_net_hw *hw;
1570 struct rte_eth_conf *dev_conf;
1571 struct rte_eth_rxmode *rxmode;
1573 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1575 PMD_INIT_FUNC_TRACE();
1577 /* Validating number of descriptors */
1578 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1579 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1580 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1581 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1585 dev_conf = &dev->data->dev_conf;
1586 rxmode = &dev_conf->rxmode;
1588 if (rx_conf->offloads != rxmode->offloads) {
1589 RTE_LOG(ERR, PMD, "queue %u rx offloads not as port offloads\n",
1591 RTE_LOG(ERR, PMD, "\tport: %" PRIx64 "\n", rxmode->offloads);
1592 RTE_LOG(ERR, PMD, "\tqueue: %" PRIx64 "\n", rx_conf->offloads);
1597 * Free memory prior to re-allocation if needed. This is the case after
1598 * calling nfp_net_stop
1600 if (dev->data->rx_queues[queue_idx]) {
1601 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1602 dev->data->rx_queues[queue_idx] = NULL;
1605 /* Allocating rx queue data structure */
1606 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1607 RTE_CACHE_LINE_SIZE, socket_id);
1611 /* Hw queues mapping based on firmware confifguration */
1612 rxq->qidx = queue_idx;
1613 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1614 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1615 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1616 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1619 * Tracking mbuf size for detecting a potential mbuf overflow due to
1623 rxq->mbuf_size = rxq->mem_pool->elt_size;
1624 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1625 hw->flbufsz = rxq->mbuf_size;
1627 rxq->rx_count = nb_desc;
1628 rxq->port_id = dev->data->port_id;
1629 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1630 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1632 rxq->drop_en = rx_conf->rx_drop_en;
1635 * Allocate RX ring hardware descriptors. A memzone large enough to
1636 * handle the maximum ring size is allocated in order to allow for
1637 * resizing in later calls to the queue setup function.
1639 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1640 sizeof(struct nfp_net_rx_desc) *
1641 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1645 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1646 nfp_net_rx_queue_release(rxq);
1650 /* Saving physical and virtual addresses for the RX ring */
1651 rxq->dma = (uint64_t)tz->iova;
1652 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1654 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1655 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1656 sizeof(*rxq->rxbufs) * nb_desc,
1657 RTE_CACHE_LINE_SIZE, socket_id);
1658 if (rxq->rxbufs == NULL) {
1659 nfp_net_rx_queue_release(rxq);
1663 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1664 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1666 nfp_net_reset_rx_queue(rxq);
1668 dev->data->rx_queues[queue_idx] = rxq;
1672 * Telling the HW about the physical address of the RX ring and number
1673 * of descriptors in log2 format
1675 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1676 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1682 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1684 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1688 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1691 for (i = 0; i < rxq->rx_count; i++) {
1692 struct nfp_net_rx_desc *rxd;
1693 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1696 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1697 (unsigned)rxq->qidx);
1701 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1703 rxd = &rxq->rxds[i];
1705 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1706 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1708 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1711 /* Make sure all writes are flushed before telling the hardware */
1714 /* Not advertising the whole ring as the firmware gets confused if so */
1715 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1718 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1724 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1725 uint16_t nb_desc, unsigned int socket_id,
1726 const struct rte_eth_txconf *tx_conf)
1728 const struct rte_memzone *tz;
1729 struct nfp_net_txq *txq;
1730 uint16_t tx_free_thresh;
1731 struct nfp_net_hw *hw;
1732 struct rte_eth_conf *dev_conf;
1733 struct rte_eth_txmode *txmode;
1735 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737 PMD_INIT_FUNC_TRACE();
1739 /* Validating number of descriptors */
1740 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1741 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1742 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1743 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1747 dev_conf = &dev->data->dev_conf;
1748 txmode = &dev_conf->txmode;
1750 if (tx_conf->offloads != txmode->offloads) {
1751 RTE_LOG(ERR, PMD, "queue %u tx offloads not as port offloads",
1756 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1757 tx_conf->tx_free_thresh :
1758 DEFAULT_TX_FREE_THRESH);
1760 if (tx_free_thresh > (nb_desc)) {
1762 "tx_free_thresh must be less than the number of TX "
1763 "descriptors. (tx_free_thresh=%u port=%d "
1764 "queue=%d)\n", (unsigned int)tx_free_thresh,
1765 dev->data->port_id, (int)queue_idx);
1770 * Free memory prior to re-allocation if needed. This is the case after
1771 * calling nfp_net_stop
1773 if (dev->data->tx_queues[queue_idx]) {
1774 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1776 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1777 dev->data->tx_queues[queue_idx] = NULL;
1780 /* Allocating tx queue data structure */
1781 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1782 RTE_CACHE_LINE_SIZE, socket_id);
1784 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1789 * Allocate TX ring hardware descriptors. A memzone large enough to
1790 * handle the maximum ring size is allocated in order to allow for
1791 * resizing in later calls to the queue setup function.
1793 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1794 sizeof(struct nfp_net_tx_desc) *
1795 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1798 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1799 nfp_net_tx_queue_release(txq);
1803 txq->tx_count = nb_desc;
1804 txq->tx_free_thresh = tx_free_thresh;
1805 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1806 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1807 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1809 /* queue mapping based on firmware configuration */
1810 txq->qidx = queue_idx;
1811 txq->tx_qcidx = queue_idx * hw->stride_tx;
1812 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1814 txq->port_id = dev->data->port_id;
1816 /* Saving physical and virtual addresses for the TX ring */
1817 txq->dma = (uint64_t)tz->iova;
1818 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1820 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1821 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1822 sizeof(*txq->txbufs) * nb_desc,
1823 RTE_CACHE_LINE_SIZE, socket_id);
1824 if (txq->txbufs == NULL) {
1825 nfp_net_tx_queue_release(txq);
1828 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1829 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1831 nfp_net_reset_tx_queue(txq);
1833 dev->data->tx_queues[queue_idx] = txq;
1837 * Telling the HW about the physical address of the TX ring and number
1838 * of descriptors in log2 format
1840 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1841 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1846 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1848 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1849 struct rte_mbuf *mb)
1852 struct nfp_net_hw *hw = txq->hw;
1854 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1857 ol_flags = mb->ol_flags;
1859 if (!(ol_flags & PKT_TX_TCP_SEG))
1862 txd->l3_offset = mb->l2_len;
1863 txd->l4_offset = mb->l2_len + mb->l3_len;
1864 txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1865 txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1866 txd->flags = PCIE_DESC_TX_LSO;
1873 txd->lso_hdrlen = 0;
1877 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1879 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1880 struct rte_mbuf *mb)
1883 struct nfp_net_hw *hw = txq->hw;
1885 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1888 ol_flags = mb->ol_flags;
1890 /* IPv6 does not need checksum */
1891 if (ol_flags & PKT_TX_IP_CKSUM)
1892 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1894 switch (ol_flags & PKT_TX_L4_MASK) {
1895 case PKT_TX_UDP_CKSUM:
1896 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1898 case PKT_TX_TCP_CKSUM:
1899 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1903 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1904 txd->flags |= PCIE_DESC_TX_CSUM;
1907 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1909 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1910 struct rte_mbuf *mb)
1912 struct nfp_net_hw *hw = rxq->hw;
1914 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1917 /* If IPv4 and IP checksum error, fail */
1918 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1919 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1920 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1922 /* If neither UDP nor TCP return */
1923 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1924 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1927 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1928 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1929 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1931 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1932 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1933 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1936 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1937 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1939 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1942 * nfp_net_set_hash - Set mbuf hash data
1944 * The RSS hash and hash-type are pre-pended to the packet data.
1945 * Extract and decode it and set the mbuf fields.
1948 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1949 struct rte_mbuf *mbuf)
1951 struct nfp_net_hw *hw = rxq->hw;
1952 uint8_t *meta_offset;
1955 uint32_t hash_type = 0;
1957 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1960 /* this is true for new firmwares */
1961 if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1962 (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1963 NFP_DESC_META_LEN(rxd))) {
1966 * <---- 32 bit ----->
1971 * ====================
1974 * Field type word contains up to 8 4bit field types
1975 * A 4bit field type refers to a data field word
1976 * A data field word can have several 4bit field types
1978 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1979 meta_offset -= NFP_DESC_META_LEN(rxd);
1980 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1982 /* NFP PMD just supports metadata for hashing */
1983 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1984 case NFP_NET_META_HASH:
1985 /* next field type is about the hash type */
1986 meta_info >>= NFP_NET_META_FIELD_SIZE;
1987 /* hash value is in the data field */
1988 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1989 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1992 /* Unsupported metadata can be a performance issue */
1996 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1999 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
2000 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
2003 mbuf->hash.rss = hash;
2004 mbuf->ol_flags |= PKT_RX_RSS_HASH;
2006 switch (hash_type) {
2007 case NFP_NET_RSS_IPV4:
2008 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
2010 case NFP_NET_RSS_IPV6:
2011 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
2013 case NFP_NET_RSS_IPV6_EX:
2014 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2017 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
2022 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
2024 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
2027 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
2032 * There are some decissions to take:
2033 * 1) How to check DD RX descriptors bit
2034 * 2) How and when to allocate new mbufs
2036 * Current implementation checks just one single DD bit each loop. As each
2037 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
2038 * a single cache line instead. Tests with this change have not shown any
2039 * performance improvement but it requires further investigation. For example,
2040 * depending on which descriptor is next, the number of descriptors could be
2041 * less than 8 for just checking those in the same cache line. This implies
2042 * extra work which could be counterproductive by itself. Indeed, last firmware
2043 * changes are just doing this: writing several descriptors with the DD bit
2044 * for saving PCIe bandwidth and DMA operations from the NFP.
2046 * Mbuf allocation is done when a new packet is received. Then the descriptor
2047 * is automatically linked with the new mbuf and the old one is given to the
2048 * user. The main drawback with this design is mbuf allocation is heavier than
2049 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
2050 * cache point of view it does not seem allocating the mbuf early on as we are
2051 * doing now have any benefit at all. Again, tests with this change have not
2052 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2053 * so looking at the implications of this type of allocation should be studied
2058 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2060 struct nfp_net_rxq *rxq;
2061 struct nfp_net_rx_desc *rxds;
2062 struct nfp_net_rx_buff *rxb;
2063 struct nfp_net_hw *hw;
2064 struct rte_mbuf *mb;
2065 struct rte_mbuf *new_mb;
2071 if (unlikely(rxq == NULL)) {
2073 * DPDK just checks the queue is lower than max queues
2074 * enabled. But the queue needs to be configured
2076 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2084 while (avail < nb_pkts) {
2085 rxb = &rxq->rxbufs[rxq->rd_p];
2086 if (unlikely(rxb == NULL)) {
2087 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2091 rxds = &rxq->rxds[rxq->rd_p];
2092 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2096 * Memory barrier to ensure that we won't do other
2097 * reads before the DD bit.
2102 * We got a packet. Let's alloc a new mbuff for refilling the
2103 * free descriptor ring as soon as possible
2105 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2106 if (unlikely(new_mb == NULL)) {
2107 RTE_LOG_DP(DEBUG, PMD,
2108 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2109 rxq->port_id, (unsigned int)rxq->qidx);
2110 nfp_net_mbuf_alloc_failed(rxq);
2117 * Grab the mbuff and refill the descriptor with the
2118 * previously allocated mbuff
2123 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
2124 rxds->rxd.data_len, rxq->mbuf_size);
2126 /* Size of this segment */
2127 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2128 /* Size of the whole packet. We just support 1 segment */
2129 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2131 if (unlikely((mb->data_len + hw->rx_offset) >
2134 * This should not happen and the user has the
2135 * responsibility of avoiding it. But we have
2136 * to give some info about the error
2138 RTE_LOG_DP(ERR, PMD,
2139 "mbuf overflow likely due to the RX offset.\n"
2140 "\t\tYour mbuf size should have extra space for"
2141 " RX offset=%u bytes.\n"
2142 "\t\tCurrently you just have %u bytes available"
2143 " but the received packet is %u bytes long",
2145 rxq->mbuf_size - hw->rx_offset,
2150 /* Filling the received mbuff with packet info */
2152 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2154 mb->data_off = RTE_PKTMBUF_HEADROOM +
2155 NFP_DESC_META_LEN(rxds);
2157 /* No scatter mode supported */
2161 mb->port = rxq->port_id;
2163 /* Checking the RSS flag */
2164 nfp_net_set_hash(rxq, rxds, mb);
2166 /* Checking the checksum flag */
2167 nfp_net_rx_cksum(rxq, rxds, mb);
2169 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2170 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2171 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2172 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2175 /* Adding the mbuff to the mbuff array passed by the app */
2176 rx_pkts[avail++] = mb;
2178 /* Now resetting and updating the descriptor */
2181 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2183 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2184 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2187 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2194 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
2195 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2197 nb_hold += rxq->nb_rx_hold;
2200 * FL descriptors needs to be written before incrementing the
2201 * FL queue WR pointer
2204 if (nb_hold > rxq->rx_free_thresh) {
2205 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2206 rxq->port_id, (unsigned int)rxq->qidx,
2207 (unsigned)nb_hold, (unsigned)avail);
2208 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2211 rxq->nb_rx_hold = nb_hold;
2217 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2219 * @txq: TX queue to work with
2220 * Returns number of descriptors freed
2223 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2228 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2229 " status\n", txq->qidx);
2231 /* Work out how many packets have been sent */
2232 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2234 if (qcp_rd_p == txq->rd_p) {
2235 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2236 "packets (%u, %u)\n", txq->qidx,
2237 qcp_rd_p, txq->rd_p);
2241 if (qcp_rd_p > txq->rd_p)
2242 todo = qcp_rd_p - txq->rd_p;
2244 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2246 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2247 qcp_rd_p, txq->rd_p, txq->rd_p);
2253 if (unlikely(txq->rd_p >= txq->tx_count))
2254 txq->rd_p -= txq->tx_count;
2259 /* Leaving always free descriptors for avoiding wrapping confusion */
2261 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2263 if (txq->wr_p >= txq->rd_p)
2264 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2266 return txq->rd_p - txq->wr_p - 8;
2270 * nfp_net_txq_full - Check if the TX queue free descriptors
2271 * is below tx_free_threshold
2273 * @txq: TX queue to check
2275 * This function uses the host copy* of read/write pointers
2278 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2280 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2284 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2286 struct nfp_net_txq *txq;
2287 struct nfp_net_hw *hw;
2288 struct nfp_net_tx_desc *txds, txd;
2289 struct rte_mbuf *pkt;
2291 int pkt_size, dma_size;
2292 uint16_t free_descs, issued_descs;
2293 struct rte_mbuf **lmbuf;
2298 txds = &txq->txds[txq->wr_p];
2300 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2301 txq->qidx, txq->wr_p, nb_pkts);
2303 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2304 nfp_net_tx_free_bufs(txq);
2306 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2307 if (unlikely(free_descs == 0))
2314 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2315 txq->qidx, nb_pkts);
2316 /* Sending packets */
2317 while ((i < nb_pkts) && free_descs) {
2318 /* Grabbing the mbuf linked to the current descriptor */
2319 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2320 /* Warming the cache for releasing the mbuf later on */
2321 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2323 pkt = *(tx_pkts + i);
2325 if (unlikely((pkt->nb_segs > 1) &&
2326 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2327 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2328 rte_panic("Multisegment packet unsupported\n");
2331 /* Checking if we have enough descriptors */
2332 if (unlikely(pkt->nb_segs > free_descs))
2336 * Checksum and VLAN flags just in the first descriptor for a
2337 * multisegment packet, but TSO info needs to be in all of them.
2339 txd.data_len = pkt->pkt_len;
2340 nfp_net_tx_tso(txq, &txd, pkt);
2341 nfp_net_tx_cksum(txq, &txd, pkt);
2343 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2344 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2345 txd.flags |= PCIE_DESC_TX_VLAN;
2346 txd.vlan = pkt->vlan_tci;
2350 * mbuf data_len is the data in one segment and pkt_len data
2351 * in the whole packet. When the packet is just one segment,
2352 * then data_len = pkt_len
2354 pkt_size = pkt->pkt_len;
2357 /* Copying TSO, VLAN and cksum info */
2360 /* Releasing mbuf used by this descriptor previously*/
2362 rte_pktmbuf_free_seg(*lmbuf);
2365 * Linking mbuf with descriptor for being released
2366 * next time descriptor is used
2370 dma_size = pkt->data_len;
2371 dma_addr = rte_mbuf_data_iova(pkt);
2372 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2373 "%" PRIx64 "\n", dma_addr);
2375 /* Filling descriptors fields */
2376 txds->dma_len = dma_size;
2377 txds->data_len = txd.data_len;
2378 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2379 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2380 ASSERT(free_descs > 0);
2384 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2387 pkt_size -= dma_size;
2390 txds->offset_eop |= PCIE_DESC_TX_EOP;
2392 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2395 /* Referencing next free TX descriptor */
2396 txds = &txq->txds[txq->wr_p];
2397 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2404 /* Increment write pointers. Force memory write before we let HW know */
2406 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2412 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2414 uint32_t new_ctrl, update;
2415 struct nfp_net_hw *hw;
2418 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2421 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2422 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2423 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2424 " ETH_VLAN_EXTEND_OFFLOAD");
2426 /* Enable vlan strip if it is not configured yet */
2427 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2428 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2429 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2431 /* Disable vlan strip just if it is configured */
2432 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2433 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2434 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2439 update = NFP_NET_CFG_UPDATE_GEN;
2441 ret = nfp_net_reconfig(hw, new_ctrl, update);
2443 hw->ctrl = new_ctrl;
2449 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2450 struct rte_eth_rss_reta_entry64 *reta_conf,
2453 uint32_t reta, mask;
2456 struct nfp_net_hw *hw =
2457 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2460 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2461 "(%d) doesn't match the number hardware can supported "
2462 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2467 * Update Redirection Table. There are 128 8bit-entries which can be
2468 * manage as 32 32bit-entries
2470 for (i = 0; i < reta_size; i += 4) {
2471 /* Handling 4 RSS entries per loop */
2472 idx = i / RTE_RETA_GROUP_SIZE;
2473 shift = i % RTE_RETA_GROUP_SIZE;
2474 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2480 /* If all 4 entries were set, don't need read RETA register */
2482 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2484 for (j = 0; j < 4; j++) {
2485 if (!(mask & (0x1 << j)))
2488 /* Clearing the entry bits */
2489 reta &= ~(0xFF << (8 * j));
2490 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2492 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2498 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2500 nfp_net_reta_update(struct rte_eth_dev *dev,
2501 struct rte_eth_rss_reta_entry64 *reta_conf,
2504 struct nfp_net_hw *hw =
2505 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2509 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2512 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2516 update = NFP_NET_CFG_UPDATE_RSS;
2518 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2524 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2526 nfp_net_reta_query(struct rte_eth_dev *dev,
2527 struct rte_eth_rss_reta_entry64 *reta_conf,
2533 struct nfp_net_hw *hw;
2535 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2540 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2541 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2542 "(%d) doesn't match the number hardware can supported "
2543 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2548 * Reading Redirection Table. There are 128 8bit-entries which can be
2549 * manage as 32 32bit-entries
2551 for (i = 0; i < reta_size; i += 4) {
2552 /* Handling 4 RSS entries per loop */
2553 idx = i / RTE_RETA_GROUP_SIZE;
2554 shift = i % RTE_RETA_GROUP_SIZE;
2555 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2560 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2562 for (j = 0; j < 4; j++) {
2563 if (!(mask & (0x1 << j)))
2565 reta_conf->reta[shift + j] =
2566 (uint8_t)((reta >> (8 * j)) & 0xF);
2573 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2574 struct rte_eth_rss_conf *rss_conf)
2576 struct nfp_net_hw *hw;
2578 uint32_t cfg_rss_ctrl = 0;
2582 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584 /* Writing the key byte a byte */
2585 for (i = 0; i < rss_conf->rss_key_len; i++) {
2586 memcpy(&key, &rss_conf->rss_key[i], 1);
2587 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2590 rss_hf = rss_conf->rss_hf;
2592 if (rss_hf & ETH_RSS_IPV4)
2593 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2594 NFP_NET_CFG_RSS_IPV4_TCP |
2595 NFP_NET_CFG_RSS_IPV4_UDP;
2597 if (rss_hf & ETH_RSS_IPV6)
2598 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2599 NFP_NET_CFG_RSS_IPV6_TCP |
2600 NFP_NET_CFG_RSS_IPV6_UDP;
2602 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2603 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2605 /* configuring where to apply the RSS hash */
2606 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2608 /* Writing the key size */
2609 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2615 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2616 struct rte_eth_rss_conf *rss_conf)
2620 struct nfp_net_hw *hw;
2622 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2624 rss_hf = rss_conf->rss_hf;
2626 /* Checking if RSS is enabled */
2627 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2628 if (rss_hf != 0) { /* Enable RSS? */
2629 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2632 return 0; /* Nothing to do */
2635 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2636 RTE_LOG(ERR, PMD, "hash key too long\n");
2640 nfp_net_rss_hash_write(dev, rss_conf);
2642 update = NFP_NET_CFG_UPDATE_RSS;
2644 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2651 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2652 struct rte_eth_rss_conf *rss_conf)
2655 uint32_t cfg_rss_ctrl;
2658 struct nfp_net_hw *hw;
2660 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2662 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2665 rss_hf = rss_conf->rss_hf;
2666 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2668 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2669 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2671 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2672 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2674 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2675 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2677 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2678 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2680 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2681 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2683 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2684 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2686 /* Reading the key size */
2687 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2689 /* Reading the key byte a byte */
2690 for (i = 0; i < rss_conf->rss_key_len; i++) {
2691 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2692 memcpy(&rss_conf->rss_key[i], &key, 1);
2699 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2701 struct rte_eth_conf *dev_conf;
2702 struct rte_eth_rss_conf rss_conf;
2703 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2704 uint16_t rx_queues = dev->data->nb_rx_queues;
2708 RTE_LOG(INFO, PMD, "setting default RSS conf for %u queues\n",
2711 nfp_reta_conf[0].mask = ~0x0;
2712 nfp_reta_conf[1].mask = ~0x0;
2715 for (i = 0; i < 0x40; i += 8) {
2716 for (j = i; j < (i + 8); j++) {
2717 nfp_reta_conf[0].reta[j] = queue;
2718 nfp_reta_conf[1].reta[j] = queue++;
2722 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2726 dev_conf = &dev->data->dev_conf;
2728 RTE_LOG(INFO, PMD, "wrong rss conf");
2731 rss_conf = dev_conf->rx_adv_conf.rss_conf;
2733 ret = nfp_net_rss_hash_write(dev, &rss_conf);
2739 /* Initialise and register driver with DPDK Application */
2740 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2741 .dev_configure = nfp_net_configure,
2742 .dev_start = nfp_net_start,
2743 .dev_stop = nfp_net_stop,
2744 .dev_close = nfp_net_close,
2745 .promiscuous_enable = nfp_net_promisc_enable,
2746 .promiscuous_disable = nfp_net_promisc_disable,
2747 .link_update = nfp_net_link_update,
2748 .stats_get = nfp_net_stats_get,
2749 .stats_reset = nfp_net_stats_reset,
2750 .dev_infos_get = nfp_net_infos_get,
2751 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2752 .mtu_set = nfp_net_dev_mtu_set,
2753 .vlan_offload_set = nfp_net_vlan_offload_set,
2754 .reta_update = nfp_net_reta_update,
2755 .reta_query = nfp_net_reta_query,
2756 .rss_hash_update = nfp_net_rss_hash_update,
2757 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2758 .rx_queue_setup = nfp_net_rx_queue_setup,
2759 .rx_queue_release = nfp_net_rx_queue_release,
2760 .rx_queue_count = nfp_net_rx_queue_count,
2761 .tx_queue_setup = nfp_net_tx_queue_setup,
2762 .tx_queue_release = nfp_net_tx_queue_release,
2763 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2764 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2768 * All eth_dev created got its private data, but before nfp_net_init, that
2769 * private data is referencing private data for all the PF ports. This is due
2770 * to how the vNIC bars are mapped based on first port, so all ports need info
2771 * about port 0 private data. Inside nfp_net_init the private data pointer is
2772 * changed to the right address for each port once the bars have been mapped.
2774 * This functions helps to find out which port and therefore which offset
2775 * inside the private data array to use.
2778 get_pf_port_number(char *name)
2780 char *pf_str = name;
2783 while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2788 * This should not happen at all and it would mean major
2789 * implementation fault.
2791 rte_panic("nfp_net: problem with pf device name\n");
2793 /* Expecting _portX with X within [0,7] */
2796 return (int)strtol(pf_str, NULL, 10);
2800 nfp_net_init(struct rte_eth_dev *eth_dev)
2802 struct rte_pci_device *pci_dev;
2803 struct nfp_net_hw *hw, *hwport0;
2805 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2811 PMD_INIT_FUNC_TRACE();
2813 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2815 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2816 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2817 port = get_pf_port_number(eth_dev->data->name);
2818 if (port < 0 || port > 7) {
2819 RTE_LOG(ERR, PMD, "Port value is wrong\n");
2823 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2825 /* This points to port 0 private data */
2826 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2828 /* This points to the specific port private data */
2829 hw = &hwport0[port];
2831 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2835 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2836 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2837 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2839 /* For secondary processes, the primary has done all the work */
2840 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2843 rte_eth_copy_pci_info(eth_dev, pci_dev);
2845 hw->device_id = pci_dev->id.device_id;
2846 hw->vendor_id = pci_dev->id.vendor_id;
2847 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2848 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2850 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2851 pci_dev->id.vendor_id, pci_dev->id.device_id,
2852 pci_dev->addr.domain, pci_dev->addr.bus,
2853 pci_dev->addr.devid, pci_dev->addr.function);
2855 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2856 if (hw->ctrl_bar == NULL) {
2858 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2862 if (hw->is_pf && port == 0) {
2863 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2864 hw->total_ports * 32768,
2866 if (!hw->ctrl_bar) {
2867 printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar\n");
2871 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2875 if (!hwport0->ctrl_bar)
2878 /* address based on port0 offset */
2879 hw->ctrl_bar = hwport0->ctrl_bar +
2880 (port * NFP_PF_CSR_SLICE_SIZE);
2883 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2885 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2886 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2888 /* Work out where in the BAR the queues start. */
2889 switch (pci_dev->id.device_id) {
2890 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2891 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2892 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2893 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2894 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2895 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2896 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2899 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2901 goto dev_err_ctrl_map;
2904 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2905 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2907 if (hw->is_pf && port == 0) {
2908 /* configure access to tx/rx vNIC BARs */
2909 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2911 NFP_QCP_QUEUE_AREA_SZ,
2912 &hw->hwqueues_area);
2914 if (!hwport0->hw_queues) {
2915 printf("nfp_rtsym_map fails for net.qc\n");
2917 goto dev_err_ctrl_map;
2920 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p\n",
2921 hwport0->hw_queues);
2925 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2926 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2927 eth_dev->data->dev_private = hw;
2929 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2931 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2935 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2936 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2938 nfp_net_cfg_queue_setup(hw);
2940 /* Get some of the read-only fields from the config BAR */
2941 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2942 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2943 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2944 hw->mtu = ETHER_MTU;
2946 /* VLAN insertion is incompatible with LSOv2 */
2947 if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2948 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2950 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2951 hw->rx_offset = NFP_NET_RX_OFFSET;
2953 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2955 PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2956 NFD_CFG_MAJOR_VERSION_of(hw->ver),
2957 NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2959 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2960 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2961 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2962 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2963 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2964 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2965 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2966 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2967 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2968 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2969 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2970 hw->cap & NFP_NET_CFG_CTRL_LSO2 ? "TSOv2 " : "",
2971 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "",
2972 hw->cap & NFP_NET_CFG_CTRL_RSS2 ? "RSSv2 " : "");
2976 hw->stride_rx = stride;
2977 hw->stride_tx = stride;
2979 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2980 hw->max_rx_queues, hw->max_tx_queues);
2982 /* Initializing spinlock for reconfigs */
2983 rte_spinlock_init(&hw->reconfig_lock);
2985 /* Allocating memory for mac addr */
2986 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2987 if (eth_dev->data->mac_addrs == NULL) {
2988 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2990 goto dev_err_queues_map;
2994 nfp_net_pf_read_mac(hwport0, port);
2995 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2997 nfp_net_vf_read_mac(hw);
3000 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
3001 PMD_INIT_LOG(INFO, "Using random mac address for port %d\n",
3003 /* Using random mac addresses for VFs */
3004 eth_random_addr(&hw->mac_addr[0]);
3005 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
3008 /* Copying mac address to DPDK eth_dev struct */
3009 ether_addr_copy((struct ether_addr *)hw->mac_addr,
3010 ð_dev->data->mac_addrs[0]);
3012 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
3013 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
3014 eth_dev->data->port_id, pci_dev->id.vendor_id,
3015 pci_dev->id.device_id,
3016 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
3017 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
3019 /* Registering LSC interrupt handler */
3020 rte_intr_callback_register(&pci_dev->intr_handle,
3021 nfp_net_dev_interrupt_handler,
3024 /* Telling the firmware about the LSC interrupt entry */
3025 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
3027 /* Recording current stats counters values */
3028 nfp_net_stats_reset(eth_dev);
3033 nfp_cpp_area_free(hw->hwqueues_area);
3035 nfp_cpp_area_free(hw->ctrl_area);
3041 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3042 struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3043 int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3045 struct rte_eth_dev *eth_dev;
3046 struct nfp_net_hw *hw;
3050 port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3055 sprintf(port_name, "%s_port%d", dev->device.name, port);
3057 sprintf(port_name, "%s", dev->device.name);
3059 eth_dev = rte_eth_dev_allocate(port_name);
3064 *priv = rte_zmalloc(port_name,
3065 sizeof(struct nfp_net_adapter) * ports,
3066 RTE_CACHE_LINE_SIZE);
3068 rte_eth_dev_release_port(eth_dev);
3073 eth_dev->data->dev_private = *priv;
3076 * dev_private pointing to port0 dev_private because we need
3077 * to configure vNIC bars based on port0 at nfp_net_init.
3078 * Then dev_private is adjusted per port.
3080 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3082 hw->hwinfo = hwinfo;
3083 hw->sym_tbl = sym_tbl;
3084 hw->pf_port_idx = phys_port;
3087 hw->pf_multiport_enabled = 1;
3089 hw->total_ports = ports;
3091 eth_dev->device = &dev->device;
3092 rte_eth_copy_pci_info(eth_dev, dev);
3094 ret = nfp_net_init(eth_dev);
3097 rte_eth_dev_release_port(eth_dev);
3099 rte_free(port_name);
3104 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
3107 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3109 struct nfp_cpp *cpp = nsp->cpp;
3114 struct stat file_stat;
3117 /* Looking for firmware file in order of priority */
3119 /* First try to find a firmware image specific for this device */
3120 sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3121 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3122 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3123 cpp->interface & 0xff);
3125 sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial);
3127 RTE_LOG(DEBUG, PMD, "Trying with fw file: %s\n", fw_name);
3128 fw_f = open(fw_name, O_RDONLY);
3132 /* Then try the PCI name */
3133 sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name);
3135 RTE_LOG(DEBUG, PMD, "Trying with fw file: %s\n", fw_name);
3136 fw_f = open(fw_name, O_RDONLY);
3140 /* Finally try the card type and media */
3141 sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card);
3142 RTE_LOG(DEBUG, PMD, "Trying with fw file: %s\n", fw_name);
3143 fw_f = open(fw_name, O_RDONLY);
3145 RTE_LOG(INFO, PMD, "Firmware file %s not found.", fw_name);
3150 if (fstat(fw_f, &file_stat) < 0) {
3151 RTE_LOG(INFO, PMD, "Firmware file %s size is unknown", fw_name);
3156 fsize = file_stat.st_size;
3157 RTE_LOG(INFO, PMD, "Firmware file found at %s with size: %" PRIu64 "\n",
3158 fw_name, (uint64_t)fsize);
3160 fw_buf = malloc((size_t)fsize);
3162 RTE_LOG(INFO, PMD, "malloc failed for fw buffer");
3166 memset(fw_buf, 0, fsize);
3168 bytes = read(fw_f, fw_buf, fsize);
3169 if (bytes != fsize) {
3170 RTE_LOG(INFO, PMD, "Reading fw to buffer failed.\n"
3171 "Just %" PRIu64 " of %" PRIu64 " bytes read",
3172 (uint64_t)bytes, (uint64_t)fsize);
3178 RTE_LOG(INFO, PMD, "Uploading the firmware ...");
3179 nfp_nsp_load_fw(nsp, fw_buf, bytes);
3180 RTE_LOG(INFO, PMD, "Done");
3189 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3190 struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3192 struct nfp_nsp *nsp;
3193 const char *nfp_fw_model;
3194 char card_desc[100];
3197 nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3200 RTE_LOG(INFO, PMD, "firmware model found: %s\n", nfp_fw_model);
3202 RTE_LOG(ERR, PMD, "firmware model NOT found\n");
3206 if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3207 RTE_LOG(ERR, PMD, "NFP ethernet table reports wrong ports: %u\n",
3208 nfp_eth_table->count);
3212 RTE_LOG(INFO, PMD, "NFP ethernet port table reports %u ports\n",
3213 nfp_eth_table->count);
3215 RTE_LOG(INFO, PMD, "Port speed: %u\n", nfp_eth_table->ports[0].speed);
3217 sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model,
3218 nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000);
3220 nsp = nfp_nsp_open(cpp);
3222 RTE_LOG(ERR, PMD, "NFP error when obtaining NSP handle\n");
3226 nfp_nsp_device_soft_reset(nsp);
3227 err = nfp_fw_upload(dev, nsp, card_desc);
3233 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3234 struct rte_pci_device *dev)
3236 struct nfp_cpp *cpp;
3237 struct nfp_hwinfo *hwinfo;
3238 struct nfp_rtsym_table *sym_tbl;
3239 struct nfp_eth_table *nfp_eth_table = NULL;
3249 cpp = nfp_cpp_from_device_name(dev->device.name);
3251 RTE_LOG(ERR, PMD, "A CPP handle can not be obtained");
3256 hwinfo = nfp_hwinfo_read(cpp);
3258 RTE_LOG(ERR, PMD, "Error reading hwinfo table");
3262 nfp_eth_table = nfp_eth_read_ports(cpp);
3263 if (!nfp_eth_table) {
3264 RTE_LOG(ERR, PMD, "Error reading NFP ethernet table\n");
3268 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3269 RTE_LOG(INFO, PMD, "Error when uploading firmware\n");
3274 /* Now the symbol table should be there */
3275 sym_tbl = nfp_rtsym_table_read(cpp);
3277 RTE_LOG(ERR, PMD, "Something is wrong with the firmware"
3283 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3284 if (total_ports != (int)nfp_eth_table->count) {
3285 RTE_LOG(ERR, PMD, "Inconsistent number of ports\n");
3289 PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
3291 if (total_ports <= 0 || total_ports > 8) {
3292 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
3297 for (i = 0; i < total_ports; i++) {
3298 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3299 nfp_eth_table->ports[i].index,
3306 free(nfp_eth_table);
3310 int nfp_logtype_init;
3311 int nfp_logtype_driver;
3313 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3315 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3316 PCI_DEVICE_ID_NFP4000_PF_NIC)
3319 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3320 PCI_DEVICE_ID_NFP6000_PF_NIC)
3327 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3329 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3330 PCI_DEVICE_ID_NFP6000_VF_NIC)
3337 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3338 struct rte_pci_device *pci_dev)
3340 return rte_eth_dev_pci_generic_probe(pci_dev,
3341 sizeof(struct nfp_net_adapter), nfp_net_init);
3344 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3346 struct rte_eth_dev *eth_dev;
3347 struct nfp_net_hw *hw, *hwport0;
3350 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3351 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3352 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3353 port = get_pf_port_number(eth_dev->data->name);
3355 * hotplug is not possible with multiport PF although freeing
3356 * data structures can be done for first port.
3360 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3361 hw = &hwport0[port];
3362 nfp_cpp_area_free(hw->ctrl_area);
3363 nfp_cpp_area_free(hw->hwqueues_area);
3366 nfp_cpp_free(hw->cpp);
3368 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3370 /* hotplug is not possible with multiport PF */
3371 if (hw->pf_multiport_enabled)
3373 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3376 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3377 .id_table = pci_id_nfp_pf_net_map,
3378 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3379 .probe = nfp_pf_pci_probe,
3380 .remove = eth_nfp_pci_remove,
3383 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3384 .id_table = pci_id_nfp_vf_net_map,
3385 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3386 .probe = eth_nfp_pci_probe,
3387 .remove = eth_nfp_pci_remove,
3390 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3391 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3392 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3393 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3394 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3395 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3397 RTE_INIT(nfp_init_log);
3401 nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3402 if (nfp_logtype_init >= 0)
3403 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3404 nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3405 if (nfp_logtype_driver >= 0)
3406 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3410 * c-file-style: "Linux"
3411 * indent-tabs-mode: t