drivers/net/nfp/nfp_net.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  */
   7
   8 /*
   9  * vim:shiftwidth=8:noexpandtab
  10  *
  11  * @file dpdk/pmd/nfp_net.c
  12  *
  13  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  14  */
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_log.h>
  19 #include <rte_debug.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_dev.h>
  23 #include <rte_ether.h>
  24 #include <rte_malloc.h>
  25 #include <rte_memzone.h>
  26 #include <rte_mempool.h>
  27 #include <rte_version.h>
  28 #include <rte_string_fns.h>
  29 #include <rte_alarm.h>
  30 #include <rte_spinlock.h>
  31 #include <rte_service_component.h>
  32
  33 #include "nfpcore/nfp_cpp.h"
  34 #include "nfpcore/nfp_nffw.h"
  35 #include "nfpcore/nfp_hwinfo.h"
  36 #include "nfpcore/nfp_mip.h"
  37 #include "nfpcore/nfp_rtsym.h"
  38 #include "nfpcore/nfp_nsp.h"
  39
  40 #include "nfp_net_pmd.h"
  41 #include "nfp_net_logs.h"
  42 #include "nfp_net_ctrl.h"
  43
  44 #include <sys/types.h>
  45 #include <sys/socket.h>
  46 #include <sys/un.h>
  47 #include <unistd.h>
  48 #include <stdio.h>
  49 #include <sys/ioctl.h>
  50 #include <errno.h>
  51
  52 /* Prototypes */
  53 static int nfp_net_close(struct rte_eth_dev *dev);
  54 static int nfp_net_configure(struct rte_eth_dev *dev);
  55 static void nfp_net_dev_interrupt_handler(void *param);
  56 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  57 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  58 static int nfp_net_infos_get(struct rte_eth_dev *dev,
  59                              struct rte_eth_dev_info *dev_info);
  60 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  61 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  62 static int nfp_net_promisc_enable(struct rte_eth_dev *dev);
  63 static int nfp_net_promisc_disable(struct rte_eth_dev *dev);
  64 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  65 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  66                                        uint16_t queue_idx);
  67 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  68                                   uint16_t nb_pkts);
  69 static void nfp_net_rx_queue_release(void *rxq);
  70 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  71                                   uint16_t nb_desc, unsigned int socket_id,
  72                                   const struct rte_eth_rxconf *rx_conf,
  73                                   struct rte_mempool *mp);
  74 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  75 static void nfp_net_tx_queue_release(void *txq);
  76 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  77                                   uint16_t nb_desc, unsigned int socket_id,
  78                                   const struct rte_eth_txconf *tx_conf);
  79 static int nfp_net_start(struct rte_eth_dev *dev);
  80 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  81                               struct rte_eth_stats *stats);
  82 static int nfp_net_stats_reset(struct rte_eth_dev *dev);
  83 static void nfp_net_stop(struct rte_eth_dev *dev);
  84 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  85                                   uint16_t nb_pkts);
  86
  87 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
  88 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
  89                                    struct rte_eth_rss_conf *rss_conf);
  90 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
  91                     struct rte_eth_rss_reta_entry64 *reta_conf,
  92                     uint16_t reta_size);
  93 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
  94                         struct rte_eth_rss_conf *rss_conf);
  95 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
  96                              struct rte_ether_addr *mac_addr);
  97
  98 /* The offset of the queue controller queues in the PCIe Target */
  99 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 100
 101 /* Maximum value which can be added to a queue with one transaction */
 102 #define NFP_QCP_MAX_ADD 0x7f
 103
 104 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 105         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 106
 107 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 108 enum nfp_qcp_ptr {
 109         NFP_QCP_READ_PTR = 0,
 110         NFP_QCP_WRITE_PTR
 111 };
 112
 113 /*
 114  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 115  * @q: Base address for queue structure
 116  * @ptr: Add to the Read or Write pointer
 117  * @val: Value to add to the queue pointer
 118  *
 119  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 120  */
 121 static inline void
 122 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 123 {
 124         uint32_t off;
 125
 126         if (ptr == NFP_QCP_READ_PTR)
 127                 off = NFP_QCP_QUEUE_ADD_RPTR;
 128         else
 129                 off = NFP_QCP_QUEUE_ADD_WPTR;
 130
 131         while (val > NFP_QCP_MAX_ADD) {
 132                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 133                 val -= NFP_QCP_MAX_ADD;
 134         }
 135
 136         nn_writel(rte_cpu_to_le_32(val), q + off);
 137 }
 138
 139 /*
 140  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 141  * @q:  Base address for queue structure
 142  * @ptr: Read or Write pointer
 143  */
 144 static inline uint32_t
 145 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 146 {
 147         uint32_t off;
 148         uint32_t val;
 149
 150         if (ptr == NFP_QCP_READ_PTR)
 151                 off = NFP_QCP_QUEUE_STS_LO;
 152         else
 153                 off = NFP_QCP_QUEUE_STS_HI;
 154
 155         val = rte_cpu_to_le_32(nn_readl(q + off));
 156
 157         if (ptr == NFP_QCP_READ_PTR)
 158                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 159         else
 160                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 161 }
 162
 163 /*
 164  * Functions to read/write from/to Config BAR
 165  * Performs any endian conversion necessary.
 166  */
 167 static inline uint8_t
 168 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 169 {
 170         return nn_readb(hw->ctrl_bar + off);
 171 }
 172
 173 static inline void
 174 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 175 {
 176         nn_writeb(val, hw->ctrl_bar + off);
 177 }
 178
 179 static inline uint32_t
 180 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 181 {
 182         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 183 }
 184
 185 static inline void
 186 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 187 {
 188         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 189 }
 190
 191 static inline uint64_t
 192 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 193 {
 194         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 195 }
 196
 197 static inline void
 198 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 199 {
 200         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 201 }
 202
 203 static void
 204 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 205 {
 206         unsigned i;
 207
 208         if (rxq->rxbufs == NULL)
 209                 return;
 210
 211         for (i = 0; i < rxq->rx_count; i++) {
 212                 if (rxq->rxbufs[i].mbuf) {
 213                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 214                         rxq->rxbufs[i].mbuf = NULL;
 215                 }
 216         }
 217 }
 218
 219 static void
 220 nfp_net_rx_queue_release(void *rx_queue)
 221 {
 222         struct nfp_net_rxq *rxq = rx_queue;
 223
 224         if (rxq) {
 225                 nfp_net_rx_queue_release_mbufs(rxq);
 226                 rte_free(rxq->rxbufs);
 227                 rte_free(rxq);
 228         }
 229 }
 230
 231 static void
 232 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 233 {
 234         nfp_net_rx_queue_release_mbufs(rxq);
 235         rxq->rd_p = 0;
 236         rxq->nb_rx_hold = 0;
 237 }
 238
 239 static void
 240 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 241 {
 242         unsigned i;
 243
 244         if (txq->txbufs == NULL)
 245                 return;
 246
 247         for (i = 0; i < txq->tx_count; i++) {
 248                 if (txq->txbufs[i].mbuf) {
 249                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 250                         txq->txbufs[i].mbuf = NULL;
 251                 }
 252         }
 253 }
 254
 255 static void
 256 nfp_net_tx_queue_release(void *tx_queue)
 257 {
 258         struct nfp_net_txq *txq = tx_queue;
 259
 260         if (txq) {
 261                 nfp_net_tx_queue_release_mbufs(txq);
 262                 rte_free(txq->txbufs);
 263                 rte_free(txq);
 264         }
 265 }
 266
 267 static void
 268 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 269 {
 270         nfp_net_tx_queue_release_mbufs(txq);
 271         txq->wr_p = 0;
 272         txq->rd_p = 0;
 273 }
 274
 275 static int
 276 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 277 {
 278         int cnt;
 279         uint32_t new;
 280         struct timespec wait;
 281
 282         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 283                     hw->qcp_cfg);
 284
 285         if (hw->qcp_cfg == NULL)
 286                 rte_panic("Bad configuration queue pointer\n");
 287
 288         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 289
 290         wait.tv_sec = 0;
 291         wait.tv_nsec = 1000000;
 292
 293         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 294
 295         /* Poll update field, waiting for NFP to ack the config */
 296         for (cnt = 0; ; cnt++) {
 297                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 298                 if (new == 0)
 299                         break;
 300                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 301                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 302                         return -1;
 303                 }
 304                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 305                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 306                                           " %dms", update, cnt);
 307                         rte_panic("Exiting\n");
 308                 }
 309                 nanosleep(&wait, 0); /* waiting for a 1ms */
 310         }
 311         PMD_DRV_LOG(DEBUG, "Ack DONE");
 312         return 0;
 313 }
 314
 315 /*
 316  * Reconfigure the NIC
 317  * @nn:    device to reconfigure
 318  * @ctrl:    The value for the ctrl field in the BAR config
 319  * @update:  The value for the update field in the BAR config
 320  *
 321  * Write the update word to the BAR and ping the reconfig queue. Then poll
 322  * until the firmware has acknowledged the update by zeroing the update word.
 323  */
 324 static int
 325 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 326 {
 327         uint32_t err;
 328
 329         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 330                     ctrl, update);
 331
 332         rte_spinlock_lock(&hw->reconfig_lock);
 333
 334         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 335         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 336
 337         rte_wmb();
 338
 339         err = __nfp_net_reconfig(hw, update);
 340
 341         rte_spinlock_unlock(&hw->reconfig_lock);
 342
 343         if (!err)
 344                 return 0;
 345
 346         /*
 347          * Reconfig errors imply situations where they can be handled.
 348          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 349          */
 350         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 351                      ctrl, update);
 352         return -EIO;
 353 }
 354
 355 /*
 356  * Configure an Ethernet device. This function must be invoked first
 357  * before any other function in the Ethernet API. This function can
 358  * also be re-invoked when a device is in the stopped state.
 359  */
 360 static int
 361 nfp_net_configure(struct rte_eth_dev *dev)
 362 {
 363         struct rte_eth_conf *dev_conf;
 364         struct rte_eth_rxmode *rxmode;
 365         struct rte_eth_txmode *txmode;
 366         struct nfp_net_hw *hw;
 367
 368         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 369
 370         /*
 371          * A DPDK app sends info about how many queues to use and how
 372          * those queues need to be configured. This is used by the
 373          * DPDK core and it makes sure no more queues than those
 374          * advertised by the driver are requested. This function is
 375          * called after that internal process
 376          */
 377
 378         PMD_INIT_LOG(DEBUG, "Configure");
 379
 380         dev_conf = &dev->data->dev_conf;
 381         rxmode = &dev_conf->rxmode;
 382         txmode = &dev_conf->txmode;
 383
 384         if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
 385                 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 386
 387         /* Checking TX mode */
 388         if (txmode->mq_mode) {
 389                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 390                 return -EINVAL;
 391         }
 392
 393         /* Checking RX mode */
 394         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 395             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 396                 PMD_INIT_LOG(INFO, "RSS not supported");
 397                 return -EINVAL;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static void
 404 nfp_net_enable_queues(struct rte_eth_dev *dev)
 405 {
 406         struct nfp_net_hw *hw;
 407         uint64_t enabled_queues = 0;
 408         int i;
 409
 410         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 411
 412         /* Enabling the required TX queues in the device */
 413         for (i = 0; i < dev->data->nb_tx_queues; i++)
 414                 enabled_queues |= (1 << i);
 415
 416         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 417
 418         enabled_queues = 0;
 419
 420         /* Enabling the required RX queues in the device */
 421         for (i = 0; i < dev->data->nb_rx_queues; i++)
 422                 enabled_queues |= (1 << i);
 423
 424         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 425 }
 426
 427 static void
 428 nfp_net_disable_queues(struct rte_eth_dev *dev)
 429 {
 430         struct nfp_net_hw *hw;
 431         uint32_t new_ctrl, update = 0;
 432
 433         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 434
 435         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 436         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 437
 438         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 439         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 440                  NFP_NET_CFG_UPDATE_MSIX;
 441
 442         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 443                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 444
 445         /* If an error when reconfig we avoid to change hw state */
 446         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 447                 return;
 448
 449         hw->ctrl = new_ctrl;
 450 }
 451
 452 static int
 453 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 454 {
 455         int i;
 456
 457         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 458                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 459                         return -1;
 460         }
 461         return 0;
 462 }
 463
 464 static void
 465 nfp_net_params_setup(struct nfp_net_hw *hw)
 466 {
 467         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 468         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 469 }
 470
 471 static void
 472 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 473 {
 474         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 475 }
 476
 477 #define ETH_ADDR_LEN    6
 478
 479 static void
 480 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 481 {
 482         int i;
 483
 484         for (i = 0; i < ETH_ADDR_LEN; i++)
 485                 dst[i] = src[i];
 486 }
 487
 488 static int
 489 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 490 {
 491         struct nfp_eth_table *nfp_eth_table;
 492
 493         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 494         /*
 495          * hw points to port0 private data. We need hw now pointing to
 496          * right port.
 497          */
 498         hw += port;
 499         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 500                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 501
 502         free(nfp_eth_table);
 503         return 0;
 504 }
 505
 506 static void
 507 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 508 {
 509         uint32_t tmp;
 510
 511         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 512         memcpy(&hw->mac_addr[0], &tmp, 4);
 513
 514         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 515         memcpy(&hw->mac_addr[4], &tmp, 2);
 516 }
 517
 518 static void
 519 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 520 {
 521         uint32_t mac0 = *(uint32_t *)mac;
 522         uint16_t mac1;
 523
 524         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 525
 526         mac += 4;
 527         mac1 = *(uint16_t *)mac;
 528         nn_writew(rte_cpu_to_be_16(mac1),
 529                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 530 }
 531
 532 int
 533 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
 534 {
 535         struct nfp_net_hw *hw;
 536         uint32_t update, ctrl;
 537
 538         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 539         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 540             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 541                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 542                                   " port enabled");
 543                 return -EBUSY;
 544         }
 545
 546         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 547             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 548                 return -EBUSY;
 549
 550         /* Writing new MAC to the specific port BAR address */
 551         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 552
 553         /* Signal the NIC about the change */
 554         update = NFP_NET_CFG_UPDATE_MACADDR;
 555         ctrl = hw->ctrl;
 556         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 557             (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 558                 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
 559         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 560                 PMD_INIT_LOG(INFO, "MAC address update failed");
 561                 return -EIO;
 562         }
 563         return 0;
 564 }
 565
 566 static int
 567 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 568                            struct rte_intr_handle *intr_handle)
 569 {
 570         struct nfp_net_hw *hw;
 571         int i;
 572
 573         if (!intr_handle->intr_vec) {
 574                 intr_handle->intr_vec =
 575                         rte_zmalloc("intr_vec",
 576                                     dev->data->nb_rx_queues * sizeof(int), 0);
 577                 if (!intr_handle->intr_vec) {
 578                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 579                                      " intr_vec", dev->data->nb_rx_queues);
 580                         return -ENOMEM;
 581                 }
 582         }
 583
 584         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 585
 586         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 587                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 588                 /* UIO just supports one queue and no LSC*/
 589                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 590                 intr_handle->intr_vec[0] = 0;
 591         } else {
 592                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 593                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 594                         /*
 595                          * The first msix vector is reserved for non
 596                          * efd interrupts
 597                         */
 598                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 599                         intr_handle->intr_vec[i] = i + 1;
 600                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 601                                             intr_handle->intr_vec[i]);
 602                 }
 603         }
 604
 605         /* Avoiding TX interrupts */
 606         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 607         return 0;
 608 }
 609
 610 static uint32_t
 611 nfp_check_offloads(struct rte_eth_dev *dev)
 612 {
 613         struct nfp_net_hw *hw;
 614         struct rte_eth_conf *dev_conf;
 615         struct rte_eth_rxmode *rxmode;
 616         struct rte_eth_txmode *txmode;
 617         uint32_t ctrl = 0;
 618
 619         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 620
 621         dev_conf = &dev->data->dev_conf;
 622         rxmode = &dev_conf->rxmode;
 623         txmode = &dev_conf->txmode;
 624
 625         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 626                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 627                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 628         }
 629
 630         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 631                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 632                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 633         }
 634
 635         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 636                 hw->mtu = rxmode->max_rx_pkt_len;
 637
 638         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 639                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 640
 641         /* L2 broadcast */
 642         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 643                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 644
 645         /* L2 multicast */
 646         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 647                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 648
 649         /* TX checksum offload */
 650         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 651             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 652             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 653                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 654
 655         /* LSO offload */
 656         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 657                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 658                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 659                 else
 660                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 661         }
 662
 663         /* RX gather */
 664         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 665                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 666
 667         return ctrl;
 668 }
 669
 670 static int
 671 nfp_net_start(struct rte_eth_dev *dev)
 672 {
 673         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 674         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 675         uint32_t new_ctrl, update = 0;
 676         struct nfp_net_hw *hw;
 677         struct rte_eth_conf *dev_conf;
 678         struct rte_eth_rxmode *rxmode;
 679         uint32_t intr_vector;
 680         int ret;
 681
 682         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 683
 684         PMD_INIT_LOG(DEBUG, "Start");
 685
 686         /* Disabling queues just in case... */
 687         nfp_net_disable_queues(dev);
 688
 689         /* Enabling the required queues in the device */
 690         nfp_net_enable_queues(dev);
 691
 692         /* check and configure queue intr-vector mapping */
 693         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 694                 if (hw->pf_multiport_enabled) {
 695                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 696                                           "with NFP multiport PF");
 697                                 return -EINVAL;
 698                 }
 699                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 700                         /*
 701                          * Better not to share LSC with RX interrupts.
 702                          * Unregistering LSC interrupt handler
 703                          */
 704                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 705                                 nfp_net_dev_interrupt_handler, (void *)dev);
 706
 707                         if (dev->data->nb_rx_queues > 1) {
 708                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 709                                              "supports 1 queue with UIO");
 710                                 return -EIO;
 711                         }
 712                 }
 713                 intr_vector = dev->data->nb_rx_queues;
 714                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 715                         return -1;
 716
 717                 nfp_configure_rx_interrupt(dev, intr_handle);
 718                 update = NFP_NET_CFG_UPDATE_MSIX;
 719         }
 720
 721         rte_intr_enable(intr_handle);
 722
 723         new_ctrl = nfp_check_offloads(dev);
 724
 725         /* Writing configuration parameters in the device */
 726         nfp_net_params_setup(hw);
 727
 728         dev_conf = &dev->data->dev_conf;
 729         rxmode = &dev_conf->rxmode;
 730
 731         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 732                 nfp_net_rss_config_default(dev);
 733                 update |= NFP_NET_CFG_UPDATE_RSS;
 734                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 735         }
 736
 737         /* Enable device */
 738         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 739
 740         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 741
 742         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 743                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 744
 745         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 746         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 747                 return -EIO;
 748
 749         /*
 750          * Allocating rte mbufs for configured rx queues.
 751          * This requires queues being enabled before
 752          */
 753         if (nfp_net_rx_freelist_setup(dev) < 0) {
 754                 ret = -ENOMEM;
 755                 goto error;
 756         }
 757
 758         if (hw->is_pf) {
 759                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 760                         /* Configure the physical port up */
 761                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 762                 else
 763                         nfp_eth_set_configured(dev->process_private,
 764                                                hw->pf_port_idx, 1);
 765         }
 766
 767         hw->ctrl = new_ctrl;
 768
 769         return 0;
 770
 771 error:
 772         /*
 773          * An error returned by this function should mean the app
 774          * exiting and then the system releasing all the memory
 775          * allocated even memory coming from hugepages.
 776          *
 777          * The device could be enabled at this point with some queues
 778          * ready for getting packets. This is true if the call to
 779          * nfp_net_rx_freelist_setup() succeeds for some queues but
 780          * fails for subsequent queues.
 781          *
 782          * This should make the app exiting but better if we tell the
 783          * device first.
 784          */
 785         nfp_net_disable_queues(dev);
 786
 787         return ret;
 788 }
 789
 790 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 791 static void
 792 nfp_net_stop(struct rte_eth_dev *dev)
 793 {
 794         int i;
 795         struct nfp_net_hw *hw;
 796
 797         PMD_INIT_LOG(DEBUG, "Stop");
 798
 799         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 800
 801         nfp_net_disable_queues(dev);
 802
 803         /* Clear queues */
 804         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 805                 nfp_net_reset_tx_queue(
 806                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 807         }
 808
 809         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 810                 nfp_net_reset_rx_queue(
 811                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 812         }
 813
 814         if (hw->is_pf) {
 815                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 816                         /* Configure the physical port down */
 817                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 818                 else
 819                         nfp_eth_set_configured(dev->process_private,
 820                                                hw->pf_port_idx, 0);
 821         }
 822 }
 823
 824 /* Set the link up. */
 825 static int
 826 nfp_net_set_link_up(struct rte_eth_dev *dev)
 827 {
 828         struct nfp_net_hw *hw;
 829
 830         PMD_DRV_LOG(DEBUG, "Set link up");
 831
 832         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 833
 834         if (!hw->is_pf)
 835                 return -ENOTSUP;
 836
 837         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 838                 /* Configure the physical port down */
 839                 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 840         else
 841                 return nfp_eth_set_configured(dev->process_private,
 842                                               hw->pf_port_idx, 1);
 843 }
 844
 845 /* Set the link down. */
 846 static int
 847 nfp_net_set_link_down(struct rte_eth_dev *dev)
 848 {
 849         struct nfp_net_hw *hw;
 850
 851         PMD_DRV_LOG(DEBUG, "Set link down");
 852
 853         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854
 855         if (!hw->is_pf)
 856                 return -ENOTSUP;
 857
 858         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 859                 /* Configure the physical port down */
 860                 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 861         else
 862                 return nfp_eth_set_configured(dev->process_private,
 863                                               hw->pf_port_idx, 0);
 864 }
 865
 866 /* Reset and stop device. The device can not be restarted. */
 867 static int
 868 nfp_net_close(struct rte_eth_dev *dev)
 869 {
 870         struct nfp_net_hw *hw;
 871         struct rte_pci_device *pci_dev;
 872         int i;
 873
 874         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 875                 return 0;
 876
 877         PMD_INIT_LOG(DEBUG, "Close");
 878
 879         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 880         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 881
 882         /*
 883          * We assume that the DPDK application is stopping all the
 884          * threads/queues before calling the device close function.
 885          */
 886
 887         nfp_net_disable_queues(dev);
 888
 889         /* Clear queues */
 890         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 891                 nfp_net_reset_tx_queue(
 892                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 893         }
 894
 895         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 896                 nfp_net_reset_rx_queue(
 897                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 898         }
 899
 900         rte_intr_disable(&pci_dev->intr_handle);
 901         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 902
 903         /* unregister callback func from eal lib */
 904         rte_intr_callback_unregister(&pci_dev->intr_handle,
 905                                      nfp_net_dev_interrupt_handler,
 906                                      (void *)dev);
 907
 908         /*
 909          * The ixgbe PMD driver disables the pcie master on the
 910          * device. The i40e does not...
 911          */
 912
 913         return 0;
 914 }
 915
 916 static int
 917 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 918 {
 919         uint32_t new_ctrl, update = 0;
 920         struct nfp_net_hw *hw;
 921         int ret;
 922
 923         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 924
 925         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 926
 927         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 928                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 929                 return -ENOTSUP;
 930         }
 931
 932         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 933                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 934                 return 0;
 935         }
 936
 937         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 938         update = NFP_NET_CFG_UPDATE_GEN;
 939
 940         /*
 941          * DPDK sets promiscuous mode on just after this call assuming
 942          * it can not fail ...
 943          */
 944         ret = nfp_net_reconfig(hw, new_ctrl, update);
 945         if (ret < 0)
 946                 return ret;
 947
 948         hw->ctrl = new_ctrl;
 949
 950         return 0;
 951 }
 952
 953 static int
 954 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 955 {
 956         uint32_t new_ctrl, update = 0;
 957         struct nfp_net_hw *hw;
 958         int ret;
 959
 960         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 961
 962         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 963                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 964                 return 0;
 965         }
 966
 967         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 968         update = NFP_NET_CFG_UPDATE_GEN;
 969
 970         /*
 971          * DPDK sets promiscuous mode off just before this call
 972          * assuming it can not fail ...
 973          */
 974         ret = nfp_net_reconfig(hw, new_ctrl, update);
 975         if (ret < 0)
 976                 return ret;
 977
 978         hw->ctrl = new_ctrl;
 979
 980         return 0;
 981 }
 982
 983 /*
 984  * return 0 means link status changed, -1 means not changed
 985  *
 986  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 987  * status.
 988  */
 989 static int
 990 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 991 {
 992         struct nfp_net_hw *hw;
 993         struct rte_eth_link link;
 994         uint32_t nn_link_status;
 995         int ret;
 996
 997         static const uint32_t ls_to_ethtool[] = {
 998                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 999                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
1000                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
1001                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
1002                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
1003                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
1004                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
1005                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
1006         };
1007
1008         PMD_DRV_LOG(DEBUG, "Link update");
1009
1010         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1011
1012         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1013
1014         memset(&link, 0, sizeof(struct rte_eth_link));
1015
1016         if (nn_link_status & NFP_NET_CFG_STS_LINK)
1017                 link.link_status = ETH_LINK_UP;
1018
1019         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1020
1021         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1022                          NFP_NET_CFG_STS_LINK_RATE_MASK;
1023
1024         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1025                 link.link_speed = ETH_SPEED_NUM_NONE;
1026         else
1027                 link.link_speed = ls_to_ethtool[nn_link_status];
1028
1029         ret = rte_eth_linkstatus_set(dev, &link);
1030         if (ret == 0) {
1031                 if (link.link_status)
1032                         PMD_DRV_LOG(INFO, "NIC Link is Up");
1033                 else
1034                         PMD_DRV_LOG(INFO, "NIC Link is Down");
1035         }
1036         return ret;
1037 }
1038
1039 static int
1040 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1041 {
1042         int i;
1043         struct nfp_net_hw *hw;
1044         struct rte_eth_stats nfp_dev_stats;
1045
1046         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1047
1048         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1049
1050         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1051
1052         /* reading per RX ring stats */
1053         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1054                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1055                         break;
1056
1057                 nfp_dev_stats.q_ipackets[i] =
1058                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1059
1060                 nfp_dev_stats.q_ipackets[i] -=
1061                         hw->eth_stats_base.q_ipackets[i];
1062
1063                 nfp_dev_stats.q_ibytes[i] =
1064                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1065
1066                 nfp_dev_stats.q_ibytes[i] -=
1067                         hw->eth_stats_base.q_ibytes[i];
1068         }
1069
1070         /* reading per TX ring stats */
1071         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1072                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1073                         break;
1074
1075                 nfp_dev_stats.q_opackets[i] =
1076                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1077
1078                 nfp_dev_stats.q_opackets[i] -=
1079                         hw->eth_stats_base.q_opackets[i];
1080
1081                 nfp_dev_stats.q_obytes[i] =
1082                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1083
1084                 nfp_dev_stats.q_obytes[i] -=
1085                         hw->eth_stats_base.q_obytes[i];
1086         }
1087
1088         nfp_dev_stats.ipackets =
1089                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1090
1091         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1092
1093         nfp_dev_stats.ibytes =
1094                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1095
1096         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1097
1098         nfp_dev_stats.opackets =
1099                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1100
1101         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1102
1103         nfp_dev_stats.obytes =
1104                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1105
1106         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1107
1108         /* reading general device stats */
1109         nfp_dev_stats.ierrors =
1110                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1111
1112         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1113
1114         nfp_dev_stats.oerrors =
1115                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1116
1117         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1118
1119         /* RX ring mbuf allocation failures */
1120         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1121
1122         nfp_dev_stats.imissed =
1123                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1124
1125         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1126
1127         if (stats) {
1128                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1129                 return 0;
1130         }
1131         return -EINVAL;
1132 }
1133
1134 static int
1135 nfp_net_stats_reset(struct rte_eth_dev *dev)
1136 {
1137         int i;
1138         struct nfp_net_hw *hw;
1139
1140         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1141
1142         /*
1143          * hw->eth_stats_base records the per counter starting point.
1144          * Lets update it now
1145          */
1146
1147         /* reading per RX ring stats */
1148         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1149                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1150                         break;
1151
1152                 hw->eth_stats_base.q_ipackets[i] =
1153                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1154
1155                 hw->eth_stats_base.q_ibytes[i] =
1156                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1157         }
1158
1159         /* reading per TX ring stats */
1160         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1161                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1162                         break;
1163
1164                 hw->eth_stats_base.q_opackets[i] =
1165                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1166
1167                 hw->eth_stats_base.q_obytes[i] =
1168                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1169         }
1170
1171         hw->eth_stats_base.ipackets =
1172                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1173
1174         hw->eth_stats_base.ibytes =
1175                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1176
1177         hw->eth_stats_base.opackets =
1178                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1179
1180         hw->eth_stats_base.obytes =
1181                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1182
1183         /* reading general device stats */
1184         hw->eth_stats_base.ierrors =
1185                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1186
1187         hw->eth_stats_base.oerrors =
1188                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1189
1190         /* RX ring mbuf allocation failures */
1191         dev->data->rx_mbuf_alloc_failed = 0;
1192
1193         hw->eth_stats_base.imissed =
1194                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1195
1196         return 0;
1197 }
1198
1199 static int
1200 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1201 {
1202         struct nfp_net_hw *hw;
1203
1204         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205
1206         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1207         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1208         dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1209         dev_info->max_rx_pktlen = hw->max_mtu;
1210         /* Next should change when PF support is implemented */
1211         dev_info->max_mac_addrs = 1;
1212
1213         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1214                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1215
1216         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1217                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1218                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1219                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1220
1221         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME |
1222                                      DEV_RX_OFFLOAD_RSS_HASH;
1223
1224         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1225                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1226
1227         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1228                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1229                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1230                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1231
1232         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1233                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1234
1235         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1236                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1237
1238         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1239                 .rx_thresh = {
1240                         .pthresh = DEFAULT_RX_PTHRESH,
1241                         .hthresh = DEFAULT_RX_HTHRESH,
1242                         .wthresh = DEFAULT_RX_WTHRESH,
1243                 },
1244                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1245                 .rx_drop_en = 0,
1246         };
1247
1248         dev_info->default_txconf = (struct rte_eth_txconf) {
1249                 .tx_thresh = {
1250                         .pthresh = DEFAULT_TX_PTHRESH,
1251                         .hthresh = DEFAULT_TX_HTHRESH,
1252                         .wthresh = DEFAULT_TX_WTHRESH,
1253                 },
1254                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1255                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1256         };
1257
1258         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1259                 .nb_max = NFP_NET_MAX_RX_DESC,
1260                 .nb_min = NFP_NET_MIN_RX_DESC,
1261                 .nb_align = NFP_ALIGN_RING_DESC,
1262         };
1263
1264         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1265                 .nb_max = NFP_NET_MAX_TX_DESC,
1266                 .nb_min = NFP_NET_MIN_TX_DESC,
1267                 .nb_align = NFP_ALIGN_RING_DESC,
1268                 .nb_seg_max = NFP_TX_MAX_SEG,
1269                 .nb_mtu_seg_max = NFP_TX_MAX_MTU_SEG,
1270         };
1271
1272         dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1273                                            ETH_RSS_NONFRAG_IPV4_TCP |
1274                                            ETH_RSS_NONFRAG_IPV4_UDP |
1275                                            ETH_RSS_IPV6 |
1276                                            ETH_RSS_NONFRAG_IPV6_TCP |
1277                                            ETH_RSS_NONFRAG_IPV6_UDP;
1278
1279         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1280         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1281
1282         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1283                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1284                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1285
1286         return 0;
1287 }
1288
1289 static const uint32_t *
1290 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1291 {
1292         static const uint32_t ptypes[] = {
1293                 /* refers to nfp_net_set_hash() */
1294                 RTE_PTYPE_INNER_L3_IPV4,
1295                 RTE_PTYPE_INNER_L3_IPV6,
1296                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1297                 RTE_PTYPE_INNER_L4_MASK,
1298                 RTE_PTYPE_UNKNOWN
1299         };
1300
1301         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1302                 return ptypes;
1303         return NULL;
1304 }
1305
1306 static uint32_t
1307 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1308 {
1309         struct nfp_net_rxq *rxq;
1310         struct nfp_net_rx_desc *rxds;
1311         uint32_t idx;
1312         uint32_t count;
1313
1314         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1315
1316         idx = rxq->rd_p;
1317
1318         count = 0;
1319
1320         /*
1321          * Other PMDs are just checking the DD bit in intervals of 4
1322          * descriptors and counting all four if the first has the DD
1323          * bit on. Of course, this is not accurate but can be good for
1324          * performance. But ideally that should be done in descriptors
1325          * chunks belonging to the same cache line
1326          */
1327
1328         while (count < rxq->rx_count) {
1329                 rxds = &rxq->rxds[idx];
1330                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1331                         break;
1332
1333                 count++;
1334                 idx++;
1335
1336                 /* Wrapping? */
1337                 if ((idx) == rxq->rx_count)
1338                         idx = 0;
1339         }
1340
1341         return count;
1342 }
1343
1344 static int
1345 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1346 {
1347         struct rte_pci_device *pci_dev;
1348         struct nfp_net_hw *hw;
1349         int base = 0;
1350
1351         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1353
1354         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1355                 base = 1;
1356
1357         /* Make sure all updates are written before un-masking */
1358         rte_wmb();
1359         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1360                       NFP_NET_CFG_ICR_UNMASKED);
1361         return 0;
1362 }
1363
1364 static int
1365 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1366 {
1367         struct rte_pci_device *pci_dev;
1368         struct nfp_net_hw *hw;
1369         int base = 0;
1370
1371         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1372         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1373
1374         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1375                 base = 1;
1376
1377         /* Make sure all updates are written before un-masking */
1378         rte_wmb();
1379         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1380         return 0;
1381 }
1382
1383 static void
1384 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1385 {
1386         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1387         struct rte_eth_link link;
1388
1389         rte_eth_linkstatus_get(dev, &link);
1390         if (link.link_status)
1391                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1392                             dev->data->port_id, link.link_speed,
1393                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1394                             ? "full-duplex" : "half-duplex");
1395         else
1396                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1397                             dev->data->port_id);
1398
1399         PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
1400                     pci_dev->addr.domain, pci_dev->addr.bus,
1401                     pci_dev->addr.devid, pci_dev->addr.function);
1402 }
1403
1404 /* Interrupt configuration and handling */
1405
1406 /*
1407  * nfp_net_irq_unmask - Unmask an interrupt
1408  *
1409  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1410  * clear the ICR for the entry.
1411  */
1412 static void
1413 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1414 {
1415         struct nfp_net_hw *hw;
1416         struct rte_pci_device *pci_dev;
1417
1418         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1420
1421         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1422                 /* If MSI-X auto-masking is used, clear the entry */
1423                 rte_wmb();
1424                 rte_intr_ack(&pci_dev->intr_handle);
1425         } else {
1426                 /* Make sure all updates are written before un-masking */
1427                 rte_wmb();
1428                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1429                               NFP_NET_CFG_ICR_UNMASKED);
1430         }
1431 }
1432
1433 static void
1434 nfp_net_dev_interrupt_handler(void *param)
1435 {
1436         int64_t timeout;
1437         struct rte_eth_link link;
1438         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1439
1440         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1441
1442         rte_eth_linkstatus_get(dev, &link);
1443
1444         nfp_net_link_update(dev, 0);
1445
1446         /* likely to up */
1447         if (!link.link_status) {
1448                 /* handle it 1 sec later, wait it being stable */
1449                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1450                 /* likely to down */
1451         } else {
1452                 /* handle it 4 sec later, wait it being stable */
1453                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1454         }
1455
1456         if (rte_eal_alarm_set(timeout * 1000,
1457                               nfp_net_dev_interrupt_delayed_handler,
1458                               (void *)dev) < 0) {
1459                 PMD_INIT_LOG(ERR, "Error setting alarm");
1460                 /* Unmasking */
1461                 nfp_net_irq_unmask(dev);
1462         }
1463 }
1464
1465 /*
1466  * Interrupt handler which shall be registered for alarm callback for delayed
1467  * handling specific interrupt to wait for the stable nic state. As the NIC
1468  * interrupt state is not stable for nfp after link is just down, it needs
1469  * to wait 4 seconds to get the stable status.
1470  *
1471  * @param handle   Pointer to interrupt handle.
1472  * @param param    The address of parameter (struct rte_eth_dev *)
1473  *
1474  * @return  void
1475  */
1476 static void
1477 nfp_net_dev_interrupt_delayed_handler(void *param)
1478 {
1479         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1480
1481         nfp_net_link_update(dev, 0);
1482         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1483
1484         nfp_net_dev_link_status_print(dev);
1485
1486         /* Unmasking */
1487         nfp_net_irq_unmask(dev);
1488 }
1489
1490 static int
1491 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1492 {
1493         struct nfp_net_hw *hw;
1494
1495         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1496
1497         /* check that mtu is within the allowed range */
1498         if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1499                 return -EINVAL;
1500
1501         /* mtu setting is forbidden if port is started */
1502         if (dev->data->dev_started) {
1503                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1504                             dev->data->port_id);
1505                 return -EBUSY;
1506         }
1507
1508         /* switch to jumbo mode if needed */
1509         if ((uint32_t)mtu > RTE_ETHER_MAX_LEN)
1510                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1511         else
1512                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1513
1514         /* update max frame size */
1515         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1516
1517         /* writing to configuration space */
1518         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1519
1520         hw->mtu = mtu;
1521
1522         return 0;
1523 }
1524
1525 static int
1526 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1527                        uint16_t queue_idx, uint16_t nb_desc,
1528                        unsigned int socket_id,
1529                        const struct rte_eth_rxconf *rx_conf,
1530                        struct rte_mempool *mp)
1531 {
1532         const struct rte_memzone *tz;
1533         struct nfp_net_rxq *rxq;
1534         struct nfp_net_hw *hw;
1535         uint32_t rx_desc_sz;
1536
1537         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1538
1539         PMD_INIT_FUNC_TRACE();
1540
1541         /* Validating number of descriptors */
1542         rx_desc_sz = nb_desc * sizeof(struct nfp_net_rx_desc);
1543         if (rx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1544             nb_desc > NFP_NET_MAX_RX_DESC ||
1545             nb_desc < NFP_NET_MIN_RX_DESC) {
1546                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1547                 return -EINVAL;
1548         }
1549
1550         /*
1551          * Free memory prior to re-allocation if needed. This is the case after
1552          * calling nfp_net_stop
1553          */
1554         if (dev->data->rx_queues[queue_idx]) {
1555                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1556                 dev->data->rx_queues[queue_idx] = NULL;
1557         }
1558
1559         /* Allocating rx queue data structure */
1560         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1561                                  RTE_CACHE_LINE_SIZE, socket_id);
1562         if (rxq == NULL)
1563                 return -ENOMEM;
1564
1565         /* Hw queues mapping based on firmware configuration */
1566         rxq->qidx = queue_idx;
1567         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1568         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1569         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1570         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1571
1572         /*
1573          * Tracking mbuf size for detecting a potential mbuf overflow due to
1574          * RX offset
1575          */
1576         rxq->mem_pool = mp;
1577         rxq->mbuf_size = rxq->mem_pool->elt_size;
1578         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1579         hw->flbufsz = rxq->mbuf_size;
1580
1581         rxq->rx_count = nb_desc;
1582         rxq->port_id = dev->data->port_id;
1583         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1584         rxq->drop_en = rx_conf->rx_drop_en;
1585
1586         /*
1587          * Allocate RX ring hardware descriptors. A memzone large enough to
1588          * handle the maximum ring size is allocated in order to allow for
1589          * resizing in later calls to the queue setup function.
1590          */
1591         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1592                                    sizeof(struct nfp_net_rx_desc) *
1593                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1594                                    socket_id);
1595
1596         if (tz == NULL) {
1597                 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1598                 nfp_net_rx_queue_release(rxq);
1599                 return -ENOMEM;
1600         }
1601
1602         /* Saving physical and virtual addresses for the RX ring */
1603         rxq->dma = (uint64_t)tz->iova;
1604         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1605
1606         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1607         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1608                                          sizeof(*rxq->rxbufs) * nb_desc,
1609                                          RTE_CACHE_LINE_SIZE, socket_id);
1610         if (rxq->rxbufs == NULL) {
1611                 nfp_net_rx_queue_release(rxq);
1612                 return -ENOMEM;
1613         }
1614
1615         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1616                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1617
1618         nfp_net_reset_rx_queue(rxq);
1619
1620         dev->data->rx_queues[queue_idx] = rxq;
1621         rxq->hw = hw;
1622
1623         /*
1624          * Telling the HW about the physical address of the RX ring and number
1625          * of descriptors in log2 format
1626          */
1627         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1628         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1629
1630         return 0;
1631 }
1632
1633 static int
1634 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1635 {
1636         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1637         uint64_t dma_addr;
1638         unsigned i;
1639
1640         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1641                    rxq->rx_count);
1642
1643         for (i = 0; i < rxq->rx_count; i++) {
1644                 struct nfp_net_rx_desc *rxd;
1645                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1646
1647                 if (mbuf == NULL) {
1648                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1649                                 (unsigned)rxq->qidx);
1650                         return -ENOMEM;
1651                 }
1652
1653                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1654
1655                 rxd = &rxq->rxds[i];
1656                 rxd->fld.dd = 0;
1657                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1658                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1659                 rxe[i].mbuf = mbuf;
1660                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1661         }
1662
1663         /* Make sure all writes are flushed before telling the hardware */
1664         rte_wmb();
1665
1666         /* Not advertising the whole ring as the firmware gets confused if so */
1667         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1668                    rxq->rx_count - 1);
1669
1670         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1671
1672         return 0;
1673 }
1674
1675 static int
1676 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1677                        uint16_t nb_desc, unsigned int socket_id,
1678                        const struct rte_eth_txconf *tx_conf)
1679 {
1680         const struct rte_memzone *tz;
1681         struct nfp_net_txq *txq;
1682         uint16_t tx_free_thresh;
1683         struct nfp_net_hw *hw;
1684         uint32_t tx_desc_sz;
1685
1686         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687
1688         PMD_INIT_FUNC_TRACE();
1689
1690         /* Validating number of descriptors */
1691         tx_desc_sz = nb_desc * sizeof(struct nfp_net_tx_desc);
1692         if (tx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1693             nb_desc > NFP_NET_MAX_TX_DESC ||
1694             nb_desc < NFP_NET_MIN_TX_DESC) {
1695                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1696                 return -EINVAL;
1697         }
1698
1699         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1700                                     tx_conf->tx_free_thresh :
1701                                     DEFAULT_TX_FREE_THRESH);
1702
1703         if (tx_free_thresh > (nb_desc)) {
1704                 PMD_DRV_LOG(ERR,
1705                         "tx_free_thresh must be less than the number of TX "
1706                         "descriptors. (tx_free_thresh=%u port=%d "
1707                         "queue=%d)", (unsigned int)tx_free_thresh,
1708                         dev->data->port_id, (int)queue_idx);
1709                 return -(EINVAL);
1710         }
1711
1712         /*
1713          * Free memory prior to re-allocation if needed. This is the case after
1714          * calling nfp_net_stop
1715          */
1716         if (dev->data->tx_queues[queue_idx]) {
1717                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1718                            queue_idx);
1719                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1720                 dev->data->tx_queues[queue_idx] = NULL;
1721         }
1722
1723         /* Allocating tx queue data structure */
1724         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1725                                  RTE_CACHE_LINE_SIZE, socket_id);
1726         if (txq == NULL) {
1727                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1728                 return -ENOMEM;
1729         }
1730
1731         /*
1732          * Allocate TX ring hardware descriptors. A memzone large enough to
1733          * handle the maximum ring size is allocated in order to allow for
1734          * resizing in later calls to the queue setup function.
1735          */
1736         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1737                                    sizeof(struct nfp_net_tx_desc) *
1738                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1739                                    socket_id);
1740         if (tz == NULL) {
1741                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1742                 nfp_net_tx_queue_release(txq);
1743                 return -ENOMEM;
1744         }
1745
1746         txq->tx_count = nb_desc;
1747         txq->tx_free_thresh = tx_free_thresh;
1748         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1749         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1750         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1751
1752         /* queue mapping based on firmware configuration */
1753         txq->qidx = queue_idx;
1754         txq->tx_qcidx = queue_idx * hw->stride_tx;
1755         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1756
1757         txq->port_id = dev->data->port_id;
1758
1759         /* Saving physical and virtual addresses for the TX ring */
1760         txq->dma = (uint64_t)tz->iova;
1761         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1762
1763         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1764         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1765                                          sizeof(*txq->txbufs) * nb_desc,
1766                                          RTE_CACHE_LINE_SIZE, socket_id);
1767         if (txq->txbufs == NULL) {
1768                 nfp_net_tx_queue_release(txq);
1769                 return -ENOMEM;
1770         }
1771         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1772                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1773
1774         nfp_net_reset_tx_queue(txq);
1775
1776         dev->data->tx_queues[queue_idx] = txq;
1777         txq->hw = hw;
1778
1779         /*
1780          * Telling the HW about the physical address of the TX ring and number
1781          * of descriptors in log2 format
1782          */
1783         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1784         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1785
1786         return 0;
1787 }
1788
1789 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1790 static inline void
1791 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1792                struct rte_mbuf *mb)
1793 {
1794         uint64_t ol_flags;
1795         struct nfp_net_hw *hw = txq->hw;
1796
1797         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1798                 goto clean_txd;
1799
1800         ol_flags = mb->ol_flags;
1801
1802         if (!(ol_flags & PKT_TX_TCP_SEG))
1803                 goto clean_txd;
1804
1805         txd->l3_offset = mb->l2_len;
1806         txd->l4_offset = mb->l2_len + mb->l3_len;
1807         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1808         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1809         txd->flags = PCIE_DESC_TX_LSO;
1810         return;
1811
1812 clean_txd:
1813         txd->flags = 0;
1814         txd->l3_offset = 0;
1815         txd->l4_offset = 0;
1816         txd->lso_hdrlen = 0;
1817         txd->mss = 0;
1818 }
1819
1820 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1821 static inline void
1822 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1823                  struct rte_mbuf *mb)
1824 {
1825         uint64_t ol_flags;
1826         struct nfp_net_hw *hw = txq->hw;
1827
1828         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1829                 return;
1830
1831         ol_flags = mb->ol_flags;
1832
1833         /* IPv6 does not need checksum */
1834         if (ol_flags & PKT_TX_IP_CKSUM)
1835                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1836
1837         switch (ol_flags & PKT_TX_L4_MASK) {
1838         case PKT_TX_UDP_CKSUM:
1839                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1840                 break;
1841         case PKT_TX_TCP_CKSUM:
1842                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1843                 break;
1844         }
1845
1846         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1847                 txd->flags |= PCIE_DESC_TX_CSUM;
1848 }
1849
1850 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1851 static inline void
1852 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1853                  struct rte_mbuf *mb)
1854 {
1855         struct nfp_net_hw *hw = rxq->hw;
1856
1857         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1858                 return;
1859
1860         /* If IPv4 and IP checksum error, fail */
1861         if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1862             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1863                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1864         else
1865                 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1866
1867         /* If neither UDP nor TCP return */
1868         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1869             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1870                 return;
1871
1872         if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1873                 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1874         else
1875                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1876 }
1877
1878 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1879 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1880
1881 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1882
1883 /*
1884  * nfp_net_set_hash - Set mbuf hash data
1885  *
1886  * The RSS hash and hash-type are pre-pended to the packet data.
1887  * Extract and decode it and set the mbuf fields.
1888  */
1889 static inline void
1890 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1891                  struct rte_mbuf *mbuf)
1892 {
1893         struct nfp_net_hw *hw = rxq->hw;
1894         uint8_t *meta_offset;
1895         uint32_t meta_info;
1896         uint32_t hash = 0;
1897         uint32_t hash_type = 0;
1898
1899         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1900                 return;
1901
1902         /* this is true for new firmwares */
1903         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1904             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1905              NFP_DESC_META_LEN(rxd))) {
1906                 /*
1907                  * new metadata api:
1908                  * <----  32 bit  ----->
1909                  * m    field type word
1910                  * e     data field #2
1911                  * t     data field #1
1912                  * a     data field #0
1913                  * ====================
1914                  *    packet data
1915                  *
1916                  * Field type word contains up to 8 4bit field types
1917                  * A 4bit field type refers to a data field word
1918                  * A data field word can have several 4bit field types
1919                  */
1920                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1921                 meta_offset -= NFP_DESC_META_LEN(rxd);
1922                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1923                 meta_offset += 4;
1924                 /* NFP PMD just supports metadata for hashing */
1925                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1926                 case NFP_NET_META_HASH:
1927                         /* next field type is about the hash type */
1928                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1929                         /* hash value is in the data field */
1930                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1931                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1932                         break;
1933                 default:
1934                         /* Unsupported metadata can be a performance issue */
1935                         return;
1936                 }
1937         } else {
1938                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1939                         return;
1940
1941                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1942                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1943         }
1944
1945         mbuf->hash.rss = hash;
1946         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1947
1948         switch (hash_type) {
1949         case NFP_NET_RSS_IPV4:
1950                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1951                 break;
1952         case NFP_NET_RSS_IPV6:
1953                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1954                 break;
1955         case NFP_NET_RSS_IPV6_EX:
1956                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1957                 break;
1958         case NFP_NET_RSS_IPV4_TCP:
1959                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1960                 break;
1961         case NFP_NET_RSS_IPV6_TCP:
1962                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1963                 break;
1964         case NFP_NET_RSS_IPV4_UDP:
1965                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1966                 break;
1967         case NFP_NET_RSS_IPV6_UDP:
1968                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1969                 break;
1970         default:
1971                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1972         }
1973 }
1974
1975 static inline void
1976 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1977 {
1978         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1979 }
1980
1981 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1982
1983 /*
1984  * RX path design:
1985  *
1986  * There are some decisions to take:
1987  * 1) How to check DD RX descriptors bit
1988  * 2) How and when to allocate new mbufs
1989  *
1990  * Current implementation checks just one single DD bit each loop. As each
1991  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1992  * a single cache line instead. Tests with this change have not shown any
1993  * performance improvement but it requires further investigation. For example,
1994  * depending on which descriptor is next, the number of descriptors could be
1995  * less than 8 for just checking those in the same cache line. This implies
1996  * extra work which could be counterproductive by itself. Indeed, last firmware
1997  * changes are just doing this: writing several descriptors with the DD bit
1998  * for saving PCIe bandwidth and DMA operations from the NFP.
1999  *
2000  * Mbuf allocation is done when a new packet is received. Then the descriptor
2001  * is automatically linked with the new mbuf and the old one is given to the
2002  * user. The main drawback with this design is mbuf allocation is heavier than
2003  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
2004  * cache point of view it does not seem allocating the mbuf early on as we are
2005  * doing now have any benefit at all. Again, tests with this change have not
2006  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2007  * so looking at the implications of this type of allocation should be studied
2008  * deeply
2009  */
2010
2011 static uint16_t
2012 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2013 {
2014         struct nfp_net_rxq *rxq;
2015         struct nfp_net_rx_desc *rxds;
2016         struct nfp_net_rx_buff *rxb;
2017         struct nfp_net_hw *hw;
2018         struct rte_mbuf *mb;
2019         struct rte_mbuf *new_mb;
2020         uint16_t nb_hold;
2021         uint64_t dma_addr;
2022         int avail;
2023
2024         rxq = rx_queue;
2025         if (unlikely(rxq == NULL)) {
2026                 /*
2027                  * DPDK just checks the queue is lower than max queues
2028                  * enabled. But the queue needs to be configured
2029                  */
2030                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2031                 return -EINVAL;
2032         }
2033
2034         hw = rxq->hw;
2035         avail = 0;
2036         nb_hold = 0;
2037
2038         while (avail < nb_pkts) {
2039                 rxb = &rxq->rxbufs[rxq->rd_p];
2040                 if (unlikely(rxb == NULL)) {
2041                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2042                         break;
2043                 }
2044
2045                 rxds = &rxq->rxds[rxq->rd_p];
2046                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2047                         break;
2048
2049                 /*
2050                  * Memory barrier to ensure that we won't do other
2051                  * reads before the DD bit.
2052                  */
2053                 rte_rmb();
2054
2055                 /*
2056                  * We got a packet. Let's alloc a new mbuf for refilling the
2057                  * free descriptor ring as soon as possible
2058                  */
2059                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2060                 if (unlikely(new_mb == NULL)) {
2061                         RTE_LOG_DP(DEBUG, PMD,
2062                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2063                                 rxq->port_id, (unsigned int)rxq->qidx);
2064                         nfp_net_mbuf_alloc_failed(rxq);
2065                         break;
2066                 }
2067
2068                 nb_hold++;
2069
2070                 /*
2071                  * Grab the mbuf and refill the descriptor with the
2072                  * previously allocated mbuf
2073                  */
2074                 mb = rxb->mbuf;
2075                 rxb->mbuf = new_mb;
2076
2077                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2078                            rxds->rxd.data_len, rxq->mbuf_size);
2079
2080                 /* Size of this segment */
2081                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2082                 /* Size of the whole packet. We just support 1 segment */
2083                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2084
2085                 if (unlikely((mb->data_len + hw->rx_offset) >
2086                              rxq->mbuf_size)) {
2087                         /*
2088                          * This should not happen and the user has the
2089                          * responsibility of avoiding it. But we have
2090                          * to give some info about the error
2091                          */
2092                         RTE_LOG_DP(ERR, PMD,
2093                                 "mbuf overflow likely due to the RX offset.\n"
2094                                 "\t\tYour mbuf size should have extra space for"
2095                                 " RX offset=%u bytes.\n"
2096                                 "\t\tCurrently you just have %u bytes available"
2097                                 " but the received packet is %u bytes long",
2098                                 hw->rx_offset,
2099                                 rxq->mbuf_size - hw->rx_offset,
2100                                 mb->data_len);
2101                         return -EINVAL;
2102                 }
2103
2104                 /* Filling the received mbuf with packet info */
2105                 if (hw->rx_offset)
2106                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2107                 else
2108                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2109                                        NFP_DESC_META_LEN(rxds);
2110
2111                 /* No scatter mode supported */
2112                 mb->nb_segs = 1;
2113                 mb->next = NULL;
2114
2115                 mb->port = rxq->port_id;
2116
2117                 /* Checking the RSS flag */
2118                 nfp_net_set_hash(rxq, rxds, mb);
2119
2120                 /* Checking the checksum flag */
2121                 nfp_net_rx_cksum(rxq, rxds, mb);
2122
2123                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2124                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2125                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2126                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2127                 }
2128
2129                 /* Adding the mbuf to the mbuf array passed by the app */
2130                 rx_pkts[avail++] = mb;
2131
2132                 /* Now resetting and updating the descriptor */
2133                 rxds->vals[0] = 0;
2134                 rxds->vals[1] = 0;
2135                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2136                 rxds->fld.dd = 0;
2137                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2138                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2139
2140                 rxq->rd_p++;
2141                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2142                         rxq->rd_p = 0;
2143         }
2144
2145         if (nb_hold == 0)
2146                 return nb_hold;
2147
2148         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2149                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2150
2151         nb_hold += rxq->nb_rx_hold;
2152
2153         /*
2154          * FL descriptors needs to be written before incrementing the
2155          * FL queue WR pointer
2156          */
2157         rte_wmb();
2158         if (nb_hold > rxq->rx_free_thresh) {
2159                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2160                            rxq->port_id, (unsigned int)rxq->qidx,
2161                            (unsigned)nb_hold, (unsigned)avail);
2162                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2163                 nb_hold = 0;
2164         }
2165         rxq->nb_rx_hold = nb_hold;
2166
2167         return avail;
2168 }
2169
2170 /*
2171  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2172  * status
2173  * @txq: TX queue to work with
2174  * Returns number of descriptors freed
2175  */
2176 int
2177 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2178 {
2179         uint32_t qcp_rd_p;
2180         int todo;
2181
2182         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2183                    " status", txq->qidx);
2184
2185         /* Work out how many packets have been sent */
2186         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2187
2188         if (qcp_rd_p == txq->rd_p) {
2189                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2190                            "packets (%u, %u)", txq->qidx,
2191                            qcp_rd_p, txq->rd_p);
2192                 return 0;
2193         }
2194
2195         if (qcp_rd_p > txq->rd_p)
2196                 todo = qcp_rd_p - txq->rd_p;
2197         else
2198                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2199
2200         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2201                    qcp_rd_p, txq->rd_p, txq->rd_p);
2202
2203         if (todo == 0)
2204                 return todo;
2205
2206         txq->rd_p += todo;
2207         if (unlikely(txq->rd_p >= txq->tx_count))
2208                 txq->rd_p -= txq->tx_count;
2209
2210         return todo;
2211 }
2212
2213 /* Leaving always free descriptors for avoiding wrapping confusion */
2214 static inline
2215 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2216 {
2217         if (txq->wr_p >= txq->rd_p)
2218                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2219         else
2220                 return txq->rd_p - txq->wr_p - 8;
2221 }
2222
2223 /*
2224  * nfp_net_txq_full - Check if the TX queue free descriptors
2225  * is below tx_free_threshold
2226  *
2227  * @txq: TX queue to check
2228  *
2229  * This function uses the host copy* of read/write pointers
2230  */
2231 static inline
2232 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2233 {
2234         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2235 }
2236
2237 static uint16_t
2238 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2239 {
2240         struct nfp_net_txq *txq;
2241         struct nfp_net_hw *hw;
2242         struct nfp_net_tx_desc *txds, txd;
2243         struct rte_mbuf *pkt;
2244         uint64_t dma_addr;
2245         int pkt_size, dma_size;
2246         uint16_t free_descs, issued_descs;
2247         struct rte_mbuf **lmbuf;
2248         int i;
2249
2250         txq = tx_queue;
2251         hw = txq->hw;
2252         txds = &txq->txds[txq->wr_p];
2253
2254         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2255                    txq->qidx, txq->wr_p, nb_pkts);
2256
2257         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2258                 nfp_net_tx_free_bufs(txq);
2259
2260         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2261         if (unlikely(free_descs == 0))
2262                 return 0;
2263
2264         pkt = *tx_pkts;
2265
2266         i = 0;
2267         issued_descs = 0;
2268         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2269                    txq->qidx, nb_pkts);
2270         /* Sending packets */
2271         while ((i < nb_pkts) && free_descs) {
2272                 /* Grabbing the mbuf linked to the current descriptor */
2273                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2274                 /* Warming the cache for releasing the mbuf later on */
2275                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2276
2277                 pkt = *(tx_pkts + i);
2278
2279                 if (unlikely((pkt->nb_segs > 1) &&
2280                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2281                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2282                         rte_panic("Multisegment packet unsupported\n");
2283                 }
2284
2285                 /* Checking if we have enough descriptors */
2286                 if (unlikely(pkt->nb_segs > free_descs))
2287                         goto xmit_end;
2288
2289                 /*
2290                  * Checksum and VLAN flags just in the first descriptor for a
2291                  * multisegment packet, but TSO info needs to be in all of them.
2292                  */
2293                 txd.data_len = pkt->pkt_len;
2294                 nfp_net_tx_tso(txq, &txd, pkt);
2295                 nfp_net_tx_cksum(txq, &txd, pkt);
2296
2297                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2298                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2299                         txd.flags |= PCIE_DESC_TX_VLAN;
2300                         txd.vlan = pkt->vlan_tci;
2301                 }
2302
2303                 /*
2304                  * mbuf data_len is the data in one segment and pkt_len data
2305                  * in the whole packet. When the packet is just one segment,
2306                  * then data_len = pkt_len
2307                  */
2308                 pkt_size = pkt->pkt_len;
2309
2310                 while (pkt) {
2311                         /* Copying TSO, VLAN and cksum info */
2312                         *txds = txd;
2313
2314                         /* Releasing mbuf used by this descriptor previously*/
2315                         if (*lmbuf)
2316                                 rte_pktmbuf_free_seg(*lmbuf);
2317
2318                         /*
2319                          * Linking mbuf with descriptor for being released
2320                          * next time descriptor is used
2321                          */
2322                         *lmbuf = pkt;
2323
2324                         dma_size = pkt->data_len;
2325                         dma_addr = rte_mbuf_data_iova(pkt);
2326                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2327                                    "%" PRIx64 "", dma_addr);
2328
2329                         /* Filling descriptors fields */
2330                         txds->dma_len = dma_size;
2331                         txds->data_len = txd.data_len;
2332                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2333                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2334                         ASSERT(free_descs > 0);
2335                         free_descs--;
2336
2337                         txq->wr_p++;
2338                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2339                                 txq->wr_p = 0;
2340
2341                         pkt_size -= dma_size;
2342
2343                         /*
2344                          * Making the EOP, packets with just one segment
2345                          * the priority
2346                          */
2347                         if (likely(!pkt_size))
2348                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2349                         else
2350                                 txds->offset_eop = 0;
2351
2352                         pkt = pkt->next;
2353                         /* Referencing next free TX descriptor */
2354                         txds = &txq->txds[txq->wr_p];
2355                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2356                         issued_descs++;
2357                 }
2358                 i++;
2359         }
2360
2361 xmit_end:
2362         /* Increment write pointers. Force memory write before we let HW know */
2363         rte_wmb();
2364         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2365
2366         return i;
2367 }
2368
2369 static int
2370 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2371 {
2372         uint32_t new_ctrl, update;
2373         struct nfp_net_hw *hw;
2374         int ret;
2375
2376         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2377         new_ctrl = 0;
2378
2379         /* Enable vlan strip if it is not configured yet */
2380         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2381             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2382                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2383
2384         /* Disable vlan strip just if it is configured */
2385         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2386             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2387                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2388
2389         if (new_ctrl == 0)
2390                 return 0;
2391
2392         update = NFP_NET_CFG_UPDATE_GEN;
2393
2394         ret = nfp_net_reconfig(hw, new_ctrl, update);
2395         if (!ret)
2396                 hw->ctrl = new_ctrl;
2397
2398         return ret;
2399 }
2400
2401 static int
2402 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2403                     struct rte_eth_rss_reta_entry64 *reta_conf,
2404                     uint16_t reta_size)
2405 {
2406         uint32_t reta, mask;
2407         int i, j;
2408         int idx, shift;
2409         struct nfp_net_hw *hw =
2410                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2411
2412         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2413                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2414                         "(%d) doesn't match the number hardware can supported "
2415                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2416                 return -EINVAL;
2417         }
2418
2419         /*
2420          * Update Redirection Table. There are 128 8bit-entries which can be
2421          * manage as 32 32bit-entries
2422          */
2423         for (i = 0; i < reta_size; i += 4) {
2424                 /* Handling 4 RSS entries per loop */
2425                 idx = i / RTE_RETA_GROUP_SIZE;
2426                 shift = i % RTE_RETA_GROUP_SIZE;
2427                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2428
2429                 if (!mask)
2430                         continue;
2431
2432                 reta = 0;
2433                 /* If all 4 entries were set, don't need read RETA register */
2434                 if (mask != 0xF)
2435                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2436
2437                 for (j = 0; j < 4; j++) {
2438                         if (!(mask & (0x1 << j)))
2439                                 continue;
2440                         if (mask != 0xF)
2441                                 /* Clearing the entry bits */
2442                                 reta &= ~(0xFF << (8 * j));
2443                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2444                 }
2445                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2446                               reta);
2447         }
2448         return 0;
2449 }
2450
2451 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2452 static int
2453 nfp_net_reta_update(struct rte_eth_dev *dev,
2454                     struct rte_eth_rss_reta_entry64 *reta_conf,
2455                     uint16_t reta_size)
2456 {
2457         struct nfp_net_hw *hw =
2458                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459         uint32_t update;
2460         int ret;
2461
2462         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2463                 return -EINVAL;
2464
2465         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2466         if (ret != 0)
2467                 return ret;
2468
2469         update = NFP_NET_CFG_UPDATE_RSS;
2470
2471         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2472                 return -EIO;
2473
2474         return 0;
2475 }
2476
2477  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2478 static int
2479 nfp_net_reta_query(struct rte_eth_dev *dev,
2480                    struct rte_eth_rss_reta_entry64 *reta_conf,
2481                    uint16_t reta_size)
2482 {
2483         uint8_t i, j, mask;
2484         int idx, shift;
2485         uint32_t reta;
2486         struct nfp_net_hw *hw;
2487
2488         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489
2490         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2491                 return -EINVAL;
2492
2493         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2494                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2495                         "(%d) doesn't match the number hardware can supported "
2496                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2497                 return -EINVAL;
2498         }
2499
2500         /*
2501          * Reading Redirection Table. There are 128 8bit-entries which can be
2502          * manage as 32 32bit-entries
2503          */
2504         for (i = 0; i < reta_size; i += 4) {
2505                 /* Handling 4 RSS entries per loop */
2506                 idx = i / RTE_RETA_GROUP_SIZE;
2507                 shift = i % RTE_RETA_GROUP_SIZE;
2508                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2509
2510                 if (!mask)
2511                         continue;
2512
2513                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2514                                     shift);
2515                 for (j = 0; j < 4; j++) {
2516                         if (!(mask & (0x1 << j)))
2517                                 continue;
2518                         reta_conf[idx].reta[shift + j] =
2519                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2520                 }
2521         }
2522         return 0;
2523 }
2524
2525 static int
2526 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2527                         struct rte_eth_rss_conf *rss_conf)
2528 {
2529         struct nfp_net_hw *hw;
2530         uint64_t rss_hf;
2531         uint32_t cfg_rss_ctrl = 0;
2532         uint8_t key;
2533         int i;
2534
2535         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536
2537         /* Writing the key byte a byte */
2538         for (i = 0; i < rss_conf->rss_key_len; i++) {
2539                 memcpy(&key, &rss_conf->rss_key[i], 1);
2540                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2541         }
2542
2543         rss_hf = rss_conf->rss_hf;
2544
2545         if (rss_hf & ETH_RSS_IPV4)
2546                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2547
2548         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2549                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2550
2551         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2552                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2553
2554         if (rss_hf & ETH_RSS_IPV6)
2555                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2556
2557         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2558                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2559
2560         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2561                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2562
2563         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2564         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2565
2566         /* configuring where to apply the RSS hash */
2567         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2568
2569         /* Writing the key size */
2570         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2571
2572         return 0;
2573 }
2574
2575 static int
2576 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2577                         struct rte_eth_rss_conf *rss_conf)
2578 {
2579         uint32_t update;
2580         uint64_t rss_hf;
2581         struct nfp_net_hw *hw;
2582
2583         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584
2585         rss_hf = rss_conf->rss_hf;
2586
2587         /* Checking if RSS is enabled */
2588         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2589                 if (rss_hf != 0) { /* Enable RSS? */
2590                         PMD_DRV_LOG(ERR, "RSS unsupported");
2591                         return -EINVAL;
2592                 }
2593                 return 0; /* Nothing to do */
2594         }
2595
2596         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2597                 PMD_DRV_LOG(ERR, "hash key too long");
2598                 return -EINVAL;
2599         }
2600
2601         nfp_net_rss_hash_write(dev, rss_conf);
2602
2603         update = NFP_NET_CFG_UPDATE_RSS;
2604
2605         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2606                 return -EIO;
2607
2608         return 0;
2609 }
2610
2611 static int
2612 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2613                           struct rte_eth_rss_conf *rss_conf)
2614 {
2615         uint64_t rss_hf;
2616         uint32_t cfg_rss_ctrl;
2617         uint8_t key;
2618         int i;
2619         struct nfp_net_hw *hw;
2620
2621         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2622
2623         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2624                 return -EINVAL;
2625
2626         rss_hf = rss_conf->rss_hf;
2627         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2628
2629         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2630                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2631
2632         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2633                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2634
2635         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2636                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2637
2638         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2639                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2640
2641         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2642                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2643
2644         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2645                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2646
2647         /* Propagate current RSS hash functions to caller */
2648         rss_conf->rss_hf = rss_hf;
2649
2650         /* Reading the key size */
2651         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2652
2653         /* Reading the key byte a byte */
2654         for (i = 0; i < rss_conf->rss_key_len; i++) {
2655                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2656                 memcpy(&rss_conf->rss_key[i], &key, 1);
2657         }
2658
2659         return 0;
2660 }
2661
2662 static int
2663 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2664 {
2665         struct rte_eth_conf *dev_conf;
2666         struct rte_eth_rss_conf rss_conf;
2667         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2668         uint16_t rx_queues = dev->data->nb_rx_queues;
2669         uint16_t queue;
2670         int i, j, ret;
2671
2672         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2673                 rx_queues);
2674
2675         nfp_reta_conf[0].mask = ~0x0;
2676         nfp_reta_conf[1].mask = ~0x0;
2677
2678         queue = 0;
2679         for (i = 0; i < 0x40; i += 8) {
2680                 for (j = i; j < (i + 8); j++) {
2681                         nfp_reta_conf[0].reta[j] = queue;
2682                         nfp_reta_conf[1].reta[j] = queue++;
2683                         queue %= rx_queues;
2684                 }
2685         }
2686         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2687         if (ret != 0)
2688                 return ret;
2689
2690         dev_conf = &dev->data->dev_conf;
2691         if (!dev_conf) {
2692                 PMD_DRV_LOG(INFO, "wrong rss conf");
2693                 return -EINVAL;
2694         }
2695         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2696
2697         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2698
2699         return ret;
2700 }
2701
2702
2703 /* Initialise and register driver with DPDK Application */
2704 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2705         .dev_configure          = nfp_net_configure,
2706         .dev_start              = nfp_net_start,
2707         .dev_stop               = nfp_net_stop,
2708         .dev_set_link_up        = nfp_net_set_link_up,
2709         .dev_set_link_down      = nfp_net_set_link_down,
2710         .dev_close              = nfp_net_close,
2711         .promiscuous_enable     = nfp_net_promisc_enable,
2712         .promiscuous_disable    = nfp_net_promisc_disable,
2713         .link_update            = nfp_net_link_update,
2714         .stats_get              = nfp_net_stats_get,
2715         .stats_reset            = nfp_net_stats_reset,
2716         .dev_infos_get          = nfp_net_infos_get,
2717         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2718         .mtu_set                = nfp_net_dev_mtu_set,
2719         .mac_addr_set           = nfp_set_mac_addr,
2720         .vlan_offload_set       = nfp_net_vlan_offload_set,
2721         .reta_update            = nfp_net_reta_update,
2722         .reta_query             = nfp_net_reta_query,
2723         .rss_hash_update        = nfp_net_rss_hash_update,
2724         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2725         .rx_queue_setup         = nfp_net_rx_queue_setup,
2726         .rx_queue_release       = nfp_net_rx_queue_release,
2727         .tx_queue_setup         = nfp_net_tx_queue_setup,
2728         .tx_queue_release       = nfp_net_tx_queue_release,
2729         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2730         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2731 };
2732
2733 /*
2734  * All eth_dev created got its private data, but before nfp_net_init, that
2735  * private data is referencing private data for all the PF ports. This is due
2736  * to how the vNIC bars are mapped based on first port, so all ports need info
2737  * about port 0 private data. Inside nfp_net_init the private data pointer is
2738  * changed to the right address for each port once the bars have been mapped.
2739  *
2740  * This functions helps to find out which port and therefore which offset
2741  * inside the private data array to use.
2742  */
2743 static int
2744 get_pf_port_number(char *name)
2745 {
2746         char *pf_str = name;
2747         int size = 0;
2748
2749         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2750                 pf_str++;
2751
2752         if (size == 30)
2753                 /*
2754                  * This should not happen at all and it would mean major
2755                  * implementation fault.
2756                  */
2757                 rte_panic("nfp_net: problem with pf device name\n");
2758
2759         /* Expecting _portX with X within [0,7] */
2760         pf_str += 5;
2761
2762         return (int)strtol(pf_str, NULL, 10);
2763 }
2764
2765 static int
2766 nfp_net_init(struct rte_eth_dev *eth_dev)
2767 {
2768         struct rte_pci_device *pci_dev;
2769         struct nfp_net_hw *hw, *hwport0;
2770
2771         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2772         uint32_t start_q;
2773         int stride = 4;
2774         int port = 0;
2775         int err;
2776
2777         PMD_INIT_FUNC_TRACE();
2778
2779         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2780
2781         /* NFP can not handle DMA addresses requiring more than 40 bits */
2782         if (rte_mem_check_dma_mask(40)) {
2783                 RTE_LOG(ERR, PMD, "device %s can not be used:",
2784                                    pci_dev->device.name);
2785                 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2786                 return -ENODEV;
2787         };
2788
2789         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2790             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2791                 port = get_pf_port_number(eth_dev->data->name);
2792                 if (port < 0 || port > 7) {
2793                         PMD_DRV_LOG(ERR, "Port value is wrong");
2794                         return -ENODEV;
2795                 }
2796
2797                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2798
2799                 /* This points to port 0 private data */
2800                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2801
2802                 /* This points to the specific port private data */
2803                 hw = &hwport0[port];
2804         } else {
2805                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2806                 hwport0 = 0;
2807         }
2808
2809         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2810         eth_dev->rx_queue_count = nfp_net_rx_queue_count;
2811         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2812         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2813
2814         /* For secondary processes, the primary has done all the work */
2815         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2816                 return 0;
2817
2818         rte_eth_copy_pci_info(eth_dev, pci_dev);
2819
2820         hw->device_id = pci_dev->id.device_id;
2821         hw->vendor_id = pci_dev->id.vendor_id;
2822         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2823         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2824
2825         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2826                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2827                      pci_dev->addr.domain, pci_dev->addr.bus,
2828                      pci_dev->addr.devid, pci_dev->addr.function);
2829
2830         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2831         if (hw->ctrl_bar == NULL) {
2832                 PMD_DRV_LOG(ERR,
2833                         "hw->ctrl_bar is NULL. BAR0 not configured");
2834                 return -ENODEV;
2835         }
2836
2837         if (hw->is_pf && port == 0) {
2838                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2839                                              hw->total_ports * 32768,
2840                                              &hw->ctrl_area);
2841                 if (!hw->ctrl_bar) {
2842                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2843                         return -EIO;
2844                 }
2845
2846                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2847         }
2848
2849         if (port > 0) {
2850                 if (!hwport0->ctrl_bar)
2851                         return -ENODEV;
2852
2853                 /* address based on port0 offset */
2854                 hw->ctrl_bar = hwport0->ctrl_bar +
2855                                (port * NFP_PF_CSR_SLICE_SIZE);
2856         }
2857
2858         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2859
2860         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2861         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2862
2863         /* Work out where in the BAR the queues start. */
2864         switch (pci_dev->id.device_id) {
2865         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2866         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2867         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2868                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2869                 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2870                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2871                 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2872                 break;
2873         default:
2874                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2875                 err = -ENODEV;
2876                 goto dev_err_ctrl_map;
2877         }
2878
2879         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2880         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2881
2882         if (hw->is_pf && port == 0) {
2883                 /* configure access to tx/rx vNIC BARs */
2884                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2885                                                       NFP_PCIE_QUEUE(0),
2886                                                       NFP_QCP_QUEUE_AREA_SZ,
2887                                                       &hw->hwqueues_area);
2888
2889                 if (!hwport0->hw_queues) {
2890                         printf("nfp_rtsym_map fails for net.qc");
2891                         err = -EIO;
2892                         goto dev_err_ctrl_map;
2893                 }
2894
2895                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2896                                     hwport0->hw_queues);
2897         }
2898
2899         if (hw->is_pf) {
2900                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2901                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2902                 eth_dev->data->dev_private = hw;
2903         } else {
2904                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2905                              tx_bar_off;
2906                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2907                              rx_bar_off;
2908         }
2909
2910         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2911                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2912
2913         nfp_net_cfg_queue_setup(hw);
2914
2915         /* Get some of the read-only fields from the config BAR */
2916         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2917         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2918         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2919         hw->mtu = RTE_ETHER_MTU;
2920
2921         /* VLAN insertion is incompatible with LSOv2 */
2922         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2923                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2924
2925         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2926                 hw->rx_offset = NFP_NET_RX_OFFSET;
2927         else
2928                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2929
2930         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2931                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2932                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2933
2934         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2935                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2936                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2937                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2938                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2939                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2940                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2941                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2942                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2943                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2944                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2945                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2946                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2947                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2948                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2949
2950         hw->ctrl = 0;
2951
2952         hw->stride_rx = stride;
2953         hw->stride_tx = stride;
2954
2955         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2956                      hw->max_rx_queues, hw->max_tx_queues);
2957
2958         /* Initializing spinlock for reconfigs */
2959         rte_spinlock_init(&hw->reconfig_lock);
2960
2961         /* Allocating memory for mac addr */
2962         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2963                                                RTE_ETHER_ADDR_LEN, 0);
2964         if (eth_dev->data->mac_addrs == NULL) {
2965                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2966                 err = -ENOMEM;
2967                 goto dev_err_queues_map;
2968         }
2969
2970         if (hw->is_pf) {
2971                 nfp_net_pf_read_mac(hwport0, port);
2972                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2973         } else {
2974                 nfp_net_vf_read_mac(hw);
2975         }
2976
2977         if (!rte_is_valid_assigned_ether_addr(
2978                     (struct rte_ether_addr *)&hw->mac_addr)) {
2979                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2980                                    port);
2981                 /* Using random mac addresses for VFs */
2982                 rte_eth_random_addr(&hw->mac_addr[0]);
2983                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2984         }
2985
2986         /* Copying mac address to DPDK eth_dev struct */
2987         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2988                         &eth_dev->data->mac_addrs[0]);
2989
2990         if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2991                 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2992
2993         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2994                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2995                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2996                      pci_dev->id.device_id,
2997                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2998                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2999
3000         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3001                 /* Registering LSC interrupt handler */
3002                 rte_intr_callback_register(&pci_dev->intr_handle,
3003                                            nfp_net_dev_interrupt_handler,
3004                                            (void *)eth_dev);
3005                 /* Telling the firmware about the LSC interrupt entry */
3006                 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
3007                 /* Recording current stats counters values */
3008                 nfp_net_stats_reset(eth_dev);
3009         }
3010
3011         return 0;
3012
3013 dev_err_queues_map:
3014                 nfp_cpp_area_free(hw->hwqueues_area);
3015 dev_err_ctrl_map:
3016                 nfp_cpp_area_free(hw->ctrl_area);
3017
3018         return err;
3019 }
3020
3021 #define NFP_CPP_MEMIO_BOUNDARY          (1 << 20)
3022
3023 /*
3024  * Serving a write request to NFP from host programs. The request
3025  * sends the write size and the CPP target. The bridge makes use
3026  * of CPP interface handler configured by the PMD setup.
3027  */
3028 static int
3029 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3030 {
3031         struct nfp_cpp_area *area;
3032         off_t offset, nfp_offset;
3033         uint32_t cpp_id, pos, len;
3034         uint32_t tmpbuf[16];
3035         size_t count, curlen, totlen = 0;
3036         int err = 0;
3037
3038         PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3039                 sizeof(off_t), sizeof(size_t));
3040
3041         /* Reading the count param */
3042         err = recv(sockfd, &count, sizeof(off_t), 0);
3043         if (err != sizeof(off_t))
3044                 return -EINVAL;
3045
3046         curlen = count;
3047
3048         /* Reading the offset param */
3049         err = recv(sockfd, &offset, sizeof(off_t), 0);
3050         if (err != sizeof(off_t))
3051                 return -EINVAL;
3052
3053         /* Obtain target's CPP ID and offset in target */
3054         cpp_id = (offset >> 40) << 8;
3055         nfp_offset = offset & ((1ull << 40) - 1);
3056
3057         PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3058                 offset);
3059         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3060                 cpp_id, nfp_offset);
3061
3062         /* Adjust length if not aligned */
3063         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3064             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3065                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3066                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3067         }
3068
3069         while (count > 0) {
3070                 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3071                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3072                                                     nfp_offset, curlen);
3073                 if (!area) {
3074                         RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3075                         return -EIO;
3076                 }
3077
3078                 /* mapping the target */
3079                 err = nfp_cpp_area_acquire(area);
3080                 if (err < 0) {
3081                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3082                         nfp_cpp_area_free(area);
3083                         return -EIO;
3084                 }
3085
3086                 for (pos = 0; pos < curlen; pos += len) {
3087                         len = curlen - pos;
3088                         if (len > sizeof(tmpbuf))
3089                                 len = sizeof(tmpbuf);
3090
3091                         PMD_CPP_LOG(DEBUG, "%s: Receive %u of %zu\n", __func__,
3092                                            len, count);
3093                         err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3094                         if (err != (int)len) {
3095                                 RTE_LOG(ERR, PMD,
3096                                         "%s: error when receiving, %d of %zu\n",
3097                                         __func__, err, count);
3098                                 nfp_cpp_area_release(area);
3099                                 nfp_cpp_area_free(area);
3100                                 return -EIO;
3101                         }
3102                         err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3103                         if (err < 0) {
3104                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3105                                 nfp_cpp_area_release(area);
3106                                 nfp_cpp_area_free(area);
3107                                 return -EIO;
3108                         }
3109                 }
3110
3111                 nfp_offset += pos;
3112                 totlen += pos;
3113                 nfp_cpp_area_release(area);
3114                 nfp_cpp_area_free(area);
3115
3116                 count -= pos;
3117                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3118                          NFP_CPP_MEMIO_BOUNDARY : count;
3119         }
3120
3121         return 0;
3122 }
3123
3124 /*
3125  * Serving a read request to NFP from host programs. The request
3126  * sends the read size and the CPP target. The bridge makes use
3127  * of CPP interface handler configured by the PMD setup. The read
3128  * data is sent to the requester using the same socket.
3129  */
3130 static int
3131 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3132 {
3133         struct nfp_cpp_area *area;
3134         off_t offset, nfp_offset;
3135         uint32_t cpp_id, pos, len;
3136         uint32_t tmpbuf[16];
3137         size_t count, curlen, totlen = 0;
3138         int err = 0;
3139
3140         PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3141                 sizeof(off_t), sizeof(size_t));
3142
3143         /* Reading the count param */
3144         err = recv(sockfd, &count, sizeof(off_t), 0);
3145         if (err != sizeof(off_t))
3146                 return -EINVAL;
3147
3148         curlen = count;
3149
3150         /* Reading the offset param */
3151         err = recv(sockfd, &offset, sizeof(off_t), 0);
3152         if (err != sizeof(off_t))
3153                 return -EINVAL;
3154
3155         /* Obtain target's CPP ID and offset in target */
3156         cpp_id = (offset >> 40) << 8;
3157         nfp_offset = offset & ((1ull << 40) - 1);
3158
3159         PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3160                            offset);
3161         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3162                            cpp_id, nfp_offset);
3163
3164         /* Adjust length if not aligned */
3165         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3166             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3167                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3168                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3169         }
3170
3171         while (count > 0) {
3172                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3173                                                     nfp_offset, curlen);
3174                 if (!area) {
3175                         RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3176                         return -EIO;
3177                 }
3178
3179                 err = nfp_cpp_area_acquire(area);
3180                 if (err < 0) {
3181                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3182                         nfp_cpp_area_free(area);
3183                         return -EIO;
3184                 }
3185
3186                 for (pos = 0; pos < curlen; pos += len) {
3187                         len = curlen - pos;
3188                         if (len > sizeof(tmpbuf))
3189                                 len = sizeof(tmpbuf);
3190
3191                         err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3192                         if (err < 0) {
3193                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3194                                 nfp_cpp_area_release(area);
3195                                 nfp_cpp_area_free(area);
3196                                 return -EIO;
3197                         }
3198                         PMD_CPP_LOG(DEBUG, "%s: sending %u of %zu\n", __func__,
3199                                            len, count);
3200
3201                         err = send(sockfd, tmpbuf, len, 0);
3202                         if (err != (int)len) {
3203                                 RTE_LOG(ERR, PMD,
3204                                         "%s: error when sending: %d of %zu\n",
3205                                         __func__, err, count);
3206                                 nfp_cpp_area_release(area);
3207                                 nfp_cpp_area_free(area);
3208                                 return -EIO;
3209                         }
3210                 }
3211
3212                 nfp_offset += pos;
3213                 totlen += pos;
3214                 nfp_cpp_area_release(area);
3215                 nfp_cpp_area_free(area);
3216
3217                 count -= pos;
3218                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3219                         NFP_CPP_MEMIO_BOUNDARY : count;
3220         }
3221         return 0;
3222 }
3223
3224 #define NFP_IOCTL 'n'
3225 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3226 /*
3227  * Serving a ioctl command from host NFP tools. This usually goes to
3228  * a kernel driver char driver but it is not available when the PF is
3229  * bound to the PMD. Currently just one ioctl command is served and it
3230  * does not require any CPP access at all.
3231  */
3232 static int
3233 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3234 {
3235         uint32_t cmd, ident_size, tmp;
3236         int err;
3237
3238         /* Reading now the IOCTL command */
3239         err = recv(sockfd, &cmd, 4, 0);
3240         if (err != 4) {
3241                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3242                 return -EIO;
3243         }
3244
3245         /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3246         if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3247                 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3248                 return -EINVAL;
3249         }
3250
3251         err = recv(sockfd, &ident_size, 4, 0);
3252         if (err != 4) {
3253                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3254                 return -EIO;
3255         }
3256
3257         tmp = nfp_cpp_model(cpp);
3258
3259         PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3260
3261         err = send(sockfd, &tmp, 4, 0);
3262         if (err != 4) {
3263                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3264                 return -EIO;
3265         }
3266
3267         tmp = cpp->interface;
3268
3269         PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3270
3271         err = send(sockfd, &tmp, 4, 0);
3272         if (err != 4) {
3273                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3274                 return -EIO;
3275         }
3276
3277         return 0;
3278 }
3279
3280 #define NFP_BRIDGE_OP_READ      20
3281 #define NFP_BRIDGE_OP_WRITE     30
3282 #define NFP_BRIDGE_OP_IOCTL     40
3283
3284 /*
3285  * This is the code to be executed by a service core. The CPP bridge interface
3286  * is based on a unix socket and requests usually received by a kernel char
3287  * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3288  * can be executed with a wrapper library and LD_LIBRARY being completely
3289  * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3290  * accesses.
3291  */
3292 static int32_t
3293 nfp_cpp_bridge_service_func(void *args)
3294 {
3295         struct sockaddr address;
3296         struct nfp_cpp *cpp = args;
3297         int sockfd, datafd, op, ret;
3298
3299         unlink("/tmp/nfp_cpp");
3300         sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3301         if (sockfd < 0) {
3302                 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3303                         __func__);
3304                 return -EIO;
3305         }
3306
3307         memset(&address, 0, sizeof(struct sockaddr));
3308
3309         address.sa_family = AF_UNIX;
3310         strcpy(address.sa_data, "/tmp/nfp_cpp");
3311
3312         ret = bind(sockfd, (const struct sockaddr *)&address,
3313                    sizeof(struct sockaddr));
3314         if (ret < 0) {
3315                 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3316                                   __func__, errno);
3317                 close(sockfd);
3318                 return ret;
3319         }
3320
3321         ret = listen(sockfd, 20);
3322         if (ret < 0) {
3323                 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3324                                   __func__, errno);
3325                 close(sockfd);
3326                 return ret;
3327         }
3328
3329         for (;;) {
3330                 datafd = accept(sockfd, NULL, NULL);
3331                 if (datafd < 0) {
3332                         RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3333                                           __func__, errno);
3334                         RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3335                         close(sockfd);
3336                         return -EIO;
3337                 }
3338
3339                 while (1) {
3340                         ret = recv(datafd, &op, 4, 0);
3341                         if (ret <= 0) {
3342                                 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3343                                                    __func__);
3344                                 break;
3345                         }
3346
3347                         PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3348
3349                         if (op == NFP_BRIDGE_OP_READ)
3350                                 nfp_cpp_bridge_serve_read(datafd, cpp);
3351
3352                         if (op == NFP_BRIDGE_OP_WRITE)
3353                                 nfp_cpp_bridge_serve_write(datafd, cpp);
3354
3355                         if (op == NFP_BRIDGE_OP_IOCTL)
3356                                 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3357
3358                         if (op == 0)
3359                                 break;
3360                 }
3361                 close(datafd);
3362         }
3363         close(sockfd);
3364
3365         return 0;
3366 }
3367
3368 static int
3369 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3370                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3371                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3372 {
3373         struct rte_eth_dev *eth_dev;
3374         struct nfp_net_hw *hw = NULL;
3375         char *port_name;
3376         struct rte_service_spec service;
3377         int retval;
3378
3379         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3380         if (!port_name)
3381                 return -ENOMEM;
3382
3383         if (ports > 1)
3384                 snprintf(port_name, 100, "%s_port%d", dev->device.name, port);
3385         else
3386                 strlcat(port_name, dev->device.name, 100);
3387
3388
3389         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3390                 eth_dev = rte_eth_dev_allocate(port_name);
3391                 if (!eth_dev) {
3392                         rte_free(port_name);
3393                         return -ENODEV;
3394                 }
3395                 if (port == 0) {
3396                         *priv = rte_zmalloc(port_name,
3397                                             sizeof(struct nfp_net_adapter) *
3398                                             ports, RTE_CACHE_LINE_SIZE);
3399                         if (!*priv) {
3400                                 rte_free(port_name);
3401                                 rte_eth_dev_release_port(eth_dev);
3402                                 return -ENOMEM;
3403                         }
3404                 }
3405                 eth_dev->data->dev_private = *priv;
3406
3407                 /*
3408                  * dev_private pointing to port0 dev_private because we need
3409                  * to configure vNIC bars based on port0 at nfp_net_init.
3410                  * Then dev_private is adjusted per port.
3411                  */
3412                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3413                 hw->cpp = cpp;
3414                 hw->hwinfo = hwinfo;
3415                 hw->sym_tbl = sym_tbl;
3416                 hw->pf_port_idx = phys_port;
3417                 hw->is_pf = 1;
3418                 if (ports > 1)
3419                         hw->pf_multiport_enabled = 1;
3420
3421                 hw->total_ports = ports;
3422         } else {
3423                 eth_dev = rte_eth_dev_attach_secondary(port_name);
3424                 if (!eth_dev) {
3425                         RTE_LOG(ERR, EAL, "secondary process attach failed, "
3426                                 "ethdev doesn't exist");
3427                         rte_free(port_name);
3428                         return -ENODEV;
3429                 }
3430                 eth_dev->process_private = cpp;
3431         }
3432
3433         eth_dev->device = &dev->device;
3434         rte_eth_copy_pci_info(eth_dev, dev);
3435
3436         retval = nfp_net_init(eth_dev);
3437
3438         if (retval) {
3439                 retval = -ENODEV;
3440                 goto probe_failed;
3441         } else {
3442                 rte_eth_dev_probing_finish(eth_dev);
3443         }
3444
3445         rte_free(port_name);
3446
3447         if (port == 0) {
3448                 /*
3449                  * The rte_service needs to be created just once per PMD.
3450                  * And the cpp handler needs to be linked to the service.
3451                  * Secondary processes will be used for debugging DPDK apps
3452                  * when requiring to use the CPP interface for accessing NFP
3453                  * components. And the cpp handler for secondary processes is
3454                  * available at this point.
3455                  */
3456                 memset(&service, 0, sizeof(struct rte_service_spec));
3457                 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3458                 service.callback = nfp_cpp_bridge_service_func;
3459                 service.callback_userdata = (void *)cpp;
3460
3461                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private);
3462
3463                 if (rte_service_component_register(&service,
3464                                                    &hw->nfp_cpp_service_id))
3465                         RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3466                 else
3467                         RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3468         }
3469
3470         return retval;
3471
3472 probe_failed:
3473         rte_free(port_name);
3474         /* free ports private data if primary process */
3475         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3476                 rte_free(eth_dev->data->dev_private);
3477                 eth_dev->data->dev_private = NULL;
3478         }
3479         rte_eth_dev_release_port(eth_dev);
3480
3481         return retval;
3482 }
3483
3484 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
3485
3486 static int
3487 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3488 {
3489         struct nfp_cpp *cpp = nsp->cpp;
3490         int fw_f;
3491         char *fw_buf;
3492         char fw_name[125];
3493         char serial[40];
3494         struct stat file_stat;
3495         off_t fsize, bytes;
3496
3497         /* Looking for firmware file in order of priority */
3498
3499         /* First try to find a firmware image specific for this device */
3500         snprintf(serial, sizeof(serial),
3501                         "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3502                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3503                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3504                 cpp->interface & 0xff);
3505
3506         snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3507                         serial);
3508
3509         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3510         fw_f = open(fw_name, O_RDONLY);
3511         if (fw_f >= 0)
3512                 goto read_fw;
3513
3514         /* Then try the PCI name */
3515         snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3516                         dev->device.name);
3517
3518         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3519         fw_f = open(fw_name, O_RDONLY);
3520         if (fw_f >= 0)
3521                 goto read_fw;
3522
3523         /* Finally try the card type and media */
3524         snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3525         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3526         fw_f = open(fw_name, O_RDONLY);
3527         if (fw_f < 0) {
3528                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3529                 return -ENOENT;
3530         }
3531
3532 read_fw:
3533         if (fstat(fw_f, &file_stat) < 0) {
3534                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3535                 close(fw_f);
3536                 return -ENOENT;
3537         }
3538
3539         fsize = file_stat.st_size;
3540         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3541                             fw_name, (uint64_t)fsize);
3542
3543         fw_buf = malloc((size_t)fsize);
3544         if (!fw_buf) {
3545                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3546                 close(fw_f);
3547                 return -ENOMEM;
3548         }
3549         memset(fw_buf, 0, fsize);
3550
3551         bytes = read(fw_f, fw_buf, fsize);
3552         if (bytes != fsize) {
3553                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3554                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3555                                    (uint64_t)bytes, (uint64_t)fsize);
3556                 free(fw_buf);
3557                 close(fw_f);
3558                 return -EIO;
3559         }
3560
3561         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3562         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3563         PMD_DRV_LOG(INFO, "Done");
3564
3565         free(fw_buf);
3566         close(fw_f);
3567
3568         return 0;
3569 }
3570
3571 static int
3572 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3573              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3574 {
3575         struct nfp_nsp *nsp;
3576         const char *nfp_fw_model;
3577         char card_desc[100];
3578         int err = 0;
3579
3580         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3581
3582         if (nfp_fw_model) {
3583                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3584         } else {
3585                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3586                 return -EIO;
3587         }
3588
3589         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3590                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3591                        nfp_eth_table->count);
3592                 return -EIO;
3593         }
3594
3595         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3596                            nfp_eth_table->count);
3597
3598         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3599
3600         snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3601                         nfp_fw_model, nfp_eth_table->count,
3602                         nfp_eth_table->ports[0].speed / 1000);
3603
3604         nsp = nfp_nsp_open(cpp);
3605         if (!nsp) {
3606                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3607                 return -EIO;
3608         }
3609
3610         nfp_nsp_device_soft_reset(nsp);
3611         err = nfp_fw_upload(dev, nsp, card_desc);
3612
3613         nfp_nsp_close(nsp);
3614         return err;
3615 }
3616
3617 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3618                             struct rte_pci_device *dev)
3619 {
3620         struct nfp_cpp *cpp;
3621         struct nfp_hwinfo *hwinfo;
3622         struct nfp_rtsym_table *sym_tbl;
3623         struct nfp_eth_table *nfp_eth_table = NULL;
3624         int total_ports;
3625         void *priv = 0;
3626         int ret = -ENODEV;
3627         int err;
3628         int i;
3629
3630         if (!dev)
3631                 return ret;
3632
3633         /*
3634          * When device bound to UIO, the device could be used, by mistake,
3635          * by two DPDK apps, and the UIO driver does not avoid it. This
3636          * could lead to a serious problem when configuring the NFP CPP
3637          * interface. Here we avoid this telling to the CPP init code to
3638          * use a lock file if UIO is being used.
3639          */
3640         if (dev->kdrv == RTE_PCI_KDRV_VFIO)
3641                 cpp = nfp_cpp_from_device_name(dev, 0);
3642         else
3643                 cpp = nfp_cpp_from_device_name(dev, 1);
3644
3645         if (!cpp) {
3646                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3647                 ret = -EIO;
3648                 goto error;
3649         }
3650
3651         hwinfo = nfp_hwinfo_read(cpp);
3652         if (!hwinfo) {
3653                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3654                 return -EIO;
3655         }
3656
3657         nfp_eth_table = nfp_eth_read_ports(cpp);
3658         if (!nfp_eth_table) {
3659                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3660                 return -EIO;
3661         }
3662
3663         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3664                 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3665                         PMD_DRV_LOG(INFO, "Error when uploading firmware");
3666                         ret = -EIO;
3667                         goto error;
3668                 }
3669         }
3670
3671         /* Now the symbol table should be there */
3672         sym_tbl = nfp_rtsym_table_read(cpp);
3673         if (!sym_tbl) {
3674                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3675                                 " symbol table");
3676                 ret = -EIO;
3677                 goto error;
3678         }
3679
3680         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3681         if (total_ports != (int)nfp_eth_table->count) {
3682                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3683                 ret = -EIO;
3684                 goto error;
3685         }
3686         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3687
3688         if (total_ports <= 0 || total_ports > 8) {
3689                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3690                 ret = -ENODEV;
3691                 goto error;
3692         }
3693
3694         for (i = 0; i < total_ports; i++) {
3695                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3696                                         nfp_eth_table->ports[i].index,
3697                                         sym_tbl, &priv);
3698                 if (ret)
3699                         break;
3700         }
3701
3702 error:
3703         free(nfp_eth_table);
3704         return ret;
3705 }
3706
3707 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3708         {
3709                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3710                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3711         },
3712         {
3713                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3714                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3715         },
3716         {
3717                 .vendor_id = 0,
3718         },
3719 };
3720
3721 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3722         {
3723                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3724                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3725         },
3726         {
3727                 .vendor_id = 0,
3728         },
3729 };
3730
3731 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3732         struct rte_pci_device *pci_dev)
3733 {
3734         return rte_eth_dev_pci_generic_probe(pci_dev,
3735                 sizeof(struct nfp_net_adapter), nfp_net_init);
3736 }
3737
3738 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3739 {
3740         struct rte_eth_dev *eth_dev;
3741         struct nfp_net_hw *hw, *hwport0;
3742         int port = 0;
3743
3744         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3745         if (eth_dev == NULL)
3746                 return 0; /* port already released */
3747         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3748             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3749                 port = get_pf_port_number(eth_dev->data->name);
3750                 /*
3751                  * hotplug is not possible with multiport PF although freeing
3752                  * data structures can be done for first port.
3753                  */
3754                 if (port != 0)
3755                         return -ENOTSUP;
3756                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3757                 hw = &hwport0[port];
3758                 nfp_cpp_area_free(hw->ctrl_area);
3759                 nfp_cpp_area_free(hw->hwqueues_area);
3760                 free(hw->hwinfo);
3761                 free(hw->sym_tbl);
3762                 nfp_cpp_free(hw->cpp);
3763         } else {
3764                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3765         }
3766         /* hotplug is not possible with multiport PF */
3767         if (hw->pf_multiport_enabled)
3768                 return -ENOTSUP;
3769         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3770 }
3771
3772 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3773         .id_table = pci_id_nfp_pf_net_map,
3774         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3775         .probe = nfp_pf_pci_probe,
3776         .remove = eth_nfp_pci_remove,
3777 };
3778
3779 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3780         .id_table = pci_id_nfp_vf_net_map,
3781         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3782         .probe = eth_nfp_pci_probe,
3783         .remove = eth_nfp_pci_remove,
3784 };
3785
3786 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3787 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3788 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3789 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3790 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3791 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3792 RTE_LOG_REGISTER(nfp_logtype_init, pmd.net.nfp.init, NOTICE);
3793 RTE_LOG_REGISTER(nfp_logtype_driver, pmd.net.nfp.driver, NOTICE);
3794 /*
3795  * Local variables:
3796  * c-file-style: "Linux"
3797  * indent-tabs-mode: t
3798  * End:
3799  */