2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
47 #include <rte_debug.h>
48 #include <rte_ethdev.h>
50 #include <rte_ether.h>
51 #include <rte_malloc.h>
52 #include <rte_memzone.h>
53 #include <rte_mempool.h>
54 #include <rte_version.h>
55 #include <rte_string_fns.h>
56 #include <rte_alarm.h>
57 #include <rte_spinlock.h>
59 #include "nfp_net_pmd.h"
60 #include "nfp_net_logs.h"
61 #include "nfp_net_ctrl.h"
64 static void nfp_net_close(struct rte_eth_dev *dev);
65 static int nfp_net_configure(struct rte_eth_dev *dev);
66 static void nfp_net_dev_interrupt_handler(void *param);
67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
70 struct rte_eth_dev_info *dev_info);
71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
80 static void nfp_net_rx_queue_release(void *rxq);
81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
82 uint16_t nb_desc, unsigned int socket_id,
83 const struct rte_eth_rxconf *rx_conf,
84 struct rte_mempool *mp);
85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
86 static void nfp_net_tx_queue_release(void *txq);
87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_txconf *tx_conf);
90 static int nfp_net_start(struct rte_eth_dev *dev);
91 static void nfp_net_stats_get(struct rte_eth_dev *dev,
92 struct rte_eth_stats *stats);
93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
94 static void nfp_net_stop(struct rte_eth_dev *dev);
95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
99 * The offset of the queue controller queues in the PCIe Target. These
100 * happen to be at the same offset on the NFP6000 and the NFP3200 so
101 * we use a single macro here.
103 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
105 /* Maximum value which can be added to a queue with one transaction */
106 #define NFP_QCP_MAX_ADD 0x7f
108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
109 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
113 NFP_QCP_READ_PTR = 0,
118 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
119 * @q: Base address for queue structure
120 * @ptr: Add to the Read or Write pointer
121 * @val: Value to add to the queue pointer
123 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
130 if (ptr == NFP_QCP_READ_PTR)
131 off = NFP_QCP_QUEUE_ADD_RPTR;
133 off = NFP_QCP_QUEUE_ADD_WPTR;
135 while (val > NFP_QCP_MAX_ADD) {
136 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
137 val -= NFP_QCP_MAX_ADD;
140 nn_writel(rte_cpu_to_le_32(val), q + off);
144 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
145 * @q: Base address for queue structure
146 * @ptr: Read or Write pointer
148 static inline uint32_t
149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
154 if (ptr == NFP_QCP_READ_PTR)
155 off = NFP_QCP_QUEUE_STS_LO;
157 off = NFP_QCP_QUEUE_STS_HI;
159 val = rte_cpu_to_le_32(nn_readl(q + off));
161 if (ptr == NFP_QCP_READ_PTR)
162 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
164 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
168 * Functions to read/write from/to Config BAR
169 * Performs any endian conversion necessary.
171 static inline uint8_t
172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
174 return nn_readb(hw->ctrl_bar + off);
178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
180 nn_writeb(val, hw->ctrl_bar + off);
183 static inline uint32_t
184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
186 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
192 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
195 static inline uint64_t
196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
198 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
204 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
208 * Atomically reads link status information from global structure rte_eth_dev.
211 * - Pointer to the structure rte_eth_dev to read from.
212 * - Pointer to the buffer to be saved with the link status.
215 * - On success, zero.
216 * - On failure, negative value.
219 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
220 struct rte_eth_link *link)
222 struct rte_eth_link *dst = link;
223 struct rte_eth_link *src = &dev->data->dev_link;
225 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
226 *(uint64_t *)src) == 0)
233 * Atomically writes the link status information into global
234 * structure rte_eth_dev.
237 * - Pointer to the structure rte_eth_dev to read from.
238 * - Pointer to the buffer to be saved with the link status.
241 * - On success, zero.
242 * - On failure, negative value.
245 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
246 struct rte_eth_link *link)
248 struct rte_eth_link *dst = &dev->data->dev_link;
249 struct rte_eth_link *src = link;
251 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
252 *(uint64_t *)src) == 0)
259 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
263 if (rxq->rxbufs == NULL)
266 for (i = 0; i < rxq->rx_count; i++) {
267 if (rxq->rxbufs[i].mbuf) {
268 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
269 rxq->rxbufs[i].mbuf = NULL;
275 nfp_net_rx_queue_release(void *rx_queue)
277 struct nfp_net_rxq *rxq = rx_queue;
280 nfp_net_rx_queue_release_mbufs(rxq);
281 rte_free(rxq->rxbufs);
287 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
289 nfp_net_rx_queue_release_mbufs(rxq);
295 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
299 if (txq->txbufs == NULL)
302 for (i = 0; i < txq->tx_count; i++) {
303 if (txq->txbufs[i].mbuf) {
304 rte_pktmbuf_free(txq->txbufs[i].mbuf);
305 txq->txbufs[i].mbuf = NULL;
311 nfp_net_tx_queue_release(void *tx_queue)
313 struct nfp_net_txq *txq = tx_queue;
316 nfp_net_tx_queue_release_mbufs(txq);
317 rte_free(txq->txbufs);
323 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
325 nfp_net_tx_queue_release_mbufs(txq);
331 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
335 struct timespec wait;
337 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
340 if (hw->qcp_cfg == NULL)
341 rte_panic("Bad configuration queue pointer\n");
343 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
346 wait.tv_nsec = 1000000;
348 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
350 /* Poll update field, waiting for NFP to ack the config */
351 for (cnt = 0; ; cnt++) {
352 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
355 if (new & NFP_NET_CFG_UPDATE_ERR) {
356 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
359 if (cnt >= NFP_NET_POLL_TIMEOUT) {
360 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
361 " %dms", update, cnt);
362 rte_panic("Exiting\n");
364 nanosleep(&wait, 0); /* waiting for a 1ms */
366 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
371 * Reconfigure the NIC
372 * @nn: device to reconfigure
373 * @ctrl: The value for the ctrl field in the BAR config
374 * @update: The value for the update field in the BAR config
376 * Write the update word to the BAR and ping the reconfig queue. Then poll
377 * until the firmware has acknowledged the update by zeroing the update word.
380 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
384 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
387 rte_spinlock_lock(&hw->reconfig_lock);
389 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
390 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
394 err = __nfp_net_reconfig(hw, update);
396 rte_spinlock_unlock(&hw->reconfig_lock);
402 * Reconfig errors imply situations where they can be handled.
403 * Otherwise, rte_panic is called inside __nfp_net_reconfig
405 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
411 * Configure an Ethernet device. This function must be invoked first
412 * before any other function in the Ethernet API. This function can
413 * also be re-invoked when a device is in the stopped state.
416 nfp_net_configure(struct rte_eth_dev *dev)
418 struct rte_eth_conf *dev_conf;
419 struct rte_eth_rxmode *rxmode;
420 struct rte_eth_txmode *txmode;
421 uint32_t new_ctrl = 0;
423 struct nfp_net_hw *hw;
425 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
428 * A DPDK app sends info about how many queues to use and how
429 * those queues need to be configured. This is used by the
430 * DPDK core and it makes sure no more queues than those
431 * advertised by the driver are requested. This function is
432 * called after that internal process
435 PMD_INIT_LOG(DEBUG, "Configure");
437 dev_conf = &dev->data->dev_conf;
438 rxmode = &dev_conf->rxmode;
439 txmode = &dev_conf->txmode;
441 /* Checking TX mode */
442 if (txmode->mq_mode) {
443 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
447 /* Checking RX mode */
448 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
449 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
450 update = NFP_NET_CFG_UPDATE_RSS;
451 new_ctrl = NFP_NET_CFG_CTRL_RSS;
453 PMD_INIT_LOG(INFO, "RSS not supported");
458 if (rxmode->split_hdr_size) {
459 PMD_INIT_LOG(INFO, "rxmode does not support split header");
463 if (rxmode->hw_ip_checksum) {
464 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
465 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
467 PMD_INIT_LOG(INFO, "RXCSUM not supported");
472 if (rxmode->hw_vlan_filter) {
473 PMD_INIT_LOG(INFO, "VLAN filter not supported");
477 if (rxmode->hw_vlan_strip) {
478 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
479 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
481 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
486 if (rxmode->hw_vlan_extend) {
487 PMD_INIT_LOG(INFO, "VLAN extended not supported");
491 /* Supporting VLAN insertion by default */
492 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
493 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
495 if (rxmode->jumbo_frame)
496 /* this is handled in rte_eth_dev_configure */
498 if (rxmode->hw_strip_crc) {
499 PMD_INIT_LOG(INFO, "strip CRC not supported");
503 if (rxmode->enable_scatter) {
504 PMD_INIT_LOG(INFO, "Scatter not supported");
511 update |= NFP_NET_CFG_UPDATE_GEN;
513 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
514 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
523 nfp_net_enable_queues(struct rte_eth_dev *dev)
525 struct nfp_net_hw *hw;
526 uint64_t enabled_queues = 0;
529 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
531 /* Enabling the required TX queues in the device */
532 for (i = 0; i < dev->data->nb_tx_queues; i++)
533 enabled_queues |= (1 << i);
535 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
539 /* Enabling the required RX queues in the device */
540 for (i = 0; i < dev->data->nb_rx_queues; i++)
541 enabled_queues |= (1 << i);
543 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
547 nfp_net_disable_queues(struct rte_eth_dev *dev)
549 struct nfp_net_hw *hw;
550 uint32_t new_ctrl, update = 0;
552 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
554 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
555 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
557 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
558 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
559 NFP_NET_CFG_UPDATE_MSIX;
561 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
562 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
564 /* If an error when reconfig we avoid to change hw state */
565 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
572 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
576 for (i = 0; i < dev->data->nb_rx_queues; i++) {
577 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
584 nfp_net_params_setup(struct nfp_net_hw *hw)
586 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
587 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
591 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
593 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
596 static void nfp_net_read_mac(struct nfp_net_hw *hw)
600 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
601 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
603 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
604 memcpy(&hw->mac_addr[4], &tmp, 2);
608 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
609 struct rte_intr_handle *intr_handle)
611 struct nfp_net_hw *hw;
614 if (!intr_handle->intr_vec) {
615 intr_handle->intr_vec =
616 rte_zmalloc("intr_vec",
617 dev->data->nb_rx_queues * sizeof(int), 0);
618 if (!intr_handle->intr_vec) {
619 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
620 " intr_vec", dev->data->nb_rx_queues);
625 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
627 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
628 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
629 /* UIO just supports one queue and no LSC*/
630 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
632 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
633 for (i = 0; i < dev->data->nb_rx_queues; i++)
635 * The first msix vector is reserved for non
638 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
641 /* Avoiding TX interrupts */
642 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
647 nfp_net_start(struct rte_eth_dev *dev)
649 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
650 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
651 uint32_t new_ctrl, update = 0;
652 struct nfp_net_hw *hw;
653 uint32_t intr_vector;
656 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
658 PMD_INIT_LOG(DEBUG, "Start");
660 /* Disabling queues just in case... */
661 nfp_net_disable_queues(dev);
663 /* Writing configuration parameters in the device */
664 nfp_net_params_setup(hw);
666 /* Enabling the required queues in the device */
667 nfp_net_enable_queues(dev);
669 /* check and configure queue intr-vector mapping */
670 if (dev->data->dev_conf.intr_conf.rxq != 0) {
671 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
673 * Better not to share LSC with RX interrupts.
674 * Unregistering LSC interrupt handler
676 rte_intr_callback_unregister(&pci_dev->intr_handle,
677 nfp_net_dev_interrupt_handler, (void *)dev);
679 if (dev->data->nb_rx_queues > 1) {
680 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
681 "supports 1 queue with UIO");
685 intr_vector = dev->data->nb_rx_queues;
686 if (rte_intr_efd_enable(intr_handle, intr_vector))
690 if (rte_intr_dp_is_en(intr_handle))
691 nfp_configure_rx_interrupt(dev, intr_handle);
693 rte_intr_enable(intr_handle);
696 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
697 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
699 /* Just configuring queues interrupts when necessary */
700 if (rte_intr_dp_is_en(intr_handle))
701 update |= NFP_NET_CFG_UPDATE_MSIX;
703 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
704 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
706 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
707 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
711 * Allocating rte mbuffs for configured rx queues.
712 * This requires queues being enabled before
714 if (nfp_net_rx_freelist_setup(dev) < 0) {
725 * An error returned by this function should mean the app
726 * exiting and then the system releasing all the memory
727 * allocated even memory coming from hugepages.
729 * The device could be enabled at this point with some queues
730 * ready for getting packets. This is true if the call to
731 * nfp_net_rx_freelist_setup() succeeds for some queues but
732 * fails for subsequent queues.
734 * This should make the app exiting but better if we tell the
737 nfp_net_disable_queues(dev);
742 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
744 nfp_net_stop(struct rte_eth_dev *dev)
748 PMD_INIT_LOG(DEBUG, "Stop");
750 nfp_net_disable_queues(dev);
753 for (i = 0; i < dev->data->nb_tx_queues; i++) {
754 nfp_net_reset_tx_queue(
755 (struct nfp_net_txq *)dev->data->tx_queues[i]);
758 for (i = 0; i < dev->data->nb_rx_queues; i++) {
759 nfp_net_reset_rx_queue(
760 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
764 /* Reset and stop device. The device can not be restarted. */
766 nfp_net_close(struct rte_eth_dev *dev)
768 struct nfp_net_hw *hw;
769 struct rte_pci_device *pci_dev;
771 PMD_INIT_LOG(DEBUG, "Close");
773 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
774 pci_dev = RTE_DEV_TO_PCI(dev->device);
777 * We assume that the DPDK application is stopping all the
778 * threads/queues before calling the device close function.
783 rte_intr_disable(&pci_dev->intr_handle);
784 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
786 /* unregister callback func from eal lib */
787 rte_intr_callback_unregister(&pci_dev->intr_handle,
788 nfp_net_dev_interrupt_handler,
792 * The ixgbe PMD driver disables the pcie master on the
793 * device. The i40e does not...
798 nfp_net_promisc_enable(struct rte_eth_dev *dev)
800 uint32_t new_ctrl, update = 0;
801 struct nfp_net_hw *hw;
803 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
805 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
807 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
808 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
812 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
813 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
817 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
818 update = NFP_NET_CFG_UPDATE_GEN;
821 * DPDK sets promiscuous mode on just after this call assuming
822 * it can not fail ...
824 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
831 nfp_net_promisc_disable(struct rte_eth_dev *dev)
833 uint32_t new_ctrl, update = 0;
834 struct nfp_net_hw *hw;
836 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
838 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
839 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
843 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
844 update = NFP_NET_CFG_UPDATE_GEN;
847 * DPDK sets promiscuous mode off just before this call
848 * assuming it can not fail ...
850 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
857 * return 0 means link status changed, -1 means not changed
859 * Wait to complete is needed as it can take up to 9 seconds to get the Link
863 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
865 struct nfp_net_hw *hw;
866 struct rte_eth_link link, old;
867 uint32_t nn_link_status;
869 static const uint32_t ls_to_ethtool[] = {
870 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
871 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
872 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
873 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
874 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
875 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
876 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
877 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
880 PMD_DRV_LOG(DEBUG, "Link update\n");
882 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
884 memset(&old, 0, sizeof(old));
885 nfp_net_dev_atomic_read_link_status(dev, &old);
887 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
889 memset(&link, 0, sizeof(struct rte_eth_link));
891 if (nn_link_status & NFP_NET_CFG_STS_LINK)
892 link.link_status = ETH_LINK_UP;
894 link.link_duplex = ETH_LINK_FULL_DUPLEX;
896 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
897 NFP_NET_CFG_STS_LINK_RATE_MASK;
899 if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
900 ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
901 (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
902 /* We really do not know the speed wil old firmware */
903 link.link_speed = ETH_SPEED_NUM_NONE;
905 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
906 link.link_speed = ETH_SPEED_NUM_NONE;
908 link.link_speed = ls_to_ethtool[nn_link_status];
911 if (old.link_status != link.link_status) {
912 nfp_net_dev_atomic_write_link_status(dev, &link);
913 if (link.link_status)
914 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
916 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
924 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
927 struct nfp_net_hw *hw;
928 struct rte_eth_stats nfp_dev_stats;
930 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
932 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
934 /* reading per RX ring stats */
935 for (i = 0; i < dev->data->nb_rx_queues; i++) {
936 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
939 nfp_dev_stats.q_ipackets[i] =
940 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
942 nfp_dev_stats.q_ipackets[i] -=
943 hw->eth_stats_base.q_ipackets[i];
945 nfp_dev_stats.q_ibytes[i] =
946 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
948 nfp_dev_stats.q_ibytes[i] -=
949 hw->eth_stats_base.q_ibytes[i];
952 /* reading per TX ring stats */
953 for (i = 0; i < dev->data->nb_tx_queues; i++) {
954 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
957 nfp_dev_stats.q_opackets[i] =
958 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
960 nfp_dev_stats.q_opackets[i] -=
961 hw->eth_stats_base.q_opackets[i];
963 nfp_dev_stats.q_obytes[i] =
964 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
966 nfp_dev_stats.q_obytes[i] -=
967 hw->eth_stats_base.q_obytes[i];
970 nfp_dev_stats.ipackets =
971 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
973 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
975 nfp_dev_stats.ibytes =
976 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
978 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
980 nfp_dev_stats.opackets =
981 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
983 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
985 nfp_dev_stats.obytes =
986 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
988 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
990 /* reading general device stats */
991 nfp_dev_stats.ierrors =
992 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
994 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
996 nfp_dev_stats.oerrors =
997 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
999 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1001 /* RX ring mbuf allocation failures */
1002 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1004 nfp_dev_stats.imissed =
1005 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1007 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1010 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1014 nfp_net_stats_reset(struct rte_eth_dev *dev)
1017 struct nfp_net_hw *hw;
1019 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022 * hw->eth_stats_base records the per counter starting point.
1023 * Lets update it now
1026 /* reading per RX ring stats */
1027 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1028 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1031 hw->eth_stats_base.q_ipackets[i] =
1032 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1034 hw->eth_stats_base.q_ibytes[i] =
1035 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1038 /* reading per TX ring stats */
1039 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1040 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1043 hw->eth_stats_base.q_opackets[i] =
1044 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1046 hw->eth_stats_base.q_obytes[i] =
1047 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1050 hw->eth_stats_base.ipackets =
1051 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1053 hw->eth_stats_base.ibytes =
1054 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1056 hw->eth_stats_base.opackets =
1057 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1059 hw->eth_stats_base.obytes =
1060 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1062 /* reading general device stats */
1063 hw->eth_stats_base.ierrors =
1064 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1066 hw->eth_stats_base.oerrors =
1067 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1069 /* RX ring mbuf allocation failures */
1070 dev->data->rx_mbuf_alloc_failed = 0;
1072 hw->eth_stats_base.imissed =
1073 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1077 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1079 struct nfp_net_hw *hw;
1081 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1083 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1084 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1085 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1086 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1087 dev_info->max_rx_pktlen = hw->mtu;
1088 /* Next should change when PF support is implemented */
1089 dev_info->max_mac_addrs = 1;
1091 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1092 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1094 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1095 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1096 DEV_RX_OFFLOAD_UDP_CKSUM |
1097 DEV_RX_OFFLOAD_TCP_CKSUM;
1099 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1100 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1102 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1103 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1104 DEV_TX_OFFLOAD_UDP_CKSUM |
1105 DEV_TX_OFFLOAD_TCP_CKSUM;
1107 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1109 .pthresh = DEFAULT_RX_PTHRESH,
1110 .hthresh = DEFAULT_RX_HTHRESH,
1111 .wthresh = DEFAULT_RX_WTHRESH,
1113 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1117 dev_info->default_txconf = (struct rte_eth_txconf) {
1119 .pthresh = DEFAULT_TX_PTHRESH,
1120 .hthresh = DEFAULT_TX_HTHRESH,
1121 .wthresh = DEFAULT_TX_WTHRESH,
1123 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1124 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1125 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1126 ETH_TXQ_FLAGS_NOOFFLOADS,
1129 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1130 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1132 dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1133 ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1134 ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1136 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1137 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1140 static const uint32_t *
1141 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1143 static const uint32_t ptypes[] = {
1144 /* refers to nfp_net_set_hash() */
1145 RTE_PTYPE_INNER_L3_IPV4,
1146 RTE_PTYPE_INNER_L3_IPV6,
1147 RTE_PTYPE_INNER_L3_IPV6_EXT,
1148 RTE_PTYPE_INNER_L4_MASK,
1152 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1158 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1160 struct nfp_net_rxq *rxq;
1161 struct nfp_net_rx_desc *rxds;
1165 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1172 * Other PMDs are just checking the DD bit in intervals of 4
1173 * descriptors and counting all four if the first has the DD
1174 * bit on. Of course, this is not accurate but can be good for
1175 * perfomance. But ideally that should be done in descriptors
1176 * chunks belonging to the same cache line
1179 while (count < rxq->rx_count) {
1180 rxds = &rxq->rxds[idx];
1181 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1188 if ((idx) == rxq->rx_count)
1196 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1198 struct rte_pci_device *pci_dev;
1199 struct nfp_net_hw *hw;
1202 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1203 pci_dev = RTE_DEV_TO_PCI(dev->device);
1205 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1208 /* Make sure all updates are written before un-masking */
1210 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1211 NFP_NET_CFG_ICR_UNMASKED);
1216 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1218 struct rte_pci_device *pci_dev;
1219 struct nfp_net_hw *hw;
1222 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1223 pci_dev = RTE_DEV_TO_PCI(dev->device);
1225 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1228 /* Make sure all updates are written before un-masking */
1230 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1235 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1237 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1238 struct rte_eth_link link;
1240 memset(&link, 0, sizeof(link));
1241 nfp_net_dev_atomic_read_link_status(dev, &link);
1242 if (link.link_status)
1243 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1244 (int)(dev->data->port_id), (unsigned)link.link_speed,
1245 link.link_duplex == ETH_LINK_FULL_DUPLEX
1246 ? "full-duplex" : "half-duplex");
1248 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1249 (int)(dev->data->port_id));
1251 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1252 pci_dev->addr.domain, pci_dev->addr.bus,
1253 pci_dev->addr.devid, pci_dev->addr.function);
1256 /* Interrupt configuration and handling */
1259 * nfp_net_irq_unmask - Unmask an interrupt
1261 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1262 * clear the ICR for the entry.
1265 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1267 struct nfp_net_hw *hw;
1268 struct rte_pci_device *pci_dev;
1270 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271 pci_dev = RTE_DEV_TO_PCI(dev->device);
1273 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1274 /* If MSI-X auto-masking is used, clear the entry */
1276 rte_intr_enable(&pci_dev->intr_handle);
1278 /* Make sure all updates are written before un-masking */
1280 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1281 NFP_NET_CFG_ICR_UNMASKED);
1286 nfp_net_dev_interrupt_handler(void *param)
1289 struct rte_eth_link link;
1290 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1292 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1294 /* get the link status */
1295 memset(&link, 0, sizeof(link));
1296 nfp_net_dev_atomic_read_link_status(dev, &link);
1298 nfp_net_link_update(dev, 0);
1301 if (!link.link_status) {
1302 /* handle it 1 sec later, wait it being stable */
1303 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1304 /* likely to down */
1306 /* handle it 4 sec later, wait it being stable */
1307 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1310 if (rte_eal_alarm_set(timeout * 1000,
1311 nfp_net_dev_interrupt_delayed_handler,
1313 RTE_LOG(ERR, PMD, "Error setting alarm");
1315 nfp_net_irq_unmask(dev);
1320 * Interrupt handler which shall be registered for alarm callback for delayed
1321 * handling specific interrupt to wait for the stable nic state. As the NIC
1322 * interrupt state is not stable for nfp after link is just down, it needs
1323 * to wait 4 seconds to get the stable status.
1325 * @param handle Pointer to interrupt handle.
1326 * @param param The address of parameter (struct rte_eth_dev *)
1331 nfp_net_dev_interrupt_delayed_handler(void *param)
1333 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1335 nfp_net_link_update(dev, 0);
1336 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1338 nfp_net_dev_link_status_print(dev);
1341 nfp_net_irq_unmask(dev);
1345 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1347 struct nfp_net_hw *hw;
1349 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351 /* check that mtu is within the allowed range */
1352 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1355 /* switch to jumbo mode if needed */
1356 if ((uint32_t)mtu > ETHER_MAX_LEN)
1357 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1359 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1361 /* update max frame size */
1362 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1364 /* writing to configuration space */
1365 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1373 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1374 uint16_t queue_idx, uint16_t nb_desc,
1375 unsigned int socket_id,
1376 const struct rte_eth_rxconf *rx_conf,
1377 struct rte_mempool *mp)
1379 const struct rte_memzone *tz;
1380 struct nfp_net_rxq *rxq;
1381 struct nfp_net_hw *hw;
1383 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1385 PMD_INIT_FUNC_TRACE();
1387 /* Validating number of descriptors */
1388 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1389 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1390 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1391 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1396 * Free memory prior to re-allocation if needed. This is the case after
1397 * calling nfp_net_stop
1399 if (dev->data->rx_queues[queue_idx]) {
1400 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1401 dev->data->rx_queues[queue_idx] = NULL;
1404 /* Allocating rx queue data structure */
1405 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1406 RTE_CACHE_LINE_SIZE, socket_id);
1410 /* Hw queues mapping based on firmware confifguration */
1411 rxq->qidx = queue_idx;
1412 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1413 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1414 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1415 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1418 * Tracking mbuf size for detecting a potential mbuf overflow due to
1422 rxq->mbuf_size = rxq->mem_pool->elt_size;
1423 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1424 hw->flbufsz = rxq->mbuf_size;
1426 rxq->rx_count = nb_desc;
1427 rxq->port_id = dev->data->port_id;
1428 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1429 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1431 rxq->drop_en = rx_conf->rx_drop_en;
1434 * Allocate RX ring hardware descriptors. A memzone large enough to
1435 * handle the maximum ring size is allocated in order to allow for
1436 * resizing in later calls to the queue setup function.
1438 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1439 sizeof(struct nfp_net_rx_desc) *
1440 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1444 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1445 nfp_net_rx_queue_release(rxq);
1449 /* Saving physical and virtual addresses for the RX ring */
1450 rxq->dma = (uint64_t)tz->phys_addr;
1451 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1453 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1454 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1455 sizeof(*rxq->rxbufs) * nb_desc,
1456 RTE_CACHE_LINE_SIZE, socket_id);
1457 if (rxq->rxbufs == NULL) {
1458 nfp_net_rx_queue_release(rxq);
1462 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1463 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1465 nfp_net_reset_rx_queue(rxq);
1467 dev->data->rx_queues[queue_idx] = rxq;
1471 * Telling the HW about the physical address of the RX ring and number
1472 * of descriptors in log2 format
1474 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1475 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1481 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1483 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1487 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1490 for (i = 0; i < rxq->rx_count; i++) {
1491 struct nfp_net_rx_desc *rxd;
1492 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1495 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1496 (unsigned)rxq->qidx);
1500 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1502 rxd = &rxq->rxds[i];
1504 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1505 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1507 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1510 /* Make sure all writes are flushed before telling the hardware */
1513 /* Not advertising the whole ring as the firmware gets confused if so */
1514 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1517 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1523 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1524 uint16_t nb_desc, unsigned int socket_id,
1525 const struct rte_eth_txconf *tx_conf)
1527 const struct rte_memzone *tz;
1528 struct nfp_net_txq *txq;
1529 uint16_t tx_free_thresh;
1530 struct nfp_net_hw *hw;
1532 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1534 PMD_INIT_FUNC_TRACE();
1536 /* Validating number of descriptors */
1537 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1538 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1539 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1540 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1544 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1545 tx_conf->tx_free_thresh :
1546 DEFAULT_TX_FREE_THRESH);
1548 if (tx_free_thresh > (nb_desc)) {
1550 "tx_free_thresh must be less than the number of TX "
1551 "descriptors. (tx_free_thresh=%u port=%d "
1552 "queue=%d)\n", (unsigned int)tx_free_thresh,
1553 (int)dev->data->port_id, (int)queue_idx);
1558 * Free memory prior to re-allocation if needed. This is the case after
1559 * calling nfp_net_stop
1561 if (dev->data->tx_queues[queue_idx]) {
1562 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1564 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1565 dev->data->tx_queues[queue_idx] = NULL;
1568 /* Allocating tx queue data structure */
1569 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1570 RTE_CACHE_LINE_SIZE, socket_id);
1572 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1577 * Allocate TX ring hardware descriptors. A memzone large enough to
1578 * handle the maximum ring size is allocated in order to allow for
1579 * resizing in later calls to the queue setup function.
1581 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1582 sizeof(struct nfp_net_tx_desc) *
1583 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1586 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1587 nfp_net_tx_queue_release(txq);
1591 txq->tx_count = nb_desc;
1592 txq->tx_free_thresh = tx_free_thresh;
1593 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1594 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1595 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1597 /* queue mapping based on firmware configuration */
1598 txq->qidx = queue_idx;
1599 txq->tx_qcidx = queue_idx * hw->stride_tx;
1600 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1602 txq->port_id = dev->data->port_id;
1603 txq->txq_flags = tx_conf->txq_flags;
1605 /* Saving physical and virtual addresses for the TX ring */
1606 txq->dma = (uint64_t)tz->phys_addr;
1607 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1609 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1610 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1611 sizeof(*txq->txbufs) * nb_desc,
1612 RTE_CACHE_LINE_SIZE, socket_id);
1613 if (txq->txbufs == NULL) {
1614 nfp_net_tx_queue_release(txq);
1617 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1618 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1620 nfp_net_reset_tx_queue(txq);
1622 dev->data->tx_queues[queue_idx] = txq;
1626 * Telling the HW about the physical address of the TX ring and number
1627 * of descriptors in log2 format
1629 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1630 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1635 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1637 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1638 struct rte_mbuf *mb)
1641 struct nfp_net_hw *hw = txq->hw;
1643 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1646 ol_flags = mb->ol_flags;
1648 if (!(ol_flags & PKT_TX_TCP_SEG))
1651 txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1652 txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1653 txd->flags = PCIE_DESC_TX_LSO;
1662 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1664 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1665 struct rte_mbuf *mb)
1668 struct nfp_net_hw *hw = txq->hw;
1670 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1673 ol_flags = mb->ol_flags;
1675 /* IPv6 does not need checksum */
1676 if (ol_flags & PKT_TX_IP_CKSUM)
1677 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1679 switch (ol_flags & PKT_TX_L4_MASK) {
1680 case PKT_TX_UDP_CKSUM:
1681 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1683 case PKT_TX_TCP_CKSUM:
1684 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1688 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1689 txd->flags |= PCIE_DESC_TX_CSUM;
1692 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1694 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1695 struct rte_mbuf *mb)
1697 struct nfp_net_hw *hw = rxq->hw;
1699 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1702 /* If IPv4 and IP checksum error, fail */
1703 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1704 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1705 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1707 /* If neither UDP nor TCP return */
1708 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1709 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1712 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1713 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1714 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1716 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1717 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1718 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1721 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1722 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1725 * nfp_net_set_hash - Set mbuf hash data
1727 * The RSS hash and hash-type are pre-pended to the packet data.
1728 * Extract and decode it and set the mbuf fields.
1731 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1732 struct rte_mbuf *mbuf)
1736 struct nfp_net_hw *hw = rxq->hw;
1738 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1741 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1744 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1745 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1747 mbuf->hash.rss = hash;
1748 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1750 switch (hash_type) {
1751 case NFP_NET_RSS_IPV4:
1752 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1754 case NFP_NET_RSS_IPV6:
1755 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1757 case NFP_NET_RSS_IPV6_EX:
1758 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1761 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1766 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1768 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1771 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1776 * There are some decissions to take:
1777 * 1) How to check DD RX descriptors bit
1778 * 2) How and when to allocate new mbufs
1780 * Current implementation checks just one single DD bit each loop. As each
1781 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1782 * a single cache line instead. Tests with this change have not shown any
1783 * performance improvement but it requires further investigation. For example,
1784 * depending on which descriptor is next, the number of descriptors could be
1785 * less than 8 for just checking those in the same cache line. This implies
1786 * extra work which could be counterproductive by itself. Indeed, last firmware
1787 * changes are just doing this: writing several descriptors with the DD bit
1788 * for saving PCIe bandwidth and DMA operations from the NFP.
1790 * Mbuf allocation is done when a new packet is received. Then the descriptor
1791 * is automatically linked with the new mbuf and the old one is given to the
1792 * user. The main drawback with this design is mbuf allocation is heavier than
1793 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1794 * cache point of view it does not seem allocating the mbuf early on as we are
1795 * doing now have any benefit at all. Again, tests with this change have not
1796 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1797 * so looking at the implications of this type of allocation should be studied
1802 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1804 struct nfp_net_rxq *rxq;
1805 struct nfp_net_rx_desc *rxds;
1806 struct nfp_net_rx_buff *rxb;
1807 struct nfp_net_hw *hw;
1808 struct rte_mbuf *mb;
1809 struct rte_mbuf *new_mb;
1815 if (unlikely(rxq == NULL)) {
1817 * DPDK just checks the queue is lower than max queues
1818 * enabled. But the queue needs to be configured
1820 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1828 while (avail < nb_pkts) {
1829 rxb = &rxq->rxbufs[rxq->rd_p];
1830 if (unlikely(rxb == NULL)) {
1831 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1836 * Memory barrier to ensure that we won't do other
1837 * reads before the DD bit.
1841 rxds = &rxq->rxds[rxq->rd_p];
1842 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1846 * We got a packet. Let's alloc a new mbuff for refilling the
1847 * free descriptor ring as soon as possible
1849 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1850 if (unlikely(new_mb == NULL)) {
1851 RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1852 "queue_id=%u\n", (unsigned)rxq->port_id,
1853 (unsigned)rxq->qidx);
1854 nfp_net_mbuf_alloc_failed(rxq);
1861 * Grab the mbuff and refill the descriptor with the
1862 * previously allocated mbuff
1867 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1868 rxds->rxd.data_len, rxq->mbuf_size);
1870 /* Size of this segment */
1871 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1872 /* Size of the whole packet. We just support 1 segment */
1873 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1875 if (unlikely((mb->data_len + hw->rx_offset) >
1878 * This should not happen and the user has the
1879 * responsibility of avoiding it. But we have
1880 * to give some info about the error
1882 RTE_LOG_DP(ERR, PMD,
1883 "mbuf overflow likely due to the RX offset.\n"
1884 "\t\tYour mbuf size should have extra space for"
1885 " RX offset=%u bytes.\n"
1886 "\t\tCurrently you just have %u bytes available"
1887 " but the received packet is %u bytes long",
1889 rxq->mbuf_size - hw->rx_offset,
1894 /* Filling the received mbuff with packet info */
1896 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1898 mb->data_off = RTE_PKTMBUF_HEADROOM +
1899 NFP_DESC_META_LEN(rxds);
1901 /* No scatter mode supported */
1905 /* Checking the RSS flag */
1906 nfp_net_set_hash(rxq, rxds, mb);
1908 /* Checking the checksum flag */
1909 nfp_net_rx_cksum(rxq, rxds, mb);
1911 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1912 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1913 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1914 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1917 /* Adding the mbuff to the mbuff array passed by the app */
1918 rx_pkts[avail++] = mb;
1920 /* Now resetting and updating the descriptor */
1923 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1925 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1926 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1929 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
1936 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1937 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1939 nb_hold += rxq->nb_rx_hold;
1942 * FL descriptors needs to be written before incrementing the
1943 * FL queue WR pointer
1946 if (nb_hold > rxq->rx_free_thresh) {
1947 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1948 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1949 (unsigned)nb_hold, (unsigned)avail);
1950 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1953 rxq->nb_rx_hold = nb_hold;
1959 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1961 * @txq: TX queue to work with
1962 * Returns number of descriptors freed
1965 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1970 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1971 " status\n", txq->qidx);
1973 /* Work out how many packets have been sent */
1974 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1976 if (qcp_rd_p == txq->rd_p) {
1977 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1978 "packets (%u, %u)\n", txq->qidx,
1979 qcp_rd_p, txq->rd_p);
1983 if (qcp_rd_p > txq->rd_p)
1984 todo = qcp_rd_p - txq->rd_p;
1986 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
1988 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
1989 qcp_rd_p, txq->rd_p, txq->rd_p);
1995 if (unlikely(txq->rd_p >= txq->tx_count))
1996 txq->rd_p -= txq->tx_count;
2001 /* Leaving always free descriptors for avoiding wrapping confusion */
2003 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2005 if (txq->wr_p >= txq->rd_p)
2006 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2008 return txq->rd_p - txq->wr_p - 8;
2012 * nfp_net_txq_full - Check if the TX queue free descriptors
2013 * is below tx_free_threshold
2015 * @txq: TX queue to check
2017 * This function uses the host copy* of read/write pointers
2020 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2022 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2026 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2028 struct nfp_net_txq *txq;
2029 struct nfp_net_hw *hw;
2030 struct nfp_net_tx_desc *txds, txd;
2031 struct rte_mbuf *pkt;
2033 int pkt_size, dma_size;
2034 uint16_t free_descs, issued_descs;
2035 struct rte_mbuf **lmbuf;
2040 txds = &txq->txds[txq->wr_p];
2042 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2043 txq->qidx, txq->wr_p, nb_pkts);
2045 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2046 nfp_net_tx_free_bufs(txq);
2048 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2049 if (unlikely(free_descs == 0))
2056 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2057 txq->qidx, nb_pkts);
2058 /* Sending packets */
2059 while ((i < nb_pkts) && free_descs) {
2060 /* Grabbing the mbuf linked to the current descriptor */
2061 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2062 /* Warming the cache for releasing the mbuf later on */
2063 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2065 pkt = *(tx_pkts + i);
2067 if (unlikely((pkt->nb_segs > 1) &&
2068 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2069 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2070 rte_panic("Multisegment packet unsupported\n");
2073 /* Checking if we have enough descriptors */
2074 if (unlikely(pkt->nb_segs > free_descs))
2078 * Checksum and VLAN flags just in the first descriptor for a
2079 * multisegment packet, but TSO info needs to be in all of them.
2081 txd.data_len = pkt->pkt_len;
2082 nfp_net_tx_tso(txq, &txd, pkt);
2083 nfp_net_tx_cksum(txq, &txd, pkt);
2085 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2086 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2087 txd.flags |= PCIE_DESC_TX_VLAN;
2088 txd.vlan = pkt->vlan_tci;
2092 * mbuf data_len is the data in one segment and pkt_len data
2093 * in the whole packet. When the packet is just one segment,
2094 * then data_len = pkt_len
2096 pkt_size = pkt->pkt_len;
2098 /* Releasing mbuf which was prefetched above */
2100 rte_pktmbuf_free(*lmbuf);
2102 * Linking mbuf with descriptor for being released
2103 * next time descriptor is used
2108 /* Copying TSO, VLAN and cksum info */
2110 dma_size = pkt->data_len;
2111 dma_addr = rte_mbuf_data_dma_addr(pkt);
2112 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2113 "%" PRIx64 "\n", dma_addr);
2115 /* Filling descriptors fields */
2116 txds->dma_len = dma_size;
2117 txds->data_len = txd.data_len;
2118 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2119 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2120 ASSERT(free_descs > 0);
2124 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2127 pkt_size -= dma_size;
2130 txds->offset_eop |= PCIE_DESC_TX_EOP;
2132 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2135 /* Referencing next free TX descriptor */
2136 txds = &txq->txds[txq->wr_p];
2143 /* Increment write pointers. Force memory write before we let HW know */
2145 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2151 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2153 uint32_t new_ctrl, update;
2154 struct nfp_net_hw *hw;
2156 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2159 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2160 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2161 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2162 " ETH_VLAN_EXTEND_OFFLOAD");
2164 /* Enable vlan strip if it is not configured yet */
2165 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2166 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2167 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2169 /* Disable vlan strip just if it is configured */
2170 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2171 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2172 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2177 update = NFP_NET_CFG_UPDATE_GEN;
2179 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2182 hw->ctrl = new_ctrl;
2185 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2187 nfp_net_reta_update(struct rte_eth_dev *dev,
2188 struct rte_eth_rss_reta_entry64 *reta_conf,
2191 uint32_t reta, mask;
2195 struct nfp_net_hw *hw =
2196 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2201 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2202 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2203 "(%d) doesn't match the number hardware can supported "
2204 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2209 * Update Redirection Table. There are 128 8bit-entries which can be
2210 * manage as 32 32bit-entries
2212 for (i = 0; i < reta_size; i += 4) {
2213 /* Handling 4 RSS entries per loop */
2214 idx = i / RTE_RETA_GROUP_SIZE;
2215 shift = i % RTE_RETA_GROUP_SIZE;
2216 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2222 /* If all 4 entries were set, don't need read RETA register */
2224 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2226 for (j = 0; j < 4; j++) {
2227 if (!(mask & (0x1 << j)))
2230 /* Clearing the entry bits */
2231 reta &= ~(0xFF << (8 * j));
2232 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2234 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2237 update = NFP_NET_CFG_UPDATE_RSS;
2239 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2245 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2247 nfp_net_reta_query(struct rte_eth_dev *dev,
2248 struct rte_eth_rss_reta_entry64 *reta_conf,
2254 struct nfp_net_hw *hw;
2256 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2258 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2261 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2262 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2263 "(%d) doesn't match the number hardware can supported "
2264 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2269 * Reading Redirection Table. There are 128 8bit-entries which can be
2270 * manage as 32 32bit-entries
2272 for (i = 0; i < reta_size; i += 4) {
2273 /* Handling 4 RSS entries per loop */
2274 idx = i / RTE_RETA_GROUP_SIZE;
2275 shift = i % RTE_RETA_GROUP_SIZE;
2276 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2281 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2282 for (j = 0; j < 4; j++) {
2283 if (!(mask & (0x1 << j)))
2285 reta_conf->reta[shift + j] =
2286 (uint8_t)((reta >> (8 * j)) & 0xF);
2293 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2294 struct rte_eth_rss_conf *rss_conf)
2297 uint32_t cfg_rss_ctrl = 0;
2301 struct nfp_net_hw *hw;
2303 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2305 rss_hf = rss_conf->rss_hf;
2307 /* Checking if RSS is enabled */
2308 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2309 if (rss_hf != 0) { /* Enable RSS? */
2310 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2313 return 0; /* Nothing to do */
2316 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2317 RTE_LOG(ERR, PMD, "hash key too long\n");
2321 if (rss_hf & ETH_RSS_IPV4)
2322 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2323 NFP_NET_CFG_RSS_IPV4_TCP |
2324 NFP_NET_CFG_RSS_IPV4_UDP;
2326 if (rss_hf & ETH_RSS_IPV6)
2327 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2328 NFP_NET_CFG_RSS_IPV6_TCP |
2329 NFP_NET_CFG_RSS_IPV6_UDP;
2331 /* configuring where to apply the RSS hash */
2332 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2334 /* Writing the key byte a byte */
2335 for (i = 0; i < rss_conf->rss_key_len; i++) {
2336 memcpy(&key, &rss_conf->rss_key[i], 1);
2337 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2340 /* Writing the key size */
2341 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2343 update = NFP_NET_CFG_UPDATE_RSS;
2345 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2352 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2353 struct rte_eth_rss_conf *rss_conf)
2356 uint32_t cfg_rss_ctrl;
2359 struct nfp_net_hw *hw;
2361 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2363 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2366 rss_hf = rss_conf->rss_hf;
2367 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2369 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2370 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2372 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2373 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2375 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2376 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2378 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2379 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2381 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2382 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2384 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2385 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2387 /* Reading the key size */
2388 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2390 /* Reading the key byte a byte */
2391 for (i = 0; i < rss_conf->rss_key_len; i++) {
2392 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2393 memcpy(&rss_conf->rss_key[i], &key, 1);
2399 /* Initialise and register driver with DPDK Application */
2400 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2401 .dev_configure = nfp_net_configure,
2402 .dev_start = nfp_net_start,
2403 .dev_stop = nfp_net_stop,
2404 .dev_close = nfp_net_close,
2405 .promiscuous_enable = nfp_net_promisc_enable,
2406 .promiscuous_disable = nfp_net_promisc_disable,
2407 .link_update = nfp_net_link_update,
2408 .stats_get = nfp_net_stats_get,
2409 .stats_reset = nfp_net_stats_reset,
2410 .dev_infos_get = nfp_net_infos_get,
2411 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2412 .mtu_set = nfp_net_dev_mtu_set,
2413 .vlan_offload_set = nfp_net_vlan_offload_set,
2414 .reta_update = nfp_net_reta_update,
2415 .reta_query = nfp_net_reta_query,
2416 .rss_hash_update = nfp_net_rss_hash_update,
2417 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2418 .rx_queue_setup = nfp_net_rx_queue_setup,
2419 .rx_queue_release = nfp_net_rx_queue_release,
2420 .rx_queue_count = nfp_net_rx_queue_count,
2421 .tx_queue_setup = nfp_net_tx_queue_setup,
2422 .tx_queue_release = nfp_net_tx_queue_release,
2423 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2424 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2428 nfp_net_init(struct rte_eth_dev *eth_dev)
2430 struct rte_pci_device *pci_dev;
2431 struct nfp_net_hw *hw;
2433 uint32_t tx_bar_off, rx_bar_off;
2437 PMD_INIT_FUNC_TRACE();
2439 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2441 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2442 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2443 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2445 /* For secondary processes, the primary has done all the work */
2446 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2449 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2450 rte_eth_copy_pci_info(eth_dev, pci_dev);
2451 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2453 hw->device_id = pci_dev->id.device_id;
2454 hw->vendor_id = pci_dev->id.vendor_id;
2455 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2456 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2458 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2459 pci_dev->id.vendor_id, pci_dev->id.device_id,
2460 pci_dev->addr.domain, pci_dev->addr.bus,
2461 pci_dev->addr.devid, pci_dev->addr.function);
2463 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2464 if (hw->ctrl_bar == NULL) {
2466 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2469 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2470 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2472 /* Work out where in the BAR the queues start. */
2473 switch (pci_dev->id.device_id) {
2474 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2475 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2476 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2477 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2478 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2481 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2485 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x", tx_bar_off);
2486 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x", rx_bar_off);
2488 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2489 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2491 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2492 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2494 nfp_net_cfg_queue_setup(hw);
2496 /* Get some of the read-only fields from the config BAR */
2497 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2498 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2499 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2500 hw->mtu = hw->max_mtu;
2502 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2503 hw->rx_offset = NFP_NET_RX_OFFSET;
2505 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2507 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2508 hw->ver, hw->max_mtu);
2509 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
2510 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2511 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2512 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2513 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2514 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2515 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2516 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2517 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2518 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2522 hw->stride_rx = stride;
2523 hw->stride_tx = stride;
2525 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2526 hw->max_rx_queues, hw->max_tx_queues);
2528 /* Initializing spinlock for reconfigs */
2529 rte_spinlock_init(&hw->reconfig_lock);
2531 /* Allocating memory for mac addr */
2532 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2533 if (eth_dev->data->mac_addrs == NULL) {
2534 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2538 nfp_net_read_mac(hw);
2540 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr))
2541 /* Using random mac addresses for VFs */
2542 eth_random_addr(&hw->mac_addr[0]);
2544 /* Copying mac address to DPDK eth_dev struct */
2545 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2546 ð_dev->data->mac_addrs[0]);
2548 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2549 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2550 eth_dev->data->port_id, pci_dev->id.vendor_id,
2551 pci_dev->id.device_id,
2552 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2553 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2555 /* Registering LSC interrupt handler */
2556 rte_intr_callback_register(&pci_dev->intr_handle,
2557 nfp_net_dev_interrupt_handler,
2560 /* Telling the firmware about the LSC interrupt entry */
2561 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2563 /* Recording current stats counters values */
2564 nfp_net_stats_reset(eth_dev);
2569 static const struct rte_pci_id pci_id_nfp_net_map[] = {
2571 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2572 PCI_DEVICE_ID_NFP6000_PF_NIC)
2575 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2576 PCI_DEVICE_ID_NFP6000_VF_NIC)
2583 static struct eth_driver rte_nfp_net_pmd = {
2585 .id_table = pci_id_nfp_net_map,
2586 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2587 .probe = rte_eth_dev_pci_probe,
2588 .remove = rte_eth_dev_pci_remove,
2590 .eth_dev_init = nfp_net_init,
2591 .dev_private_size = sizeof(struct nfp_net_adapter),
2594 RTE_PMD_REGISTER_PCI(net_nfp, rte_nfp_net_pmd.pci_drv);
2595 RTE_PMD_REGISTER_PCI_TABLE(net_nfp, pci_id_nfp_net_map);
2596 RTE_PMD_REGISTER_KMOD_DEP(net_nfp, "* igb_uio | uio_pci_generic | vfio");
2600 * c-file-style: "Linux"
2601 * indent-tabs-mode: t