drivers/net/nfp/nfp_net.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  */
   7
   8 /*
   9  * vim:shiftwidth=8:noexpandtab
  10  *
  11  * @file dpdk/pmd/nfp_net.c
  12  *
  13  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  14  */
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_log.h>
  19 #include <rte_debug.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_dev.h>
  23 #include <rte_ether.h>
  24 #include <rte_malloc.h>
  25 #include <rte_memzone.h>
  26 #include <rte_mempool.h>
  27 #include <rte_version.h>
  28 #include <rte_string_fns.h>
  29 #include <rte_alarm.h>
  30 #include <rte_spinlock.h>
  31 #include <rte_service_component.h>
  32
  33 #include "nfpcore/nfp_cpp.h"
  34 #include "nfpcore/nfp_nffw.h"
  35 #include "nfpcore/nfp_hwinfo.h"
  36 #include "nfpcore/nfp_mip.h"
  37 #include "nfpcore/nfp_rtsym.h"
  38 #include "nfpcore/nfp_nsp.h"
  39
  40 #include "nfp_net_pmd.h"
  41 #include "nfp_net_logs.h"
  42 #include "nfp_net_ctrl.h"
  43
  44 #include <sys/types.h>
  45 #include <sys/socket.h>
  46 #include <sys/un.h>
  47 #include <unistd.h>
  48 #include <stdio.h>
  49 #include <sys/ioctl.h>
  50 #include <errno.h>
  51
  52 /* Prototypes */
  53 static void nfp_net_close(struct rte_eth_dev *dev);
  54 static int nfp_net_configure(struct rte_eth_dev *dev);
  55 static void nfp_net_dev_interrupt_handler(void *param);
  56 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  57 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  58 static int nfp_net_infos_get(struct rte_eth_dev *dev,
  59                              struct rte_eth_dev_info *dev_info);
  60 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  61 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  62 static int nfp_net_promisc_enable(struct rte_eth_dev *dev);
  63 static int nfp_net_promisc_disable(struct rte_eth_dev *dev);
  64 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  65 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  66                                        uint16_t queue_idx);
  67 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  68                                   uint16_t nb_pkts);
  69 static void nfp_net_rx_queue_release(void *rxq);
  70 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  71                                   uint16_t nb_desc, unsigned int socket_id,
  72                                   const struct rte_eth_rxconf *rx_conf,
  73                                   struct rte_mempool *mp);
  74 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  75 static void nfp_net_tx_queue_release(void *txq);
  76 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  77                                   uint16_t nb_desc, unsigned int socket_id,
  78                                   const struct rte_eth_txconf *tx_conf);
  79 static int nfp_net_start(struct rte_eth_dev *dev);
  80 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  81                               struct rte_eth_stats *stats);
  82 static int nfp_net_stats_reset(struct rte_eth_dev *dev);
  83 static void nfp_net_stop(struct rte_eth_dev *dev);
  84 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  85                                   uint16_t nb_pkts);
  86
  87 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
  88 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
  89                                    struct rte_eth_rss_conf *rss_conf);
  90 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
  91                     struct rte_eth_rss_reta_entry64 *reta_conf,
  92                     uint16_t reta_size);
  93 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
  94                         struct rte_eth_rss_conf *rss_conf);
  95 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
  96                              struct rte_ether_addr *mac_addr);
  97
  98 /* The offset of the queue controller queues in the PCIe Target */
  99 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 100
 101 /* Maximum value which can be added to a queue with one transaction */
 102 #define NFP_QCP_MAX_ADD 0x7f
 103
 104 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 105         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 106
 107 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 108 enum nfp_qcp_ptr {
 109         NFP_QCP_READ_PTR = 0,
 110         NFP_QCP_WRITE_PTR
 111 };
 112
 113 /*
 114  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 115  * @q: Base address for queue structure
 116  * @ptr: Add to the Read or Write pointer
 117  * @val: Value to add to the queue pointer
 118  *
 119  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 120  */
 121 static inline void
 122 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 123 {
 124         uint32_t off;
 125
 126         if (ptr == NFP_QCP_READ_PTR)
 127                 off = NFP_QCP_QUEUE_ADD_RPTR;
 128         else
 129                 off = NFP_QCP_QUEUE_ADD_WPTR;
 130
 131         while (val > NFP_QCP_MAX_ADD) {
 132                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 133                 val -= NFP_QCP_MAX_ADD;
 134         }
 135
 136         nn_writel(rte_cpu_to_le_32(val), q + off);
 137 }
 138
 139 /*
 140  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 141  * @q:  Base address for queue structure
 142  * @ptr: Read or Write pointer
 143  */
 144 static inline uint32_t
 145 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 146 {
 147         uint32_t off;
 148         uint32_t val;
 149
 150         if (ptr == NFP_QCP_READ_PTR)
 151                 off = NFP_QCP_QUEUE_STS_LO;
 152         else
 153                 off = NFP_QCP_QUEUE_STS_HI;
 154
 155         val = rte_cpu_to_le_32(nn_readl(q + off));
 156
 157         if (ptr == NFP_QCP_READ_PTR)
 158                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 159         else
 160                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 161 }
 162
 163 /*
 164  * Functions to read/write from/to Config BAR
 165  * Performs any endian conversion necessary.
 166  */
 167 static inline uint8_t
 168 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 169 {
 170         return nn_readb(hw->ctrl_bar + off);
 171 }
 172
 173 static inline void
 174 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 175 {
 176         nn_writeb(val, hw->ctrl_bar + off);
 177 }
 178
 179 static inline uint32_t
 180 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 181 {
 182         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 183 }
 184
 185 static inline void
 186 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 187 {
 188         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 189 }
 190
 191 static inline uint64_t
 192 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 193 {
 194         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 195 }
 196
 197 static inline void
 198 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 199 {
 200         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 201 }
 202
 203 static void
 204 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 205 {
 206         unsigned i;
 207
 208         if (rxq->rxbufs == NULL)
 209                 return;
 210
 211         for (i = 0; i < rxq->rx_count; i++) {
 212                 if (rxq->rxbufs[i].mbuf) {
 213                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 214                         rxq->rxbufs[i].mbuf = NULL;
 215                 }
 216         }
 217 }
 218
 219 static void
 220 nfp_net_rx_queue_release(void *rx_queue)
 221 {
 222         struct nfp_net_rxq *rxq = rx_queue;
 223
 224         if (rxq) {
 225                 nfp_net_rx_queue_release_mbufs(rxq);
 226                 rte_free(rxq->rxbufs);
 227                 rte_free(rxq);
 228         }
 229 }
 230
 231 static void
 232 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 233 {
 234         nfp_net_rx_queue_release_mbufs(rxq);
 235         rxq->rd_p = 0;
 236         rxq->nb_rx_hold = 0;
 237 }
 238
 239 static void
 240 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 241 {
 242         unsigned i;
 243
 244         if (txq->txbufs == NULL)
 245                 return;
 246
 247         for (i = 0; i < txq->tx_count; i++) {
 248                 if (txq->txbufs[i].mbuf) {
 249                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 250                         txq->txbufs[i].mbuf = NULL;
 251                 }
 252         }
 253 }
 254
 255 static void
 256 nfp_net_tx_queue_release(void *tx_queue)
 257 {
 258         struct nfp_net_txq *txq = tx_queue;
 259
 260         if (txq) {
 261                 nfp_net_tx_queue_release_mbufs(txq);
 262                 rte_free(txq->txbufs);
 263                 rte_free(txq);
 264         }
 265 }
 266
 267 static void
 268 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 269 {
 270         nfp_net_tx_queue_release_mbufs(txq);
 271         txq->wr_p = 0;
 272         txq->rd_p = 0;
 273 }
 274
 275 static int
 276 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 277 {
 278         int cnt;
 279         uint32_t new;
 280         struct timespec wait;
 281
 282         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 283                     hw->qcp_cfg);
 284
 285         if (hw->qcp_cfg == NULL)
 286                 rte_panic("Bad configuration queue pointer\n");
 287
 288         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 289
 290         wait.tv_sec = 0;
 291         wait.tv_nsec = 1000000;
 292
 293         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 294
 295         /* Poll update field, waiting for NFP to ack the config */
 296         for (cnt = 0; ; cnt++) {
 297                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 298                 if (new == 0)
 299                         break;
 300                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 301                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 302                         return -1;
 303                 }
 304                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 305                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 306                                           " %dms", update, cnt);
 307                         rte_panic("Exiting\n");
 308                 }
 309                 nanosleep(&wait, 0); /* waiting for a 1ms */
 310         }
 311         PMD_DRV_LOG(DEBUG, "Ack DONE");
 312         return 0;
 313 }
 314
 315 /*
 316  * Reconfigure the NIC
 317  * @nn:    device to reconfigure
 318  * @ctrl:    The value for the ctrl field in the BAR config
 319  * @update:  The value for the update field in the BAR config
 320  *
 321  * Write the update word to the BAR and ping the reconfig queue. Then poll
 322  * until the firmware has acknowledged the update by zeroing the update word.
 323  */
 324 static int
 325 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 326 {
 327         uint32_t err;
 328
 329         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 330                     ctrl, update);
 331
 332         rte_spinlock_lock(&hw->reconfig_lock);
 333
 334         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 335         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 336
 337         rte_wmb();
 338
 339         err = __nfp_net_reconfig(hw, update);
 340
 341         rte_spinlock_unlock(&hw->reconfig_lock);
 342
 343         if (!err)
 344                 return 0;
 345
 346         /*
 347          * Reconfig errors imply situations where they can be handled.
 348          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 349          */
 350         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 351                      ctrl, update);
 352         return -EIO;
 353 }
 354
 355 /*
 356  * Configure an Ethernet device. This function must be invoked first
 357  * before any other function in the Ethernet API. This function can
 358  * also be re-invoked when a device is in the stopped state.
 359  */
 360 static int
 361 nfp_net_configure(struct rte_eth_dev *dev)
 362 {
 363         struct rte_eth_conf *dev_conf;
 364         struct rte_eth_rxmode *rxmode;
 365         struct rte_eth_txmode *txmode;
 366         struct nfp_net_hw *hw;
 367
 368         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 369
 370         /*
 371          * A DPDK app sends info about how many queues to use and how
 372          * those queues need to be configured. This is used by the
 373          * DPDK core and it makes sure no more queues than those
 374          * advertised by the driver are requested. This function is
 375          * called after that internal process
 376          */
 377
 378         PMD_INIT_LOG(DEBUG, "Configure");
 379
 380         dev_conf = &dev->data->dev_conf;
 381         rxmode = &dev_conf->rxmode;
 382         txmode = &dev_conf->txmode;
 383
 384         if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
 385                 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 386
 387         /* Checking TX mode */
 388         if (txmode->mq_mode) {
 389                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 390                 return -EINVAL;
 391         }
 392
 393         /* Checking RX mode */
 394         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 395             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 396                 PMD_INIT_LOG(INFO, "RSS not supported");
 397                 return -EINVAL;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static void
 404 nfp_net_enable_queues(struct rte_eth_dev *dev)
 405 {
 406         struct nfp_net_hw *hw;
 407         uint64_t enabled_queues = 0;
 408         int i;
 409
 410         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 411
 412         /* Enabling the required TX queues in the device */
 413         for (i = 0; i < dev->data->nb_tx_queues; i++)
 414                 enabled_queues |= (1 << i);
 415
 416         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 417
 418         enabled_queues = 0;
 419
 420         /* Enabling the required RX queues in the device */
 421         for (i = 0; i < dev->data->nb_rx_queues; i++)
 422                 enabled_queues |= (1 << i);
 423
 424         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 425 }
 426
 427 static void
 428 nfp_net_disable_queues(struct rte_eth_dev *dev)
 429 {
 430         struct nfp_net_hw *hw;
 431         uint32_t new_ctrl, update = 0;
 432
 433         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 434
 435         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 436         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 437
 438         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 439         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 440                  NFP_NET_CFG_UPDATE_MSIX;
 441
 442         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 443                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 444
 445         /* If an error when reconfig we avoid to change hw state */
 446         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 447                 return;
 448
 449         hw->ctrl = new_ctrl;
 450 }
 451
 452 static int
 453 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 454 {
 455         int i;
 456
 457         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 458                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 459                         return -1;
 460         }
 461         return 0;
 462 }
 463
 464 static void
 465 nfp_net_params_setup(struct nfp_net_hw *hw)
 466 {
 467         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 468         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 469 }
 470
 471 static void
 472 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 473 {
 474         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 475 }
 476
 477 #define ETH_ADDR_LEN    6
 478
 479 static void
 480 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 481 {
 482         int i;
 483
 484         for (i = 0; i < ETH_ADDR_LEN; i++)
 485                 dst[i] = src[i];
 486 }
 487
 488 static int
 489 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 490 {
 491         struct nfp_eth_table *nfp_eth_table;
 492
 493         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 494         /*
 495          * hw points to port0 private data. We need hw now pointing to
 496          * right port.
 497          */
 498         hw += port;
 499         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 500                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 501
 502         free(nfp_eth_table);
 503         return 0;
 504 }
 505
 506 static void
 507 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 508 {
 509         uint32_t tmp;
 510
 511         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 512         memcpy(&hw->mac_addr[0], &tmp, 4);
 513
 514         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 515         memcpy(&hw->mac_addr[4], &tmp, 2);
 516 }
 517
 518 static void
 519 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 520 {
 521         uint32_t mac0 = *(uint32_t *)mac;
 522         uint16_t mac1;
 523
 524         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 525
 526         mac += 4;
 527         mac1 = *(uint16_t *)mac;
 528         nn_writew(rte_cpu_to_be_16(mac1),
 529                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 530 }
 531
 532 int
 533 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
 534 {
 535         struct nfp_net_hw *hw;
 536         uint32_t update, ctrl;
 537
 538         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 539         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 540             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 541                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 542                                   " port enabled");
 543                 return -EBUSY;
 544         }
 545
 546         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 547             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 548                 return -EBUSY;
 549
 550         /* Writing new MAC to the specific port BAR address */
 551         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 552
 553         /* Signal the NIC about the change */
 554         update = NFP_NET_CFG_UPDATE_MACADDR;
 555         ctrl = hw->ctrl;
 556         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 557             (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 558                 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
 559         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 560                 PMD_INIT_LOG(INFO, "MAC address update failed");
 561                 return -EIO;
 562         }
 563         return 0;
 564 }
 565
 566 static int
 567 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 568                            struct rte_intr_handle *intr_handle)
 569 {
 570         struct nfp_net_hw *hw;
 571         int i;
 572
 573         if (!intr_handle->intr_vec) {
 574                 intr_handle->intr_vec =
 575                         rte_zmalloc("intr_vec",
 576                                     dev->data->nb_rx_queues * sizeof(int), 0);
 577                 if (!intr_handle->intr_vec) {
 578                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 579                                      " intr_vec", dev->data->nb_rx_queues);
 580                         return -ENOMEM;
 581                 }
 582         }
 583
 584         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 585
 586         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 587                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 588                 /* UIO just supports one queue and no LSC*/
 589                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 590                 intr_handle->intr_vec[0] = 0;
 591         } else {
 592                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 593                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 594                         /*
 595                          * The first msix vector is reserved for non
 596                          * efd interrupts
 597                         */
 598                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 599                         intr_handle->intr_vec[i] = i + 1;
 600                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 601                                             intr_handle->intr_vec[i]);
 602                 }
 603         }
 604
 605         /* Avoiding TX interrupts */
 606         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 607         return 0;
 608 }
 609
 610 static uint32_t
 611 nfp_check_offloads(struct rte_eth_dev *dev)
 612 {
 613         struct nfp_net_hw *hw;
 614         struct rte_eth_conf *dev_conf;
 615         struct rte_eth_rxmode *rxmode;
 616         struct rte_eth_txmode *txmode;
 617         uint32_t ctrl = 0;
 618
 619         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 620
 621         dev_conf = &dev->data->dev_conf;
 622         rxmode = &dev_conf->rxmode;
 623         txmode = &dev_conf->txmode;
 624
 625         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 626                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 627                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 628         }
 629
 630         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 631                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 632                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 633         }
 634
 635         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 636                 hw->mtu = rxmode->max_rx_pkt_len;
 637
 638         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 639                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 640
 641         /* L2 broadcast */
 642         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 643                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 644
 645         /* L2 multicast */
 646         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 647                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 648
 649         /* TX checksum offload */
 650         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 651             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 652             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 653                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 654
 655         /* LSO offload */
 656         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 657                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 658                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 659                 else
 660                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 661         }
 662
 663         /* RX gather */
 664         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 665                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 666
 667         return ctrl;
 668 }
 669
 670 static int
 671 nfp_net_start(struct rte_eth_dev *dev)
 672 {
 673         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 674         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 675         uint32_t new_ctrl, update = 0;
 676         struct nfp_net_hw *hw;
 677         struct rte_eth_conf *dev_conf;
 678         struct rte_eth_rxmode *rxmode;
 679         uint32_t intr_vector;
 680         int ret;
 681
 682         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 683
 684         PMD_INIT_LOG(DEBUG, "Start");
 685
 686         /* Disabling queues just in case... */
 687         nfp_net_disable_queues(dev);
 688
 689         /* Enabling the required queues in the device */
 690         nfp_net_enable_queues(dev);
 691
 692         /* check and configure queue intr-vector mapping */
 693         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 694                 if (hw->pf_multiport_enabled) {
 695                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 696                                           "with NFP multiport PF");
 697                                 return -EINVAL;
 698                 }
 699                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 700                         /*
 701                          * Better not to share LSC with RX interrupts.
 702                          * Unregistering LSC interrupt handler
 703                          */
 704                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 705                                 nfp_net_dev_interrupt_handler, (void *)dev);
 706
 707                         if (dev->data->nb_rx_queues > 1) {
 708                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 709                                              "supports 1 queue with UIO");
 710                                 return -EIO;
 711                         }
 712                 }
 713                 intr_vector = dev->data->nb_rx_queues;
 714                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 715                         return -1;
 716
 717                 nfp_configure_rx_interrupt(dev, intr_handle);
 718                 update = NFP_NET_CFG_UPDATE_MSIX;
 719         }
 720
 721         rte_intr_enable(intr_handle);
 722
 723         new_ctrl = nfp_check_offloads(dev);
 724
 725         /* Writing configuration parameters in the device */
 726         nfp_net_params_setup(hw);
 727
 728         dev_conf = &dev->data->dev_conf;
 729         rxmode = &dev_conf->rxmode;
 730
 731         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 732                 nfp_net_rss_config_default(dev);
 733                 update |= NFP_NET_CFG_UPDATE_RSS;
 734                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 735         }
 736
 737         /* Enable device */
 738         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 739
 740         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 741
 742         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 743                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 744
 745         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 746         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 747                 return -EIO;
 748
 749         /*
 750          * Allocating rte mbufs for configured rx queues.
 751          * This requires queues being enabled before
 752          */
 753         if (nfp_net_rx_freelist_setup(dev) < 0) {
 754                 ret = -ENOMEM;
 755                 goto error;
 756         }
 757
 758         if (hw->is_pf) {
 759                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 760                         /* Configure the physical port up */
 761                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 762                 else
 763                         nfp_eth_set_configured(dev->process_private,
 764                                                hw->pf_port_idx, 1);
 765         }
 766
 767         hw->ctrl = new_ctrl;
 768
 769         return 0;
 770
 771 error:
 772         /*
 773          * An error returned by this function should mean the app
 774          * exiting and then the system releasing all the memory
 775          * allocated even memory coming from hugepages.
 776          *
 777          * The device could be enabled at this point with some queues
 778          * ready for getting packets. This is true if the call to
 779          * nfp_net_rx_freelist_setup() succeeds for some queues but
 780          * fails for subsequent queues.
 781          *
 782          * This should make the app exiting but better if we tell the
 783          * device first.
 784          */
 785         nfp_net_disable_queues(dev);
 786
 787         return ret;
 788 }
 789
 790 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 791 static void
 792 nfp_net_stop(struct rte_eth_dev *dev)
 793 {
 794         int i;
 795         struct nfp_net_hw *hw;
 796
 797         PMD_INIT_LOG(DEBUG, "Stop");
 798
 799         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 800
 801         nfp_net_disable_queues(dev);
 802
 803         /* Clear queues */
 804         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 805                 nfp_net_reset_tx_queue(
 806                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 807         }
 808
 809         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 810                 nfp_net_reset_rx_queue(
 811                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 812         }
 813
 814         if (hw->is_pf) {
 815                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 816                         /* Configure the physical port down */
 817                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 818                 else
 819                         nfp_eth_set_configured(dev->process_private,
 820                                                hw->pf_port_idx, 0);
 821         }
 822 }
 823
 824 /* Set the link up. */
 825 static int
 826 nfp_net_set_link_up(struct rte_eth_dev *dev)
 827 {
 828         struct nfp_net_hw *hw;
 829
 830         PMD_DRV_LOG(DEBUG, "Set link up");
 831
 832         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 833
 834         if (!hw->is_pf)
 835                 return -ENOTSUP;
 836
 837         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 838                 /* Configure the physical port down */
 839                 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 840         else
 841                 return nfp_eth_set_configured(dev->process_private,
 842                                               hw->pf_port_idx, 1);
 843 }
 844
 845 /* Set the link down. */
 846 static int
 847 nfp_net_set_link_down(struct rte_eth_dev *dev)
 848 {
 849         struct nfp_net_hw *hw;
 850
 851         PMD_DRV_LOG(DEBUG, "Set link down");
 852
 853         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854
 855         if (!hw->is_pf)
 856                 return -ENOTSUP;
 857
 858         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 859                 /* Configure the physical port down */
 860                 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 861         else
 862                 return nfp_eth_set_configured(dev->process_private,
 863                                               hw->pf_port_idx, 0);
 864 }
 865
 866 /* Reset and stop device. The device can not be restarted. */
 867 static void
 868 nfp_net_close(struct rte_eth_dev *dev)
 869 {
 870         struct nfp_net_hw *hw;
 871         struct rte_pci_device *pci_dev;
 872         int i;
 873
 874         PMD_INIT_LOG(DEBUG, "Close");
 875
 876         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 877         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 878
 879         /*
 880          * We assume that the DPDK application is stopping all the
 881          * threads/queues before calling the device close function.
 882          */
 883
 884         nfp_net_disable_queues(dev);
 885
 886         /* Clear queues */
 887         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 888                 nfp_net_reset_tx_queue(
 889                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 890         }
 891
 892         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 893                 nfp_net_reset_rx_queue(
 894                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 895         }
 896
 897         rte_intr_disable(&pci_dev->intr_handle);
 898         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 899
 900         /* unregister callback func from eal lib */
 901         rte_intr_callback_unregister(&pci_dev->intr_handle,
 902                                      nfp_net_dev_interrupt_handler,
 903                                      (void *)dev);
 904
 905         /*
 906          * The ixgbe PMD driver disables the pcie master on the
 907          * device. The i40e does not...
 908          */
 909 }
 910
 911 static int
 912 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 913 {
 914         uint32_t new_ctrl, update = 0;
 915         struct nfp_net_hw *hw;
 916         int ret;
 917
 918         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 919
 920         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 921
 922         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 923                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 924                 return -ENOTSUP;
 925         }
 926
 927         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 928                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 929                 return 0;
 930         }
 931
 932         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 933         update = NFP_NET_CFG_UPDATE_GEN;
 934
 935         /*
 936          * DPDK sets promiscuous mode on just after this call assuming
 937          * it can not fail ...
 938          */
 939         ret = nfp_net_reconfig(hw, new_ctrl, update);
 940         if (ret < 0)
 941                 return ret;
 942
 943         hw->ctrl = new_ctrl;
 944
 945         return 0;
 946 }
 947
 948 static int
 949 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 950 {
 951         uint32_t new_ctrl, update = 0;
 952         struct nfp_net_hw *hw;
 953         int ret;
 954
 955         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 956
 957         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 958                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 959                 return 0;
 960         }
 961
 962         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 963         update = NFP_NET_CFG_UPDATE_GEN;
 964
 965         /*
 966          * DPDK sets promiscuous mode off just before this call
 967          * assuming it can not fail ...
 968          */
 969         ret = nfp_net_reconfig(hw, new_ctrl, update);
 970         if (ret < 0)
 971                 return ret;
 972
 973         hw->ctrl = new_ctrl;
 974
 975         return 0;
 976 }
 977
 978 /*
 979  * return 0 means link status changed, -1 means not changed
 980  *
 981  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 982  * status.
 983  */
 984 static int
 985 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 986 {
 987         struct nfp_net_hw *hw;
 988         struct rte_eth_link link;
 989         uint32_t nn_link_status;
 990         int ret;
 991
 992         static const uint32_t ls_to_ethtool[] = {
 993                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 994                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 995                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 996                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 997                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 998                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 999                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
1000                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
1001         };
1002
1003         PMD_DRV_LOG(DEBUG, "Link update");
1004
1005         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006
1007         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1008
1009         memset(&link, 0, sizeof(struct rte_eth_link));
1010
1011         if (nn_link_status & NFP_NET_CFG_STS_LINK)
1012                 link.link_status = ETH_LINK_UP;
1013
1014         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1015
1016         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1017                          NFP_NET_CFG_STS_LINK_RATE_MASK;
1018
1019         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1020                 link.link_speed = ETH_SPEED_NUM_NONE;
1021         else
1022                 link.link_speed = ls_to_ethtool[nn_link_status];
1023
1024         ret = rte_eth_linkstatus_set(dev, &link);
1025         if (ret == 0) {
1026                 if (link.link_status)
1027                         PMD_DRV_LOG(INFO, "NIC Link is Up");
1028                 else
1029                         PMD_DRV_LOG(INFO, "NIC Link is Down");
1030         }
1031         return ret;
1032 }
1033
1034 static int
1035 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1036 {
1037         int i;
1038         struct nfp_net_hw *hw;
1039         struct rte_eth_stats nfp_dev_stats;
1040
1041         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1042
1043         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1044
1045         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1046
1047         /* reading per RX ring stats */
1048         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1049                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1050                         break;
1051
1052                 nfp_dev_stats.q_ipackets[i] =
1053                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1054
1055                 nfp_dev_stats.q_ipackets[i] -=
1056                         hw->eth_stats_base.q_ipackets[i];
1057
1058                 nfp_dev_stats.q_ibytes[i] =
1059                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1060
1061                 nfp_dev_stats.q_ibytes[i] -=
1062                         hw->eth_stats_base.q_ibytes[i];
1063         }
1064
1065         /* reading per TX ring stats */
1066         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1067                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1068                         break;
1069
1070                 nfp_dev_stats.q_opackets[i] =
1071                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1072
1073                 nfp_dev_stats.q_opackets[i] -=
1074                         hw->eth_stats_base.q_opackets[i];
1075
1076                 nfp_dev_stats.q_obytes[i] =
1077                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1078
1079                 nfp_dev_stats.q_obytes[i] -=
1080                         hw->eth_stats_base.q_obytes[i];
1081         }
1082
1083         nfp_dev_stats.ipackets =
1084                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1085
1086         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1087
1088         nfp_dev_stats.ibytes =
1089                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1090
1091         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1092
1093         nfp_dev_stats.opackets =
1094                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1095
1096         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1097
1098         nfp_dev_stats.obytes =
1099                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1100
1101         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1102
1103         /* reading general device stats */
1104         nfp_dev_stats.ierrors =
1105                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1106
1107         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1108
1109         nfp_dev_stats.oerrors =
1110                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1111
1112         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1113
1114         /* RX ring mbuf allocation failures */
1115         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1116
1117         nfp_dev_stats.imissed =
1118                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1119
1120         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1121
1122         if (stats) {
1123                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1124                 return 0;
1125         }
1126         return -EINVAL;
1127 }
1128
1129 static int
1130 nfp_net_stats_reset(struct rte_eth_dev *dev)
1131 {
1132         int i;
1133         struct nfp_net_hw *hw;
1134
1135         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1136
1137         /*
1138          * hw->eth_stats_base records the per counter starting point.
1139          * Lets update it now
1140          */
1141
1142         /* reading per RX ring stats */
1143         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1144                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1145                         break;
1146
1147                 hw->eth_stats_base.q_ipackets[i] =
1148                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1149
1150                 hw->eth_stats_base.q_ibytes[i] =
1151                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1152         }
1153
1154         /* reading per TX ring stats */
1155         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1156                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1157                         break;
1158
1159                 hw->eth_stats_base.q_opackets[i] =
1160                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1161
1162                 hw->eth_stats_base.q_obytes[i] =
1163                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1164         }
1165
1166         hw->eth_stats_base.ipackets =
1167                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1168
1169         hw->eth_stats_base.ibytes =
1170                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1171
1172         hw->eth_stats_base.opackets =
1173                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1174
1175         hw->eth_stats_base.obytes =
1176                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1177
1178         /* reading general device stats */
1179         hw->eth_stats_base.ierrors =
1180                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1181
1182         hw->eth_stats_base.oerrors =
1183                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1184
1185         /* RX ring mbuf allocation failures */
1186         dev->data->rx_mbuf_alloc_failed = 0;
1187
1188         hw->eth_stats_base.imissed =
1189                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1190
1191         return 0;
1192 }
1193
1194 static int
1195 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1196 {
1197         struct nfp_net_hw *hw;
1198
1199         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1200
1201         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1202         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1203         dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1204         dev_info->max_rx_pktlen = hw->max_mtu;
1205         /* Next should change when PF support is implemented */
1206         dev_info->max_mac_addrs = 1;
1207
1208         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1209                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1210
1211         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1212                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1213                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1214                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1215
1216         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME |
1217                                      DEV_RX_OFFLOAD_RSS_HASH;
1218
1219         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1220                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1221
1222         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1223                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1224                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1225                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1226
1227         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1228                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1229
1230         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1231                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1232
1233         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1234                 .rx_thresh = {
1235                         .pthresh = DEFAULT_RX_PTHRESH,
1236                         .hthresh = DEFAULT_RX_HTHRESH,
1237                         .wthresh = DEFAULT_RX_WTHRESH,
1238                 },
1239                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1240                 .rx_drop_en = 0,
1241         };
1242
1243         dev_info->default_txconf = (struct rte_eth_txconf) {
1244                 .tx_thresh = {
1245                         .pthresh = DEFAULT_TX_PTHRESH,
1246                         .hthresh = DEFAULT_TX_HTHRESH,
1247                         .wthresh = DEFAULT_TX_WTHRESH,
1248                 },
1249                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1250                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1251         };
1252
1253         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1254                 .nb_max = NFP_NET_MAX_RX_DESC,
1255                 .nb_min = NFP_NET_MIN_RX_DESC,
1256                 .nb_align = NFP_ALIGN_RING_DESC,
1257         };
1258
1259         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1260                 .nb_max = NFP_NET_MAX_TX_DESC,
1261                 .nb_min = NFP_NET_MIN_TX_DESC,
1262                 .nb_align = NFP_ALIGN_RING_DESC,
1263                 .nb_seg_max = NFP_TX_MAX_SEG,
1264                 .nb_mtu_seg_max = NFP_TX_MAX_MTU_SEG,
1265         };
1266
1267         dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1268                                            ETH_RSS_NONFRAG_IPV4_TCP |
1269                                            ETH_RSS_NONFRAG_IPV4_UDP |
1270                                            ETH_RSS_IPV6 |
1271                                            ETH_RSS_NONFRAG_IPV6_TCP |
1272                                            ETH_RSS_NONFRAG_IPV6_UDP;
1273
1274         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1275         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1276
1277         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1278                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1279                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1280
1281         return 0;
1282 }
1283
1284 static const uint32_t *
1285 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1286 {
1287         static const uint32_t ptypes[] = {
1288                 /* refers to nfp_net_set_hash() */
1289                 RTE_PTYPE_INNER_L3_IPV4,
1290                 RTE_PTYPE_INNER_L3_IPV6,
1291                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1292                 RTE_PTYPE_INNER_L4_MASK,
1293                 RTE_PTYPE_UNKNOWN
1294         };
1295
1296         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1297                 return ptypes;
1298         return NULL;
1299 }
1300
1301 static uint32_t
1302 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1303 {
1304         struct nfp_net_rxq *rxq;
1305         struct nfp_net_rx_desc *rxds;
1306         uint32_t idx;
1307         uint32_t count;
1308
1309         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1310
1311         idx = rxq->rd_p;
1312
1313         count = 0;
1314
1315         /*
1316          * Other PMDs are just checking the DD bit in intervals of 4
1317          * descriptors and counting all four if the first has the DD
1318          * bit on. Of course, this is not accurate but can be good for
1319          * performance. But ideally that should be done in descriptors
1320          * chunks belonging to the same cache line
1321          */
1322
1323         while (count < rxq->rx_count) {
1324                 rxds = &rxq->rxds[idx];
1325                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1326                         break;
1327
1328                 count++;
1329                 idx++;
1330
1331                 /* Wrapping? */
1332                 if ((idx) == rxq->rx_count)
1333                         idx = 0;
1334         }
1335
1336         return count;
1337 }
1338
1339 static int
1340 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1341 {
1342         struct rte_pci_device *pci_dev;
1343         struct nfp_net_hw *hw;
1344         int base = 0;
1345
1346         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1348
1349         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1350                 base = 1;
1351
1352         /* Make sure all updates are written before un-masking */
1353         rte_wmb();
1354         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1355                       NFP_NET_CFG_ICR_UNMASKED);
1356         return 0;
1357 }
1358
1359 static int
1360 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1361 {
1362         struct rte_pci_device *pci_dev;
1363         struct nfp_net_hw *hw;
1364         int base = 0;
1365
1366         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1367         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1368
1369         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1370                 base = 1;
1371
1372         /* Make sure all updates are written before un-masking */
1373         rte_wmb();
1374         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1375         return 0;
1376 }
1377
1378 static void
1379 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1380 {
1381         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1382         struct rte_eth_link link;
1383
1384         rte_eth_linkstatus_get(dev, &link);
1385         if (link.link_status)
1386                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1387                             dev->data->port_id, link.link_speed,
1388                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1389                             ? "full-duplex" : "half-duplex");
1390         else
1391                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1392                             dev->data->port_id);
1393
1394         PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
1395                     pci_dev->addr.domain, pci_dev->addr.bus,
1396                     pci_dev->addr.devid, pci_dev->addr.function);
1397 }
1398
1399 /* Interrupt configuration and handling */
1400
1401 /*
1402  * nfp_net_irq_unmask - Unmask an interrupt
1403  *
1404  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1405  * clear the ICR for the entry.
1406  */
1407 static void
1408 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1409 {
1410         struct nfp_net_hw *hw;
1411         struct rte_pci_device *pci_dev;
1412
1413         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1415
1416         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1417                 /* If MSI-X auto-masking is used, clear the entry */
1418                 rte_wmb();
1419                 rte_intr_ack(&pci_dev->intr_handle);
1420         } else {
1421                 /* Make sure all updates are written before un-masking */
1422                 rte_wmb();
1423                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1424                               NFP_NET_CFG_ICR_UNMASKED);
1425         }
1426 }
1427
1428 static void
1429 nfp_net_dev_interrupt_handler(void *param)
1430 {
1431         int64_t timeout;
1432         struct rte_eth_link link;
1433         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1434
1435         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1436
1437         rte_eth_linkstatus_get(dev, &link);
1438
1439         nfp_net_link_update(dev, 0);
1440
1441         /* likely to up */
1442         if (!link.link_status) {
1443                 /* handle it 1 sec later, wait it being stable */
1444                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1445                 /* likely to down */
1446         } else {
1447                 /* handle it 4 sec later, wait it being stable */
1448                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1449         }
1450
1451         if (rte_eal_alarm_set(timeout * 1000,
1452                               nfp_net_dev_interrupt_delayed_handler,
1453                               (void *)dev) < 0) {
1454                 PMD_INIT_LOG(ERR, "Error setting alarm");
1455                 /* Unmasking */
1456                 nfp_net_irq_unmask(dev);
1457         }
1458 }
1459
1460 /*
1461  * Interrupt handler which shall be registered for alarm callback for delayed
1462  * handling specific interrupt to wait for the stable nic state. As the NIC
1463  * interrupt state is not stable for nfp after link is just down, it needs
1464  * to wait 4 seconds to get the stable status.
1465  *
1466  * @param handle   Pointer to interrupt handle.
1467  * @param param    The address of parameter (struct rte_eth_dev *)
1468  *
1469  * @return  void
1470  */
1471 static void
1472 nfp_net_dev_interrupt_delayed_handler(void *param)
1473 {
1474         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1475
1476         nfp_net_link_update(dev, 0);
1477         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1478
1479         nfp_net_dev_link_status_print(dev);
1480
1481         /* Unmasking */
1482         nfp_net_irq_unmask(dev);
1483 }
1484
1485 static int
1486 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1487 {
1488         struct nfp_net_hw *hw;
1489
1490         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1491
1492         /* check that mtu is within the allowed range */
1493         if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1494                 return -EINVAL;
1495
1496         /* mtu setting is forbidden if port is started */
1497         if (dev->data->dev_started) {
1498                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1499                             dev->data->port_id);
1500                 return -EBUSY;
1501         }
1502
1503         /* switch to jumbo mode if needed */
1504         if ((uint32_t)mtu > RTE_ETHER_MAX_LEN)
1505                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1506         else
1507                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1508
1509         /* update max frame size */
1510         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1511
1512         /* writing to configuration space */
1513         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1514
1515         hw->mtu = mtu;
1516
1517         return 0;
1518 }
1519
1520 static int
1521 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1522                        uint16_t queue_idx, uint16_t nb_desc,
1523                        unsigned int socket_id,
1524                        const struct rte_eth_rxconf *rx_conf,
1525                        struct rte_mempool *mp)
1526 {
1527         const struct rte_memzone *tz;
1528         struct nfp_net_rxq *rxq;
1529         struct nfp_net_hw *hw;
1530         uint32_t rx_desc_sz;
1531
1532         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533
1534         PMD_INIT_FUNC_TRACE();
1535
1536         /* Validating number of descriptors */
1537         rx_desc_sz = nb_desc * sizeof(struct nfp_net_rx_desc);
1538         if (rx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1539             nb_desc > NFP_NET_MAX_RX_DESC ||
1540             nb_desc < NFP_NET_MIN_RX_DESC) {
1541                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1542                 return -EINVAL;
1543         }
1544
1545         /*
1546          * Free memory prior to re-allocation if needed. This is the case after
1547          * calling nfp_net_stop
1548          */
1549         if (dev->data->rx_queues[queue_idx]) {
1550                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1551                 dev->data->rx_queues[queue_idx] = NULL;
1552         }
1553
1554         /* Allocating rx queue data structure */
1555         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1556                                  RTE_CACHE_LINE_SIZE, socket_id);
1557         if (rxq == NULL)
1558                 return -ENOMEM;
1559
1560         /* Hw queues mapping based on firmware configuration */
1561         rxq->qidx = queue_idx;
1562         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1563         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1564         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1565         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1566
1567         /*
1568          * Tracking mbuf size for detecting a potential mbuf overflow due to
1569          * RX offset
1570          */
1571         rxq->mem_pool = mp;
1572         rxq->mbuf_size = rxq->mem_pool->elt_size;
1573         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1574         hw->flbufsz = rxq->mbuf_size;
1575
1576         rxq->rx_count = nb_desc;
1577         rxq->port_id = dev->data->port_id;
1578         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1579         rxq->drop_en = rx_conf->rx_drop_en;
1580
1581         /*
1582          * Allocate RX ring hardware descriptors. A memzone large enough to
1583          * handle the maximum ring size is allocated in order to allow for
1584          * resizing in later calls to the queue setup function.
1585          */
1586         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1587                                    sizeof(struct nfp_net_rx_desc) *
1588                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1589                                    socket_id);
1590
1591         if (tz == NULL) {
1592                 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1593                 nfp_net_rx_queue_release(rxq);
1594                 return -ENOMEM;
1595         }
1596
1597         /* Saving physical and virtual addresses for the RX ring */
1598         rxq->dma = (uint64_t)tz->iova;
1599         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1600
1601         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1602         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1603                                          sizeof(*rxq->rxbufs) * nb_desc,
1604                                          RTE_CACHE_LINE_SIZE, socket_id);
1605         if (rxq->rxbufs == NULL) {
1606                 nfp_net_rx_queue_release(rxq);
1607                 return -ENOMEM;
1608         }
1609
1610         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1611                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1612
1613         nfp_net_reset_rx_queue(rxq);
1614
1615         dev->data->rx_queues[queue_idx] = rxq;
1616         rxq->hw = hw;
1617
1618         /*
1619          * Telling the HW about the physical address of the RX ring and number
1620          * of descriptors in log2 format
1621          */
1622         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1623         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1624
1625         return 0;
1626 }
1627
1628 static int
1629 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1630 {
1631         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1632         uint64_t dma_addr;
1633         unsigned i;
1634
1635         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1636                    rxq->rx_count);
1637
1638         for (i = 0; i < rxq->rx_count; i++) {
1639                 struct nfp_net_rx_desc *rxd;
1640                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1641
1642                 if (mbuf == NULL) {
1643                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1644                                 (unsigned)rxq->qidx);
1645                         return -ENOMEM;
1646                 }
1647
1648                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1649
1650                 rxd = &rxq->rxds[i];
1651                 rxd->fld.dd = 0;
1652                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1653                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1654                 rxe[i].mbuf = mbuf;
1655                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1656         }
1657
1658         /* Make sure all writes are flushed before telling the hardware */
1659         rte_wmb();
1660
1661         /* Not advertising the whole ring as the firmware gets confused if so */
1662         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1663                    rxq->rx_count - 1);
1664
1665         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1666
1667         return 0;
1668 }
1669
1670 static int
1671 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1672                        uint16_t nb_desc, unsigned int socket_id,
1673                        const struct rte_eth_txconf *tx_conf)
1674 {
1675         const struct rte_memzone *tz;
1676         struct nfp_net_txq *txq;
1677         uint16_t tx_free_thresh;
1678         struct nfp_net_hw *hw;
1679         uint32_t tx_desc_sz;
1680
1681         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1682
1683         PMD_INIT_FUNC_TRACE();
1684
1685         /* Validating number of descriptors */
1686         tx_desc_sz = nb_desc * sizeof(struct nfp_net_tx_desc);
1687         if (tx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1688             nb_desc > NFP_NET_MAX_TX_DESC ||
1689             nb_desc < NFP_NET_MIN_TX_DESC) {
1690                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1691                 return -EINVAL;
1692         }
1693
1694         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1695                                     tx_conf->tx_free_thresh :
1696                                     DEFAULT_TX_FREE_THRESH);
1697
1698         if (tx_free_thresh > (nb_desc)) {
1699                 PMD_DRV_LOG(ERR,
1700                         "tx_free_thresh must be less than the number of TX "
1701                         "descriptors. (tx_free_thresh=%u port=%d "
1702                         "queue=%d)", (unsigned int)tx_free_thresh,
1703                         dev->data->port_id, (int)queue_idx);
1704                 return -(EINVAL);
1705         }
1706
1707         /*
1708          * Free memory prior to re-allocation if needed. This is the case after
1709          * calling nfp_net_stop
1710          */
1711         if (dev->data->tx_queues[queue_idx]) {
1712                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1713                            queue_idx);
1714                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1715                 dev->data->tx_queues[queue_idx] = NULL;
1716         }
1717
1718         /* Allocating tx queue data structure */
1719         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1720                                  RTE_CACHE_LINE_SIZE, socket_id);
1721         if (txq == NULL) {
1722                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1723                 return -ENOMEM;
1724         }
1725
1726         /*
1727          * Allocate TX ring hardware descriptors. A memzone large enough to
1728          * handle the maximum ring size is allocated in order to allow for
1729          * resizing in later calls to the queue setup function.
1730          */
1731         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1732                                    sizeof(struct nfp_net_tx_desc) *
1733                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1734                                    socket_id);
1735         if (tz == NULL) {
1736                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1737                 nfp_net_tx_queue_release(txq);
1738                 return -ENOMEM;
1739         }
1740
1741         txq->tx_count = nb_desc;
1742         txq->tx_free_thresh = tx_free_thresh;
1743         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1744         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1745         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1746
1747         /* queue mapping based on firmware configuration */
1748         txq->qidx = queue_idx;
1749         txq->tx_qcidx = queue_idx * hw->stride_tx;
1750         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1751
1752         txq->port_id = dev->data->port_id;
1753
1754         /* Saving physical and virtual addresses for the TX ring */
1755         txq->dma = (uint64_t)tz->iova;
1756         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1757
1758         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1759         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1760                                          sizeof(*txq->txbufs) * nb_desc,
1761                                          RTE_CACHE_LINE_SIZE, socket_id);
1762         if (txq->txbufs == NULL) {
1763                 nfp_net_tx_queue_release(txq);
1764                 return -ENOMEM;
1765         }
1766         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1767                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1768
1769         nfp_net_reset_tx_queue(txq);
1770
1771         dev->data->tx_queues[queue_idx] = txq;
1772         txq->hw = hw;
1773
1774         /*
1775          * Telling the HW about the physical address of the TX ring and number
1776          * of descriptors in log2 format
1777          */
1778         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1779         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1780
1781         return 0;
1782 }
1783
1784 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1785 static inline void
1786 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1787                struct rte_mbuf *mb)
1788 {
1789         uint64_t ol_flags;
1790         struct nfp_net_hw *hw = txq->hw;
1791
1792         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1793                 goto clean_txd;
1794
1795         ol_flags = mb->ol_flags;
1796
1797         if (!(ol_flags & PKT_TX_TCP_SEG))
1798                 goto clean_txd;
1799
1800         txd->l3_offset = mb->l2_len;
1801         txd->l4_offset = mb->l2_len + mb->l3_len;
1802         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1803         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1804         txd->flags = PCIE_DESC_TX_LSO;
1805         return;
1806
1807 clean_txd:
1808         txd->flags = 0;
1809         txd->l3_offset = 0;
1810         txd->l4_offset = 0;
1811         txd->lso_hdrlen = 0;
1812         txd->mss = 0;
1813 }
1814
1815 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1816 static inline void
1817 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1818                  struct rte_mbuf *mb)
1819 {
1820         uint64_t ol_flags;
1821         struct nfp_net_hw *hw = txq->hw;
1822
1823         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1824                 return;
1825
1826         ol_flags = mb->ol_flags;
1827
1828         /* IPv6 does not need checksum */
1829         if (ol_flags & PKT_TX_IP_CKSUM)
1830                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1831
1832         switch (ol_flags & PKT_TX_L4_MASK) {
1833         case PKT_TX_UDP_CKSUM:
1834                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1835                 break;
1836         case PKT_TX_TCP_CKSUM:
1837                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1838                 break;
1839         }
1840
1841         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1842                 txd->flags |= PCIE_DESC_TX_CSUM;
1843 }
1844
1845 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1846 static inline void
1847 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1848                  struct rte_mbuf *mb)
1849 {
1850         struct nfp_net_hw *hw = rxq->hw;
1851
1852         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1853                 return;
1854
1855         /* If IPv4 and IP checksum error, fail */
1856         if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1857             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1858                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1859         else
1860                 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1861
1862         /* If neither UDP nor TCP return */
1863         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1864             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1865                 return;
1866
1867         if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1868                 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1869         else
1870                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1871 }
1872
1873 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1874 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1875
1876 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1877
1878 /*
1879  * nfp_net_set_hash - Set mbuf hash data
1880  *
1881  * The RSS hash and hash-type are pre-pended to the packet data.
1882  * Extract and decode it and set the mbuf fields.
1883  */
1884 static inline void
1885 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1886                  struct rte_mbuf *mbuf)
1887 {
1888         struct nfp_net_hw *hw = rxq->hw;
1889         uint8_t *meta_offset;
1890         uint32_t meta_info;
1891         uint32_t hash = 0;
1892         uint32_t hash_type = 0;
1893
1894         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1895                 return;
1896
1897         /* this is true for new firmwares */
1898         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1899             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1900              NFP_DESC_META_LEN(rxd))) {
1901                 /*
1902                  * new metadata api:
1903                  * <----  32 bit  ----->
1904                  * m    field type word
1905                  * e     data field #2
1906                  * t     data field #1
1907                  * a     data field #0
1908                  * ====================
1909                  *    packet data
1910                  *
1911                  * Field type word contains up to 8 4bit field types
1912                  * A 4bit field type refers to a data field word
1913                  * A data field word can have several 4bit field types
1914                  */
1915                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1916                 meta_offset -= NFP_DESC_META_LEN(rxd);
1917                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1918                 meta_offset += 4;
1919                 /* NFP PMD just supports metadata for hashing */
1920                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1921                 case NFP_NET_META_HASH:
1922                         /* next field type is about the hash type */
1923                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1924                         /* hash value is in the data field */
1925                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1926                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1927                         break;
1928                 default:
1929                         /* Unsupported metadata can be a performance issue */
1930                         return;
1931                 }
1932         } else {
1933                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1934                         return;
1935
1936                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1937                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1938         }
1939
1940         mbuf->hash.rss = hash;
1941         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1942
1943         switch (hash_type) {
1944         case NFP_NET_RSS_IPV4:
1945                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1946                 break;
1947         case NFP_NET_RSS_IPV6:
1948                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1949                 break;
1950         case NFP_NET_RSS_IPV6_EX:
1951                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1952                 break;
1953         case NFP_NET_RSS_IPV4_TCP:
1954                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1955                 break;
1956         case NFP_NET_RSS_IPV6_TCP:
1957                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1958                 break;
1959         case NFP_NET_RSS_IPV4_UDP:
1960                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1961                 break;
1962         case NFP_NET_RSS_IPV6_UDP:
1963                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1964                 break;
1965         default:
1966                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1967         }
1968 }
1969
1970 static inline void
1971 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1972 {
1973         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1974 }
1975
1976 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1977
1978 /*
1979  * RX path design:
1980  *
1981  * There are some decisions to take:
1982  * 1) How to check DD RX descriptors bit
1983  * 2) How and when to allocate new mbufs
1984  *
1985  * Current implementation checks just one single DD bit each loop. As each
1986  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1987  * a single cache line instead. Tests with this change have not shown any
1988  * performance improvement but it requires further investigation. For example,
1989  * depending on which descriptor is next, the number of descriptors could be
1990  * less than 8 for just checking those in the same cache line. This implies
1991  * extra work which could be counterproductive by itself. Indeed, last firmware
1992  * changes are just doing this: writing several descriptors with the DD bit
1993  * for saving PCIe bandwidth and DMA operations from the NFP.
1994  *
1995  * Mbuf allocation is done when a new packet is received. Then the descriptor
1996  * is automatically linked with the new mbuf and the old one is given to the
1997  * user. The main drawback with this design is mbuf allocation is heavier than
1998  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1999  * cache point of view it does not seem allocating the mbuf early on as we are
2000  * doing now have any benefit at all. Again, tests with this change have not
2001  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2002  * so looking at the implications of this type of allocation should be studied
2003  * deeply
2004  */
2005
2006 static uint16_t
2007 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2008 {
2009         struct nfp_net_rxq *rxq;
2010         struct nfp_net_rx_desc *rxds;
2011         struct nfp_net_rx_buff *rxb;
2012         struct nfp_net_hw *hw;
2013         struct rte_mbuf *mb;
2014         struct rte_mbuf *new_mb;
2015         uint16_t nb_hold;
2016         uint64_t dma_addr;
2017         int avail;
2018
2019         rxq = rx_queue;
2020         if (unlikely(rxq == NULL)) {
2021                 /*
2022                  * DPDK just checks the queue is lower than max queues
2023                  * enabled. But the queue needs to be configured
2024                  */
2025                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2026                 return -EINVAL;
2027         }
2028
2029         hw = rxq->hw;
2030         avail = 0;
2031         nb_hold = 0;
2032
2033         while (avail < nb_pkts) {
2034                 rxb = &rxq->rxbufs[rxq->rd_p];
2035                 if (unlikely(rxb == NULL)) {
2036                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2037                         break;
2038                 }
2039
2040                 rxds = &rxq->rxds[rxq->rd_p];
2041                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2042                         break;
2043
2044                 /*
2045                  * Memory barrier to ensure that we won't do other
2046                  * reads before the DD bit.
2047                  */
2048                 rte_rmb();
2049
2050                 /*
2051                  * We got a packet. Let's alloc a new mbuf for refilling the
2052                  * free descriptor ring as soon as possible
2053                  */
2054                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2055                 if (unlikely(new_mb == NULL)) {
2056                         RTE_LOG_DP(DEBUG, PMD,
2057                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2058                                 rxq->port_id, (unsigned int)rxq->qidx);
2059                         nfp_net_mbuf_alloc_failed(rxq);
2060                         break;
2061                 }
2062
2063                 nb_hold++;
2064
2065                 /*
2066                  * Grab the mbuf and refill the descriptor with the
2067                  * previously allocated mbuf
2068                  */
2069                 mb = rxb->mbuf;
2070                 rxb->mbuf = new_mb;
2071
2072                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2073                            rxds->rxd.data_len, rxq->mbuf_size);
2074
2075                 /* Size of this segment */
2076                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2077                 /* Size of the whole packet. We just support 1 segment */
2078                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2079
2080                 if (unlikely((mb->data_len + hw->rx_offset) >
2081                              rxq->mbuf_size)) {
2082                         /*
2083                          * This should not happen and the user has the
2084                          * responsibility of avoiding it. But we have
2085                          * to give some info about the error
2086                          */
2087                         RTE_LOG_DP(ERR, PMD,
2088                                 "mbuf overflow likely due to the RX offset.\n"
2089                                 "\t\tYour mbuf size should have extra space for"
2090                                 " RX offset=%u bytes.\n"
2091                                 "\t\tCurrently you just have %u bytes available"
2092                                 " but the received packet is %u bytes long",
2093                                 hw->rx_offset,
2094                                 rxq->mbuf_size - hw->rx_offset,
2095                                 mb->data_len);
2096                         return -EINVAL;
2097                 }
2098
2099                 /* Filling the received mbuf with packet info */
2100                 if (hw->rx_offset)
2101                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2102                 else
2103                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2104                                        NFP_DESC_META_LEN(rxds);
2105
2106                 /* No scatter mode supported */
2107                 mb->nb_segs = 1;
2108                 mb->next = NULL;
2109
2110                 mb->port = rxq->port_id;
2111
2112                 /* Checking the RSS flag */
2113                 nfp_net_set_hash(rxq, rxds, mb);
2114
2115                 /* Checking the checksum flag */
2116                 nfp_net_rx_cksum(rxq, rxds, mb);
2117
2118                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2119                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2120                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2121                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2122                 }
2123
2124                 /* Adding the mbuf to the mbuf array passed by the app */
2125                 rx_pkts[avail++] = mb;
2126
2127                 /* Now resetting and updating the descriptor */
2128                 rxds->vals[0] = 0;
2129                 rxds->vals[1] = 0;
2130                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2131                 rxds->fld.dd = 0;
2132                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2133                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2134
2135                 rxq->rd_p++;
2136                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2137                         rxq->rd_p = 0;
2138         }
2139
2140         if (nb_hold == 0)
2141                 return nb_hold;
2142
2143         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2144                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2145
2146         nb_hold += rxq->nb_rx_hold;
2147
2148         /*
2149          * FL descriptors needs to be written before incrementing the
2150          * FL queue WR pointer
2151          */
2152         rte_wmb();
2153         if (nb_hold > rxq->rx_free_thresh) {
2154                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2155                            rxq->port_id, (unsigned int)rxq->qidx,
2156                            (unsigned)nb_hold, (unsigned)avail);
2157                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2158                 nb_hold = 0;
2159         }
2160         rxq->nb_rx_hold = nb_hold;
2161
2162         return avail;
2163 }
2164
2165 /*
2166  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2167  * status
2168  * @txq: TX queue to work with
2169  * Returns number of descriptors freed
2170  */
2171 int
2172 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2173 {
2174         uint32_t qcp_rd_p;
2175         int todo;
2176
2177         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2178                    " status", txq->qidx);
2179
2180         /* Work out how many packets have been sent */
2181         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2182
2183         if (qcp_rd_p == txq->rd_p) {
2184                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2185                            "packets (%u, %u)", txq->qidx,
2186                            qcp_rd_p, txq->rd_p);
2187                 return 0;
2188         }
2189
2190         if (qcp_rd_p > txq->rd_p)
2191                 todo = qcp_rd_p - txq->rd_p;
2192         else
2193                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2194
2195         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2196                    qcp_rd_p, txq->rd_p, txq->rd_p);
2197
2198         if (todo == 0)
2199                 return todo;
2200
2201         txq->rd_p += todo;
2202         if (unlikely(txq->rd_p >= txq->tx_count))
2203                 txq->rd_p -= txq->tx_count;
2204
2205         return todo;
2206 }
2207
2208 /* Leaving always free descriptors for avoiding wrapping confusion */
2209 static inline
2210 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2211 {
2212         if (txq->wr_p >= txq->rd_p)
2213                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2214         else
2215                 return txq->rd_p - txq->wr_p - 8;
2216 }
2217
2218 /*
2219  * nfp_net_txq_full - Check if the TX queue free descriptors
2220  * is below tx_free_threshold
2221  *
2222  * @txq: TX queue to check
2223  *
2224  * This function uses the host copy* of read/write pointers
2225  */
2226 static inline
2227 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2228 {
2229         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2230 }
2231
2232 static uint16_t
2233 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2234 {
2235         struct nfp_net_txq *txq;
2236         struct nfp_net_hw *hw;
2237         struct nfp_net_tx_desc *txds, txd;
2238         struct rte_mbuf *pkt;
2239         uint64_t dma_addr;
2240         int pkt_size, dma_size;
2241         uint16_t free_descs, issued_descs;
2242         struct rte_mbuf **lmbuf;
2243         int i;
2244
2245         txq = tx_queue;
2246         hw = txq->hw;
2247         txds = &txq->txds[txq->wr_p];
2248
2249         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2250                    txq->qidx, txq->wr_p, nb_pkts);
2251
2252         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2253                 nfp_net_tx_free_bufs(txq);
2254
2255         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2256         if (unlikely(free_descs == 0))
2257                 return 0;
2258
2259         pkt = *tx_pkts;
2260
2261         i = 0;
2262         issued_descs = 0;
2263         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2264                    txq->qidx, nb_pkts);
2265         /* Sending packets */
2266         while ((i < nb_pkts) && free_descs) {
2267                 /* Grabbing the mbuf linked to the current descriptor */
2268                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2269                 /* Warming the cache for releasing the mbuf later on */
2270                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2271
2272                 pkt = *(tx_pkts + i);
2273
2274                 if (unlikely((pkt->nb_segs > 1) &&
2275                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2276                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2277                         rte_panic("Multisegment packet unsupported\n");
2278                 }
2279
2280                 /* Checking if we have enough descriptors */
2281                 if (unlikely(pkt->nb_segs > free_descs))
2282                         goto xmit_end;
2283
2284                 /*
2285                  * Checksum and VLAN flags just in the first descriptor for a
2286                  * multisegment packet, but TSO info needs to be in all of them.
2287                  */
2288                 txd.data_len = pkt->pkt_len;
2289                 nfp_net_tx_tso(txq, &txd, pkt);
2290                 nfp_net_tx_cksum(txq, &txd, pkt);
2291
2292                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2293                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2294                         txd.flags |= PCIE_DESC_TX_VLAN;
2295                         txd.vlan = pkt->vlan_tci;
2296                 }
2297
2298                 /*
2299                  * mbuf data_len is the data in one segment and pkt_len data
2300                  * in the whole packet. When the packet is just one segment,
2301                  * then data_len = pkt_len
2302                  */
2303                 pkt_size = pkt->pkt_len;
2304
2305                 while (pkt) {
2306                         /* Copying TSO, VLAN and cksum info */
2307                         *txds = txd;
2308
2309                         /* Releasing mbuf used by this descriptor previously*/
2310                         if (*lmbuf)
2311                                 rte_pktmbuf_free_seg(*lmbuf);
2312
2313                         /*
2314                          * Linking mbuf with descriptor for being released
2315                          * next time descriptor is used
2316                          */
2317                         *lmbuf = pkt;
2318
2319                         dma_size = pkt->data_len;
2320                         dma_addr = rte_mbuf_data_iova(pkt);
2321                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2322                                    "%" PRIx64 "", dma_addr);
2323
2324                         /* Filling descriptors fields */
2325                         txds->dma_len = dma_size;
2326                         txds->data_len = txd.data_len;
2327                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2328                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2329                         ASSERT(free_descs > 0);
2330                         free_descs--;
2331
2332                         txq->wr_p++;
2333                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2334                                 txq->wr_p = 0;
2335
2336                         pkt_size -= dma_size;
2337
2338                         /*
2339                          * Making the EOP, packets with just one segment
2340                          * the priority
2341                          */
2342                         if (likely(!pkt_size))
2343                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2344                         else
2345                                 txds->offset_eop = 0;
2346
2347                         pkt = pkt->next;
2348                         /* Referencing next free TX descriptor */
2349                         txds = &txq->txds[txq->wr_p];
2350                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2351                         issued_descs++;
2352                 }
2353                 i++;
2354         }
2355
2356 xmit_end:
2357         /* Increment write pointers. Force memory write before we let HW know */
2358         rte_wmb();
2359         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2360
2361         return i;
2362 }
2363
2364 static int
2365 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2366 {
2367         uint32_t new_ctrl, update;
2368         struct nfp_net_hw *hw;
2369         int ret;
2370
2371         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372         new_ctrl = 0;
2373
2374         /* Enable vlan strip if it is not configured yet */
2375         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2376             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2377                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2378
2379         /* Disable vlan strip just if it is configured */
2380         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2381             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2382                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2383
2384         if (new_ctrl == 0)
2385                 return 0;
2386
2387         update = NFP_NET_CFG_UPDATE_GEN;
2388
2389         ret = nfp_net_reconfig(hw, new_ctrl, update);
2390         if (!ret)
2391                 hw->ctrl = new_ctrl;
2392
2393         return ret;
2394 }
2395
2396 static int
2397 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2398                     struct rte_eth_rss_reta_entry64 *reta_conf,
2399                     uint16_t reta_size)
2400 {
2401         uint32_t reta, mask;
2402         int i, j;
2403         int idx, shift;
2404         struct nfp_net_hw *hw =
2405                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406
2407         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2408                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2409                         "(%d) doesn't match the number hardware can supported "
2410                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2411                 return -EINVAL;
2412         }
2413
2414         /*
2415          * Update Redirection Table. There are 128 8bit-entries which can be
2416          * manage as 32 32bit-entries
2417          */
2418         for (i = 0; i < reta_size; i += 4) {
2419                 /* Handling 4 RSS entries per loop */
2420                 idx = i / RTE_RETA_GROUP_SIZE;
2421                 shift = i % RTE_RETA_GROUP_SIZE;
2422                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2423
2424                 if (!mask)
2425                         continue;
2426
2427                 reta = 0;
2428                 /* If all 4 entries were set, don't need read RETA register */
2429                 if (mask != 0xF)
2430                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2431
2432                 for (j = 0; j < 4; j++) {
2433                         if (!(mask & (0x1 << j)))
2434                                 continue;
2435                         if (mask != 0xF)
2436                                 /* Clearing the entry bits */
2437                                 reta &= ~(0xFF << (8 * j));
2438                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2439                 }
2440                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2441                               reta);
2442         }
2443         return 0;
2444 }
2445
2446 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2447 static int
2448 nfp_net_reta_update(struct rte_eth_dev *dev,
2449                     struct rte_eth_rss_reta_entry64 *reta_conf,
2450                     uint16_t reta_size)
2451 {
2452         struct nfp_net_hw *hw =
2453                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2454         uint32_t update;
2455         int ret;
2456
2457         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2458                 return -EINVAL;
2459
2460         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2461         if (ret != 0)
2462                 return ret;
2463
2464         update = NFP_NET_CFG_UPDATE_RSS;
2465
2466         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2467                 return -EIO;
2468
2469         return 0;
2470 }
2471
2472  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2473 static int
2474 nfp_net_reta_query(struct rte_eth_dev *dev,
2475                    struct rte_eth_rss_reta_entry64 *reta_conf,
2476                    uint16_t reta_size)
2477 {
2478         uint8_t i, j, mask;
2479         int idx, shift;
2480         uint32_t reta;
2481         struct nfp_net_hw *hw;
2482
2483         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2484
2485         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2486                 return -EINVAL;
2487
2488         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2489                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2490                         "(%d) doesn't match the number hardware can supported "
2491                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2492                 return -EINVAL;
2493         }
2494
2495         /*
2496          * Reading Redirection Table. There are 128 8bit-entries which can be
2497          * manage as 32 32bit-entries
2498          */
2499         for (i = 0; i < reta_size; i += 4) {
2500                 /* Handling 4 RSS entries per loop */
2501                 idx = i / RTE_RETA_GROUP_SIZE;
2502                 shift = i % RTE_RETA_GROUP_SIZE;
2503                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2504
2505                 if (!mask)
2506                         continue;
2507
2508                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2509                                     shift);
2510                 for (j = 0; j < 4; j++) {
2511                         if (!(mask & (0x1 << j)))
2512                                 continue;
2513                         reta_conf[idx].reta[shift + j] =
2514                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2515                 }
2516         }
2517         return 0;
2518 }
2519
2520 static int
2521 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2522                         struct rte_eth_rss_conf *rss_conf)
2523 {
2524         struct nfp_net_hw *hw;
2525         uint64_t rss_hf;
2526         uint32_t cfg_rss_ctrl = 0;
2527         uint8_t key;
2528         int i;
2529
2530         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531
2532         /* Writing the key byte a byte */
2533         for (i = 0; i < rss_conf->rss_key_len; i++) {
2534                 memcpy(&key, &rss_conf->rss_key[i], 1);
2535                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2536         }
2537
2538         rss_hf = rss_conf->rss_hf;
2539
2540         if (rss_hf & ETH_RSS_IPV4)
2541                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2542
2543         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2544                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2545
2546         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2547                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2548
2549         if (rss_hf & ETH_RSS_IPV6)
2550                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2551
2552         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2553                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2554
2555         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2556                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2557
2558         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2559         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2560
2561         /* configuring where to apply the RSS hash */
2562         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2563
2564         /* Writing the key size */
2565         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2566
2567         return 0;
2568 }
2569
2570 static int
2571 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2572                         struct rte_eth_rss_conf *rss_conf)
2573 {
2574         uint32_t update;
2575         uint64_t rss_hf;
2576         struct nfp_net_hw *hw;
2577
2578         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579
2580         rss_hf = rss_conf->rss_hf;
2581
2582         /* Checking if RSS is enabled */
2583         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2584                 if (rss_hf != 0) { /* Enable RSS? */
2585                         PMD_DRV_LOG(ERR, "RSS unsupported");
2586                         return -EINVAL;
2587                 }
2588                 return 0; /* Nothing to do */
2589         }
2590
2591         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2592                 PMD_DRV_LOG(ERR, "hash key too long");
2593                 return -EINVAL;
2594         }
2595
2596         nfp_net_rss_hash_write(dev, rss_conf);
2597
2598         update = NFP_NET_CFG_UPDATE_RSS;
2599
2600         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2601                 return -EIO;
2602
2603         return 0;
2604 }
2605
2606 static int
2607 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2608                           struct rte_eth_rss_conf *rss_conf)
2609 {
2610         uint64_t rss_hf;
2611         uint32_t cfg_rss_ctrl;
2612         uint8_t key;
2613         int i;
2614         struct nfp_net_hw *hw;
2615
2616         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2617
2618         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2619                 return -EINVAL;
2620
2621         rss_hf = rss_conf->rss_hf;
2622         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2623
2624         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2625                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2626
2627         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2628                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2629
2630         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2631                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2632
2633         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2634                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2635
2636         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2637                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2638
2639         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2640                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2641
2642         /* Propagate current RSS hash functions to caller */
2643         rss_conf->rss_hf = rss_hf;
2644
2645         /* Reading the key size */
2646         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2647
2648         /* Reading the key byte a byte */
2649         for (i = 0; i < rss_conf->rss_key_len; i++) {
2650                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2651                 memcpy(&rss_conf->rss_key[i], &key, 1);
2652         }
2653
2654         return 0;
2655 }
2656
2657 static int
2658 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2659 {
2660         struct rte_eth_conf *dev_conf;
2661         struct rte_eth_rss_conf rss_conf;
2662         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2663         uint16_t rx_queues = dev->data->nb_rx_queues;
2664         uint16_t queue;
2665         int i, j, ret;
2666
2667         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2668                 rx_queues);
2669
2670         nfp_reta_conf[0].mask = ~0x0;
2671         nfp_reta_conf[1].mask = ~0x0;
2672
2673         queue = 0;
2674         for (i = 0; i < 0x40; i += 8) {
2675                 for (j = i; j < (i + 8); j++) {
2676                         nfp_reta_conf[0].reta[j] = queue;
2677                         nfp_reta_conf[1].reta[j] = queue++;
2678                         queue %= rx_queues;
2679                 }
2680         }
2681         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2682         if (ret != 0)
2683                 return ret;
2684
2685         dev_conf = &dev->data->dev_conf;
2686         if (!dev_conf) {
2687                 PMD_DRV_LOG(INFO, "wrong rss conf");
2688                 return -EINVAL;
2689         }
2690         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2691
2692         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2693
2694         return ret;
2695 }
2696
2697
2698 /* Initialise and register driver with DPDK Application */
2699 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2700         .dev_configure          = nfp_net_configure,
2701         .dev_start              = nfp_net_start,
2702         .dev_stop               = nfp_net_stop,
2703         .dev_set_link_up        = nfp_net_set_link_up,
2704         .dev_set_link_down      = nfp_net_set_link_down,
2705         .dev_close              = nfp_net_close,
2706         .promiscuous_enable     = nfp_net_promisc_enable,
2707         .promiscuous_disable    = nfp_net_promisc_disable,
2708         .link_update            = nfp_net_link_update,
2709         .stats_get              = nfp_net_stats_get,
2710         .stats_reset            = nfp_net_stats_reset,
2711         .dev_infos_get          = nfp_net_infos_get,
2712         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2713         .mtu_set                = nfp_net_dev_mtu_set,
2714         .mac_addr_set           = nfp_set_mac_addr,
2715         .vlan_offload_set       = nfp_net_vlan_offload_set,
2716         .reta_update            = nfp_net_reta_update,
2717         .reta_query             = nfp_net_reta_query,
2718         .rss_hash_update        = nfp_net_rss_hash_update,
2719         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2720         .rx_queue_setup         = nfp_net_rx_queue_setup,
2721         .rx_queue_release       = nfp_net_rx_queue_release,
2722         .tx_queue_setup         = nfp_net_tx_queue_setup,
2723         .tx_queue_release       = nfp_net_tx_queue_release,
2724         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2725         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2726 };
2727
2728 /*
2729  * All eth_dev created got its private data, but before nfp_net_init, that
2730  * private data is referencing private data for all the PF ports. This is due
2731  * to how the vNIC bars are mapped based on first port, so all ports need info
2732  * about port 0 private data. Inside nfp_net_init the private data pointer is
2733  * changed to the right address for each port once the bars have been mapped.
2734  *
2735  * This functions helps to find out which port and therefore which offset
2736  * inside the private data array to use.
2737  */
2738 static int
2739 get_pf_port_number(char *name)
2740 {
2741         char *pf_str = name;
2742         int size = 0;
2743
2744         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2745                 pf_str++;
2746
2747         if (size == 30)
2748                 /*
2749                  * This should not happen at all and it would mean major
2750                  * implementation fault.
2751                  */
2752                 rte_panic("nfp_net: problem with pf device name\n");
2753
2754         /* Expecting _portX with X within [0,7] */
2755         pf_str += 5;
2756
2757         return (int)strtol(pf_str, NULL, 10);
2758 }
2759
2760 static int
2761 nfp_net_init(struct rte_eth_dev *eth_dev)
2762 {
2763         struct rte_pci_device *pci_dev;
2764         struct nfp_net_hw *hw, *hwport0;
2765
2766         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2767         uint32_t start_q;
2768         int stride = 4;
2769         int port = 0;
2770         int err;
2771
2772         PMD_INIT_FUNC_TRACE();
2773
2774         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2775
2776         /* NFP can not handle DMA addresses requiring more than 40 bits */
2777         if (rte_mem_check_dma_mask(40)) {
2778                 RTE_LOG(ERR, PMD, "device %s can not be used:",
2779                                    pci_dev->device.name);
2780                 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2781                 return -ENODEV;
2782         };
2783
2784         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2785             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2786                 port = get_pf_port_number(eth_dev->data->name);
2787                 if (port < 0 || port > 7) {
2788                         PMD_DRV_LOG(ERR, "Port value is wrong");
2789                         return -ENODEV;
2790                 }
2791
2792                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2793
2794                 /* This points to port 0 private data */
2795                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2796
2797                 /* This points to the specific port private data */
2798                 hw = &hwport0[port];
2799         } else {
2800                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2801                 hwport0 = 0;
2802         }
2803
2804         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2805         eth_dev->rx_queue_count = nfp_net_rx_queue_count;
2806         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2807         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2808
2809         /* For secondary processes, the primary has done all the work */
2810         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2811                 return 0;
2812
2813         rte_eth_copy_pci_info(eth_dev, pci_dev);
2814
2815         hw->device_id = pci_dev->id.device_id;
2816         hw->vendor_id = pci_dev->id.vendor_id;
2817         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2818         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2819
2820         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2821                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2822                      pci_dev->addr.domain, pci_dev->addr.bus,
2823                      pci_dev->addr.devid, pci_dev->addr.function);
2824
2825         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2826         if (hw->ctrl_bar == NULL) {
2827                 PMD_DRV_LOG(ERR,
2828                         "hw->ctrl_bar is NULL. BAR0 not configured");
2829                 return -ENODEV;
2830         }
2831
2832         if (hw->is_pf && port == 0) {
2833                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2834                                              hw->total_ports * 32768,
2835                                              &hw->ctrl_area);
2836                 if (!hw->ctrl_bar) {
2837                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2838                         return -EIO;
2839                 }
2840
2841                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2842         }
2843
2844         if (port > 0) {
2845                 if (!hwport0->ctrl_bar)
2846                         return -ENODEV;
2847
2848                 /* address based on port0 offset */
2849                 hw->ctrl_bar = hwport0->ctrl_bar +
2850                                (port * NFP_PF_CSR_SLICE_SIZE);
2851         }
2852
2853         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2854
2855         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2856         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2857
2858         /* Work out where in the BAR the queues start. */
2859         switch (pci_dev->id.device_id) {
2860         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2861         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2862         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2863                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2864                 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2865                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2866                 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2867                 break;
2868         default:
2869                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2870                 err = -ENODEV;
2871                 goto dev_err_ctrl_map;
2872         }
2873
2874         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2875         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2876
2877         if (hw->is_pf && port == 0) {
2878                 /* configure access to tx/rx vNIC BARs */
2879                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2880                                                       NFP_PCIE_QUEUE(0),
2881                                                       NFP_QCP_QUEUE_AREA_SZ,
2882                                                       &hw->hwqueues_area);
2883
2884                 if (!hwport0->hw_queues) {
2885                         printf("nfp_rtsym_map fails for net.qc");
2886                         err = -EIO;
2887                         goto dev_err_ctrl_map;
2888                 }
2889
2890                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2891                                     hwport0->hw_queues);
2892         }
2893
2894         if (hw->is_pf) {
2895                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2896                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2897                 eth_dev->data->dev_private = hw;
2898         } else {
2899                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2900                              tx_bar_off;
2901                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2902                              rx_bar_off;
2903         }
2904
2905         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2906                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2907
2908         nfp_net_cfg_queue_setup(hw);
2909
2910         /* Get some of the read-only fields from the config BAR */
2911         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2912         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2913         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2914         hw->mtu = RTE_ETHER_MTU;
2915
2916         /* VLAN insertion is incompatible with LSOv2 */
2917         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2918                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2919
2920         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2921                 hw->rx_offset = NFP_NET_RX_OFFSET;
2922         else
2923                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2924
2925         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2926                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2927                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2928
2929         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2930                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2931                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2932                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2933                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2934                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2935                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2936                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2937                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2938                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2939                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2940                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2941                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2942                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2943                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2944
2945         hw->ctrl = 0;
2946
2947         hw->stride_rx = stride;
2948         hw->stride_tx = stride;
2949
2950         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2951                      hw->max_rx_queues, hw->max_tx_queues);
2952
2953         /* Initializing spinlock for reconfigs */
2954         rte_spinlock_init(&hw->reconfig_lock);
2955
2956         /* Allocating memory for mac addr */
2957         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2958                                                RTE_ETHER_ADDR_LEN, 0);
2959         if (eth_dev->data->mac_addrs == NULL) {
2960                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2961                 err = -ENOMEM;
2962                 goto dev_err_queues_map;
2963         }
2964
2965         if (hw->is_pf) {
2966                 nfp_net_pf_read_mac(hwport0, port);
2967                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2968         } else {
2969                 nfp_net_vf_read_mac(hw);
2970         }
2971
2972         if (!rte_is_valid_assigned_ether_addr(
2973                     (struct rte_ether_addr *)&hw->mac_addr)) {
2974                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2975                                    port);
2976                 /* Using random mac addresses for VFs */
2977                 rte_eth_random_addr(&hw->mac_addr[0]);
2978                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2979         }
2980
2981         /* Copying mac address to DPDK eth_dev struct */
2982         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2983                         &eth_dev->data->mac_addrs[0]);
2984
2985         if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2986                 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2987
2988         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2989                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2990                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2991                      pci_dev->id.device_id,
2992                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2993                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2994
2995         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2996                 /* Registering LSC interrupt handler */
2997                 rte_intr_callback_register(&pci_dev->intr_handle,
2998                                            nfp_net_dev_interrupt_handler,
2999                                            (void *)eth_dev);
3000                 /* Telling the firmware about the LSC interrupt entry */
3001                 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
3002                 /* Recording current stats counters values */
3003                 nfp_net_stats_reset(eth_dev);
3004         }
3005
3006         return 0;
3007
3008 dev_err_queues_map:
3009                 nfp_cpp_area_free(hw->hwqueues_area);
3010 dev_err_ctrl_map:
3011                 nfp_cpp_area_free(hw->ctrl_area);
3012
3013         return err;
3014 }
3015
3016 #define NFP_CPP_MEMIO_BOUNDARY          (1 << 20)
3017
3018 /*
3019  * Serving a write request to NFP from host programs. The request
3020  * sends the write size and the CPP target. The bridge makes use
3021  * of CPP interface handler configured by the PMD setup.
3022  */
3023 static int
3024 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3025 {
3026         struct nfp_cpp_area *area;
3027         off_t offset, nfp_offset;
3028         uint32_t cpp_id, pos, len;
3029         uint32_t tmpbuf[16];
3030         size_t count, curlen, totlen = 0;
3031         int err = 0;
3032
3033         PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3034                 sizeof(off_t), sizeof(size_t));
3035
3036         /* Reading the count param */
3037         err = recv(sockfd, &count, sizeof(off_t), 0);
3038         if (err != sizeof(off_t))
3039                 return -EINVAL;
3040
3041         curlen = count;
3042
3043         /* Reading the offset param */
3044         err = recv(sockfd, &offset, sizeof(off_t), 0);
3045         if (err != sizeof(off_t))
3046                 return -EINVAL;
3047
3048         /* Obtain target's CPP ID and offset in target */
3049         cpp_id = (offset >> 40) << 8;
3050         nfp_offset = offset & ((1ull << 40) - 1);
3051
3052         PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3053                 offset);
3054         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3055                 cpp_id, nfp_offset);
3056
3057         /* Adjust length if not aligned */
3058         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3059             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3060                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3061                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3062         }
3063
3064         while (count > 0) {
3065                 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3066                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3067                                                     nfp_offset, curlen);
3068                 if (!area) {
3069                         RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3070                         return -EIO;
3071                 }
3072
3073                 /* mapping the target */
3074                 err = nfp_cpp_area_acquire(area);
3075                 if (err < 0) {
3076                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3077                         nfp_cpp_area_free(area);
3078                         return -EIO;
3079                 }
3080
3081                 for (pos = 0; pos < curlen; pos += len) {
3082                         len = curlen - pos;
3083                         if (len > sizeof(tmpbuf))
3084                                 len = sizeof(tmpbuf);
3085
3086                         PMD_CPP_LOG(DEBUG, "%s: Receive %u of %zu\n", __func__,
3087                                            len, count);
3088                         err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3089                         if (err != (int)len) {
3090                                 RTE_LOG(ERR, PMD,
3091                                         "%s: error when receiving, %d of %zu\n",
3092                                         __func__, err, count);
3093                                 nfp_cpp_area_release(area);
3094                                 nfp_cpp_area_free(area);
3095                                 return -EIO;
3096                         }
3097                         err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3098                         if (err < 0) {
3099                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3100                                 nfp_cpp_area_release(area);
3101                                 nfp_cpp_area_free(area);
3102                                 return -EIO;
3103                         }
3104                 }
3105
3106                 nfp_offset += pos;
3107                 totlen += pos;
3108                 nfp_cpp_area_release(area);
3109                 nfp_cpp_area_free(area);
3110
3111                 count -= pos;
3112                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3113                          NFP_CPP_MEMIO_BOUNDARY : count;
3114         }
3115
3116         return 0;
3117 }
3118
3119 /*
3120  * Serving a read request to NFP from host programs. The request
3121  * sends the read size and the CPP target. The bridge makes use
3122  * of CPP interface handler configured by the PMD setup. The read
3123  * data is sent to the requester using the same socket.
3124  */
3125 static int
3126 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3127 {
3128         struct nfp_cpp_area *area;
3129         off_t offset, nfp_offset;
3130         uint32_t cpp_id, pos, len;
3131         uint32_t tmpbuf[16];
3132         size_t count, curlen, totlen = 0;
3133         int err = 0;
3134
3135         PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3136                 sizeof(off_t), sizeof(size_t));
3137
3138         /* Reading the count param */
3139         err = recv(sockfd, &count, sizeof(off_t), 0);
3140         if (err != sizeof(off_t))
3141                 return -EINVAL;
3142
3143         curlen = count;
3144
3145         /* Reading the offset param */
3146         err = recv(sockfd, &offset, sizeof(off_t), 0);
3147         if (err != sizeof(off_t))
3148                 return -EINVAL;
3149
3150         /* Obtain target's CPP ID and offset in target */
3151         cpp_id = (offset >> 40) << 8;
3152         nfp_offset = offset & ((1ull << 40) - 1);
3153
3154         PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3155                            offset);
3156         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3157                            cpp_id, nfp_offset);
3158
3159         /* Adjust length if not aligned */
3160         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3161             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3162                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3163                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3164         }
3165
3166         while (count > 0) {
3167                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3168                                                     nfp_offset, curlen);
3169                 if (!area) {
3170                         RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3171                         return -EIO;
3172                 }
3173
3174                 err = nfp_cpp_area_acquire(area);
3175                 if (err < 0) {
3176                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3177                         nfp_cpp_area_free(area);
3178                         return -EIO;
3179                 }
3180
3181                 for (pos = 0; pos < curlen; pos += len) {
3182                         len = curlen - pos;
3183                         if (len > sizeof(tmpbuf))
3184                                 len = sizeof(tmpbuf);
3185
3186                         err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3187                         if (err < 0) {
3188                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3189                                 nfp_cpp_area_release(area);
3190                                 nfp_cpp_area_free(area);
3191                                 return -EIO;
3192                         }
3193                         PMD_CPP_LOG(DEBUG, "%s: sending %u of %zu\n", __func__,
3194                                            len, count);
3195
3196                         err = send(sockfd, tmpbuf, len, 0);
3197                         if (err != (int)len) {
3198                                 RTE_LOG(ERR, PMD,
3199                                         "%s: error when sending: %d of %zu\n",
3200                                         __func__, err, count);
3201                                 nfp_cpp_area_release(area);
3202                                 nfp_cpp_area_free(area);
3203                                 return -EIO;
3204                         }
3205                 }
3206
3207                 nfp_offset += pos;
3208                 totlen += pos;
3209                 nfp_cpp_area_release(area);
3210                 nfp_cpp_area_free(area);
3211
3212                 count -= pos;
3213                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3214                         NFP_CPP_MEMIO_BOUNDARY : count;
3215         }
3216         return 0;
3217 }
3218
3219 #define NFP_IOCTL 'n'
3220 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3221 /*
3222  * Serving a ioctl command from host NFP tools. This usually goes to
3223  * a kernel driver char driver but it is not available when the PF is
3224  * bound to the PMD. Currently just one ioctl command is served and it
3225  * does not require any CPP access at all.
3226  */
3227 static int
3228 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3229 {
3230         uint32_t cmd, ident_size, tmp;
3231         int err;
3232
3233         /* Reading now the IOCTL command */
3234         err = recv(sockfd, &cmd, 4, 0);
3235         if (err != 4) {
3236                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3237                 return -EIO;
3238         }
3239
3240         /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3241         if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3242                 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3243                 return -EINVAL;
3244         }
3245
3246         err = recv(sockfd, &ident_size, 4, 0);
3247         if (err != 4) {
3248                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3249                 return -EIO;
3250         }
3251
3252         tmp = nfp_cpp_model(cpp);
3253
3254         PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3255
3256         err = send(sockfd, &tmp, 4, 0);
3257         if (err != 4) {
3258                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3259                 return -EIO;
3260         }
3261
3262         tmp = cpp->interface;
3263
3264         PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3265
3266         err = send(sockfd, &tmp, 4, 0);
3267         if (err != 4) {
3268                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3269                 return -EIO;
3270         }
3271
3272         return 0;
3273 }
3274
3275 #define NFP_BRIDGE_OP_READ      20
3276 #define NFP_BRIDGE_OP_WRITE     30
3277 #define NFP_BRIDGE_OP_IOCTL     40
3278
3279 /*
3280  * This is the code to be executed by a service core. The CPP bridge interface
3281  * is based on a unix socket and requests usually received by a kernel char
3282  * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3283  * can be executed with a wrapper library and LD_LIBRARY being completely
3284  * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3285  * accesses.
3286  */
3287 static int32_t
3288 nfp_cpp_bridge_service_func(void *args)
3289 {
3290         struct sockaddr address;
3291         struct nfp_cpp *cpp = args;
3292         int sockfd, datafd, op, ret;
3293
3294         unlink("/tmp/nfp_cpp");
3295         sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3296         if (sockfd < 0) {
3297                 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3298                         __func__);
3299                 return -EIO;
3300         }
3301
3302         memset(&address, 0, sizeof(struct sockaddr));
3303
3304         address.sa_family = AF_UNIX;
3305         strcpy(address.sa_data, "/tmp/nfp_cpp");
3306
3307         ret = bind(sockfd, (const struct sockaddr *)&address,
3308                    sizeof(struct sockaddr));
3309         if (ret < 0) {
3310                 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3311                                   __func__, errno);
3312                 close(sockfd);
3313                 return ret;
3314         }
3315
3316         ret = listen(sockfd, 20);
3317         if (ret < 0) {
3318                 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3319                                   __func__, errno);
3320                 close(sockfd);
3321                 return ret;
3322         }
3323
3324         for (;;) {
3325                 datafd = accept(sockfd, NULL, NULL);
3326                 if (datafd < 0) {
3327                         RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3328                                           __func__, errno);
3329                         RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3330                         close(sockfd);
3331                         return -EIO;
3332                 }
3333
3334                 while (1) {
3335                         ret = recv(datafd, &op, 4, 0);
3336                         if (ret <= 0) {
3337                                 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3338                                                    __func__);
3339                                 break;
3340                         }
3341
3342                         PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3343
3344                         if (op == NFP_BRIDGE_OP_READ)
3345                                 nfp_cpp_bridge_serve_read(datafd, cpp);
3346
3347                         if (op == NFP_BRIDGE_OP_WRITE)
3348                                 nfp_cpp_bridge_serve_write(datafd, cpp);
3349
3350                         if (op == NFP_BRIDGE_OP_IOCTL)
3351                                 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3352
3353                         if (op == 0)
3354                                 break;
3355                 }
3356                 close(datafd);
3357         }
3358         close(sockfd);
3359
3360         return 0;
3361 }
3362
3363 static int
3364 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3365                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3366                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3367 {
3368         struct rte_eth_dev *eth_dev;
3369         struct nfp_net_hw *hw = NULL;
3370         char *port_name;
3371         struct rte_service_spec service;
3372         int retval;
3373
3374         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3375         if (!port_name)
3376                 return -ENOMEM;
3377
3378         if (ports > 1)
3379                 snprintf(port_name, 100, "%s_port%d", dev->device.name, port);
3380         else
3381                 strlcat(port_name, dev->device.name, 100);
3382
3383
3384         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3385                 eth_dev = rte_eth_dev_allocate(port_name);
3386                 if (!eth_dev) {
3387                         rte_free(port_name);
3388                         return -ENODEV;
3389                 }
3390                 if (port == 0) {
3391                         *priv = rte_zmalloc(port_name,
3392                                             sizeof(struct nfp_net_adapter) *
3393                                             ports, RTE_CACHE_LINE_SIZE);
3394                         if (!*priv) {
3395                                 rte_free(port_name);
3396                                 rte_eth_dev_release_port(eth_dev);
3397                                 return -ENOMEM;
3398                         }
3399                 }
3400                 eth_dev->data->dev_private = *priv;
3401
3402                 /*
3403                  * dev_private pointing to port0 dev_private because we need
3404                  * to configure vNIC bars based on port0 at nfp_net_init.
3405                  * Then dev_private is adjusted per port.
3406                  */
3407                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3408                 hw->cpp = cpp;
3409                 hw->hwinfo = hwinfo;
3410                 hw->sym_tbl = sym_tbl;
3411                 hw->pf_port_idx = phys_port;
3412                 hw->is_pf = 1;
3413                 if (ports > 1)
3414                         hw->pf_multiport_enabled = 1;
3415
3416                 hw->total_ports = ports;
3417         } else {
3418                 eth_dev = rte_eth_dev_attach_secondary(port_name);
3419                 if (!eth_dev) {
3420                         RTE_LOG(ERR, EAL, "secondary process attach failed, "
3421                                 "ethdev doesn't exist");
3422                         rte_free(port_name);
3423                         return -ENODEV;
3424                 }
3425                 eth_dev->process_private = cpp;
3426         }
3427
3428         eth_dev->device = &dev->device;
3429         rte_eth_copy_pci_info(eth_dev, dev);
3430
3431         retval = nfp_net_init(eth_dev);
3432
3433         if (retval) {
3434                 retval = -ENODEV;
3435                 goto probe_failed;
3436         } else {
3437                 rte_eth_dev_probing_finish(eth_dev);
3438         }
3439
3440         rte_free(port_name);
3441
3442         if (port == 0) {
3443                 /*
3444                  * The rte_service needs to be created just once per PMD.
3445                  * And the cpp handler needs to be linked to the service.
3446                  * Secondary processes will be used for debugging DPDK apps
3447                  * when requiring to use the CPP interface for accessing NFP
3448                  * components. And the cpp handler for secondary processes is
3449                  * available at this point.
3450                  */
3451                 memset(&service, 0, sizeof(struct rte_service_spec));
3452                 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3453                 service.callback = nfp_cpp_bridge_service_func;
3454                 service.callback_userdata = (void *)cpp;
3455
3456                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private);
3457
3458                 if (rte_service_component_register(&service,
3459                                                    &hw->nfp_cpp_service_id))
3460                         RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3461                 else
3462                         RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3463         }
3464
3465         return retval;
3466
3467 probe_failed:
3468         rte_free(port_name);
3469         /* free ports private data if primary process */
3470         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3471                 rte_free(eth_dev->data->dev_private);
3472                 eth_dev->data->dev_private = NULL;
3473         }
3474         rte_eth_dev_release_port(eth_dev);
3475
3476         return retval;
3477 }
3478
3479 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
3480
3481 static int
3482 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3483 {
3484         struct nfp_cpp *cpp = nsp->cpp;
3485         int fw_f;
3486         char *fw_buf;
3487         char fw_name[125];
3488         char serial[40];
3489         struct stat file_stat;
3490         off_t fsize, bytes;
3491
3492         /* Looking for firmware file in order of priority */
3493
3494         /* First try to find a firmware image specific for this device */
3495         snprintf(serial, sizeof(serial),
3496                         "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3497                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3498                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3499                 cpp->interface & 0xff);
3500
3501         snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3502                         serial);
3503
3504         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3505         fw_f = open(fw_name, O_RDONLY);
3506         if (fw_f >= 0)
3507                 goto read_fw;
3508
3509         /* Then try the PCI name */
3510         snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3511                         dev->device.name);
3512
3513         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3514         fw_f = open(fw_name, O_RDONLY);
3515         if (fw_f >= 0)
3516                 goto read_fw;
3517
3518         /* Finally try the card type and media */
3519         snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3520         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3521         fw_f = open(fw_name, O_RDONLY);
3522         if (fw_f < 0) {
3523                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3524                 return -ENOENT;
3525         }
3526
3527 read_fw:
3528         if (fstat(fw_f, &file_stat) < 0) {
3529                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3530                 close(fw_f);
3531                 return -ENOENT;
3532         }
3533
3534         fsize = file_stat.st_size;
3535         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3536                             fw_name, (uint64_t)fsize);
3537
3538         fw_buf = malloc((size_t)fsize);
3539         if (!fw_buf) {
3540                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3541                 close(fw_f);
3542                 return -ENOMEM;
3543         }
3544         memset(fw_buf, 0, fsize);
3545
3546         bytes = read(fw_f, fw_buf, fsize);
3547         if (bytes != fsize) {
3548                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3549                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3550                                    (uint64_t)bytes, (uint64_t)fsize);
3551                 free(fw_buf);
3552                 close(fw_f);
3553                 return -EIO;
3554         }
3555
3556         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3557         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3558         PMD_DRV_LOG(INFO, "Done");
3559
3560         free(fw_buf);
3561         close(fw_f);
3562
3563         return 0;
3564 }
3565
3566 static int
3567 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3568              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3569 {
3570         struct nfp_nsp *nsp;
3571         const char *nfp_fw_model;
3572         char card_desc[100];
3573         int err = 0;
3574
3575         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3576
3577         if (nfp_fw_model) {
3578                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3579         } else {
3580                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3581                 return -EIO;
3582         }
3583
3584         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3585                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3586                        nfp_eth_table->count);
3587                 return -EIO;
3588         }
3589
3590         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3591                            nfp_eth_table->count);
3592
3593         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3594
3595         snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3596                         nfp_fw_model, nfp_eth_table->count,
3597                         nfp_eth_table->ports[0].speed / 1000);
3598
3599         nsp = nfp_nsp_open(cpp);
3600         if (!nsp) {
3601                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3602                 return -EIO;
3603         }
3604
3605         nfp_nsp_device_soft_reset(nsp);
3606         err = nfp_fw_upload(dev, nsp, card_desc);
3607
3608         nfp_nsp_close(nsp);
3609         return err;
3610 }
3611
3612 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3613                             struct rte_pci_device *dev)
3614 {
3615         struct nfp_cpp *cpp;
3616         struct nfp_hwinfo *hwinfo;
3617         struct nfp_rtsym_table *sym_tbl;
3618         struct nfp_eth_table *nfp_eth_table = NULL;
3619         int total_ports;
3620         void *priv = 0;
3621         int ret = -ENODEV;
3622         int err;
3623         int i;
3624
3625         if (!dev)
3626                 return ret;
3627
3628         /*
3629          * When device bound to UIO, the device could be used, by mistake,
3630          * by two DPDK apps, and the UIO driver does not avoid it. This
3631          * could lead to a serious problem when configuring the NFP CPP
3632          * interface. Here we avoid this telling to the CPP init code to
3633          * use a lock file if UIO is being used.
3634          */
3635         if (dev->kdrv == RTE_PCI_KDRV_VFIO)
3636                 cpp = nfp_cpp_from_device_name(dev, 0);
3637         else
3638                 cpp = nfp_cpp_from_device_name(dev, 1);
3639
3640         if (!cpp) {
3641                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3642                 ret = -EIO;
3643                 goto error;
3644         }
3645
3646         hwinfo = nfp_hwinfo_read(cpp);
3647         if (!hwinfo) {
3648                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3649                 return -EIO;
3650         }
3651
3652         nfp_eth_table = nfp_eth_read_ports(cpp);
3653         if (!nfp_eth_table) {
3654                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3655                 return -EIO;
3656         }
3657
3658         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3659                 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3660                         PMD_DRV_LOG(INFO, "Error when uploading firmware");
3661                         ret = -EIO;
3662                         goto error;
3663                 }
3664         }
3665
3666         /* Now the symbol table should be there */
3667         sym_tbl = nfp_rtsym_table_read(cpp);
3668         if (!sym_tbl) {
3669                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3670                                 " symbol table");
3671                 ret = -EIO;
3672                 goto error;
3673         }
3674
3675         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3676         if (total_ports != (int)nfp_eth_table->count) {
3677                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3678                 ret = -EIO;
3679                 goto error;
3680         }
3681         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3682
3683         if (total_ports <= 0 || total_ports > 8) {
3684                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3685                 ret = -ENODEV;
3686                 goto error;
3687         }
3688
3689         for (i = 0; i < total_ports; i++) {
3690                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3691                                         nfp_eth_table->ports[i].index,
3692                                         sym_tbl, &priv);
3693                 if (ret)
3694                         break;
3695         }
3696
3697 error:
3698         free(nfp_eth_table);
3699         return ret;
3700 }
3701
3702 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3703         {
3704                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3705                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3706         },
3707         {
3708                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3709                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3710         },
3711         {
3712                 .vendor_id = 0,
3713         },
3714 };
3715
3716 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3717         {
3718                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3719                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3720         },
3721         {
3722                 .vendor_id = 0,
3723         },
3724 };
3725
3726 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3727         struct rte_pci_device *pci_dev)
3728 {
3729         return rte_eth_dev_pci_generic_probe(pci_dev,
3730                 sizeof(struct nfp_net_adapter), nfp_net_init);
3731 }
3732
3733 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3734 {
3735         struct rte_eth_dev *eth_dev;
3736         struct nfp_net_hw *hw, *hwport0;
3737         int port = 0;
3738
3739         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3740         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3741             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3742                 port = get_pf_port_number(eth_dev->data->name);
3743                 /*
3744                  * hotplug is not possible with multiport PF although freeing
3745                  * data structures can be done for first port.
3746                  */
3747                 if (port != 0)
3748                         return -ENOTSUP;
3749                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3750                 hw = &hwport0[port];
3751                 nfp_cpp_area_free(hw->ctrl_area);
3752                 nfp_cpp_area_free(hw->hwqueues_area);
3753                 free(hw->hwinfo);
3754                 free(hw->sym_tbl);
3755                 nfp_cpp_free(hw->cpp);
3756         } else {
3757                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3758         }
3759         /* hotplug is not possible with multiport PF */
3760         if (hw->pf_multiport_enabled)
3761                 return -ENOTSUP;
3762         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3763 }
3764
3765 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3766         .id_table = pci_id_nfp_pf_net_map,
3767         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3768         .probe = nfp_pf_pci_probe,
3769         .remove = eth_nfp_pci_remove,
3770 };
3771
3772 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3773         .id_table = pci_id_nfp_vf_net_map,
3774         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3775         .probe = eth_nfp_pci_probe,
3776         .remove = eth_nfp_pci_remove,
3777 };
3778
3779 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3780 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3781 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3782 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3783 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3784 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3785 RTE_LOG_REGISTER(nfp_logtype_init, pmd.net.nfp.init, NOTICE);
3786 RTE_LOG_REGISTER(nfp_logtype_driver, pmd.net.nfp.driver, NOTICE);
3787 /*
3788  * Local variables:
3789  * c-file-style: "Linux"
3790  * indent-tabs-mode: t
3791  * End:
3792  */