2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
59 #include "nfp_net_pmd.h"
60 #include "nfp_net_logs.h"
61 #include "nfp_net_ctrl.h"
64 static void nfp_net_close(struct rte_eth_dev *dev);
65 static int nfp_net_configure(struct rte_eth_dev *dev);
66 static void nfp_net_dev_interrupt_handler(void *param);
67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
70 struct rte_eth_dev_info *dev_info);
71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
80 static void nfp_net_rx_queue_release(void *rxq);
81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
82 uint16_t nb_desc, unsigned int socket_id,
83 const struct rte_eth_rxconf *rx_conf,
84 struct rte_mempool *mp);
85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
86 static void nfp_net_tx_queue_release(void *txq);
87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_txconf *tx_conf);
90 static int nfp_net_start(struct rte_eth_dev *dev);
91 static int nfp_net_stats_get(struct rte_eth_dev *dev,
92 struct rte_eth_stats *stats);
93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
94 static void nfp_net_stop(struct rte_eth_dev *dev);
95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
99 * The offset of the queue controller queues in the PCIe Target. These
100 * happen to be at the same offset on the NFP6000 and the NFP3200 so
101 * we use a single macro here.
103 #define NFP_PCIE_QUEUE(_q) (0x800 * ((_q) & 0xff))
105 /* Maximum value which can be added to a queue with one transaction */
106 #define NFP_QCP_MAX_ADD 0x7f
108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
109 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
113 NFP_QCP_READ_PTR = 0,
118 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
119 * @q: Base address for queue structure
120 * @ptr: Add to the Read or Write pointer
121 * @val: Value to add to the queue pointer
123 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
130 if (ptr == NFP_QCP_READ_PTR)
131 off = NFP_QCP_QUEUE_ADD_RPTR;
133 off = NFP_QCP_QUEUE_ADD_WPTR;
135 while (val > NFP_QCP_MAX_ADD) {
136 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
137 val -= NFP_QCP_MAX_ADD;
140 nn_writel(rte_cpu_to_le_32(val), q + off);
144 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
145 * @q: Base address for queue structure
146 * @ptr: Read or Write pointer
148 static inline uint32_t
149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
154 if (ptr == NFP_QCP_READ_PTR)
155 off = NFP_QCP_QUEUE_STS_LO;
157 off = NFP_QCP_QUEUE_STS_HI;
159 val = rte_cpu_to_le_32(nn_readl(q + off));
161 if (ptr == NFP_QCP_READ_PTR)
162 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
164 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
168 * Functions to read/write from/to Config BAR
169 * Performs any endian conversion necessary.
171 static inline uint8_t
172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
174 return nn_readb(hw->ctrl_bar + off);
178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
180 nn_writeb(val, hw->ctrl_bar + off);
183 static inline uint32_t
184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
186 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
192 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
195 static inline uint64_t
196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
198 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
204 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
208 * Atomically reads link status information from global structure rte_eth_dev.
211 * - Pointer to the structure rte_eth_dev to read from.
212 * - Pointer to the buffer to be saved with the link status.
215 * - On success, zero.
216 * - On failure, negative value.
219 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
220 struct rte_eth_link *link)
222 struct rte_eth_link *dst = link;
223 struct rte_eth_link *src = &dev->data->dev_link;
225 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
226 *(uint64_t *)src) == 0)
233 * Atomically writes the link status information into global
234 * structure rte_eth_dev.
237 * - Pointer to the structure rte_eth_dev to read from.
238 * - Pointer to the buffer to be saved with the link status.
241 * - On success, zero.
242 * - On failure, negative value.
245 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
246 struct rte_eth_link *link)
248 struct rte_eth_link *dst = &dev->data->dev_link;
249 struct rte_eth_link *src = link;
251 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
252 *(uint64_t *)src) == 0)
259 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
263 if (rxq->rxbufs == NULL)
266 for (i = 0; i < rxq->rx_count; i++) {
267 if (rxq->rxbufs[i].mbuf) {
268 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
269 rxq->rxbufs[i].mbuf = NULL;
275 nfp_net_rx_queue_release(void *rx_queue)
277 struct nfp_net_rxq *rxq = rx_queue;
280 nfp_net_rx_queue_release_mbufs(rxq);
281 rte_free(rxq->rxbufs);
287 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
289 nfp_net_rx_queue_release_mbufs(rxq);
295 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
299 if (txq->txbufs == NULL)
302 for (i = 0; i < txq->tx_count; i++) {
303 if (txq->txbufs[i].mbuf) {
304 rte_pktmbuf_free(txq->txbufs[i].mbuf);
305 txq->txbufs[i].mbuf = NULL;
311 nfp_net_tx_queue_release(void *tx_queue)
313 struct nfp_net_txq *txq = tx_queue;
316 nfp_net_tx_queue_release_mbufs(txq);
317 rte_free(txq->txbufs);
323 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
325 nfp_net_tx_queue_release_mbufs(txq);
331 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
335 struct timespec wait;
337 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
340 if (hw->qcp_cfg == NULL)
341 rte_panic("Bad configuration queue pointer\n");
343 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
346 wait.tv_nsec = 1000000;
348 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
350 /* Poll update field, waiting for NFP to ack the config */
351 for (cnt = 0; ; cnt++) {
352 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
355 if (new & NFP_NET_CFG_UPDATE_ERR) {
356 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
359 if (cnt >= NFP_NET_POLL_TIMEOUT) {
360 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
361 " %dms", update, cnt);
362 rte_panic("Exiting\n");
364 nanosleep(&wait, 0); /* waiting for a 1ms */
366 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
371 * Reconfigure the NIC
372 * @nn: device to reconfigure
373 * @ctrl: The value for the ctrl field in the BAR config
374 * @update: The value for the update field in the BAR config
376 * Write the update word to the BAR and ping the reconfig queue. Then poll
377 * until the firmware has acknowledged the update by zeroing the update word.
380 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
384 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
387 rte_spinlock_lock(&hw->reconfig_lock);
389 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
390 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
394 err = __nfp_net_reconfig(hw, update);
396 rte_spinlock_unlock(&hw->reconfig_lock);
402 * Reconfig errors imply situations where they can be handled.
403 * Otherwise, rte_panic is called inside __nfp_net_reconfig
405 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
411 * Configure an Ethernet device. This function must be invoked first
412 * before any other function in the Ethernet API. This function can
413 * also be re-invoked when a device is in the stopped state.
416 nfp_net_configure(struct rte_eth_dev *dev)
418 struct rte_eth_conf *dev_conf;
419 struct rte_eth_rxmode *rxmode;
420 struct rte_eth_txmode *txmode;
421 uint32_t new_ctrl = 0;
423 struct nfp_net_hw *hw;
425 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
428 * A DPDK app sends info about how many queues to use and how
429 * those queues need to be configured. This is used by the
430 * DPDK core and it makes sure no more queues than those
431 * advertised by the driver are requested. This function is
432 * called after that internal process
435 PMD_INIT_LOG(DEBUG, "Configure");
437 dev_conf = &dev->data->dev_conf;
438 rxmode = &dev_conf->rxmode;
439 txmode = &dev_conf->txmode;
441 /* Checking TX mode */
442 if (txmode->mq_mode) {
443 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
447 /* Checking RX mode */
448 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
449 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
450 update = NFP_NET_CFG_UPDATE_RSS;
451 new_ctrl = NFP_NET_CFG_CTRL_RSS;
453 PMD_INIT_LOG(INFO, "RSS not supported");
458 if (rxmode->split_hdr_size) {
459 PMD_INIT_LOG(INFO, "rxmode does not support split header");
463 if (rxmode->hw_ip_checksum) {
464 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
465 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
467 PMD_INIT_LOG(INFO, "RXCSUM not supported");
472 if (rxmode->hw_vlan_filter) {
473 PMD_INIT_LOG(INFO, "VLAN filter not supported");
477 if (rxmode->hw_vlan_strip) {
478 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
479 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
481 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
486 if (rxmode->hw_vlan_extend) {
487 PMD_INIT_LOG(INFO, "VLAN extended not supported");
491 if (rxmode->jumbo_frame)
492 hw->mtu = rxmode->max_rx_pkt_len;
494 if (!rxmode->hw_strip_crc)
495 PMD_INIT_LOG(INFO, "HW does strip CRC and it is not configurable");
497 if (rxmode->enable_scatter) {
498 PMD_INIT_LOG(INFO, "Scatter not supported");
502 /* If next capabilities are supported, configure them by default */
505 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
506 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
509 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
510 new_ctrl |= NFP_NET_CFG_CTRL_L2BC;
513 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
514 new_ctrl |= NFP_NET_CFG_CTRL_L2MC;
516 /* TX checksum offload */
517 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
518 new_ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
521 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
522 new_ctrl |= NFP_NET_CFG_CTRL_LSO;
525 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
526 new_ctrl |= NFP_NET_CFG_CTRL_GATHER;
531 update |= NFP_NET_CFG_UPDATE_GEN;
533 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
534 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
543 nfp_net_enable_queues(struct rte_eth_dev *dev)
545 struct nfp_net_hw *hw;
546 uint64_t enabled_queues = 0;
549 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
551 /* Enabling the required TX queues in the device */
552 for (i = 0; i < dev->data->nb_tx_queues; i++)
553 enabled_queues |= (1 << i);
555 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
559 /* Enabling the required RX queues in the device */
560 for (i = 0; i < dev->data->nb_rx_queues; i++)
561 enabled_queues |= (1 << i);
563 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
567 nfp_net_disable_queues(struct rte_eth_dev *dev)
569 struct nfp_net_hw *hw;
570 uint32_t new_ctrl, update = 0;
572 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
574 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
575 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
577 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
578 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
579 NFP_NET_CFG_UPDATE_MSIX;
581 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
582 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
584 /* If an error when reconfig we avoid to change hw state */
585 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
592 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
596 for (i = 0; i < dev->data->nb_rx_queues; i++) {
597 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
604 nfp_net_params_setup(struct nfp_net_hw *hw)
606 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
607 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
611 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
613 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
616 #define ETH_ADDR_LEN 6
619 nfp_eth_copy_mac_reverse(uint8_t *dst, const uint8_t *src)
623 for (i = 0; i < ETH_ADDR_LEN; i++)
624 dst[ETH_ADDR_LEN - i - 1] = src[i];
628 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
630 union eth_table_entry *entry;
634 entry = hw->eth_table;
636 /* Reading NFP ethernet table obtained before */
637 for (i = 0; i < NSP_ETH_MAX_COUNT; i++) {
638 if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) {
639 /* port not in use */
649 if (i == NSP_ETH_MAX_COUNT)
653 * hw points to port0 private data. We need hw now pointing to
657 nfp_eth_copy_mac_reverse((uint8_t *)&hw->mac_addr,
658 (uint8_t *)&entry->mac_addr);
664 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
668 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
669 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
671 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
672 memcpy(&hw->mac_addr[4], &tmp, 2);
676 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
678 uint32_t mac0 = *(uint32_t *)mac;
681 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
684 mac1 = *(uint16_t *)mac;
685 nn_writew(rte_cpu_to_be_16(mac1),
686 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
690 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
691 struct rte_intr_handle *intr_handle)
693 struct nfp_net_hw *hw;
696 if (!intr_handle->intr_vec) {
697 intr_handle->intr_vec =
698 rte_zmalloc("intr_vec",
699 dev->data->nb_rx_queues * sizeof(int), 0);
700 if (!intr_handle->intr_vec) {
701 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
702 " intr_vec", dev->data->nb_rx_queues);
707 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
709 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
710 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
711 /* UIO just supports one queue and no LSC*/
712 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
713 intr_handle->intr_vec[0] = 0;
715 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
716 for (i = 0; i < dev->data->nb_rx_queues; i++) {
718 * The first msix vector is reserved for non
721 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
722 intr_handle->intr_vec[i] = i + 1;
723 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
724 intr_handle->intr_vec[i]);
728 /* Avoiding TX interrupts */
729 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
734 nfp_net_start(struct rte_eth_dev *dev)
736 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
737 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
738 uint32_t new_ctrl, update = 0;
739 struct nfp_net_hw *hw;
740 uint32_t intr_vector;
743 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
745 PMD_INIT_LOG(DEBUG, "Start");
747 /* Disabling queues just in case... */
748 nfp_net_disable_queues(dev);
750 /* Writing configuration parameters in the device */
751 nfp_net_params_setup(hw);
753 /* Enabling the required queues in the device */
754 nfp_net_enable_queues(dev);
756 /* check and configure queue intr-vector mapping */
757 if (dev->data->dev_conf.intr_conf.rxq != 0) {
758 if (hw->pf_multiport_enabled) {
759 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
760 "with NFP multiport PF");
763 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
765 * Better not to share LSC with RX interrupts.
766 * Unregistering LSC interrupt handler
768 rte_intr_callback_unregister(&pci_dev->intr_handle,
769 nfp_net_dev_interrupt_handler, (void *)dev);
771 if (dev->data->nb_rx_queues > 1) {
772 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
773 "supports 1 queue with UIO");
777 intr_vector = dev->data->nb_rx_queues;
778 if (rte_intr_efd_enable(intr_handle, intr_vector))
781 nfp_configure_rx_interrupt(dev, intr_handle);
782 update = NFP_NET_CFG_UPDATE_MSIX;
785 rte_intr_enable(intr_handle);
788 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
790 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
792 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
793 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
795 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
796 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
800 * Allocating rte mbuffs for configured rx queues.
801 * This requires queues being enabled before
803 if (nfp_net_rx_freelist_setup(dev) < 0) {
809 /* Configure the physical port up */
810 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 1);
818 * An error returned by this function should mean the app
819 * exiting and then the system releasing all the memory
820 * allocated even memory coming from hugepages.
822 * The device could be enabled at this point with some queues
823 * ready for getting packets. This is true if the call to
824 * nfp_net_rx_freelist_setup() succeeds for some queues but
825 * fails for subsequent queues.
827 * This should make the app exiting but better if we tell the
830 nfp_net_disable_queues(dev);
835 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
837 nfp_net_stop(struct rte_eth_dev *dev)
840 struct nfp_net_hw *hw;
842 PMD_INIT_LOG(DEBUG, "Stop");
844 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
846 nfp_net_disable_queues(dev);
849 for (i = 0; i < dev->data->nb_tx_queues; i++) {
850 nfp_net_reset_tx_queue(
851 (struct nfp_net_txq *)dev->data->tx_queues[i]);
854 for (i = 0; i < dev->data->nb_rx_queues; i++) {
855 nfp_net_reset_rx_queue(
856 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
860 /* Configure the physical port down */
861 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 0);
864 /* Reset and stop device. The device can not be restarted. */
866 nfp_net_close(struct rte_eth_dev *dev)
868 struct nfp_net_hw *hw;
869 struct rte_pci_device *pci_dev;
872 PMD_INIT_LOG(DEBUG, "Close");
874 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
875 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
878 * We assume that the DPDK application is stopping all the
879 * threads/queues before calling the device close function.
882 nfp_net_disable_queues(dev);
885 for (i = 0; i < dev->data->nb_tx_queues; i++) {
886 nfp_net_reset_tx_queue(
887 (struct nfp_net_txq *)dev->data->tx_queues[i]);
890 for (i = 0; i < dev->data->nb_rx_queues; i++) {
891 nfp_net_reset_rx_queue(
892 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
895 rte_intr_disable(&pci_dev->intr_handle);
896 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
898 /* unregister callback func from eal lib */
899 rte_intr_callback_unregister(&pci_dev->intr_handle,
900 nfp_net_dev_interrupt_handler,
904 * The ixgbe PMD driver disables the pcie master on the
905 * device. The i40e does not...
910 nfp_net_promisc_enable(struct rte_eth_dev *dev)
912 uint32_t new_ctrl, update = 0;
913 struct nfp_net_hw *hw;
915 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
917 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
919 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
920 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
924 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
925 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
929 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
930 update = NFP_NET_CFG_UPDATE_GEN;
933 * DPDK sets promiscuous mode on just after this call assuming
934 * it can not fail ...
936 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
943 nfp_net_promisc_disable(struct rte_eth_dev *dev)
945 uint32_t new_ctrl, update = 0;
946 struct nfp_net_hw *hw;
948 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
950 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
951 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
955 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
956 update = NFP_NET_CFG_UPDATE_GEN;
959 * DPDK sets promiscuous mode off just before this call
960 * assuming it can not fail ...
962 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
969 * return 0 means link status changed, -1 means not changed
971 * Wait to complete is needed as it can take up to 9 seconds to get the Link
975 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
977 struct nfp_net_hw *hw;
978 struct rte_eth_link link, old;
979 uint32_t nn_link_status;
981 static const uint32_t ls_to_ethtool[] = {
982 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
983 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
984 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
985 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
986 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
987 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
988 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
989 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
992 PMD_DRV_LOG(DEBUG, "Link update\n");
994 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
996 memset(&old, 0, sizeof(old));
997 nfp_net_dev_atomic_read_link_status(dev, &old);
999 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1001 memset(&link, 0, sizeof(struct rte_eth_link));
1003 if (nn_link_status & NFP_NET_CFG_STS_LINK)
1004 link.link_status = ETH_LINK_UP;
1006 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1008 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1009 NFP_NET_CFG_STS_LINK_RATE_MASK;
1011 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1012 link.link_speed = ETH_SPEED_NUM_NONE;
1014 link.link_speed = ls_to_ethtool[nn_link_status];
1016 if (old.link_status != link.link_status) {
1017 nfp_net_dev_atomic_write_link_status(dev, &link);
1018 if (link.link_status)
1019 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
1021 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
1029 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1032 struct nfp_net_hw *hw;
1033 struct rte_eth_stats nfp_dev_stats;
1035 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1039 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1041 /* reading per RX ring stats */
1042 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1043 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1046 nfp_dev_stats.q_ipackets[i] =
1047 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1049 nfp_dev_stats.q_ipackets[i] -=
1050 hw->eth_stats_base.q_ipackets[i];
1052 nfp_dev_stats.q_ibytes[i] =
1053 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1055 nfp_dev_stats.q_ibytes[i] -=
1056 hw->eth_stats_base.q_ibytes[i];
1059 /* reading per TX ring stats */
1060 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1061 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1064 nfp_dev_stats.q_opackets[i] =
1065 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1067 nfp_dev_stats.q_opackets[i] -=
1068 hw->eth_stats_base.q_opackets[i];
1070 nfp_dev_stats.q_obytes[i] =
1071 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1073 nfp_dev_stats.q_obytes[i] -=
1074 hw->eth_stats_base.q_obytes[i];
1077 nfp_dev_stats.ipackets =
1078 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1080 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1082 nfp_dev_stats.ibytes =
1083 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1085 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1087 nfp_dev_stats.opackets =
1088 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1090 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1092 nfp_dev_stats.obytes =
1093 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1095 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1097 /* reading general device stats */
1098 nfp_dev_stats.ierrors =
1099 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1101 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1103 nfp_dev_stats.oerrors =
1104 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1106 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1108 /* RX ring mbuf allocation failures */
1109 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1111 nfp_dev_stats.imissed =
1112 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1114 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1117 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1124 nfp_net_stats_reset(struct rte_eth_dev *dev)
1127 struct nfp_net_hw *hw;
1129 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1132 * hw->eth_stats_base records the per counter starting point.
1133 * Lets update it now
1136 /* reading per RX ring stats */
1137 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1138 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1141 hw->eth_stats_base.q_ipackets[i] =
1142 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1144 hw->eth_stats_base.q_ibytes[i] =
1145 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1148 /* reading per TX ring stats */
1149 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1150 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1153 hw->eth_stats_base.q_opackets[i] =
1154 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1156 hw->eth_stats_base.q_obytes[i] =
1157 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1160 hw->eth_stats_base.ipackets =
1161 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1163 hw->eth_stats_base.ibytes =
1164 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1166 hw->eth_stats_base.opackets =
1167 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1169 hw->eth_stats_base.obytes =
1170 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1172 /* reading general device stats */
1173 hw->eth_stats_base.ierrors =
1174 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1176 hw->eth_stats_base.oerrors =
1177 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1179 /* RX ring mbuf allocation failures */
1180 dev->data->rx_mbuf_alloc_failed = 0;
1182 hw->eth_stats_base.imissed =
1183 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1187 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1189 struct nfp_net_hw *hw;
1191 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1193 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1194 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1195 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1196 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1197 dev_info->max_rx_pktlen = hw->max_mtu;
1198 /* Next should change when PF support is implemented */
1199 dev_info->max_mac_addrs = 1;
1201 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1202 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1204 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1205 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1206 DEV_RX_OFFLOAD_UDP_CKSUM |
1207 DEV_RX_OFFLOAD_TCP_CKSUM;
1209 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1210 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1212 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1213 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1214 DEV_TX_OFFLOAD_UDP_CKSUM |
1215 DEV_TX_OFFLOAD_TCP_CKSUM;
1217 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1219 .pthresh = DEFAULT_RX_PTHRESH,
1220 .hthresh = DEFAULT_RX_HTHRESH,
1221 .wthresh = DEFAULT_RX_WTHRESH,
1223 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1227 dev_info->default_txconf = (struct rte_eth_txconf) {
1229 .pthresh = DEFAULT_TX_PTHRESH,
1230 .hthresh = DEFAULT_TX_HTHRESH,
1231 .wthresh = DEFAULT_TX_WTHRESH,
1233 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1234 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1235 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1236 ETH_TXQ_FLAGS_NOOFFLOADS,
1239 dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1240 ETH_RSS_NONFRAG_IPV4_UDP |
1241 ETH_RSS_NONFRAG_IPV6_TCP |
1242 ETH_RSS_NONFRAG_IPV6_UDP;
1244 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1245 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1247 dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1248 ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1249 ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1251 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1252 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1255 static const uint32_t *
1256 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1258 static const uint32_t ptypes[] = {
1259 /* refers to nfp_net_set_hash() */
1260 RTE_PTYPE_INNER_L3_IPV4,
1261 RTE_PTYPE_INNER_L3_IPV6,
1262 RTE_PTYPE_INNER_L3_IPV6_EXT,
1263 RTE_PTYPE_INNER_L4_MASK,
1267 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1273 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1275 struct nfp_net_rxq *rxq;
1276 struct nfp_net_rx_desc *rxds;
1280 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1287 * Other PMDs are just checking the DD bit in intervals of 4
1288 * descriptors and counting all four if the first has the DD
1289 * bit on. Of course, this is not accurate but can be good for
1290 * performance. But ideally that should be done in descriptors
1291 * chunks belonging to the same cache line
1294 while (count < rxq->rx_count) {
1295 rxds = &rxq->rxds[idx];
1296 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1303 if ((idx) == rxq->rx_count)
1311 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1313 struct rte_pci_device *pci_dev;
1314 struct nfp_net_hw *hw;
1317 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1318 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1320 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1323 /* Make sure all updates are written before un-masking */
1325 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1326 NFP_NET_CFG_ICR_UNMASKED);
1331 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1333 struct rte_pci_device *pci_dev;
1334 struct nfp_net_hw *hw;
1337 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1338 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1340 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1343 /* Make sure all updates are written before un-masking */
1345 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1350 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1352 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1353 struct rte_eth_link link;
1355 memset(&link, 0, sizeof(link));
1356 nfp_net_dev_atomic_read_link_status(dev, &link);
1357 if (link.link_status)
1358 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1359 dev->data->port_id, link.link_speed,
1360 link.link_duplex == ETH_LINK_FULL_DUPLEX
1361 ? "full-duplex" : "half-duplex");
1363 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1364 dev->data->port_id);
1366 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1367 pci_dev->addr.domain, pci_dev->addr.bus,
1368 pci_dev->addr.devid, pci_dev->addr.function);
1371 /* Interrupt configuration and handling */
1374 * nfp_net_irq_unmask - Unmask an interrupt
1376 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1377 * clear the ICR for the entry.
1380 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1382 struct nfp_net_hw *hw;
1383 struct rte_pci_device *pci_dev;
1385 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1386 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1388 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1389 /* If MSI-X auto-masking is used, clear the entry */
1391 rte_intr_enable(&pci_dev->intr_handle);
1393 /* Make sure all updates are written before un-masking */
1395 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1396 NFP_NET_CFG_ICR_UNMASKED);
1401 nfp_net_dev_interrupt_handler(void *param)
1404 struct rte_eth_link link;
1405 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1407 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1409 /* get the link status */
1410 memset(&link, 0, sizeof(link));
1411 nfp_net_dev_atomic_read_link_status(dev, &link);
1413 nfp_net_link_update(dev, 0);
1416 if (!link.link_status) {
1417 /* handle it 1 sec later, wait it being stable */
1418 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1419 /* likely to down */
1421 /* handle it 4 sec later, wait it being stable */
1422 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1425 if (rte_eal_alarm_set(timeout * 1000,
1426 nfp_net_dev_interrupt_delayed_handler,
1428 RTE_LOG(ERR, PMD, "Error setting alarm");
1430 nfp_net_irq_unmask(dev);
1435 * Interrupt handler which shall be registered for alarm callback for delayed
1436 * handling specific interrupt to wait for the stable nic state. As the NIC
1437 * interrupt state is not stable for nfp after link is just down, it needs
1438 * to wait 4 seconds to get the stable status.
1440 * @param handle Pointer to interrupt handle.
1441 * @param param The address of parameter (struct rte_eth_dev *)
1446 nfp_net_dev_interrupt_delayed_handler(void *param)
1448 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1450 nfp_net_link_update(dev, 0);
1451 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1453 nfp_net_dev_link_status_print(dev);
1456 nfp_net_irq_unmask(dev);
1460 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1462 struct nfp_net_hw *hw;
1464 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1466 /* check that mtu is within the allowed range */
1467 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1470 /* mtu setting is forbidden if port is started */
1471 if (dev->data->dev_started) {
1472 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1473 dev->data->port_id);
1477 /* switch to jumbo mode if needed */
1478 if ((uint32_t)mtu > ETHER_MAX_LEN)
1479 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1481 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1483 /* update max frame size */
1484 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1486 /* writing to configuration space */
1487 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1495 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1496 uint16_t queue_idx, uint16_t nb_desc,
1497 unsigned int socket_id,
1498 const struct rte_eth_rxconf *rx_conf,
1499 struct rte_mempool *mp)
1501 const struct rte_memzone *tz;
1502 struct nfp_net_rxq *rxq;
1503 struct nfp_net_hw *hw;
1505 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507 PMD_INIT_FUNC_TRACE();
1509 /* Validating number of descriptors */
1510 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1511 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1512 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1513 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1518 * Free memory prior to re-allocation if needed. This is the case after
1519 * calling nfp_net_stop
1521 if (dev->data->rx_queues[queue_idx]) {
1522 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1523 dev->data->rx_queues[queue_idx] = NULL;
1526 /* Allocating rx queue data structure */
1527 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1528 RTE_CACHE_LINE_SIZE, socket_id);
1532 /* Hw queues mapping based on firmware confifguration */
1533 rxq->qidx = queue_idx;
1534 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1535 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1536 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1537 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1540 * Tracking mbuf size for detecting a potential mbuf overflow due to
1544 rxq->mbuf_size = rxq->mem_pool->elt_size;
1545 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1546 hw->flbufsz = rxq->mbuf_size;
1548 rxq->rx_count = nb_desc;
1549 rxq->port_id = dev->data->port_id;
1550 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1551 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1553 rxq->drop_en = rx_conf->rx_drop_en;
1556 * Allocate RX ring hardware descriptors. A memzone large enough to
1557 * handle the maximum ring size is allocated in order to allow for
1558 * resizing in later calls to the queue setup function.
1560 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1561 sizeof(struct nfp_net_rx_desc) *
1562 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1566 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1567 nfp_net_rx_queue_release(rxq);
1571 /* Saving physical and virtual addresses for the RX ring */
1572 rxq->dma = (uint64_t)tz->iova;
1573 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1575 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1576 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1577 sizeof(*rxq->rxbufs) * nb_desc,
1578 RTE_CACHE_LINE_SIZE, socket_id);
1579 if (rxq->rxbufs == NULL) {
1580 nfp_net_rx_queue_release(rxq);
1584 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1585 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1587 nfp_net_reset_rx_queue(rxq);
1589 dev->data->rx_queues[queue_idx] = rxq;
1593 * Telling the HW about the physical address of the RX ring and number
1594 * of descriptors in log2 format
1596 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1597 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1603 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1605 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1609 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1612 for (i = 0; i < rxq->rx_count; i++) {
1613 struct nfp_net_rx_desc *rxd;
1614 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1617 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1618 (unsigned)rxq->qidx);
1622 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1624 rxd = &rxq->rxds[i];
1626 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1627 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1629 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1632 /* Make sure all writes are flushed before telling the hardware */
1635 /* Not advertising the whole ring as the firmware gets confused if so */
1636 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1639 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1645 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1646 uint16_t nb_desc, unsigned int socket_id,
1647 const struct rte_eth_txconf *tx_conf)
1649 const struct rte_memzone *tz;
1650 struct nfp_net_txq *txq;
1651 uint16_t tx_free_thresh;
1652 struct nfp_net_hw *hw;
1654 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656 PMD_INIT_FUNC_TRACE();
1658 /* Validating number of descriptors */
1659 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1660 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1661 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1662 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1666 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1667 tx_conf->tx_free_thresh :
1668 DEFAULT_TX_FREE_THRESH);
1670 if (tx_free_thresh > (nb_desc)) {
1672 "tx_free_thresh must be less than the number of TX "
1673 "descriptors. (tx_free_thresh=%u port=%d "
1674 "queue=%d)\n", (unsigned int)tx_free_thresh,
1675 dev->data->port_id, (int)queue_idx);
1680 * Free memory prior to re-allocation if needed. This is the case after
1681 * calling nfp_net_stop
1683 if (dev->data->tx_queues[queue_idx]) {
1684 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1686 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1687 dev->data->tx_queues[queue_idx] = NULL;
1690 /* Allocating tx queue data structure */
1691 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1692 RTE_CACHE_LINE_SIZE, socket_id);
1694 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1699 * Allocate TX ring hardware descriptors. A memzone large enough to
1700 * handle the maximum ring size is allocated in order to allow for
1701 * resizing in later calls to the queue setup function.
1703 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1704 sizeof(struct nfp_net_tx_desc) *
1705 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1708 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1709 nfp_net_tx_queue_release(txq);
1713 txq->tx_count = nb_desc;
1714 txq->tx_free_thresh = tx_free_thresh;
1715 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1716 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1717 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1719 /* queue mapping based on firmware configuration */
1720 txq->qidx = queue_idx;
1721 txq->tx_qcidx = queue_idx * hw->stride_tx;
1722 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1724 txq->port_id = dev->data->port_id;
1725 txq->txq_flags = tx_conf->txq_flags;
1727 /* Saving physical and virtual addresses for the TX ring */
1728 txq->dma = (uint64_t)tz->iova;
1729 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1731 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1732 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1733 sizeof(*txq->txbufs) * nb_desc,
1734 RTE_CACHE_LINE_SIZE, socket_id);
1735 if (txq->txbufs == NULL) {
1736 nfp_net_tx_queue_release(txq);
1739 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1740 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1742 nfp_net_reset_tx_queue(txq);
1744 dev->data->tx_queues[queue_idx] = txq;
1748 * Telling the HW about the physical address of the TX ring and number
1749 * of descriptors in log2 format
1751 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1752 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1757 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1759 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1760 struct rte_mbuf *mb)
1763 struct nfp_net_hw *hw = txq->hw;
1765 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1768 ol_flags = mb->ol_flags;
1770 if (!(ol_flags & PKT_TX_TCP_SEG))
1773 txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1774 txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1775 txd->flags = PCIE_DESC_TX_LSO;
1784 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1786 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1787 struct rte_mbuf *mb)
1790 struct nfp_net_hw *hw = txq->hw;
1792 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1795 ol_flags = mb->ol_flags;
1797 /* IPv6 does not need checksum */
1798 if (ol_flags & PKT_TX_IP_CKSUM)
1799 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1801 switch (ol_flags & PKT_TX_L4_MASK) {
1802 case PKT_TX_UDP_CKSUM:
1803 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1805 case PKT_TX_TCP_CKSUM:
1806 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1810 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1811 txd->flags |= PCIE_DESC_TX_CSUM;
1814 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1816 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1817 struct rte_mbuf *mb)
1819 struct nfp_net_hw *hw = rxq->hw;
1821 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1824 /* If IPv4 and IP checksum error, fail */
1825 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1826 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1827 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1829 /* If neither UDP nor TCP return */
1830 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1831 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1834 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1835 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1836 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1838 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1839 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1840 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1843 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1844 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1846 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1849 * nfp_net_set_hash - Set mbuf hash data
1851 * The RSS hash and hash-type are pre-pended to the packet data.
1852 * Extract and decode it and set the mbuf fields.
1855 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1856 struct rte_mbuf *mbuf)
1858 struct nfp_net_hw *hw = rxq->hw;
1859 uint8_t *meta_offset;
1862 uint32_t hash_type = 0;
1864 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1867 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1868 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1871 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1872 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1874 } else if (NFP_DESC_META_LEN(rxd)) {
1877 * <---- 32 bit ----->
1882 * ====================
1885 * Field type word contains up to 8 4bit field types
1886 * A 4bit field type refers to a data field word
1887 * A data field word can have several 4bit field types
1889 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1890 meta_offset -= NFP_DESC_META_LEN(rxd);
1891 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1893 /* NFP PMD just supports metadata for hashing */
1894 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1895 case NFP_NET_META_HASH:
1896 /* next field type is about the hash type */
1897 meta_info >>= NFP_NET_META_FIELD_SIZE;
1898 /* hash value is in the data field */
1899 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1900 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1903 /* Unsupported metadata can be a performance issue */
1910 mbuf->hash.rss = hash;
1911 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1913 switch (hash_type) {
1914 case NFP_NET_RSS_IPV4:
1915 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1917 case NFP_NET_RSS_IPV6:
1918 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1920 case NFP_NET_RSS_IPV6_EX:
1921 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1924 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1929 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1931 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1934 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1939 * There are some decissions to take:
1940 * 1) How to check DD RX descriptors bit
1941 * 2) How and when to allocate new mbufs
1943 * Current implementation checks just one single DD bit each loop. As each
1944 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1945 * a single cache line instead. Tests with this change have not shown any
1946 * performance improvement but it requires further investigation. For example,
1947 * depending on which descriptor is next, the number of descriptors could be
1948 * less than 8 for just checking those in the same cache line. This implies
1949 * extra work which could be counterproductive by itself. Indeed, last firmware
1950 * changes are just doing this: writing several descriptors with the DD bit
1951 * for saving PCIe bandwidth and DMA operations from the NFP.
1953 * Mbuf allocation is done when a new packet is received. Then the descriptor
1954 * is automatically linked with the new mbuf and the old one is given to the
1955 * user. The main drawback with this design is mbuf allocation is heavier than
1956 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1957 * cache point of view it does not seem allocating the mbuf early on as we are
1958 * doing now have any benefit at all. Again, tests with this change have not
1959 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1960 * so looking at the implications of this type of allocation should be studied
1965 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1967 struct nfp_net_rxq *rxq;
1968 struct nfp_net_rx_desc *rxds;
1969 struct nfp_net_rx_buff *rxb;
1970 struct nfp_net_hw *hw;
1971 struct rte_mbuf *mb;
1972 struct rte_mbuf *new_mb;
1978 if (unlikely(rxq == NULL)) {
1980 * DPDK just checks the queue is lower than max queues
1981 * enabled. But the queue needs to be configured
1983 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1991 while (avail < nb_pkts) {
1992 rxb = &rxq->rxbufs[rxq->rd_p];
1993 if (unlikely(rxb == NULL)) {
1994 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1999 * Memory barrier to ensure that we won't do other
2000 * reads before the DD bit.
2004 rxds = &rxq->rxds[rxq->rd_p];
2005 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2009 * We got a packet. Let's alloc a new mbuff for refilling the
2010 * free descriptor ring as soon as possible
2012 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2013 if (unlikely(new_mb == NULL)) {
2014 RTE_LOG_DP(DEBUG, PMD,
2015 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2016 rxq->port_id, (unsigned int)rxq->qidx);
2017 nfp_net_mbuf_alloc_failed(rxq);
2024 * Grab the mbuff and refill the descriptor with the
2025 * previously allocated mbuff
2030 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
2031 rxds->rxd.data_len, rxq->mbuf_size);
2033 /* Size of this segment */
2034 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2035 /* Size of the whole packet. We just support 1 segment */
2036 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2038 if (unlikely((mb->data_len + hw->rx_offset) >
2041 * This should not happen and the user has the
2042 * responsibility of avoiding it. But we have
2043 * to give some info about the error
2045 RTE_LOG_DP(ERR, PMD,
2046 "mbuf overflow likely due to the RX offset.\n"
2047 "\t\tYour mbuf size should have extra space for"
2048 " RX offset=%u bytes.\n"
2049 "\t\tCurrently you just have %u bytes available"
2050 " but the received packet is %u bytes long",
2052 rxq->mbuf_size - hw->rx_offset,
2057 /* Filling the received mbuff with packet info */
2059 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2061 mb->data_off = RTE_PKTMBUF_HEADROOM +
2062 NFP_DESC_META_LEN(rxds);
2064 /* No scatter mode supported */
2068 /* Checking the RSS flag */
2069 nfp_net_set_hash(rxq, rxds, mb);
2071 /* Checking the checksum flag */
2072 nfp_net_rx_cksum(rxq, rxds, mb);
2074 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2075 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2076 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2077 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2080 /* Adding the mbuff to the mbuff array passed by the app */
2081 rx_pkts[avail++] = mb;
2083 /* Now resetting and updating the descriptor */
2086 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2088 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2089 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2092 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2099 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
2100 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2102 nb_hold += rxq->nb_rx_hold;
2105 * FL descriptors needs to be written before incrementing the
2106 * FL queue WR pointer
2109 if (nb_hold > rxq->rx_free_thresh) {
2110 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2111 rxq->port_id, (unsigned int)rxq->qidx,
2112 (unsigned)nb_hold, (unsigned)avail);
2113 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2116 rxq->nb_rx_hold = nb_hold;
2122 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2124 * @txq: TX queue to work with
2125 * Returns number of descriptors freed
2128 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2133 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2134 " status\n", txq->qidx);
2136 /* Work out how many packets have been sent */
2137 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2139 if (qcp_rd_p == txq->rd_p) {
2140 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2141 "packets (%u, %u)\n", txq->qidx,
2142 qcp_rd_p, txq->rd_p);
2146 if (qcp_rd_p > txq->rd_p)
2147 todo = qcp_rd_p - txq->rd_p;
2149 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2151 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2152 qcp_rd_p, txq->rd_p, txq->rd_p);
2158 if (unlikely(txq->rd_p >= txq->tx_count))
2159 txq->rd_p -= txq->tx_count;
2164 /* Leaving always free descriptors for avoiding wrapping confusion */
2166 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2168 if (txq->wr_p >= txq->rd_p)
2169 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2171 return txq->rd_p - txq->wr_p - 8;
2175 * nfp_net_txq_full - Check if the TX queue free descriptors
2176 * is below tx_free_threshold
2178 * @txq: TX queue to check
2180 * This function uses the host copy* of read/write pointers
2183 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2185 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2189 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2191 struct nfp_net_txq *txq;
2192 struct nfp_net_hw *hw;
2193 struct nfp_net_tx_desc *txds, txd;
2194 struct rte_mbuf *pkt;
2196 int pkt_size, dma_size;
2197 uint16_t free_descs, issued_descs;
2198 struct rte_mbuf **lmbuf;
2203 txds = &txq->txds[txq->wr_p];
2205 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2206 txq->qidx, txq->wr_p, nb_pkts);
2208 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2209 nfp_net_tx_free_bufs(txq);
2211 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2212 if (unlikely(free_descs == 0))
2219 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2220 txq->qidx, nb_pkts);
2221 /* Sending packets */
2222 while ((i < nb_pkts) && free_descs) {
2223 /* Grabbing the mbuf linked to the current descriptor */
2224 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2225 /* Warming the cache for releasing the mbuf later on */
2226 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2228 pkt = *(tx_pkts + i);
2230 if (unlikely((pkt->nb_segs > 1) &&
2231 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2232 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2233 rte_panic("Multisegment packet unsupported\n");
2236 /* Checking if we have enough descriptors */
2237 if (unlikely(pkt->nb_segs > free_descs))
2241 * Checksum and VLAN flags just in the first descriptor for a
2242 * multisegment packet, but TSO info needs to be in all of them.
2244 txd.data_len = pkt->pkt_len;
2245 nfp_net_tx_tso(txq, &txd, pkt);
2246 nfp_net_tx_cksum(txq, &txd, pkt);
2248 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2249 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2250 txd.flags |= PCIE_DESC_TX_VLAN;
2251 txd.vlan = pkt->vlan_tci;
2255 * mbuf data_len is the data in one segment and pkt_len data
2256 * in the whole packet. When the packet is just one segment,
2257 * then data_len = pkt_len
2259 pkt_size = pkt->pkt_len;
2262 /* Copying TSO, VLAN and cksum info */
2265 /* Releasing mbuf used by this descriptor previously*/
2267 rte_pktmbuf_free_seg(*lmbuf);
2270 * Linking mbuf with descriptor for being released
2271 * next time descriptor is used
2275 dma_size = pkt->data_len;
2276 dma_addr = rte_mbuf_data_iova(pkt);
2277 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2278 "%" PRIx64 "\n", dma_addr);
2280 /* Filling descriptors fields */
2281 txds->dma_len = dma_size;
2282 txds->data_len = txd.data_len;
2283 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2284 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2285 ASSERT(free_descs > 0);
2289 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2292 pkt_size -= dma_size;
2295 txds->offset_eop |= PCIE_DESC_TX_EOP;
2297 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2300 /* Referencing next free TX descriptor */
2301 txds = &txq->txds[txq->wr_p];
2302 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2309 /* Increment write pointers. Force memory write before we let HW know */
2311 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2317 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2319 uint32_t new_ctrl, update;
2320 struct nfp_net_hw *hw;
2323 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2327 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2328 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2329 " ETH_VLAN_EXTEND_OFFLOAD");
2331 /* Enable vlan strip if it is not configured yet */
2332 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2333 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2334 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2336 /* Disable vlan strip just if it is configured */
2337 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2338 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2339 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2344 update = NFP_NET_CFG_UPDATE_GEN;
2346 ret = nfp_net_reconfig(hw, new_ctrl, update);
2348 hw->ctrl = new_ctrl;
2353 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2355 nfp_net_reta_update(struct rte_eth_dev *dev,
2356 struct rte_eth_rss_reta_entry64 *reta_conf,
2359 uint32_t reta, mask;
2363 struct nfp_net_hw *hw =
2364 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2369 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2370 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2371 "(%d) doesn't match the number hardware can supported "
2372 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2377 * Update Redirection Table. There are 128 8bit-entries which can be
2378 * manage as 32 32bit-entries
2380 for (i = 0; i < reta_size; i += 4) {
2381 /* Handling 4 RSS entries per loop */
2382 idx = i / RTE_RETA_GROUP_SIZE;
2383 shift = i % RTE_RETA_GROUP_SIZE;
2384 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2390 /* If all 4 entries were set, don't need read RETA register */
2392 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2394 for (j = 0; j < 4; j++) {
2395 if (!(mask & (0x1 << j)))
2398 /* Clearing the entry bits */
2399 reta &= ~(0xFF << (8 * j));
2400 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2402 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2406 update = NFP_NET_CFG_UPDATE_RSS;
2408 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2414 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2416 nfp_net_reta_query(struct rte_eth_dev *dev,
2417 struct rte_eth_rss_reta_entry64 *reta_conf,
2423 struct nfp_net_hw *hw;
2425 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2430 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2431 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2432 "(%d) doesn't match the number hardware can supported "
2433 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2438 * Reading Redirection Table. There are 128 8bit-entries which can be
2439 * manage as 32 32bit-entries
2441 for (i = 0; i < reta_size; i += 4) {
2442 /* Handling 4 RSS entries per loop */
2443 idx = i / RTE_RETA_GROUP_SIZE;
2444 shift = i % RTE_RETA_GROUP_SIZE;
2445 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2450 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2452 for (j = 0; j < 4; j++) {
2453 if (!(mask & (0x1 << j)))
2455 reta_conf->reta[shift + j] =
2456 (uint8_t)((reta >> (8 * j)) & 0xF);
2463 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2464 struct rte_eth_rss_conf *rss_conf)
2467 uint32_t cfg_rss_ctrl = 0;
2471 struct nfp_net_hw *hw;
2473 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475 rss_hf = rss_conf->rss_hf;
2477 /* Checking if RSS is enabled */
2478 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2479 if (rss_hf != 0) { /* Enable RSS? */
2480 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2483 return 0; /* Nothing to do */
2486 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2487 RTE_LOG(ERR, PMD, "hash key too long\n");
2491 if (rss_hf & ETH_RSS_IPV4)
2492 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2493 NFP_NET_CFG_RSS_IPV4_TCP |
2494 NFP_NET_CFG_RSS_IPV4_UDP;
2496 if (rss_hf & ETH_RSS_IPV6)
2497 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2498 NFP_NET_CFG_RSS_IPV6_TCP |
2499 NFP_NET_CFG_RSS_IPV6_UDP;
2501 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2502 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2504 /* configuring where to apply the RSS hash */
2505 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2507 /* Writing the key byte a byte */
2508 for (i = 0; i < rss_conf->rss_key_len; i++) {
2509 memcpy(&key, &rss_conf->rss_key[i], 1);
2510 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2513 /* Writing the key size */
2514 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2516 update = NFP_NET_CFG_UPDATE_RSS;
2518 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2525 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2526 struct rte_eth_rss_conf *rss_conf)
2529 uint32_t cfg_rss_ctrl;
2532 struct nfp_net_hw *hw;
2534 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2539 rss_hf = rss_conf->rss_hf;
2540 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2542 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2543 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2545 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2546 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2548 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2549 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2551 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2552 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2554 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2555 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2557 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2558 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2560 /* Reading the key size */
2561 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2563 /* Reading the key byte a byte */
2564 for (i = 0; i < rss_conf->rss_key_len; i++) {
2565 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2566 memcpy(&rss_conf->rss_key[i], &key, 1);
2572 /* Initialise and register driver with DPDK Application */
2573 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2574 .dev_configure = nfp_net_configure,
2575 .dev_start = nfp_net_start,
2576 .dev_stop = nfp_net_stop,
2577 .dev_close = nfp_net_close,
2578 .promiscuous_enable = nfp_net_promisc_enable,
2579 .promiscuous_disable = nfp_net_promisc_disable,
2580 .link_update = nfp_net_link_update,
2581 .stats_get = nfp_net_stats_get,
2582 .stats_reset = nfp_net_stats_reset,
2583 .dev_infos_get = nfp_net_infos_get,
2584 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2585 .mtu_set = nfp_net_dev_mtu_set,
2586 .vlan_offload_set = nfp_net_vlan_offload_set,
2587 .reta_update = nfp_net_reta_update,
2588 .reta_query = nfp_net_reta_query,
2589 .rss_hash_update = nfp_net_rss_hash_update,
2590 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2591 .rx_queue_setup = nfp_net_rx_queue_setup,
2592 .rx_queue_release = nfp_net_rx_queue_release,
2593 .rx_queue_count = nfp_net_rx_queue_count,
2594 .tx_queue_setup = nfp_net_tx_queue_setup,
2595 .tx_queue_release = nfp_net_tx_queue_release,
2596 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2597 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2601 * All eth_dev created got its private data, but before nfp_net_init, that
2602 * private data is referencing private data for all the PF ports. This is due
2603 * to how the vNIC bars are mapped based on first port, so all ports need info
2604 * about port 0 private data. Inside nfp_net_init the private data pointer is
2605 * changed to the right address for each port once the bars have been mapped.
2607 * This functions helps to find out which port and therefore which offset
2608 * inside the private data array to use.
2611 get_pf_port_number(char *name)
2613 char *pf_str = name;
2616 while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2621 * This should not happen at all and it would mean major
2622 * implementation fault.
2624 rte_panic("nfp_net: problem with pf device name\n");
2626 /* Expecting _portX with X within [0,7] */
2629 return (int)strtol(pf_str, NULL, 10);
2633 nfp_net_init(struct rte_eth_dev *eth_dev)
2635 struct rte_pci_device *pci_dev;
2636 struct nfp_net_hw *hw, *hwport0;
2638 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2642 nspu_desc_t *nspu_desc = NULL;
2643 uint64_t bar_offset;
2646 PMD_INIT_FUNC_TRACE();
2648 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2650 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2651 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2652 port = get_pf_port_number(eth_dev->data->name);
2653 if (port < 0 || port > 7) {
2654 RTE_LOG(ERR, PMD, "Port value is wrong\n");
2658 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2660 /* This points to port 0 private data */
2661 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2663 /* This points to the specific port private data */
2664 hw = &hwport0[port];
2665 hw->pf_port_idx = port;
2667 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2671 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2672 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2673 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2675 /* For secondary processes, the primary has done all the work */
2676 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2679 rte_eth_copy_pci_info(eth_dev, pci_dev);
2681 hw->device_id = pci_dev->id.device_id;
2682 hw->vendor_id = pci_dev->id.vendor_id;
2683 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2684 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2686 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2687 pci_dev->id.vendor_id, pci_dev->id.device_id,
2688 pci_dev->addr.domain, pci_dev->addr.bus,
2689 pci_dev->addr.devid, pci_dev->addr.function);
2691 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2692 if (hw->ctrl_bar == NULL) {
2694 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2698 if (hw->is_pf && port == 0) {
2699 nspu_desc = hw->nspu_desc;
2701 if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
2703 * A firmware should be there after PF probe so this
2704 * should not happen.
2706 RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
2710 /* vNIC PF control BAR is a subset of PF PCI device BAR */
2711 hw->ctrl_bar += bar_offset;
2712 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2716 if (!hwport0->ctrl_bar)
2719 /* address based on port0 offset */
2720 hw->ctrl_bar = hwport0->ctrl_bar +
2721 (port * NFP_PF_CSR_SLICE_SIZE);
2724 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2726 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2727 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2729 /* Work out where in the BAR the queues start. */
2730 switch (pci_dev->id.device_id) {
2731 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2732 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2733 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2734 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2735 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2736 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2737 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2740 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2744 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2745 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2747 if (hw->is_pf && port == 0) {
2748 /* configure access to tx/rx vNIC BARs */
2749 nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
2750 PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
2752 hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
2754 /* vNIC PF tx/rx BARs are a subset of PF PCI device */
2755 hwport0->hw_queues += bar_offset;
2757 /* Lets seize the chance to read eth table from hw */
2758 if (nfp_nsp_eth_read_table(nspu_desc, &hw->eth_table))
2763 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2764 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2765 eth_dev->data->dev_private = hw;
2767 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2769 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2773 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2774 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2776 nfp_net_cfg_queue_setup(hw);
2778 /* Get some of the read-only fields from the config BAR */
2779 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2780 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2781 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2782 hw->mtu = ETHER_MTU;
2784 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2785 hw->rx_offset = NFP_NET_RX_OFFSET;
2787 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2789 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2790 hw->ver, hw->max_mtu);
2791 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2792 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2793 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2794 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2795 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2796 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2797 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2798 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2799 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2800 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2801 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2802 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2806 hw->stride_rx = stride;
2807 hw->stride_tx = stride;
2809 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2810 hw->max_rx_queues, hw->max_tx_queues);
2812 /* Initializing spinlock for reconfigs */
2813 rte_spinlock_init(&hw->reconfig_lock);
2815 /* Allocating memory for mac addr */
2816 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2817 if (eth_dev->data->mac_addrs == NULL) {
2818 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2823 nfp_net_pf_read_mac(hwport0, port);
2824 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2826 nfp_net_vf_read_mac(hw);
2829 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2830 /* Using random mac addresses for VFs */
2831 eth_random_addr(&hw->mac_addr[0]);
2832 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2835 /* Copying mac address to DPDK eth_dev struct */
2836 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2837 ð_dev->data->mac_addrs[0]);
2839 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2840 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2841 eth_dev->data->port_id, pci_dev->id.vendor_id,
2842 pci_dev->id.device_id,
2843 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2844 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2846 /* Registering LSC interrupt handler */
2847 rte_intr_callback_register(&pci_dev->intr_handle,
2848 nfp_net_dev_interrupt_handler,
2851 /* Telling the firmware about the LSC interrupt entry */
2852 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2854 /* Recording current stats counters values */
2855 nfp_net_stats_reset(eth_dev);
2861 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2862 nfpu_desc_t *nfpu_desc, void **priv)
2864 struct rte_eth_dev *eth_dev;
2865 struct nfp_net_hw *hw;
2869 port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2874 sprintf(port_name, "%s_port%d", dev->device.name, port);
2876 sprintf(port_name, "%s", dev->device.name);
2878 eth_dev = rte_eth_dev_allocate(port_name);
2883 *priv = rte_zmalloc(port_name,
2884 sizeof(struct nfp_net_adapter) * ports,
2885 RTE_CACHE_LINE_SIZE);
2887 rte_eth_dev_release_port(eth_dev);
2892 eth_dev->data->dev_private = *priv;
2895 * dev_private pointing to port0 dev_private because we need
2896 * to configure vNIC bars based on port0 at nfp_net_init.
2897 * Then dev_private is adjusted per port.
2899 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2900 hw->nspu_desc = nfpu_desc->nspu;
2901 hw->nfpu_desc = nfpu_desc;
2904 hw->pf_multiport_enabled = 1;
2906 eth_dev->device = &dev->device;
2907 rte_eth_copy_pci_info(eth_dev, dev);
2909 ret = nfp_net_init(eth_dev);
2912 rte_eth_dev_release_port(eth_dev);
2914 rte_free(port_name);
2919 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2920 struct rte_pci_device *dev)
2922 nfpu_desc_t *nfpu_desc;
2923 nspu_desc_t *nspu_desc;
2924 uint64_t offset_symbol;
2925 uint8_t *bar_offset;
2935 nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
2939 if (nfpu_open(dev, nfpu_desc, 0) < 0) {
2941 "nfpu_open failed\n");
2945 nspu_desc = nfpu_desc->nspu;
2948 /* Check NSP ABI version */
2949 if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
2950 RTE_LOG(INFO, PMD, "NFP NSP not present\n");
2953 PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
2955 if ((major == 0) && (minor < 20)) {
2956 RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
2960 ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
2965 bar_offset = (uint8_t *)dev->mem_resource[0].addr;
2966 bar_offset += offset_symbol;
2967 total_ports = (uint32_t)*bar_offset;
2968 PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
2970 if (total_ports <= 0 || total_ports > 8) {
2971 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
2976 for (i = 0; i < total_ports; i++) {
2977 ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv);
2985 nfpu_close(nfpu_desc);
2987 rte_free(nfpu_desc);
2992 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
2994 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2995 PCI_DEVICE_ID_NFP4000_PF_NIC)
2998 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2999 PCI_DEVICE_ID_NFP6000_PF_NIC)
3006 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3008 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3009 PCI_DEVICE_ID_NFP6000_VF_NIC)
3016 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3017 struct rte_pci_device *pci_dev)
3019 return rte_eth_dev_pci_generic_probe(pci_dev,
3020 sizeof(struct nfp_net_adapter), nfp_net_init);
3023 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3025 struct rte_eth_dev *eth_dev;
3026 struct nfp_net_hw *hw, *hwport0;
3029 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3030 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3031 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3032 port = get_pf_port_number(eth_dev->data->name);
3033 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3034 hw = &hwport0[port];
3036 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3038 /* hotplug is not possible with multiport PF */
3039 if (hw->pf_multiport_enabled)
3041 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3044 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3045 .id_table = pci_id_nfp_pf_net_map,
3046 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3047 .probe = nfp_pf_pci_probe,
3048 .remove = eth_nfp_pci_remove,
3051 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3052 .id_table = pci_id_nfp_vf_net_map,
3053 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3054 .probe = eth_nfp_pci_probe,
3055 .remove = eth_nfp_pci_remove,
3058 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3059 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3060 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3061 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3062 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3063 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3067 * c-file-style: "Linux"
3068 * indent-tabs-mode: t