2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
47 #include <rte_debug.h>
48 #include <rte_ethdev.h>
49 #include <rte_ethdev_pci.h>
51 #include <rte_ether.h>
52 #include <rte_malloc.h>
53 #include <rte_memzone.h>
54 #include <rte_mempool.h>
55 #include <rte_version.h>
56 #include <rte_string_fns.h>
57 #include <rte_alarm.h>
58 #include <rte_spinlock.h>
60 #include "nfp_net_pmd.h"
61 #include "nfp_net_logs.h"
62 #include "nfp_net_ctrl.h"
65 static void nfp_net_close(struct rte_eth_dev *dev);
66 static int nfp_net_configure(struct rte_eth_dev *dev);
67 static void nfp_net_dev_interrupt_handler(void *param);
68 static void nfp_net_dev_interrupt_delayed_handler(void *param);
69 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
70 static void nfp_net_infos_get(struct rte_eth_dev *dev,
71 struct rte_eth_dev_info *dev_info);
72 static int nfp_net_init(struct rte_eth_dev *eth_dev);
73 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
74 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
75 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
76 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
77 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
79 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
81 static void nfp_net_rx_queue_release(void *rxq);
82 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
83 uint16_t nb_desc, unsigned int socket_id,
84 const struct rte_eth_rxconf *rx_conf,
85 struct rte_mempool *mp);
86 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
87 static void nfp_net_tx_queue_release(void *txq);
88 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
89 uint16_t nb_desc, unsigned int socket_id,
90 const struct rte_eth_txconf *tx_conf);
91 static int nfp_net_start(struct rte_eth_dev *dev);
92 static void nfp_net_stats_get(struct rte_eth_dev *dev,
93 struct rte_eth_stats *stats);
94 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
95 static void nfp_net_stop(struct rte_eth_dev *dev);
96 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
100 * The offset of the queue controller queues in the PCIe Target. These
101 * happen to be at the same offset on the NFP6000 and the NFP3200 so
102 * we use a single macro here.
104 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
106 /* Maximum value which can be added to a queue with one transaction */
107 #define NFP_QCP_MAX_ADD 0x7f
109 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
110 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
112 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
114 NFP_QCP_READ_PTR = 0,
119 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
120 * @q: Base address for queue structure
121 * @ptr: Add to the Read or Write pointer
122 * @val: Value to add to the queue pointer
124 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
127 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
131 if (ptr == NFP_QCP_READ_PTR)
132 off = NFP_QCP_QUEUE_ADD_RPTR;
134 off = NFP_QCP_QUEUE_ADD_WPTR;
136 while (val > NFP_QCP_MAX_ADD) {
137 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
138 val -= NFP_QCP_MAX_ADD;
141 nn_writel(rte_cpu_to_le_32(val), q + off);
145 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
146 * @q: Base address for queue structure
147 * @ptr: Read or Write pointer
149 static inline uint32_t
150 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
155 if (ptr == NFP_QCP_READ_PTR)
156 off = NFP_QCP_QUEUE_STS_LO;
158 off = NFP_QCP_QUEUE_STS_HI;
160 val = rte_cpu_to_le_32(nn_readl(q + off));
162 if (ptr == NFP_QCP_READ_PTR)
163 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
165 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
169 * Functions to read/write from/to Config BAR
170 * Performs any endian conversion necessary.
172 static inline uint8_t
173 nn_cfg_readb(struct nfp_net_hw *hw, int off)
175 return nn_readb(hw->ctrl_bar + off);
179 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
181 nn_writeb(val, hw->ctrl_bar + off);
184 static inline uint32_t
185 nn_cfg_readl(struct nfp_net_hw *hw, int off)
187 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
191 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
193 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
196 static inline uint64_t
197 nn_cfg_readq(struct nfp_net_hw *hw, int off)
199 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
203 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
205 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
209 * Atomically reads link status information from global structure rte_eth_dev.
212 * - Pointer to the structure rte_eth_dev to read from.
213 * - Pointer to the buffer to be saved with the link status.
216 * - On success, zero.
217 * - On failure, negative value.
220 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
221 struct rte_eth_link *link)
223 struct rte_eth_link *dst = link;
224 struct rte_eth_link *src = &dev->data->dev_link;
226 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
227 *(uint64_t *)src) == 0)
234 * Atomically writes the link status information into global
235 * structure rte_eth_dev.
238 * - Pointer to the structure rte_eth_dev to read from.
239 * - Pointer to the buffer to be saved with the link status.
242 * - On success, zero.
243 * - On failure, negative value.
246 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
247 struct rte_eth_link *link)
249 struct rte_eth_link *dst = &dev->data->dev_link;
250 struct rte_eth_link *src = link;
252 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
253 *(uint64_t *)src) == 0)
260 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
264 if (rxq->rxbufs == NULL)
267 for (i = 0; i < rxq->rx_count; i++) {
268 if (rxq->rxbufs[i].mbuf) {
269 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
270 rxq->rxbufs[i].mbuf = NULL;
276 nfp_net_rx_queue_release(void *rx_queue)
278 struct nfp_net_rxq *rxq = rx_queue;
281 nfp_net_rx_queue_release_mbufs(rxq);
282 rte_free(rxq->rxbufs);
288 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
290 nfp_net_rx_queue_release_mbufs(rxq);
296 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
300 if (txq->txbufs == NULL)
303 for (i = 0; i < txq->tx_count; i++) {
304 if (txq->txbufs[i].mbuf) {
305 rte_pktmbuf_free(txq->txbufs[i].mbuf);
306 txq->txbufs[i].mbuf = NULL;
312 nfp_net_tx_queue_release(void *tx_queue)
314 struct nfp_net_txq *txq = tx_queue;
317 nfp_net_tx_queue_release_mbufs(txq);
318 rte_free(txq->txbufs);
324 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
326 nfp_net_tx_queue_release_mbufs(txq);
332 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
336 struct timespec wait;
338 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
341 if (hw->qcp_cfg == NULL)
342 rte_panic("Bad configuration queue pointer\n");
344 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
347 wait.tv_nsec = 1000000;
349 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
351 /* Poll update field, waiting for NFP to ack the config */
352 for (cnt = 0; ; cnt++) {
353 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
356 if (new & NFP_NET_CFG_UPDATE_ERR) {
357 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
360 if (cnt >= NFP_NET_POLL_TIMEOUT) {
361 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
362 " %dms", update, cnt);
363 rte_panic("Exiting\n");
365 nanosleep(&wait, 0); /* waiting for a 1ms */
367 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
372 * Reconfigure the NIC
373 * @nn: device to reconfigure
374 * @ctrl: The value for the ctrl field in the BAR config
375 * @update: The value for the update field in the BAR config
377 * Write the update word to the BAR and ping the reconfig queue. Then poll
378 * until the firmware has acknowledged the update by zeroing the update word.
381 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
385 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
388 rte_spinlock_lock(&hw->reconfig_lock);
390 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
391 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
395 err = __nfp_net_reconfig(hw, update);
397 rte_spinlock_unlock(&hw->reconfig_lock);
403 * Reconfig errors imply situations where they can be handled.
404 * Otherwise, rte_panic is called inside __nfp_net_reconfig
406 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
412 * Configure an Ethernet device. This function must be invoked first
413 * before any other function in the Ethernet API. This function can
414 * also be re-invoked when a device is in the stopped state.
417 nfp_net_configure(struct rte_eth_dev *dev)
419 struct rte_eth_conf *dev_conf;
420 struct rte_eth_rxmode *rxmode;
421 struct rte_eth_txmode *txmode;
422 uint32_t new_ctrl = 0;
424 struct nfp_net_hw *hw;
426 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
429 * A DPDK app sends info about how many queues to use and how
430 * those queues need to be configured. This is used by the
431 * DPDK core and it makes sure no more queues than those
432 * advertised by the driver are requested. This function is
433 * called after that internal process
436 PMD_INIT_LOG(DEBUG, "Configure");
438 dev_conf = &dev->data->dev_conf;
439 rxmode = &dev_conf->rxmode;
440 txmode = &dev_conf->txmode;
442 /* Checking TX mode */
443 if (txmode->mq_mode) {
444 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
448 /* Checking RX mode */
449 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
450 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
451 update = NFP_NET_CFG_UPDATE_RSS;
452 new_ctrl = NFP_NET_CFG_CTRL_RSS;
454 PMD_INIT_LOG(INFO, "RSS not supported");
459 if (rxmode->split_hdr_size) {
460 PMD_INIT_LOG(INFO, "rxmode does not support split header");
464 if (rxmode->hw_ip_checksum) {
465 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
466 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
468 PMD_INIT_LOG(INFO, "RXCSUM not supported");
473 if (rxmode->hw_vlan_filter) {
474 PMD_INIT_LOG(INFO, "VLAN filter not supported");
478 if (rxmode->hw_vlan_strip) {
479 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
480 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
482 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
487 if (rxmode->hw_vlan_extend) {
488 PMD_INIT_LOG(INFO, "VLAN extended not supported");
492 /* Supporting VLAN insertion by default */
493 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
494 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
496 if (rxmode->jumbo_frame)
497 /* this is handled in rte_eth_dev_configure */
499 if (rxmode->hw_strip_crc) {
500 PMD_INIT_LOG(INFO, "strip CRC not supported");
504 if (rxmode->enable_scatter) {
505 PMD_INIT_LOG(INFO, "Scatter not supported");
512 update |= NFP_NET_CFG_UPDATE_GEN;
514 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
515 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
524 nfp_net_enable_queues(struct rte_eth_dev *dev)
526 struct nfp_net_hw *hw;
527 uint64_t enabled_queues = 0;
530 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
532 /* Enabling the required TX queues in the device */
533 for (i = 0; i < dev->data->nb_tx_queues; i++)
534 enabled_queues |= (1 << i);
536 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
540 /* Enabling the required RX queues in the device */
541 for (i = 0; i < dev->data->nb_rx_queues; i++)
542 enabled_queues |= (1 << i);
544 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
548 nfp_net_disable_queues(struct rte_eth_dev *dev)
550 struct nfp_net_hw *hw;
551 uint32_t new_ctrl, update = 0;
553 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
555 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
556 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
558 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
559 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
560 NFP_NET_CFG_UPDATE_MSIX;
562 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
563 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
565 /* If an error when reconfig we avoid to change hw state */
566 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
573 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
577 for (i = 0; i < dev->data->nb_rx_queues; i++) {
578 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
585 nfp_net_params_setup(struct nfp_net_hw *hw)
587 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
588 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
592 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
594 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
597 static void nfp_net_read_mac(struct nfp_net_hw *hw)
601 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
602 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
604 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
605 memcpy(&hw->mac_addr[4], &tmp, 2);
609 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
610 struct rte_intr_handle *intr_handle)
612 struct nfp_net_hw *hw;
615 if (!intr_handle->intr_vec) {
616 intr_handle->intr_vec =
617 rte_zmalloc("intr_vec",
618 dev->data->nb_rx_queues * sizeof(int), 0);
619 if (!intr_handle->intr_vec) {
620 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
621 " intr_vec", dev->data->nb_rx_queues);
626 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
628 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
629 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
630 /* UIO just supports one queue and no LSC*/
631 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
633 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
634 for (i = 0; i < dev->data->nb_rx_queues; i++)
636 * The first msix vector is reserved for non
639 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
642 /* Avoiding TX interrupts */
643 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
648 nfp_net_start(struct rte_eth_dev *dev)
650 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
651 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
652 uint32_t new_ctrl, update = 0;
653 struct nfp_net_hw *hw;
654 uint32_t intr_vector;
657 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
659 PMD_INIT_LOG(DEBUG, "Start");
661 /* Disabling queues just in case... */
662 nfp_net_disable_queues(dev);
664 /* Writing configuration parameters in the device */
665 nfp_net_params_setup(hw);
667 /* Enabling the required queues in the device */
668 nfp_net_enable_queues(dev);
670 /* check and configure queue intr-vector mapping */
671 if (dev->data->dev_conf.intr_conf.rxq != 0) {
672 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
674 * Better not to share LSC with RX interrupts.
675 * Unregistering LSC interrupt handler
677 rte_intr_callback_unregister(&pci_dev->intr_handle,
678 nfp_net_dev_interrupt_handler, (void *)dev);
680 if (dev->data->nb_rx_queues > 1) {
681 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
682 "supports 1 queue with UIO");
686 intr_vector = dev->data->nb_rx_queues;
687 if (rte_intr_efd_enable(intr_handle, intr_vector))
691 if (rte_intr_dp_is_en(intr_handle))
692 nfp_configure_rx_interrupt(dev, intr_handle);
694 rte_intr_enable(intr_handle);
697 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
698 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
700 /* Just configuring queues interrupts when necessary */
701 if (rte_intr_dp_is_en(intr_handle))
702 update |= NFP_NET_CFG_UPDATE_MSIX;
704 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
705 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
707 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
708 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
712 * Allocating rte mbuffs for configured rx queues.
713 * This requires queues being enabled before
715 if (nfp_net_rx_freelist_setup(dev) < 0) {
726 * An error returned by this function should mean the app
727 * exiting and then the system releasing all the memory
728 * allocated even memory coming from hugepages.
730 * The device could be enabled at this point with some queues
731 * ready for getting packets. This is true if the call to
732 * nfp_net_rx_freelist_setup() succeeds for some queues but
733 * fails for subsequent queues.
735 * This should make the app exiting but better if we tell the
738 nfp_net_disable_queues(dev);
743 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
745 nfp_net_stop(struct rte_eth_dev *dev)
749 PMD_INIT_LOG(DEBUG, "Stop");
751 nfp_net_disable_queues(dev);
754 for (i = 0; i < dev->data->nb_tx_queues; i++) {
755 nfp_net_reset_tx_queue(
756 (struct nfp_net_txq *)dev->data->tx_queues[i]);
759 for (i = 0; i < dev->data->nb_rx_queues; i++) {
760 nfp_net_reset_rx_queue(
761 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
765 /* Reset and stop device. The device can not be restarted. */
767 nfp_net_close(struct rte_eth_dev *dev)
769 struct nfp_net_hw *hw;
770 struct rte_pci_device *pci_dev;
772 PMD_INIT_LOG(DEBUG, "Close");
774 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
775 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
778 * We assume that the DPDK application is stopping all the
779 * threads/queues before calling the device close function.
784 rte_intr_disable(&pci_dev->intr_handle);
785 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
787 /* unregister callback func from eal lib */
788 rte_intr_callback_unregister(&pci_dev->intr_handle,
789 nfp_net_dev_interrupt_handler,
793 * The ixgbe PMD driver disables the pcie master on the
794 * device. The i40e does not...
799 nfp_net_promisc_enable(struct rte_eth_dev *dev)
801 uint32_t new_ctrl, update = 0;
802 struct nfp_net_hw *hw;
804 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
806 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
808 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
809 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
813 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
814 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
818 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
819 update = NFP_NET_CFG_UPDATE_GEN;
822 * DPDK sets promiscuous mode on just after this call assuming
823 * it can not fail ...
825 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
832 nfp_net_promisc_disable(struct rte_eth_dev *dev)
834 uint32_t new_ctrl, update = 0;
835 struct nfp_net_hw *hw;
837 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
839 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
840 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
844 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
845 update = NFP_NET_CFG_UPDATE_GEN;
848 * DPDK sets promiscuous mode off just before this call
849 * assuming it can not fail ...
851 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
858 * return 0 means link status changed, -1 means not changed
860 * Wait to complete is needed as it can take up to 9 seconds to get the Link
864 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
866 struct nfp_net_hw *hw;
867 struct rte_eth_link link, old;
868 uint32_t nn_link_status;
870 static const uint32_t ls_to_ethtool[] = {
871 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
872 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
873 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
874 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
875 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
876 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
877 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
878 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
881 PMD_DRV_LOG(DEBUG, "Link update\n");
883 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
885 memset(&old, 0, sizeof(old));
886 nfp_net_dev_atomic_read_link_status(dev, &old);
888 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
890 memset(&link, 0, sizeof(struct rte_eth_link));
892 if (nn_link_status & NFP_NET_CFG_STS_LINK)
893 link.link_status = ETH_LINK_UP;
895 link.link_duplex = ETH_LINK_FULL_DUPLEX;
897 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
898 NFP_NET_CFG_STS_LINK_RATE_MASK;
900 if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
901 ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
902 (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
903 /* We really do not know the speed wil old firmware */
904 link.link_speed = ETH_SPEED_NUM_NONE;
906 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
907 link.link_speed = ETH_SPEED_NUM_NONE;
909 link.link_speed = ls_to_ethtool[nn_link_status];
912 if (old.link_status != link.link_status) {
913 nfp_net_dev_atomic_write_link_status(dev, &link);
914 if (link.link_status)
915 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
917 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
925 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
928 struct nfp_net_hw *hw;
929 struct rte_eth_stats nfp_dev_stats;
931 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
933 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
935 /* reading per RX ring stats */
936 for (i = 0; i < dev->data->nb_rx_queues; i++) {
937 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
940 nfp_dev_stats.q_ipackets[i] =
941 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
943 nfp_dev_stats.q_ipackets[i] -=
944 hw->eth_stats_base.q_ipackets[i];
946 nfp_dev_stats.q_ibytes[i] =
947 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
949 nfp_dev_stats.q_ibytes[i] -=
950 hw->eth_stats_base.q_ibytes[i];
953 /* reading per TX ring stats */
954 for (i = 0; i < dev->data->nb_tx_queues; i++) {
955 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
958 nfp_dev_stats.q_opackets[i] =
959 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
961 nfp_dev_stats.q_opackets[i] -=
962 hw->eth_stats_base.q_opackets[i];
964 nfp_dev_stats.q_obytes[i] =
965 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
967 nfp_dev_stats.q_obytes[i] -=
968 hw->eth_stats_base.q_obytes[i];
971 nfp_dev_stats.ipackets =
972 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
974 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
976 nfp_dev_stats.ibytes =
977 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
979 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
981 nfp_dev_stats.opackets =
982 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
984 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
986 nfp_dev_stats.obytes =
987 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
989 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
991 /* reading general device stats */
992 nfp_dev_stats.ierrors =
993 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
995 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
997 nfp_dev_stats.oerrors =
998 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1000 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1002 /* RX ring mbuf allocation failures */
1003 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1005 nfp_dev_stats.imissed =
1006 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1008 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1011 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1015 nfp_net_stats_reset(struct rte_eth_dev *dev)
1018 struct nfp_net_hw *hw;
1020 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1023 * hw->eth_stats_base records the per counter starting point.
1024 * Lets update it now
1027 /* reading per RX ring stats */
1028 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1029 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1032 hw->eth_stats_base.q_ipackets[i] =
1033 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1035 hw->eth_stats_base.q_ibytes[i] =
1036 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1039 /* reading per TX ring stats */
1040 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1041 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1044 hw->eth_stats_base.q_opackets[i] =
1045 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1047 hw->eth_stats_base.q_obytes[i] =
1048 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1051 hw->eth_stats_base.ipackets =
1052 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1054 hw->eth_stats_base.ibytes =
1055 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1057 hw->eth_stats_base.opackets =
1058 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1060 hw->eth_stats_base.obytes =
1061 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1063 /* reading general device stats */
1064 hw->eth_stats_base.ierrors =
1065 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1067 hw->eth_stats_base.oerrors =
1068 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1070 /* RX ring mbuf allocation failures */
1071 dev->data->rx_mbuf_alloc_failed = 0;
1073 hw->eth_stats_base.imissed =
1074 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1078 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1080 struct nfp_net_hw *hw;
1082 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1084 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1085 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1086 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1087 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1088 dev_info->max_rx_pktlen = hw->mtu;
1089 /* Next should change when PF support is implemented */
1090 dev_info->max_mac_addrs = 1;
1092 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1093 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1095 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1096 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1097 DEV_RX_OFFLOAD_UDP_CKSUM |
1098 DEV_RX_OFFLOAD_TCP_CKSUM;
1100 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1101 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1103 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1104 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1105 DEV_TX_OFFLOAD_UDP_CKSUM |
1106 DEV_TX_OFFLOAD_TCP_CKSUM;
1108 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1110 .pthresh = DEFAULT_RX_PTHRESH,
1111 .hthresh = DEFAULT_RX_HTHRESH,
1112 .wthresh = DEFAULT_RX_WTHRESH,
1114 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1118 dev_info->default_txconf = (struct rte_eth_txconf) {
1120 .pthresh = DEFAULT_TX_PTHRESH,
1121 .hthresh = DEFAULT_TX_HTHRESH,
1122 .wthresh = DEFAULT_TX_WTHRESH,
1124 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1125 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1126 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1127 ETH_TXQ_FLAGS_NOOFFLOADS,
1130 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1131 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1133 dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1134 ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1135 ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1137 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1138 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1141 static const uint32_t *
1142 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1144 static const uint32_t ptypes[] = {
1145 /* refers to nfp_net_set_hash() */
1146 RTE_PTYPE_INNER_L3_IPV4,
1147 RTE_PTYPE_INNER_L3_IPV6,
1148 RTE_PTYPE_INNER_L3_IPV6_EXT,
1149 RTE_PTYPE_INNER_L4_MASK,
1153 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1159 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1161 struct nfp_net_rxq *rxq;
1162 struct nfp_net_rx_desc *rxds;
1166 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1173 * Other PMDs are just checking the DD bit in intervals of 4
1174 * descriptors and counting all four if the first has the DD
1175 * bit on. Of course, this is not accurate but can be good for
1176 * perfomance. But ideally that should be done in descriptors
1177 * chunks belonging to the same cache line
1180 while (count < rxq->rx_count) {
1181 rxds = &rxq->rxds[idx];
1182 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1189 if ((idx) == rxq->rx_count)
1197 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1199 struct rte_pci_device *pci_dev;
1200 struct nfp_net_hw *hw;
1203 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1204 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1206 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1209 /* Make sure all updates are written before un-masking */
1211 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1212 NFP_NET_CFG_ICR_UNMASKED);
1217 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1219 struct rte_pci_device *pci_dev;
1220 struct nfp_net_hw *hw;
1223 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1226 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1229 /* Make sure all updates are written before un-masking */
1231 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1236 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1238 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1239 struct rte_eth_link link;
1241 memset(&link, 0, sizeof(link));
1242 nfp_net_dev_atomic_read_link_status(dev, &link);
1243 if (link.link_status)
1244 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1245 (int)(dev->data->port_id), (unsigned)link.link_speed,
1246 link.link_duplex == ETH_LINK_FULL_DUPLEX
1247 ? "full-duplex" : "half-duplex");
1249 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1250 (int)(dev->data->port_id));
1252 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1253 pci_dev->addr.domain, pci_dev->addr.bus,
1254 pci_dev->addr.devid, pci_dev->addr.function);
1257 /* Interrupt configuration and handling */
1260 * nfp_net_irq_unmask - Unmask an interrupt
1262 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1263 * clear the ICR for the entry.
1266 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1268 struct nfp_net_hw *hw;
1269 struct rte_pci_device *pci_dev;
1271 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1272 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1274 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1275 /* If MSI-X auto-masking is used, clear the entry */
1277 rte_intr_enable(&pci_dev->intr_handle);
1279 /* Make sure all updates are written before un-masking */
1281 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1282 NFP_NET_CFG_ICR_UNMASKED);
1287 nfp_net_dev_interrupt_handler(void *param)
1290 struct rte_eth_link link;
1291 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1293 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1295 /* get the link status */
1296 memset(&link, 0, sizeof(link));
1297 nfp_net_dev_atomic_read_link_status(dev, &link);
1299 nfp_net_link_update(dev, 0);
1302 if (!link.link_status) {
1303 /* handle it 1 sec later, wait it being stable */
1304 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1305 /* likely to down */
1307 /* handle it 4 sec later, wait it being stable */
1308 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1311 if (rte_eal_alarm_set(timeout * 1000,
1312 nfp_net_dev_interrupt_delayed_handler,
1314 RTE_LOG(ERR, PMD, "Error setting alarm");
1316 nfp_net_irq_unmask(dev);
1321 * Interrupt handler which shall be registered for alarm callback for delayed
1322 * handling specific interrupt to wait for the stable nic state. As the NIC
1323 * interrupt state is not stable for nfp after link is just down, it needs
1324 * to wait 4 seconds to get the stable status.
1326 * @param handle Pointer to interrupt handle.
1327 * @param param The address of parameter (struct rte_eth_dev *)
1332 nfp_net_dev_interrupt_delayed_handler(void *param)
1334 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1336 nfp_net_link_update(dev, 0);
1337 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1339 nfp_net_dev_link_status_print(dev);
1342 nfp_net_irq_unmask(dev);
1346 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1348 struct nfp_net_hw *hw;
1350 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352 /* check that mtu is within the allowed range */
1353 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1356 /* switch to jumbo mode if needed */
1357 if ((uint32_t)mtu > ETHER_MAX_LEN)
1358 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1360 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1362 /* update max frame size */
1363 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1365 /* writing to configuration space */
1366 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1374 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1375 uint16_t queue_idx, uint16_t nb_desc,
1376 unsigned int socket_id,
1377 const struct rte_eth_rxconf *rx_conf,
1378 struct rte_mempool *mp)
1380 const struct rte_memzone *tz;
1381 struct nfp_net_rxq *rxq;
1382 struct nfp_net_hw *hw;
1384 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1386 PMD_INIT_FUNC_TRACE();
1388 /* Validating number of descriptors */
1389 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1390 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1391 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1392 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1397 * Free memory prior to re-allocation if needed. This is the case after
1398 * calling nfp_net_stop
1400 if (dev->data->rx_queues[queue_idx]) {
1401 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1402 dev->data->rx_queues[queue_idx] = NULL;
1405 /* Allocating rx queue data structure */
1406 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1407 RTE_CACHE_LINE_SIZE, socket_id);
1411 /* Hw queues mapping based on firmware confifguration */
1412 rxq->qidx = queue_idx;
1413 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1414 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1415 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1416 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1419 * Tracking mbuf size for detecting a potential mbuf overflow due to
1423 rxq->mbuf_size = rxq->mem_pool->elt_size;
1424 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1425 hw->flbufsz = rxq->mbuf_size;
1427 rxq->rx_count = nb_desc;
1428 rxq->port_id = dev->data->port_id;
1429 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1430 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1432 rxq->drop_en = rx_conf->rx_drop_en;
1435 * Allocate RX ring hardware descriptors. A memzone large enough to
1436 * handle the maximum ring size is allocated in order to allow for
1437 * resizing in later calls to the queue setup function.
1439 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1440 sizeof(struct nfp_net_rx_desc) *
1441 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1445 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1446 nfp_net_rx_queue_release(rxq);
1450 /* Saving physical and virtual addresses for the RX ring */
1451 rxq->dma = (uint64_t)tz->phys_addr;
1452 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1454 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1455 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1456 sizeof(*rxq->rxbufs) * nb_desc,
1457 RTE_CACHE_LINE_SIZE, socket_id);
1458 if (rxq->rxbufs == NULL) {
1459 nfp_net_rx_queue_release(rxq);
1463 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1464 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1466 nfp_net_reset_rx_queue(rxq);
1468 dev->data->rx_queues[queue_idx] = rxq;
1472 * Telling the HW about the physical address of the RX ring and number
1473 * of descriptors in log2 format
1475 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1476 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1482 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1484 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1488 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1491 for (i = 0; i < rxq->rx_count; i++) {
1492 struct nfp_net_rx_desc *rxd;
1493 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1496 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1497 (unsigned)rxq->qidx);
1501 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1503 rxd = &rxq->rxds[i];
1505 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1506 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1508 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1511 /* Make sure all writes are flushed before telling the hardware */
1514 /* Not advertising the whole ring as the firmware gets confused if so */
1515 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1518 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1524 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1525 uint16_t nb_desc, unsigned int socket_id,
1526 const struct rte_eth_txconf *tx_conf)
1528 const struct rte_memzone *tz;
1529 struct nfp_net_txq *txq;
1530 uint16_t tx_free_thresh;
1531 struct nfp_net_hw *hw;
1533 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1535 PMD_INIT_FUNC_TRACE();
1537 /* Validating number of descriptors */
1538 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1539 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1540 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1541 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1545 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1546 tx_conf->tx_free_thresh :
1547 DEFAULT_TX_FREE_THRESH);
1549 if (tx_free_thresh > (nb_desc)) {
1551 "tx_free_thresh must be less than the number of TX "
1552 "descriptors. (tx_free_thresh=%u port=%d "
1553 "queue=%d)\n", (unsigned int)tx_free_thresh,
1554 (int)dev->data->port_id, (int)queue_idx);
1559 * Free memory prior to re-allocation if needed. This is the case after
1560 * calling nfp_net_stop
1562 if (dev->data->tx_queues[queue_idx]) {
1563 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1565 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1566 dev->data->tx_queues[queue_idx] = NULL;
1569 /* Allocating tx queue data structure */
1570 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1571 RTE_CACHE_LINE_SIZE, socket_id);
1573 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1578 * Allocate TX ring hardware descriptors. A memzone large enough to
1579 * handle the maximum ring size is allocated in order to allow for
1580 * resizing in later calls to the queue setup function.
1582 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1583 sizeof(struct nfp_net_tx_desc) *
1584 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1587 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1588 nfp_net_tx_queue_release(txq);
1592 txq->tx_count = nb_desc;
1593 txq->tx_free_thresh = tx_free_thresh;
1594 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1595 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1596 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1598 /* queue mapping based on firmware configuration */
1599 txq->qidx = queue_idx;
1600 txq->tx_qcidx = queue_idx * hw->stride_tx;
1601 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1603 txq->port_id = dev->data->port_id;
1604 txq->txq_flags = tx_conf->txq_flags;
1606 /* Saving physical and virtual addresses for the TX ring */
1607 txq->dma = (uint64_t)tz->phys_addr;
1608 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1610 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1611 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1612 sizeof(*txq->txbufs) * nb_desc,
1613 RTE_CACHE_LINE_SIZE, socket_id);
1614 if (txq->txbufs == NULL) {
1615 nfp_net_tx_queue_release(txq);
1618 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1619 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1621 nfp_net_reset_tx_queue(txq);
1623 dev->data->tx_queues[queue_idx] = txq;
1627 * Telling the HW about the physical address of the TX ring and number
1628 * of descriptors in log2 format
1630 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1631 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1636 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1638 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1639 struct rte_mbuf *mb)
1642 struct nfp_net_hw *hw = txq->hw;
1644 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1647 ol_flags = mb->ol_flags;
1649 if (!(ol_flags & PKT_TX_TCP_SEG))
1652 txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1653 txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1654 txd->flags = PCIE_DESC_TX_LSO;
1663 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1665 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1666 struct rte_mbuf *mb)
1669 struct nfp_net_hw *hw = txq->hw;
1671 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1674 ol_flags = mb->ol_flags;
1676 /* IPv6 does not need checksum */
1677 if (ol_flags & PKT_TX_IP_CKSUM)
1678 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1680 switch (ol_flags & PKT_TX_L4_MASK) {
1681 case PKT_TX_UDP_CKSUM:
1682 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1684 case PKT_TX_TCP_CKSUM:
1685 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1689 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1690 txd->flags |= PCIE_DESC_TX_CSUM;
1693 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1695 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1696 struct rte_mbuf *mb)
1698 struct nfp_net_hw *hw = rxq->hw;
1700 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1703 /* If IPv4 and IP checksum error, fail */
1704 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1705 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1706 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1708 /* If neither UDP nor TCP return */
1709 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1710 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1713 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1714 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1715 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1717 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1718 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1719 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1722 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1723 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1726 * nfp_net_set_hash - Set mbuf hash data
1728 * The RSS hash and hash-type are pre-pended to the packet data.
1729 * Extract and decode it and set the mbuf fields.
1732 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1733 struct rte_mbuf *mbuf)
1737 struct nfp_net_hw *hw = rxq->hw;
1739 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1742 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1745 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1746 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1748 mbuf->hash.rss = hash;
1749 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1751 switch (hash_type) {
1752 case NFP_NET_RSS_IPV4:
1753 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1755 case NFP_NET_RSS_IPV6:
1756 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1758 case NFP_NET_RSS_IPV6_EX:
1759 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1762 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1767 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1769 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1772 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1777 * There are some decissions to take:
1778 * 1) How to check DD RX descriptors bit
1779 * 2) How and when to allocate new mbufs
1781 * Current implementation checks just one single DD bit each loop. As each
1782 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1783 * a single cache line instead. Tests with this change have not shown any
1784 * performance improvement but it requires further investigation. For example,
1785 * depending on which descriptor is next, the number of descriptors could be
1786 * less than 8 for just checking those in the same cache line. This implies
1787 * extra work which could be counterproductive by itself. Indeed, last firmware
1788 * changes are just doing this: writing several descriptors with the DD bit
1789 * for saving PCIe bandwidth and DMA operations from the NFP.
1791 * Mbuf allocation is done when a new packet is received. Then the descriptor
1792 * is automatically linked with the new mbuf and the old one is given to the
1793 * user. The main drawback with this design is mbuf allocation is heavier than
1794 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1795 * cache point of view it does not seem allocating the mbuf early on as we are
1796 * doing now have any benefit at all. Again, tests with this change have not
1797 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1798 * so looking at the implications of this type of allocation should be studied
1803 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1805 struct nfp_net_rxq *rxq;
1806 struct nfp_net_rx_desc *rxds;
1807 struct nfp_net_rx_buff *rxb;
1808 struct nfp_net_hw *hw;
1809 struct rte_mbuf *mb;
1810 struct rte_mbuf *new_mb;
1816 if (unlikely(rxq == NULL)) {
1818 * DPDK just checks the queue is lower than max queues
1819 * enabled. But the queue needs to be configured
1821 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1829 while (avail < nb_pkts) {
1830 rxb = &rxq->rxbufs[rxq->rd_p];
1831 if (unlikely(rxb == NULL)) {
1832 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1837 * Memory barrier to ensure that we won't do other
1838 * reads before the DD bit.
1842 rxds = &rxq->rxds[rxq->rd_p];
1843 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1847 * We got a packet. Let's alloc a new mbuff for refilling the
1848 * free descriptor ring as soon as possible
1850 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1851 if (unlikely(new_mb == NULL)) {
1852 RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1853 "queue_id=%u\n", (unsigned)rxq->port_id,
1854 (unsigned)rxq->qidx);
1855 nfp_net_mbuf_alloc_failed(rxq);
1862 * Grab the mbuff and refill the descriptor with the
1863 * previously allocated mbuff
1868 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1869 rxds->rxd.data_len, rxq->mbuf_size);
1871 /* Size of this segment */
1872 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1873 /* Size of the whole packet. We just support 1 segment */
1874 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1876 if (unlikely((mb->data_len + hw->rx_offset) >
1879 * This should not happen and the user has the
1880 * responsibility of avoiding it. But we have
1881 * to give some info about the error
1883 RTE_LOG_DP(ERR, PMD,
1884 "mbuf overflow likely due to the RX offset.\n"
1885 "\t\tYour mbuf size should have extra space for"
1886 " RX offset=%u bytes.\n"
1887 "\t\tCurrently you just have %u bytes available"
1888 " but the received packet is %u bytes long",
1890 rxq->mbuf_size - hw->rx_offset,
1895 /* Filling the received mbuff with packet info */
1897 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1899 mb->data_off = RTE_PKTMBUF_HEADROOM +
1900 NFP_DESC_META_LEN(rxds);
1902 /* No scatter mode supported */
1906 /* Checking the RSS flag */
1907 nfp_net_set_hash(rxq, rxds, mb);
1909 /* Checking the checksum flag */
1910 nfp_net_rx_cksum(rxq, rxds, mb);
1912 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1913 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1914 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1915 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1918 /* Adding the mbuff to the mbuff array passed by the app */
1919 rx_pkts[avail++] = mb;
1921 /* Now resetting and updating the descriptor */
1924 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1926 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1927 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1930 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
1937 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1938 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1940 nb_hold += rxq->nb_rx_hold;
1943 * FL descriptors needs to be written before incrementing the
1944 * FL queue WR pointer
1947 if (nb_hold > rxq->rx_free_thresh) {
1948 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1949 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1950 (unsigned)nb_hold, (unsigned)avail);
1951 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1954 rxq->nb_rx_hold = nb_hold;
1960 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1962 * @txq: TX queue to work with
1963 * Returns number of descriptors freed
1966 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1971 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1972 " status\n", txq->qidx);
1974 /* Work out how many packets have been sent */
1975 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1977 if (qcp_rd_p == txq->rd_p) {
1978 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1979 "packets (%u, %u)\n", txq->qidx,
1980 qcp_rd_p, txq->rd_p);
1984 if (qcp_rd_p > txq->rd_p)
1985 todo = qcp_rd_p - txq->rd_p;
1987 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
1989 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
1990 qcp_rd_p, txq->rd_p, txq->rd_p);
1996 if (unlikely(txq->rd_p >= txq->tx_count))
1997 txq->rd_p -= txq->tx_count;
2002 /* Leaving always free descriptors for avoiding wrapping confusion */
2004 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2006 if (txq->wr_p >= txq->rd_p)
2007 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2009 return txq->rd_p - txq->wr_p - 8;
2013 * nfp_net_txq_full - Check if the TX queue free descriptors
2014 * is below tx_free_threshold
2016 * @txq: TX queue to check
2018 * This function uses the host copy* of read/write pointers
2021 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2023 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2027 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2029 struct nfp_net_txq *txq;
2030 struct nfp_net_hw *hw;
2031 struct nfp_net_tx_desc *txds, txd;
2032 struct rte_mbuf *pkt;
2034 int pkt_size, dma_size;
2035 uint16_t free_descs, issued_descs;
2036 struct rte_mbuf **lmbuf;
2041 txds = &txq->txds[txq->wr_p];
2043 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2044 txq->qidx, txq->wr_p, nb_pkts);
2046 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2047 nfp_net_tx_free_bufs(txq);
2049 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2050 if (unlikely(free_descs == 0))
2057 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2058 txq->qidx, nb_pkts);
2059 /* Sending packets */
2060 while ((i < nb_pkts) && free_descs) {
2061 /* Grabbing the mbuf linked to the current descriptor */
2062 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2063 /* Warming the cache for releasing the mbuf later on */
2064 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2066 pkt = *(tx_pkts + i);
2068 if (unlikely((pkt->nb_segs > 1) &&
2069 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2070 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2071 rte_panic("Multisegment packet unsupported\n");
2074 /* Checking if we have enough descriptors */
2075 if (unlikely(pkt->nb_segs > free_descs))
2079 * Checksum and VLAN flags just in the first descriptor for a
2080 * multisegment packet, but TSO info needs to be in all of them.
2082 txd.data_len = pkt->pkt_len;
2083 nfp_net_tx_tso(txq, &txd, pkt);
2084 nfp_net_tx_cksum(txq, &txd, pkt);
2086 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2087 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2088 txd.flags |= PCIE_DESC_TX_VLAN;
2089 txd.vlan = pkt->vlan_tci;
2093 * mbuf data_len is the data in one segment and pkt_len data
2094 * in the whole packet. When the packet is just one segment,
2095 * then data_len = pkt_len
2097 pkt_size = pkt->pkt_len;
2100 /* Copying TSO, VLAN and cksum info */
2103 /* Releasing mbuf used by this descriptor previously*/
2105 rte_pktmbuf_free_seg(*lmbuf);
2108 * Linking mbuf with descriptor for being released
2109 * next time descriptor is used
2113 dma_size = pkt->data_len;
2114 dma_addr = rte_mbuf_data_dma_addr(pkt);
2115 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2116 "%" PRIx64 "\n", dma_addr);
2118 /* Filling descriptors fields */
2119 txds->dma_len = dma_size;
2120 txds->data_len = txd.data_len;
2121 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2122 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2123 ASSERT(free_descs > 0);
2127 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2130 pkt_size -= dma_size;
2133 txds->offset_eop |= PCIE_DESC_TX_EOP;
2135 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2138 /* Referencing next free TX descriptor */
2139 txds = &txq->txds[txq->wr_p];
2140 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2147 /* Increment write pointers. Force memory write before we let HW know */
2149 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2155 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2157 uint32_t new_ctrl, update;
2158 struct nfp_net_hw *hw;
2160 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2164 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2165 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2166 " ETH_VLAN_EXTEND_OFFLOAD");
2168 /* Enable vlan strip if it is not configured yet */
2169 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2170 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2171 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2173 /* Disable vlan strip just if it is configured */
2174 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2175 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2176 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2181 update = NFP_NET_CFG_UPDATE_GEN;
2183 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2186 hw->ctrl = new_ctrl;
2189 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2191 nfp_net_reta_update(struct rte_eth_dev *dev,
2192 struct rte_eth_rss_reta_entry64 *reta_conf,
2195 uint32_t reta, mask;
2199 struct nfp_net_hw *hw =
2200 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2205 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2206 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2207 "(%d) doesn't match the number hardware can supported "
2208 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2213 * Update Redirection Table. There are 128 8bit-entries which can be
2214 * manage as 32 32bit-entries
2216 for (i = 0; i < reta_size; i += 4) {
2217 /* Handling 4 RSS entries per loop */
2218 idx = i / RTE_RETA_GROUP_SIZE;
2219 shift = i % RTE_RETA_GROUP_SIZE;
2220 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2226 /* If all 4 entries were set, don't need read RETA register */
2228 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2230 for (j = 0; j < 4; j++) {
2231 if (!(mask & (0x1 << j)))
2234 /* Clearing the entry bits */
2235 reta &= ~(0xFF << (8 * j));
2236 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2238 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2241 update = NFP_NET_CFG_UPDATE_RSS;
2243 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2249 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2251 nfp_net_reta_query(struct rte_eth_dev *dev,
2252 struct rte_eth_rss_reta_entry64 *reta_conf,
2258 struct nfp_net_hw *hw;
2260 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2265 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2266 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2267 "(%d) doesn't match the number hardware can supported "
2268 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2273 * Reading Redirection Table. There are 128 8bit-entries which can be
2274 * manage as 32 32bit-entries
2276 for (i = 0; i < reta_size; i += 4) {
2277 /* Handling 4 RSS entries per loop */
2278 idx = i / RTE_RETA_GROUP_SIZE;
2279 shift = i % RTE_RETA_GROUP_SIZE;
2280 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2285 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2286 for (j = 0; j < 4; j++) {
2287 if (!(mask & (0x1 << j)))
2289 reta_conf->reta[shift + j] =
2290 (uint8_t)((reta >> (8 * j)) & 0xF);
2297 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2298 struct rte_eth_rss_conf *rss_conf)
2301 uint32_t cfg_rss_ctrl = 0;
2305 struct nfp_net_hw *hw;
2307 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2309 rss_hf = rss_conf->rss_hf;
2311 /* Checking if RSS is enabled */
2312 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2313 if (rss_hf != 0) { /* Enable RSS? */
2314 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2317 return 0; /* Nothing to do */
2320 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2321 RTE_LOG(ERR, PMD, "hash key too long\n");
2325 if (rss_hf & ETH_RSS_IPV4)
2326 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2327 NFP_NET_CFG_RSS_IPV4_TCP |
2328 NFP_NET_CFG_RSS_IPV4_UDP;
2330 if (rss_hf & ETH_RSS_IPV6)
2331 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2332 NFP_NET_CFG_RSS_IPV6_TCP |
2333 NFP_NET_CFG_RSS_IPV6_UDP;
2335 /* configuring where to apply the RSS hash */
2336 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2338 /* Writing the key byte a byte */
2339 for (i = 0; i < rss_conf->rss_key_len; i++) {
2340 memcpy(&key, &rss_conf->rss_key[i], 1);
2341 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2344 /* Writing the key size */
2345 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2347 update = NFP_NET_CFG_UPDATE_RSS;
2349 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2356 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2357 struct rte_eth_rss_conf *rss_conf)
2360 uint32_t cfg_rss_ctrl;
2363 struct nfp_net_hw *hw;
2365 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2367 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2370 rss_hf = rss_conf->rss_hf;
2371 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2373 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2374 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2376 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2377 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2379 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2380 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2382 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2383 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2385 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2386 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2388 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2389 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2391 /* Reading the key size */
2392 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2394 /* Reading the key byte a byte */
2395 for (i = 0; i < rss_conf->rss_key_len; i++) {
2396 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2397 memcpy(&rss_conf->rss_key[i], &key, 1);
2403 /* Initialise and register driver with DPDK Application */
2404 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2405 .dev_configure = nfp_net_configure,
2406 .dev_start = nfp_net_start,
2407 .dev_stop = nfp_net_stop,
2408 .dev_close = nfp_net_close,
2409 .promiscuous_enable = nfp_net_promisc_enable,
2410 .promiscuous_disable = nfp_net_promisc_disable,
2411 .link_update = nfp_net_link_update,
2412 .stats_get = nfp_net_stats_get,
2413 .stats_reset = nfp_net_stats_reset,
2414 .dev_infos_get = nfp_net_infos_get,
2415 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2416 .mtu_set = nfp_net_dev_mtu_set,
2417 .vlan_offload_set = nfp_net_vlan_offload_set,
2418 .reta_update = nfp_net_reta_update,
2419 .reta_query = nfp_net_reta_query,
2420 .rss_hash_update = nfp_net_rss_hash_update,
2421 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2422 .rx_queue_setup = nfp_net_rx_queue_setup,
2423 .rx_queue_release = nfp_net_rx_queue_release,
2424 .rx_queue_count = nfp_net_rx_queue_count,
2425 .tx_queue_setup = nfp_net_tx_queue_setup,
2426 .tx_queue_release = nfp_net_tx_queue_release,
2427 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2428 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2432 nfp_net_init(struct rte_eth_dev *eth_dev)
2434 struct rte_pci_device *pci_dev;
2435 struct nfp_net_hw *hw;
2437 uint32_t tx_bar_off, rx_bar_off;
2441 PMD_INIT_FUNC_TRACE();
2443 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2445 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2446 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2447 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2449 /* For secondary processes, the primary has done all the work */
2450 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2453 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2454 rte_eth_copy_pci_info(eth_dev, pci_dev);
2455 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2457 hw->device_id = pci_dev->id.device_id;
2458 hw->vendor_id = pci_dev->id.vendor_id;
2459 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2460 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2462 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2463 pci_dev->id.vendor_id, pci_dev->id.device_id,
2464 pci_dev->addr.domain, pci_dev->addr.bus,
2465 pci_dev->addr.devid, pci_dev->addr.function);
2467 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2468 if (hw->ctrl_bar == NULL) {
2470 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2473 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2474 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2476 /* Work out where in the BAR the queues start. */
2477 switch (pci_dev->id.device_id) {
2478 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2479 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2480 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2481 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2482 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2485 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2489 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x", tx_bar_off);
2490 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x", rx_bar_off);
2492 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2493 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2495 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2496 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2498 nfp_net_cfg_queue_setup(hw);
2500 /* Get some of the read-only fields from the config BAR */
2501 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2502 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2503 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2504 hw->mtu = hw->max_mtu;
2506 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2507 hw->rx_offset = NFP_NET_RX_OFFSET;
2509 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2511 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2512 hw->ver, hw->max_mtu);
2513 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
2514 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2515 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2516 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2517 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2518 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2519 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2520 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2521 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2522 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2526 hw->stride_rx = stride;
2527 hw->stride_tx = stride;
2529 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2530 hw->max_rx_queues, hw->max_tx_queues);
2532 /* Initializing spinlock for reconfigs */
2533 rte_spinlock_init(&hw->reconfig_lock);
2535 /* Allocating memory for mac addr */
2536 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2537 if (eth_dev->data->mac_addrs == NULL) {
2538 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2542 nfp_net_read_mac(hw);
2544 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr))
2545 /* Using random mac addresses for VFs */
2546 eth_random_addr(&hw->mac_addr[0]);
2548 /* Copying mac address to DPDK eth_dev struct */
2549 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2550 ð_dev->data->mac_addrs[0]);
2552 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2553 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2554 eth_dev->data->port_id, pci_dev->id.vendor_id,
2555 pci_dev->id.device_id,
2556 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2557 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2559 /* Registering LSC interrupt handler */
2560 rte_intr_callback_register(&pci_dev->intr_handle,
2561 nfp_net_dev_interrupt_handler,
2564 /* Telling the firmware about the LSC interrupt entry */
2565 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2567 /* Recording current stats counters values */
2568 nfp_net_stats_reset(eth_dev);
2573 static const struct rte_pci_id pci_id_nfp_net_map[] = {
2575 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2576 PCI_DEVICE_ID_NFP6000_PF_NIC)
2579 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2580 PCI_DEVICE_ID_NFP6000_VF_NIC)
2587 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2588 struct rte_pci_device *pci_dev)
2590 return rte_eth_dev_pci_generic_probe(pci_dev,
2591 sizeof(struct nfp_net_adapter), nfp_net_init);
2594 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
2596 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2599 static struct rte_pci_driver rte_nfp_net_pmd = {
2600 .id_table = pci_id_nfp_net_map,
2601 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2602 .probe = eth_nfp_pci_probe,
2603 .remove = eth_nfp_pci_remove,
2606 RTE_PMD_REGISTER_PCI(net_nfp, rte_nfp_net_pmd);
2607 RTE_PMD_REGISTER_PCI_TABLE(net_nfp, pci_id_nfp_net_map);
2608 RTE_PMD_REGISTER_KMOD_DEP(net_nfp, "* igb_uio | uio_pci_generic | vfio-pci");
2612 * c-file-style: "Linux"
2613 * indent-tabs-mode: t