2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
47 #include <rte_debug.h>
48 #include <rte_ethdev.h>
50 #include <rte_ether.h>
51 #include <rte_malloc.h>
52 #include <rte_memzone.h>
53 #include <rte_mempool.h>
54 #include <rte_version.h>
55 #include <rte_string_fns.h>
56 #include <rte_alarm.h>
58 #include "nfp_net_pmd.h"
59 #include "nfp_net_logs.h"
60 #include "nfp_net_ctrl.h"
63 static void nfp_net_close(struct rte_eth_dev *dev);
64 static int nfp_net_configure(struct rte_eth_dev *dev);
65 static void nfp_net_dev_interrupt_handler(struct rte_intr_handle *handle,
67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
70 struct rte_eth_dev_info *dev_info);
71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
80 static void nfp_net_rx_queue_release(void *rxq);
81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
82 uint16_t nb_desc, unsigned int socket_id,
83 const struct rte_eth_rxconf *rx_conf,
84 struct rte_mempool *mp);
85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
86 static void nfp_net_tx_queue_release(void *txq);
87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_txconf *tx_conf);
90 static int nfp_net_start(struct rte_eth_dev *dev);
91 static void nfp_net_stats_get(struct rte_eth_dev *dev,
92 struct rte_eth_stats *stats);
93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
94 static void nfp_net_stop(struct rte_eth_dev *dev);
95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
99 * The offset of the queue controller queues in the PCIe Target. These
100 * happen to be at the same offset on the NFP6000 and the NFP3200 so
101 * we use a single macro here.
103 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
105 /* Maximum value which can be added to a queue with one transaction */
106 #define NFP_QCP_MAX_ADD 0x7f
108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
109 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
113 NFP_QCP_READ_PTR = 0,
118 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
119 * @q: Base address for queue structure
120 * @ptr: Add to the Read or Write pointer
121 * @val: Value to add to the queue pointer
123 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
130 if (ptr == NFP_QCP_READ_PTR)
131 off = NFP_QCP_QUEUE_ADD_RPTR;
133 off = NFP_QCP_QUEUE_ADD_WPTR;
135 while (val > NFP_QCP_MAX_ADD) {
136 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
137 val -= NFP_QCP_MAX_ADD;
140 nn_writel(rte_cpu_to_le_32(val), q + off);
144 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
145 * @q: Base address for queue structure
146 * @ptr: Read or Write pointer
148 static inline uint32_t
149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
154 if (ptr == NFP_QCP_READ_PTR)
155 off = NFP_QCP_QUEUE_STS_LO;
157 off = NFP_QCP_QUEUE_STS_HI;
159 val = rte_cpu_to_le_32(nn_readl(q + off));
161 if (ptr == NFP_QCP_READ_PTR)
162 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
164 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
168 * Functions to read/write from/to Config BAR
169 * Performs any endian conversion necessary.
171 static inline uint8_t
172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
174 return nn_readb(hw->ctrl_bar + off);
178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
180 nn_writeb(val, hw->ctrl_bar + off);
183 static inline uint32_t
184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
186 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
192 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
195 static inline uint64_t
196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
198 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
204 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
207 /* Creating memzone for hardware rings. */
208 static const struct rte_memzone *
209 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
210 uint16_t queue_id, uint32_t ring_size, int socket_id)
212 char z_name[RTE_MEMZONE_NAMESIZE];
213 const struct rte_memzone *mz;
215 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
216 dev->driver->pci_drv.name,
217 ring_name, dev->data->port_id, queue_id);
219 mz = rte_memzone_lookup(z_name);
223 return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
228 * Atomically reads link status information from global structure rte_eth_dev.
231 * - Pointer to the structure rte_eth_dev to read from.
232 * - Pointer to the buffer to be saved with the link status.
235 * - On success, zero.
236 * - On failure, negative value.
239 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
240 struct rte_eth_link *link)
242 struct rte_eth_link *dst = link;
243 struct rte_eth_link *src = &dev->data->dev_link;
245 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
246 *(uint64_t *)src) == 0)
253 * Atomically writes the link status information into global
254 * structure rte_eth_dev.
257 * - Pointer to the structure rte_eth_dev to read from.
258 * - Pointer to the buffer to be saved with the link status.
261 * - On success, zero.
262 * - On failure, negative value.
265 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
266 struct rte_eth_link *link)
268 struct rte_eth_link *dst = &dev->data->dev_link;
269 struct rte_eth_link *src = link;
271 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
272 *(uint64_t *)src) == 0)
279 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
283 if (rxq->rxbufs == NULL)
286 for (i = 0; i < rxq->rx_count; i++) {
287 if (rxq->rxbufs[i].mbuf) {
288 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
289 rxq->rxbufs[i].mbuf = NULL;
295 nfp_net_rx_queue_release(void *rx_queue)
297 struct nfp_net_rxq *rxq = rx_queue;
300 nfp_net_rx_queue_release_mbufs(rxq);
301 rte_free(rxq->rxbufs);
307 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
309 nfp_net_rx_queue_release_mbufs(rxq);
316 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
320 if (txq->txbufs == NULL)
323 for (i = 0; i < txq->tx_count; i++) {
324 if (txq->txbufs[i].mbuf) {
325 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
326 txq->txbufs[i].mbuf = NULL;
332 nfp_net_tx_queue_release(void *tx_queue)
334 struct nfp_net_txq *txq = tx_queue;
337 nfp_net_tx_queue_release_mbufs(txq);
338 rte_free(txq->txbufs);
344 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
346 nfp_net_tx_queue_release_mbufs(txq);
353 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
357 struct timespec wait;
359 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
362 if (hw->qcp_cfg == NULL)
363 rte_panic("Bad configuration queue pointer\n");
365 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
368 wait.tv_nsec = 1000000;
370 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
372 /* Poll update field, waiting for NFP to ack the config */
373 for (cnt = 0; ; cnt++) {
374 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
377 if (new & NFP_NET_CFG_UPDATE_ERR) {
378 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x\n", new);
381 if (cnt >= NFP_NET_POLL_TIMEOUT) {
382 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
383 " %dms\n", update, cnt);
384 rte_panic("Exiting\n");
386 nanosleep(&wait, 0); /* waiting for a 1ms */
388 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
393 * Reconfigure the NIC
394 * @nn: device to reconfigure
395 * @ctrl: The value for the ctrl field in the BAR config
396 * @update: The value for the update field in the BAR config
398 * Write the update word to the BAR and ping the reconfig queue. Then poll
399 * until the firmware has acknowledged the update by zeroing the update word.
402 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
406 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
409 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
410 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
414 err = __nfp_net_reconfig(hw, update);
420 * Reconfig errors imply situations where they can be handled.
421 * Otherwise, rte_panic is called inside __nfp_net_reconfig
423 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x\n",
429 * Configure an Ethernet device. This function must be invoked first
430 * before any other function in the Ethernet API. This function can
431 * also be re-invoked when a device is in the stopped state.
434 nfp_net_configure(struct rte_eth_dev *dev)
436 struct rte_eth_conf *dev_conf;
437 struct rte_eth_rxmode *rxmode;
438 struct rte_eth_txmode *txmode;
439 uint32_t new_ctrl = 0;
441 struct nfp_net_hw *hw;
443 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
446 * A DPDK app sends info about how many queues to use and how
447 * those queues need to be configured. This is used by the
448 * DPDK core and it makes sure no more queues than those
449 * advertised by the driver are requested. This function is
450 * called after that internal process
453 PMD_INIT_LOG(DEBUG, "Configure\n");
455 dev_conf = &dev->data->dev_conf;
456 rxmode = &dev_conf->rxmode;
457 txmode = &dev_conf->txmode;
459 /* Checking TX mode */
460 if (txmode->mq_mode) {
461 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported\n");
465 /* Checking RX mode */
466 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
467 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
468 update = NFP_NET_CFG_UPDATE_RSS;
469 new_ctrl = NFP_NET_CFG_CTRL_RSS;
471 PMD_INIT_LOG(INFO, "RSS not supported\n");
476 if (rxmode->split_hdr_size) {
477 PMD_INIT_LOG(INFO, "rxmode does not support split header\n");
481 if (rxmode->hw_ip_checksum) {
482 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
483 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
485 PMD_INIT_LOG(INFO, "RXCSUM not supported\n");
490 if (rxmode->hw_vlan_filter) {
491 PMD_INIT_LOG(INFO, "VLAN filter not supported\n");
495 if (rxmode->hw_vlan_strip) {
496 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
497 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
499 PMD_INIT_LOG(INFO, "hw vlan strip not supported\n");
504 if (rxmode->hw_vlan_extend) {
505 PMD_INIT_LOG(INFO, "VLAN extended not supported\n");
509 /* Supporting VLAN insertion by default */
510 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
511 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
513 if (rxmode->jumbo_frame)
514 /* this is handled in rte_eth_dev_configure */
516 if (rxmode->hw_strip_crc) {
517 PMD_INIT_LOG(INFO, "strip CRC not supported\n");
521 if (rxmode->enable_scatter) {
522 PMD_INIT_LOG(INFO, "Scatter not supported\n");
529 update |= NFP_NET_CFG_UPDATE_GEN;
531 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
532 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
541 nfp_net_enable_queues(struct rte_eth_dev *dev)
543 struct nfp_net_hw *hw;
544 uint64_t enabled_queues = 0;
547 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
549 /* Enabling the required TX queues in the device */
550 for (i = 0; i < dev->data->nb_tx_queues; i++)
551 enabled_queues |= (1 << i);
553 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
557 /* Enabling the required RX queues in the device */
558 for (i = 0; i < dev->data->nb_rx_queues; i++)
559 enabled_queues |= (1 << i);
561 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
565 nfp_net_disable_queues(struct rte_eth_dev *dev)
567 struct nfp_net_hw *hw;
568 uint32_t new_ctrl, update = 0;
570 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
572 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
573 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
575 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
576 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
577 NFP_NET_CFG_UPDATE_MSIX;
579 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
580 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
582 /* If an error when reconfig we avoid to change hw state */
583 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
590 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
594 for (i = 0; i < dev->data->nb_rx_queues; i++) {
595 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
602 nfp_net_params_setup(struct nfp_net_hw *hw)
604 uint32_t *mac_address;
606 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
607 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
609 /* A MAC address is 8 bytes long */
610 mac_address = (uint32_t *)(hw->mac_addr);
612 nn_cfg_writel(hw, NFP_NET_CFG_MACADDR,
613 rte_cpu_to_be_32(*mac_address));
614 nn_cfg_writel(hw, NFP_NET_CFG_MACADDR + 4,
615 rte_cpu_to_be_32(*(mac_address + 4)));
619 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
621 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
625 nfp_net_start(struct rte_eth_dev *dev)
627 uint32_t new_ctrl, update = 0;
628 struct nfp_net_hw *hw;
631 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
633 PMD_INIT_LOG(DEBUG, "Start\n");
635 /* Disabling queues just in case... */
636 nfp_net_disable_queues(dev);
638 /* Writing configuration parameters in the device */
639 nfp_net_params_setup(hw);
641 /* Enabling the required queues in the device */
642 nfp_net_enable_queues(dev);
645 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE | NFP_NET_CFG_UPDATE_MSIX;
646 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
648 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
649 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
651 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
652 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
656 * Allocating rte mbuffs for configured rx queues.
657 * This requires queues being enabled before
659 if (nfp_net_rx_freelist_setup(dev) < 0) {
670 * An error returned by this function should mean the app
671 * exiting and then the system releasing all the memory
672 * allocated even memory coming from hugepages.
674 * The device could be enabled at this point with some queues
675 * ready for getting packets. This is true if the call to
676 * nfp_net_rx_freelist_setup() succeeds for some queues but
677 * fails for subsequent queues.
679 * This should make the app exiting but better if we tell the
682 nfp_net_disable_queues(dev);
687 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
689 nfp_net_stop(struct rte_eth_dev *dev)
693 PMD_INIT_LOG(DEBUG, "Stop\n");
695 nfp_net_disable_queues(dev);
698 for (i = 0; i < dev->data->nb_tx_queues; i++) {
699 nfp_net_reset_tx_queue(
700 (struct nfp_net_txq *)dev->data->tx_queues[i]);
703 for (i = 0; i < dev->data->nb_rx_queues; i++) {
704 nfp_net_reset_rx_queue(
705 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
709 /* Reset and stop device. The device can not be restarted. */
711 nfp_net_close(struct rte_eth_dev *dev)
713 struct nfp_net_hw *hw;
715 PMD_INIT_LOG(DEBUG, "Close\n");
717 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
720 * We assume that the DPDK application is stopping all the
721 * threads/queues before calling the device close function.
726 rte_intr_disable(&dev->pci_dev->intr_handle);
727 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
730 * The ixgbe PMD driver disables the pcie master on the
731 * device. The i40e does not...
736 nfp_net_promisc_enable(struct rte_eth_dev *dev)
738 uint32_t new_ctrl, update = 0;
739 struct nfp_net_hw *hw;
741 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
743 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
745 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
746 PMD_INIT_LOG(INFO, "Promiscuous mode not supported\n");
750 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
751 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
755 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
756 update = NFP_NET_CFG_UPDATE_GEN;
759 * DPDK sets promiscuous mode on just after this call assuming
760 * it can not fail ...
762 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
769 nfp_net_promisc_disable(struct rte_eth_dev *dev)
771 uint32_t new_ctrl, update = 0;
772 struct nfp_net_hw *hw;
774 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
776 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
777 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
781 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
782 update = NFP_NET_CFG_UPDATE_GEN;
785 * DPDK sets promiscuous mode off just before this call
786 * assuming it can not fail ...
788 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
795 * return 0 means link status changed, -1 means not changed
797 * Wait to complete is needed as it can take up to 9 seconds to get the Link
801 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
803 struct nfp_net_hw *hw;
804 struct rte_eth_link link, old;
805 uint32_t nn_link_status;
807 PMD_DRV_LOG(DEBUG, "Link update\n");
809 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
811 memset(&old, 0, sizeof(old));
812 nfp_net_dev_atomic_read_link_status(dev, &old);
814 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
816 memset(&link, 0, sizeof(struct rte_eth_link));
818 if (nn_link_status & NFP_NET_CFG_STS_LINK)
819 link.link_status = 1;
821 link.link_duplex = ETH_LINK_FULL_DUPLEX;
822 /* Other cards can limit the tx and rx rate per VF */
823 link.link_speed = ETH_LINK_SPEED_40G;
825 if (old.link_status != link.link_status) {
826 nfp_net_dev_atomic_write_link_status(dev, &link);
827 if (link.link_status)
828 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
830 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
838 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
841 struct nfp_net_hw *hw;
842 struct rte_eth_stats nfp_dev_stats;
844 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
846 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
848 /* reading per RX ring stats */
849 for (i = 0; i < dev->data->nb_rx_queues; i++) {
850 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
853 nfp_dev_stats.q_ipackets[i] =
854 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
856 nfp_dev_stats.q_ipackets[i] -=
857 hw->eth_stats_base.q_ipackets[i];
859 nfp_dev_stats.q_ibytes[i] =
860 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
862 nfp_dev_stats.q_ibytes[i] -=
863 hw->eth_stats_base.q_ibytes[i];
866 /* reading per TX ring stats */
867 for (i = 0; i < dev->data->nb_tx_queues; i++) {
868 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
871 nfp_dev_stats.q_opackets[i] =
872 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
874 nfp_dev_stats.q_opackets[i] -=
875 hw->eth_stats_base.q_opackets[i];
877 nfp_dev_stats.q_obytes[i] =
878 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
880 nfp_dev_stats.q_obytes[i] -=
881 hw->eth_stats_base.q_obytes[i];
884 nfp_dev_stats.ipackets =
885 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
887 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
889 nfp_dev_stats.ibytes =
890 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
892 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
894 nfp_dev_stats.opackets =
895 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
897 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
899 nfp_dev_stats.obytes =
900 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
902 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
904 nfp_dev_stats.imcasts =
905 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
907 nfp_dev_stats.imcasts -= hw->eth_stats_base.imcasts;
909 /* reading general device stats */
910 nfp_dev_stats.ierrors =
911 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
913 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
915 nfp_dev_stats.oerrors =
916 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
918 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
920 /* Multicast frames received */
921 nfp_dev_stats.imcasts =
922 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
924 nfp_dev_stats.imcasts -= hw->eth_stats_base.imcasts;
926 /* RX ring mbuf allocation failures */
927 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
929 nfp_dev_stats.imissed =
930 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
932 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
935 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
939 nfp_net_stats_reset(struct rte_eth_dev *dev)
942 struct nfp_net_hw *hw;
944 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
947 * hw->eth_stats_base records the per counter starting point.
951 /* reading per RX ring stats */
952 for (i = 0; i < dev->data->nb_rx_queues; i++) {
953 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
956 hw->eth_stats_base.q_ipackets[i] =
957 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
959 hw->eth_stats_base.q_ibytes[i] =
960 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
963 /* reading per TX ring stats */
964 for (i = 0; i < dev->data->nb_tx_queues; i++) {
965 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
968 hw->eth_stats_base.q_opackets[i] =
969 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
971 hw->eth_stats_base.q_obytes[i] =
972 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
975 hw->eth_stats_base.ipackets =
976 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
978 hw->eth_stats_base.ibytes =
979 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
981 hw->eth_stats_base.opackets =
982 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
984 hw->eth_stats_base.obytes =
985 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
987 hw->eth_stats_base.imcasts =
988 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
990 /* reading general device stats */
991 hw->eth_stats_base.ierrors =
992 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
994 hw->eth_stats_base.oerrors =
995 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
997 /* Multicast frames received */
998 hw->eth_stats_base.imcasts =
999 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
1001 /* RX ring mbuf allocation failures */
1002 dev->data->rx_mbuf_alloc_failed = 0;
1004 hw->eth_stats_base.imissed =
1005 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1009 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1011 struct nfp_net_hw *hw;
1013 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1015 dev_info->driver_name = dev->driver->pci_drv.name;
1016 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1017 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1018 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1019 dev_info->max_rx_pktlen = hw->mtu;
1020 /* Next should change when PF support is implemented */
1021 dev_info->max_mac_addrs = 1;
1023 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1024 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1026 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1027 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1028 DEV_RX_OFFLOAD_UDP_CKSUM |
1029 DEV_RX_OFFLOAD_TCP_CKSUM;
1031 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1032 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1034 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1035 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1036 DEV_RX_OFFLOAD_UDP_CKSUM |
1037 DEV_RX_OFFLOAD_TCP_CKSUM;
1039 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1041 .pthresh = DEFAULT_RX_PTHRESH,
1042 .hthresh = DEFAULT_RX_HTHRESH,
1043 .wthresh = DEFAULT_RX_WTHRESH,
1045 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1049 dev_info->default_txconf = (struct rte_eth_txconf) {
1051 .pthresh = DEFAULT_TX_PTHRESH,
1052 .hthresh = DEFAULT_TX_HTHRESH,
1053 .wthresh = DEFAULT_TX_WTHRESH,
1055 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1056 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1057 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1058 ETH_TXQ_FLAGS_NOOFFLOADS,
1061 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1062 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1066 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1068 struct nfp_net_rxq *rxq;
1069 struct nfp_net_rx_desc *rxds;
1073 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1076 PMD_INIT_LOG(ERR, "Bad queue: %u\n", queue_idx);
1080 idx = rxq->rd_p % rxq->rx_count;
1081 rxds = &rxq->rxds[idx];
1086 * Other PMDs are just checking the DD bit in intervals of 4
1087 * descriptors and counting all four if the first has the DD
1088 * bit on. Of course, this is not accurate but can be good for
1089 * perfomance. But ideally that should be done in descriptors
1090 * chunks belonging to the same cache line
1093 while (count < rxq->rx_count) {
1094 rxds = &rxq->rxds[idx];
1095 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1102 if ((idx) == rxq->rx_count)
1110 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1112 struct rte_eth_link link;
1114 memset(&link, 0, sizeof(link));
1115 nfp_net_dev_atomic_read_link_status(dev, &link);
1116 if (link.link_status)
1117 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1118 (int)(dev->data->port_id), (unsigned)link.link_speed,
1119 link.link_duplex == ETH_LINK_FULL_DUPLEX
1120 ? "full-duplex" : "half-duplex");
1122 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1123 (int)(dev->data->port_id));
1125 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1126 dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1127 dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1130 /* Interrupt configuration and handling */
1133 * nfp_net_irq_unmask - Unmask an interrupt
1135 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1136 * clear the ICR for the entry.
1139 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1141 struct nfp_net_hw *hw;
1143 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1145 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1146 /* If MSI-X auto-masking is used, clear the entry */
1148 rte_intr_enable(&dev->pci_dev->intr_handle);
1150 /* Make sure all updates are written before un-masking */
1152 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1153 NFP_NET_CFG_ICR_UNMASKED);
1158 nfp_net_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1162 struct rte_eth_link link;
1163 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1165 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1167 /* get the link status */
1168 memset(&link, 0, sizeof(link));
1169 nfp_net_dev_atomic_read_link_status(dev, &link);
1171 nfp_net_link_update(dev, 0);
1174 if (!link.link_status) {
1175 /* handle it 1 sec later, wait it being stable */
1176 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1177 /* likely to down */
1179 /* handle it 4 sec later, wait it being stable */
1180 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1183 if (rte_eal_alarm_set(timeout * 1000,
1184 nfp_net_dev_interrupt_delayed_handler,
1186 RTE_LOG(ERR, PMD, "Error setting alarm");
1188 nfp_net_irq_unmask(dev);
1193 * Interrupt handler which shall be registered for alarm callback for delayed
1194 * handling specific interrupt to wait for the stable nic state. As the NIC
1195 * interrupt state is not stable for nfp after link is just down, it needs
1196 * to wait 4 seconds to get the stable status.
1198 * @param handle Pointer to interrupt handle.
1199 * @param param The address of parameter (struct rte_eth_dev *)
1204 nfp_net_dev_interrupt_delayed_handler(void *param)
1206 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1208 nfp_net_link_update(dev, 0);
1209 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1211 nfp_net_dev_link_status_print(dev);
1214 nfp_net_irq_unmask(dev);
1218 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1220 struct nfp_net_hw *hw;
1222 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224 /* check that mtu is within the allowed range */
1225 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1228 /* switch to jumbo mode if needed */
1229 if ((uint32_t)mtu > ETHER_MAX_LEN)
1230 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1232 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1234 /* update max frame size */
1235 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1237 /* writing to configuration space */
1238 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1246 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1247 uint16_t queue_idx, uint16_t nb_desc,
1248 unsigned int socket_id,
1249 const struct rte_eth_rxconf *rx_conf,
1250 struct rte_mempool *mp)
1252 const struct rte_memzone *tz;
1253 struct nfp_net_rxq *rxq;
1254 struct nfp_net_hw *hw;
1256 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1258 PMD_INIT_FUNC_TRACE();
1260 /* Validating number of descriptors */
1261 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1262 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1263 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1264 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1269 * Free memory prior to re-allocation if needed. This is the case after
1270 * calling nfp_net_stop
1272 if (dev->data->rx_queues[queue_idx]) {
1273 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1274 dev->data->rx_queues[queue_idx] = NULL;
1277 /* Allocating rx queue data structure */
1278 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1279 RTE_CACHE_LINE_SIZE, socket_id);
1283 /* Hw queues mapping based on firmware confifguration */
1284 rxq->qidx = queue_idx;
1285 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1286 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1287 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1288 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1291 * Tracking mbuf size for detecting a potential mbuf overflow due to
1295 rxq->mbuf_size = rxq->mem_pool->elt_size;
1296 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1297 hw->flbufsz = rxq->mbuf_size;
1299 rxq->rx_count = nb_desc;
1300 rxq->port_id = dev->data->port_id;
1301 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1302 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1304 rxq->drop_en = rx_conf->rx_drop_en;
1307 * Allocate RX ring hardware descriptors. A memzone large enough to
1308 * handle the maximum ring size is allocated in order to allow for
1309 * resizing in later calls to the queue setup function.
1311 tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1312 sizeof(struct nfp_net_rx_desc) *
1313 NFP_NET_MAX_RX_DESC, socket_id);
1316 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1317 nfp_net_rx_queue_release(rxq);
1321 /* Saving physical and virtual addresses for the RX ring */
1322 rxq->dma = (uint64_t)tz->phys_addr;
1323 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1325 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1326 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1327 sizeof(*rxq->rxbufs) * nb_desc,
1328 RTE_CACHE_LINE_SIZE, socket_id);
1329 if (rxq->rxbufs == NULL) {
1330 nfp_net_rx_queue_release(rxq);
1334 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1335 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1337 nfp_net_reset_rx_queue(rxq);
1339 dev->data->rx_queues[queue_idx] = rxq;
1343 * Telling the HW about the physical address of the RX ring and number
1344 * of descriptors in log2 format
1346 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1347 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1353 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1355 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1359 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1362 for (i = 0; i < rxq->rx_count; i++) {
1363 struct nfp_net_rx_desc *rxd;
1364 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1367 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1368 (unsigned)rxq->qidx);
1372 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1374 rxd = &rxq->rxds[i];
1376 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1377 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1379 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1384 /* Make sure all writes are flushed before telling the hardware */
1387 /* Not advertising the whole ring as the firmware gets confused if so */
1388 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1391 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1397 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1398 uint16_t nb_desc, unsigned int socket_id,
1399 const struct rte_eth_txconf *tx_conf)
1401 const struct rte_memzone *tz;
1402 struct nfp_net_txq *txq;
1403 uint16_t tx_free_thresh;
1404 struct nfp_net_hw *hw;
1406 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1408 PMD_INIT_FUNC_TRACE();
1410 /* Validating number of descriptors */
1411 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1412 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1413 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1414 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1418 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1419 tx_conf->tx_free_thresh :
1420 DEFAULT_TX_FREE_THRESH);
1422 if (tx_free_thresh > (nb_desc)) {
1424 "tx_free_thresh must be less than the number of TX "
1425 "descriptors. (tx_free_thresh=%u port=%d "
1426 "queue=%d)\n", (unsigned int)tx_free_thresh,
1427 (int)dev->data->port_id, (int)queue_idx);
1432 * Free memory prior to re-allocation if needed. This is the case after
1433 * calling nfp_net_stop
1435 if (dev->data->tx_queues[queue_idx]) {
1436 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1438 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1439 dev->data->tx_queues[queue_idx] = NULL;
1442 /* Allocating tx queue data structure */
1443 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1444 RTE_CACHE_LINE_SIZE, socket_id);
1446 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1451 * Allocate TX ring hardware descriptors. A memzone large enough to
1452 * handle the maximum ring size is allocated in order to allow for
1453 * resizing in later calls to the queue setup function.
1455 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1456 sizeof(struct nfp_net_tx_desc) *
1457 NFP_NET_MAX_TX_DESC, socket_id);
1459 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1460 nfp_net_tx_queue_release(txq);
1464 txq->tx_count = nb_desc;
1466 txq->tx_free_thresh = tx_free_thresh;
1467 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1468 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1469 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1471 /* queue mapping based on firmware configuration */
1472 txq->qidx = queue_idx;
1473 txq->tx_qcidx = queue_idx * hw->stride_tx;
1474 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1476 txq->port_id = dev->data->port_id;
1477 txq->txq_flags = tx_conf->txq_flags;
1479 /* Saving physical and virtual addresses for the TX ring */
1480 txq->dma = (uint64_t)tz->phys_addr;
1481 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1483 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1484 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1485 sizeof(*txq->txbufs) * nb_desc,
1486 RTE_CACHE_LINE_SIZE, socket_id);
1487 if (txq->txbufs == NULL) {
1488 nfp_net_tx_queue_release(txq);
1491 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1492 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1494 nfp_net_reset_tx_queue(txq);
1496 dev->data->tx_queues[queue_idx] = txq;
1500 * Telling the HW about the physical address of the TX ring and number
1501 * of descriptors in log2 format
1503 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1504 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1509 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1511 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1512 struct rte_mbuf *mb)
1515 struct nfp_net_hw *hw = txq->hw;
1517 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1520 ol_flags = mb->ol_flags;
1522 /* IPv6 does not need checksum */
1523 if (ol_flags & PKT_TX_IP_CKSUM)
1524 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1526 switch (ol_flags & PKT_TX_L4_MASK) {
1527 case PKT_TX_UDP_CKSUM:
1528 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1530 case PKT_TX_TCP_CKSUM:
1531 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1535 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1536 txd->flags |= PCIE_DESC_TX_CSUM;
1539 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1541 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1542 struct rte_mbuf *mb)
1544 struct nfp_net_hw *hw = rxq->hw;
1546 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1549 /* If IPv4 and IP checksum error, fail */
1550 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1551 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1552 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1554 /* If neither UDP nor TCP return */
1555 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1556 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1559 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1560 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1561 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1563 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1564 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1565 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1568 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1569 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1572 * nfp_net_set_hash - Set mbuf hash data
1574 * The RSS hash and hash-type are pre-pended to the packet data.
1575 * Extract and decode it and set the mbuf fields.
1578 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1579 struct rte_mbuf *mbuf)
1583 struct nfp_net_hw *hw = rxq->hw;
1585 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1588 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1591 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1592 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1595 * hash type is sharing the same word with input port info
1600 mbuf->hash.rss = hash;
1601 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1603 switch (hash_type) {
1604 case NFP_NET_RSS_IPV4:
1605 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1607 case NFP_NET_RSS_IPV6:
1608 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1610 case NFP_NET_RSS_IPV6_EX:
1611 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1614 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1618 /* nfp_net_check_port - Set mbuf in_port field */
1620 nfp_net_check_port(struct nfp_net_rx_desc *rxd, struct rte_mbuf *mbuf)
1624 if (!(rxd->rxd.flags & PCIE_DESC_RX_INGRESS_PORT)) {
1629 port = rte_be_to_cpu_32(*(uint32_t *)((uint8_t *)mbuf->buf_addr +
1630 mbuf->data_off - 8));
1633 * hash type is sharing the same word with input port info
1637 port = (uint8_t)(port >> 8);
1642 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1644 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1647 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1652 * There are some decissions to take:
1653 * 1) How to check DD RX descriptors bit
1654 * 2) How and when to allocate new mbufs
1656 * Current implementation checks just one single DD bit each loop. As each
1657 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1658 * a single cache line instead. Tests with this change have not shown any
1659 * performance improvement but it requires further investigation. For example,
1660 * depending on which descriptor is next, the number of descriptors could be
1661 * less than 8 for just checking those in the same cache line. This implies
1662 * extra work which could be counterproductive by itself. Indeed, last firmware
1663 * changes are just doing this: writing several descriptors with the DD bit
1664 * for saving PCIe bandwidth and DMA operations from the NFP.
1666 * Mbuf allocation is done when a new packet is received. Then the descriptor
1667 * is automatically linked with the new mbuf and the old one is given to the
1668 * user. The main drawback with this design is mbuf allocation is heavier than
1669 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1670 * cache point of view it does not seem allocating the mbuf early on as we are
1671 * doing now have any benefit at all. Again, tests with this change have not
1672 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1673 * so looking at the implications of this type of allocation should be studied
1678 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1680 struct nfp_net_rxq *rxq;
1681 struct nfp_net_rx_desc *rxds;
1682 struct nfp_net_rx_buff *rxb;
1683 struct nfp_net_hw *hw;
1684 struct rte_mbuf *mb;
1685 struct rte_mbuf *new_mb;
1692 if (unlikely(rxq == NULL)) {
1694 * DPDK just checks the queue is lower than max queues
1695 * enabled. But the queue needs to be configured
1697 RTE_LOG(ERR, PMD, "RX Bad queue\n");
1705 while (avail < nb_pkts) {
1706 idx = rxq->rd_p % rxq->rx_count;
1708 rxb = &rxq->rxbufs[idx];
1709 if (unlikely(rxb == NULL)) {
1710 RTE_LOG(ERR, PMD, "rxb does not exist!\n");
1715 * Memory barrier to ensure that we won't do other
1716 * reads before the DD bit.
1720 rxds = &rxq->rxds[idx];
1721 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1725 * We got a packet. Let's alloc a new mbuff for refilling the
1726 * free descriptor ring as soon as possible
1728 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1729 if (unlikely(new_mb == NULL)) {
1730 RTE_LOG(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1731 "queue_id=%u\n", (unsigned)rxq->port_id,
1732 (unsigned)rxq->qidx);
1733 nfp_net_mbuf_alloc_failed(rxq);
1740 * Grab the mbuff and refill the descriptor with the
1741 * previously allocated mbuff
1746 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1747 rxds->rxd.data_len, rxq->mbuf_size);
1749 /* Size of this segment */
1750 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1751 /* Size of the whole packet. We just support 1 segment */
1752 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1754 if (unlikely((mb->data_len + hw->rx_offset) >
1757 * This should not happen and the user has the
1758 * responsibility of avoiding it. But we have
1759 * to give some info about the error
1762 "mbuf overflow likely due to the RX offset.\n"
1763 "\t\tYour mbuf size should have extra space for"
1764 " RX offset=%u bytes.\n"
1765 "\t\tCurrently you just have %u bytes available"
1766 " but the received packet is %u bytes long",
1768 rxq->mbuf_size - hw->rx_offset,
1773 /* Filling the received mbuff with packet info */
1775 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1777 mb->data_off = RTE_PKTMBUF_HEADROOM +
1778 NFP_DESC_META_LEN(rxds);
1780 /* No scatter mode supported */
1784 /* Checking the RSS flag */
1785 nfp_net_set_hash(rxq, rxds, mb);
1787 /* Checking the checksum flag */
1788 nfp_net_rx_cksum(rxq, rxds, mb);
1790 /* Checking the port flag */
1791 nfp_net_check_port(rxds, mb);
1793 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1794 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1795 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1796 mb->ol_flags |= PKT_RX_VLAN_PKT;
1799 /* Adding the mbuff to the mbuff array passed by the app */
1800 rx_pkts[avail++] = mb;
1802 /* Now resetting and updating the descriptor */
1805 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1807 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1808 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1816 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1817 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1819 nb_hold += rxq->nb_rx_hold;
1822 * FL descriptors needs to be written before incrementing the
1823 * FL queue WR pointer
1826 if (nb_hold > rxq->rx_free_thresh) {
1827 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1828 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1829 (unsigned)nb_hold, (unsigned)avail);
1830 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1833 rxq->nb_rx_hold = nb_hold;
1839 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1841 * @txq: TX queue to work with
1842 * Returns number of descriptors freed
1845 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1850 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1851 " status\n", txq->qidx);
1853 /* Work out how many packets have been sent */
1854 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1856 if (qcp_rd_p == txq->qcp_rd_p) {
1857 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1858 "packets (%u, %u)\n", txq->qidx,
1859 qcp_rd_p, txq->qcp_rd_p);
1863 if (qcp_rd_p > txq->qcp_rd_p)
1864 todo = qcp_rd_p - txq->qcp_rd_p;
1866 todo = qcp_rd_p + txq->tx_count - txq->qcp_rd_p;
1868 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->qcp_rd_p: %u, qcp->rd_p: %u\n",
1869 qcp_rd_p, txq->qcp_rd_p, txq->rd_p);
1874 txq->qcp_rd_p += todo;
1875 txq->qcp_rd_p %= txq->tx_count;
1881 /* Leaving always free descriptors for avoiding wrapping confusion */
1882 #define NFP_FREE_TX_DESC(t) (t->tx_count - (t->wr_p - t->rd_p) - 8)
1885 * nfp_net_txq_full - Check if the TX queue free descriptors
1886 * is below tx_free_threshold
1888 * @txq: TX queue to check
1890 * This function uses the host copy* of read/write pointers
1893 int nfp_net_txq_full(struct nfp_net_txq *txq)
1895 return NFP_FREE_TX_DESC(txq) < txq->tx_free_thresh;
1899 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1901 struct nfp_net_txq *txq;
1902 struct nfp_net_hw *hw;
1903 struct nfp_net_tx_desc *txds;
1904 struct rte_mbuf *pkt;
1906 int pkt_size, dma_size;
1907 uint16_t free_descs, issued_descs;
1908 struct rte_mbuf **lmbuf;
1913 txds = &txq->txds[txq->tail];
1915 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
1916 txq->qidx, txq->tail, nb_pkts);
1918 if ((NFP_FREE_TX_DESC(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
1919 nfp_net_tx_free_bufs(txq);
1921 free_descs = (uint16_t)NFP_FREE_TX_DESC(txq);
1922 if (unlikely(free_descs == 0))
1929 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
1930 txq->qidx, nb_pkts);
1931 /* Sending packets */
1932 while ((i < nb_pkts) && free_descs) {
1933 /* Grabbing the mbuf linked to the current descriptor */
1934 lmbuf = &txq->txbufs[txq->tail].mbuf;
1935 /* Warming the cache for releasing the mbuf later on */
1936 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
1938 pkt = *(tx_pkts + i);
1940 if (unlikely((pkt->nb_segs > 1) &&
1941 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
1942 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set\n");
1943 rte_panic("Multisegment packet unsupported\n");
1946 /* Checking if we have enough descriptors */
1947 if (unlikely(pkt->nb_segs > free_descs))
1951 * Checksum and VLAN flags just in the first descriptor for a
1952 * multisegment packet
1954 nfp_net_tx_cksum(txq, txds, pkt);
1956 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
1957 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
1958 txds->flags |= PCIE_DESC_TX_VLAN;
1959 txds->vlan = pkt->vlan_tci;
1962 if (pkt->ol_flags & PKT_TX_TCP_SEG)
1963 rte_panic("TSO is not supported\n");
1966 * mbuf data_len is the data in one segment and pkt_len data
1967 * in the whole packet. When the packet is just one segment,
1968 * then data_len = pkt_len
1970 pkt_size = pkt->pkt_len;
1973 /* Releasing mbuf which was prefetched above */
1975 rte_pktmbuf_free_seg(*lmbuf);
1977 dma_size = pkt->data_len;
1978 dma_addr = rte_mbuf_data_dma_addr(pkt);
1979 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
1980 "%" PRIx64 "\n", dma_addr);
1982 /* Filling descriptors fields */
1983 txds->dma_len = dma_size;
1984 txds->data_len = pkt->pkt_len;
1985 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
1986 txds->dma_addr_lo = (dma_addr & 0xffffffff);
1987 ASSERT(free_descs > 0);
1991 * Linking mbuf with descriptor for being released
1992 * next time descriptor is used
1998 if (unlikely(txq->tail == txq->tx_count)) /* wrapping?*/
2001 pkt_size -= dma_size;
2004 txds->offset_eop |= PCIE_DESC_TX_EOP;
2006 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2009 /* Referencing next free TX descriptor */
2010 txds = &txq->txds[txq->tail];
2017 /* Increment write pointers. Force memory write before we let HW know */
2019 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2025 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2027 uint32_t new_ctrl, update;
2028 struct nfp_net_hw *hw;
2030 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2033 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2034 (mask & ETH_VLAN_FILTER_OFFLOAD))
2035 RTE_LOG(INFO, PMD, "Not support for ETH_VLAN_FILTER_OFFLOAD or"
2036 " ETH_VLAN_FILTER_EXTEND");
2038 /* Enable vlan strip if it is not configured yet */
2039 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2040 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2041 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2043 /* Disable vlan strip just if it is configured */
2044 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2045 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2046 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2051 update = NFP_NET_CFG_UPDATE_GEN;
2053 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2056 hw->ctrl = new_ctrl;
2059 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2061 nfp_net_reta_update(struct rte_eth_dev *dev,
2062 struct rte_eth_rss_reta_entry64 *reta_conf,
2065 uint32_t reta, mask;
2069 struct nfp_net_hw *hw =
2070 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2072 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2075 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2076 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2077 "(%d) doesn't match the number hardware can supported "
2078 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2083 * Update Redirection Table. There are 128 8bit-entries which can be
2084 * manage as 32 32bit-entries
2086 for (i = 0; i < reta_size; i += 4) {
2087 /* Handling 4 RSS entries per loop */
2088 idx = i / RTE_RETA_GROUP_SIZE;
2089 shift = i % RTE_RETA_GROUP_SIZE;
2090 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2096 /* If all 4 entries were set, don't need read RETA register */
2098 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2100 for (j = 0; j < 4; j++) {
2101 if (!(mask & (0x1 << j)))
2104 /* Clearing the entry bits */
2105 reta &= ~(0xFF << (8 * j));
2106 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2108 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2111 update = NFP_NET_CFG_UPDATE_RSS;
2113 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2119 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2121 nfp_net_reta_query(struct rte_eth_dev *dev,
2122 struct rte_eth_rss_reta_entry64 *reta_conf,
2128 struct nfp_net_hw *hw;
2130 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2135 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2136 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2137 "(%d) doesn't match the number hardware can supported "
2138 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2143 * Reading Redirection Table. There are 128 8bit-entries which can be
2144 * manage as 32 32bit-entries
2146 for (i = 0; i < reta_size; i += 4) {
2147 /* Handling 4 RSS entries per loop */
2148 idx = i / RTE_RETA_GROUP_SIZE;
2149 shift = i % RTE_RETA_GROUP_SIZE;
2150 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2155 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2156 for (j = 0; j < 4; j++) {
2157 if (!(mask & (0x1 << j)))
2159 reta_conf->reta[shift + j] =
2160 (uint8_t)((reta >> (8 * j)) & 0xF);
2167 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2168 struct rte_eth_rss_conf *rss_conf)
2171 uint32_t cfg_rss_ctrl = 0;
2175 struct nfp_net_hw *hw;
2177 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2179 rss_hf = rss_conf->rss_hf;
2181 /* Checking if RSS is enabled */
2182 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2183 if (rss_hf != 0) { /* Enable RSS? */
2184 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2187 return 0; /* Nothing to do */
2190 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2191 RTE_LOG(ERR, PMD, "hash key too long\n");
2195 if (rss_hf & ETH_RSS_IPV4)
2196 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2197 NFP_NET_CFG_RSS_IPV4_TCP |
2198 NFP_NET_CFG_RSS_IPV4_UDP;
2200 if (rss_hf & ETH_RSS_IPV6)
2201 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2202 NFP_NET_CFG_RSS_IPV6_TCP |
2203 NFP_NET_CFG_RSS_IPV6_UDP;
2205 /* configuring where to apply the RSS hash */
2206 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2208 /* Writing the key byte a byte */
2209 for (i = 0; i < rss_conf->rss_key_len; i++) {
2210 memcpy(&key, &rss_conf->rss_key[i], 1);
2211 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2214 /* Writing the key size */
2215 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2217 update = NFP_NET_CFG_UPDATE_RSS;
2219 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2226 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2227 struct rte_eth_rss_conf *rss_conf)
2230 uint32_t cfg_rss_ctrl;
2233 struct nfp_net_hw *hw;
2235 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2240 rss_hf = rss_conf->rss_hf;
2241 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2243 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2244 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2246 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2247 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2249 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2250 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2252 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2253 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2255 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2256 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2258 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2259 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2261 /* Reading the key size */
2262 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2264 /* Reading the key byte a byte */
2265 for (i = 0; i < rss_conf->rss_key_len; i++) {
2266 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2267 memcpy(&rss_conf->rss_key[i], &key, 1);
2273 /* Initialise and register driver with DPDK Application */
2274 static struct eth_dev_ops nfp_net_eth_dev_ops = {
2275 .dev_configure = nfp_net_configure,
2276 .dev_start = nfp_net_start,
2277 .dev_stop = nfp_net_stop,
2278 .dev_close = nfp_net_close,
2279 .promiscuous_enable = nfp_net_promisc_enable,
2280 .promiscuous_disable = nfp_net_promisc_disable,
2281 .link_update = nfp_net_link_update,
2282 .stats_get = nfp_net_stats_get,
2283 .stats_reset = nfp_net_stats_reset,
2284 .dev_infos_get = nfp_net_infos_get,
2285 .mtu_set = nfp_net_dev_mtu_set,
2286 .vlan_offload_set = nfp_net_vlan_offload_set,
2287 .reta_update = nfp_net_reta_update,
2288 .reta_query = nfp_net_reta_query,
2289 .rss_hash_update = nfp_net_rss_hash_update,
2290 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2291 .rx_queue_setup = nfp_net_rx_queue_setup,
2292 .rx_queue_release = nfp_net_rx_queue_release,
2293 .rx_queue_count = nfp_net_rx_queue_count,
2294 .tx_queue_setup = nfp_net_tx_queue_setup,
2295 .tx_queue_release = nfp_net_tx_queue_release,
2299 nfp_net_init(struct rte_eth_dev *eth_dev)
2301 struct rte_pci_device *pci_dev;
2302 struct nfp_net_hw *hw;
2304 uint32_t tx_bar_off, rx_bar_off;
2308 PMD_INIT_FUNC_TRACE();
2310 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2312 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2313 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2314 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2316 /* For secondary processes, the primary has done all the work */
2317 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2320 pci_dev = eth_dev->pci_dev;
2321 hw->device_id = pci_dev->id.device_id;
2322 hw->vendor_id = pci_dev->id.vendor_id;
2323 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2324 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2326 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u\n",
2327 pci_dev->id.vendor_id, pci_dev->id.device_id,
2328 pci_dev->addr.domain, pci_dev->addr.bus,
2329 pci_dev->addr.devid, pci_dev->addr.function);
2331 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2332 if (hw->ctrl_bar == NULL) {
2334 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2337 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2338 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2340 /* Work out where in the BAR the queues start. */
2341 switch (pci_dev->id.device_id) {
2342 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2343 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2344 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2345 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2346 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2349 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2353 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x\n", tx_bar_off);
2354 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x\n", rx_bar_off);
2356 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2357 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2359 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p\n",
2360 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2362 nfp_net_cfg_queue_setup(hw);
2364 /* Get some of the read-only fields from the config BAR */
2365 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2366 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2367 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2368 hw->mtu = hw->max_mtu;
2370 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2371 hw->rx_offset = NFP_NET_RX_OFFSET;
2373 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2375 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d\n",
2376 hw->ver, hw->max_mtu);
2377 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s\n", hw->cap,
2378 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2379 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2380 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2381 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2382 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2383 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2384 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2385 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2386 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2388 pci_dev = eth_dev->pci_dev;
2391 hw->stride_rx = stride;
2392 hw->stride_tx = stride;
2394 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u\n",
2395 hw->max_rx_queues, hw->max_tx_queues);
2397 /* Allocating memory for mac addr */
2398 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2399 if (eth_dev->data->mac_addrs == NULL) {
2400 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2404 /* Using random mac addresses for VFs */
2405 eth_random_addr(&hw->mac_addr[0]);
2407 /* Copying mac address to DPDK eth_dev struct */
2408 ether_addr_copy(ð_dev->data->mac_addrs[0],
2409 (struct ether_addr *)hw->mac_addr);
2411 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2412 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2413 eth_dev->data->port_id, pci_dev->id.vendor_id,
2414 pci_dev->id.device_id,
2415 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2416 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2418 /* Registering LSC interrupt handler */
2419 rte_intr_callback_register(&pci_dev->intr_handle,
2420 nfp_net_dev_interrupt_handler,
2423 /* enable uio intr after callback register */
2424 rte_intr_enable(&pci_dev->intr_handle);
2426 /* Telling the firmware about the LSC interrupt entry */
2427 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2429 /* Recording current stats counters values */
2430 nfp_net_stats_reset(eth_dev);
2435 static struct rte_pci_id pci_id_nfp_net_map[] = {
2437 .vendor_id = PCI_VENDOR_ID_NETRONOME,
2438 .device_id = PCI_DEVICE_ID_NFP6000_PF_NIC,
2439 .subsystem_vendor_id = PCI_ANY_ID,
2440 .subsystem_device_id = PCI_ANY_ID,
2443 .vendor_id = PCI_VENDOR_ID_NETRONOME,
2444 .device_id = PCI_DEVICE_ID_NFP6000_VF_NIC,
2445 .subsystem_vendor_id = PCI_ANY_ID,
2446 .subsystem_device_id = PCI_ANY_ID,
2453 static struct eth_driver rte_nfp_net_pmd = {
2455 .name = "rte_nfp_net_pmd",
2456 .id_table = pci_id_nfp_net_map,
2457 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2459 .eth_dev_init = nfp_net_init,
2460 .dev_private_size = sizeof(struct nfp_net_adapter),
2464 nfp_net_pmd_init(const char *name __rte_unused,
2465 const char *params __rte_unused)
2467 PMD_INIT_FUNC_TRACE();
2468 PMD_INIT_LOG(INFO, "librte_pmd_nfp_net version %s\n",
2469 NFP_NET_PMD_VERSION);
2471 rte_eth_driver_register(&rte_nfp_net_pmd);
2475 static struct rte_driver rte_nfp_net_driver = {
2477 .init = nfp_net_pmd_init,
2480 PMD_REGISTER_DRIVER(rte_nfp_net_driver);
2484 * c-file-style: "Linux"
2485 * indent-tabs-mode: t