drivers/net/nfp/nfp_net.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  */
   7
   8 /*
   9  * vim:shiftwidth=8:noexpandtab
  10  *
  11  * @file dpdk/pmd/nfp_net.c
  12  *
  13  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  14  */
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_log.h>
  19 #include <rte_debug.h>
  20 #include <ethdev_driver.h>
  21 #include <ethdev_pci.h>
  22 #include <rte_dev.h>
  23 #include <rte_ether.h>
  24 #include <rte_malloc.h>
  25 #include <rte_memzone.h>
  26 #include <rte_mempool.h>
  27 #include <rte_version.h>
  28 #include <rte_string_fns.h>
  29 #include <rte_alarm.h>
  30 #include <rte_spinlock.h>
  31 #include <rte_service_component.h>
  32
  33 #include "eal_firmware.h"
  34
  35 #include "nfpcore/nfp_cpp.h"
  36 #include "nfpcore/nfp_nffw.h"
  37 #include "nfpcore/nfp_hwinfo.h"
  38 #include "nfpcore/nfp_mip.h"
  39 #include "nfpcore/nfp_rtsym.h"
  40 #include "nfpcore/nfp_nsp.h"
  41
  42 #include "nfp_net_pmd.h"
  43 #include "nfp_rxtx.h"
  44 #include "nfp_net_logs.h"
  45 #include "nfp_net_ctrl.h"
  46 #include "nfp_cpp_bridge.h"
  47
  48 #include <sys/types.h>
  49 #include <sys/socket.h>
  50 #include <sys/un.h>
  51 #include <unistd.h>
  52 #include <stdio.h>
  53 #include <sys/ioctl.h>
  54 #include <errno.h>
  55
  56 /* Prototypes */
  57 static int nfp_net_close(struct rte_eth_dev *dev);
  58 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  59 static int nfp_pf_init(struct rte_pci_device *pci_dev);
  60 static int nfp_pf_secondary_init(struct rte_pci_device *pci_dev);
  61 static int nfp_net_pf_read_mac(struct nfp_pf_dev *pf_dev, int port);
  62 static int nfp_pci_uninit(struct rte_eth_dev *eth_dev);
  63 static int nfp_init_phyports(struct nfp_pf_dev *pf_dev);
  64 static int nfp_net_stop(struct rte_eth_dev *dev);
  65 static int nfp_fw_setup(struct rte_pci_device *dev,
  66                         struct nfp_cpp *cpp,
  67                         struct nfp_eth_table *nfp_eth_table,
  68                         struct nfp_hwinfo *hwinfo);
  69
  70 static int
  71 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
  72 {
  73         int cnt;
  74         uint32_t new;
  75         struct timespec wait;
  76
  77         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
  78                     hw->qcp_cfg);
  79
  80         if (hw->qcp_cfg == NULL)
  81                 rte_panic("Bad configuration queue pointer\n");
  82
  83         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
  84
  85         wait.tv_sec = 0;
  86         wait.tv_nsec = 1000000;
  87
  88         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
  89
  90         /* Poll update field, waiting for NFP to ack the config */
  91         for (cnt = 0; ; cnt++) {
  92                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
  93                 if (new == 0)
  94                         break;
  95                 if (new & NFP_NET_CFG_UPDATE_ERR) {
  96                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
  97                         return -1;
  98                 }
  99                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 100                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 101                                           " %dms", update, cnt);
 102                         rte_panic("Exiting\n");
 103                 }
 104                 nanosleep(&wait, 0); /* waiting for a 1ms */
 105         }
 106         PMD_DRV_LOG(DEBUG, "Ack DONE");
 107         return 0;
 108 }
 109
 110 /*
 111  * Reconfigure the NIC
 112  * @nn:    device to reconfigure
 113  * @ctrl:    The value for the ctrl field in the BAR config
 114  * @update:  The value for the update field in the BAR config
 115  *
 116  * Write the update word to the BAR and ping the reconfig queue. Then poll
 117  * until the firmware has acknowledged the update by zeroing the update word.
 118  */
 119 int
 120 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 121 {
 122         uint32_t err;
 123
 124         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 125                     ctrl, update);
 126
 127         rte_spinlock_lock(&hw->reconfig_lock);
 128
 129         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 130         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 131
 132         rte_wmb();
 133
 134         err = __nfp_net_reconfig(hw, update);
 135
 136         rte_spinlock_unlock(&hw->reconfig_lock);
 137
 138         if (!err)
 139                 return 0;
 140
 141         /*
 142          * Reconfig errors imply situations where they can be handled.
 143          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 144          */
 145         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 146                      ctrl, update);
 147         return -EIO;
 148 }
 149
 150 /*
 151  * Configure an Ethernet device. This function must be invoked first
 152  * before any other function in the Ethernet API. This function can
 153  * also be re-invoked when a device is in the stopped state.
 154  */
 155 int
 156 nfp_net_configure(struct rte_eth_dev *dev)
 157 {
 158         struct rte_eth_conf *dev_conf;
 159         struct rte_eth_rxmode *rxmode;
 160         struct rte_eth_txmode *txmode;
 161         struct nfp_net_hw *hw;
 162
 163         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 164
 165         /*
 166          * A DPDK app sends info about how many queues to use and how
 167          * those queues need to be configured. This is used by the
 168          * DPDK core and it makes sure no more queues than those
 169          * advertised by the driver are requested. This function is
 170          * called after that internal process
 171          */
 172
 173         PMD_INIT_LOG(DEBUG, "Configure");
 174
 175         dev_conf = &dev->data->dev_conf;
 176         rxmode = &dev_conf->rxmode;
 177         txmode = &dev_conf->txmode;
 178
 179         if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
 180                 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 181
 182         /* Checking TX mode */
 183         if (txmode->mq_mode) {
 184                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 185                 return -EINVAL;
 186         }
 187
 188         /* Checking RX mode */
 189         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 190             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 191                 PMD_INIT_LOG(INFO, "RSS not supported");
 192                 return -EINVAL;
 193         }
 194
 195         return 0;
 196 }
 197
 198 void
 199 nfp_net_enable_queues(struct rte_eth_dev *dev)
 200 {
 201         struct nfp_net_hw *hw;
 202         uint64_t enabled_queues = 0;
 203         int i;
 204
 205         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 206
 207         /* Enabling the required TX queues in the device */
 208         for (i = 0; i < dev->data->nb_tx_queues; i++)
 209                 enabled_queues |= (1 << i);
 210
 211         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 212
 213         enabled_queues = 0;
 214
 215         /* Enabling the required RX queues in the device */
 216         for (i = 0; i < dev->data->nb_rx_queues; i++)
 217                 enabled_queues |= (1 << i);
 218
 219         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 220 }
 221
 222 void
 223 nfp_net_disable_queues(struct rte_eth_dev *dev)
 224 {
 225         struct nfp_net_hw *hw;
 226         uint32_t new_ctrl, update = 0;
 227
 228         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 229
 230         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 231         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 232
 233         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 234         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 235                  NFP_NET_CFG_UPDATE_MSIX;
 236
 237         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 238                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 239
 240         /* If an error when reconfig we avoid to change hw state */
 241         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 242                 return;
 243
 244         hw->ctrl = new_ctrl;
 245 }
 246
 247 void
 248 nfp_net_params_setup(struct nfp_net_hw *hw)
 249 {
 250         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 251         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 252 }
 253
 254 void
 255 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 256 {
 257         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 258 }
 259
 260 #define ETH_ADDR_LEN    6
 261
 262 void
 263 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 264 {
 265         int i;
 266
 267         for (i = 0; i < ETH_ADDR_LEN; i++)
 268                 dst[i] = src[i];
 269 }
 270
 271 static int
 272 nfp_net_pf_read_mac(struct nfp_pf_dev *pf_dev, int port)
 273 {
 274         struct nfp_eth_table *nfp_eth_table;
 275         struct nfp_net_hw *hw = NULL;
 276
 277         /* Grab a pointer to the correct physical port */
 278         hw = pf_dev->ports[port];
 279
 280         nfp_eth_table = nfp_eth_read_ports(pf_dev->cpp);
 281
 282         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 283                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 284
 285         free(nfp_eth_table);
 286         return 0;
 287 }
 288
 289 void
 290 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 291 {
 292         uint32_t mac0 = *(uint32_t *)mac;
 293         uint16_t mac1;
 294
 295         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 296
 297         mac += 4;
 298         mac1 = *(uint16_t *)mac;
 299         nn_writew(rte_cpu_to_be_16(mac1),
 300                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 301 }
 302
 303 int
 304 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
 305 {
 306         struct nfp_net_hw *hw;
 307         uint32_t update, ctrl;
 308
 309         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 310         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 311             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 312                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 313                                   " port enabled");
 314                 return -EBUSY;
 315         }
 316
 317         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 318             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 319                 return -EBUSY;
 320
 321         /* Writing new MAC to the specific port BAR address */
 322         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 323
 324         /* Signal the NIC about the change */
 325         update = NFP_NET_CFG_UPDATE_MACADDR;
 326         ctrl = hw->ctrl;
 327         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 328             (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 329                 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
 330         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 331                 PMD_INIT_LOG(INFO, "MAC address update failed");
 332                 return -EIO;
 333         }
 334         return 0;
 335 }
 336
 337 int
 338 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 339                            struct rte_intr_handle *intr_handle)
 340 {
 341         struct nfp_net_hw *hw;
 342         int i;
 343
 344         if (!intr_handle->intr_vec) {
 345                 intr_handle->intr_vec =
 346                         rte_zmalloc("intr_vec",
 347                                     dev->data->nb_rx_queues * sizeof(int), 0);
 348                 if (!intr_handle->intr_vec) {
 349                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 350                                      " intr_vec", dev->data->nb_rx_queues);
 351                         return -ENOMEM;
 352                 }
 353         }
 354
 355         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 356
 357         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 358                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 359                 /* UIO just supports one queue and no LSC*/
 360                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 361                 intr_handle->intr_vec[0] = 0;
 362         } else {
 363                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 364                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 365                         /*
 366                          * The first msix vector is reserved for non
 367                          * efd interrupts
 368                         */
 369                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 370                         intr_handle->intr_vec[i] = i + 1;
 371                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 372                                             intr_handle->intr_vec[i]);
 373                 }
 374         }
 375
 376         /* Avoiding TX interrupts */
 377         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 378         return 0;
 379 }
 380
 381 uint32_t
 382 nfp_check_offloads(struct rte_eth_dev *dev)
 383 {
 384         struct nfp_net_hw *hw;
 385         struct rte_eth_conf *dev_conf;
 386         struct rte_eth_rxmode *rxmode;
 387         struct rte_eth_txmode *txmode;
 388         uint32_t ctrl = 0;
 389
 390         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 391
 392         dev_conf = &dev->data->dev_conf;
 393         rxmode = &dev_conf->rxmode;
 394         txmode = &dev_conf->txmode;
 395
 396         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 397                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 398                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 399         }
 400
 401         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 402                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 403                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 404         }
 405
 406         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 407                 hw->mtu = rxmode->max_rx_pkt_len;
 408
 409         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 410                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 411
 412         /* L2 broadcast */
 413         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 414                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 415
 416         /* L2 multicast */
 417         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 418                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 419
 420         /* TX checksum offload */
 421         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 422             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 423             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 424                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 425
 426         /* LSO offload */
 427         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 428                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 429                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 430                 else
 431                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 432         }
 433
 434         /* RX gather */
 435         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 436                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 437
 438         return ctrl;
 439 }
 440
 441 static int
 442 nfp_net_start(struct rte_eth_dev *dev)
 443 {
 444         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 445         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 446         uint32_t new_ctrl, update = 0;
 447         struct nfp_net_hw *hw;
 448         struct nfp_pf_dev *pf_dev;
 449         struct rte_eth_conf *dev_conf;
 450         struct rte_eth_rxmode *rxmode;
 451         uint32_t intr_vector;
 452         int ret;
 453
 454         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 455         pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 456
 457         PMD_INIT_LOG(DEBUG, "Start");
 458
 459         /* Disabling queues just in case... */
 460         nfp_net_disable_queues(dev);
 461
 462         /* Enabling the required queues in the device */
 463         nfp_net_enable_queues(dev);
 464
 465         /* check and configure queue intr-vector mapping */
 466         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 467                 if (pf_dev->multiport) {
 468                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 469                                           "with NFP multiport PF");
 470                                 return -EINVAL;
 471                 }
 472                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 473                         /*
 474                          * Better not to share LSC with RX interrupts.
 475                          * Unregistering LSC interrupt handler
 476                          */
 477                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 478                                 nfp_net_dev_interrupt_handler, (void *)dev);
 479
 480                         if (dev->data->nb_rx_queues > 1) {
 481                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 482                                              "supports 1 queue with UIO");
 483                                 return -EIO;
 484                         }
 485                 }
 486                 intr_vector = dev->data->nb_rx_queues;
 487                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 488                         return -1;
 489
 490                 nfp_configure_rx_interrupt(dev, intr_handle);
 491                 update = NFP_NET_CFG_UPDATE_MSIX;
 492         }
 493
 494         rte_intr_enable(intr_handle);
 495
 496         new_ctrl = nfp_check_offloads(dev);
 497
 498         /* Writing configuration parameters in the device */
 499         nfp_net_params_setup(hw);
 500
 501         dev_conf = &dev->data->dev_conf;
 502         rxmode = &dev_conf->rxmode;
 503
 504         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 505                 nfp_net_rss_config_default(dev);
 506                 update |= NFP_NET_CFG_UPDATE_RSS;
 507                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 508         }
 509
 510         /* Enable device */
 511         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 512
 513         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 514
 515         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 516                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 517
 518         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 519         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 520                 return -EIO;
 521
 522         /*
 523          * Allocating rte mbufs for configured rx queues.
 524          * This requires queues being enabled before
 525          */
 526         if (nfp_net_rx_freelist_setup(dev) < 0) {
 527                 ret = -ENOMEM;
 528                 goto error;
 529         }
 530
 531         if (hw->is_phyport) {
 532                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 533                         /* Configure the physical port up */
 534                         nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 1);
 535                 else
 536                         nfp_eth_set_configured(dev->process_private,
 537                                                hw->nfp_idx, 1);
 538         }
 539
 540         hw->ctrl = new_ctrl;
 541
 542         return 0;
 543
 544 error:
 545         /*
 546          * An error returned by this function should mean the app
 547          * exiting and then the system releasing all the memory
 548          * allocated even memory coming from hugepages.
 549          *
 550          * The device could be enabled at this point with some queues
 551          * ready for getting packets. This is true if the call to
 552          * nfp_net_rx_freelist_setup() succeeds for some queues but
 553          * fails for subsequent queues.
 554          *
 555          * This should make the app exiting but better if we tell the
 556          * device first.
 557          */
 558         nfp_net_disable_queues(dev);
 559
 560         return ret;
 561 }
 562
 563 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 564 static int
 565 nfp_net_stop(struct rte_eth_dev *dev)
 566 {
 567         int i;
 568         struct nfp_net_hw *hw;
 569
 570         PMD_INIT_LOG(DEBUG, "Stop");
 571
 572         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 573
 574         nfp_net_disable_queues(dev);
 575
 576         /* Clear queues */
 577         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 578                 nfp_net_reset_tx_queue(
 579                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 580         }
 581
 582         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 583                 nfp_net_reset_rx_queue(
 584                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 585         }
 586
 587         if (hw->is_phyport) {
 588                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 589                         /* Configure the physical port down */
 590                         nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 0);
 591                 else
 592                         nfp_eth_set_configured(dev->process_private,
 593                                                hw->nfp_idx, 0);
 594         }
 595
 596         return 0;
 597 }
 598
 599 /* Set the link up. */
 600 static int
 601 nfp_net_set_link_up(struct rte_eth_dev *dev)
 602 {
 603         struct nfp_net_hw *hw;
 604
 605         PMD_DRV_LOG(DEBUG, "Set link up");
 606
 607         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 608
 609         if (!hw->is_phyport)
 610                 return -ENOTSUP;
 611
 612         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 613                 /* Configure the physical port down */
 614                 return nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 1);
 615         else
 616                 return nfp_eth_set_configured(dev->process_private,
 617                                               hw->nfp_idx, 1);
 618 }
 619
 620 /* Set the link down. */
 621 static int
 622 nfp_net_set_link_down(struct rte_eth_dev *dev)
 623 {
 624         struct nfp_net_hw *hw;
 625
 626         PMD_DRV_LOG(DEBUG, "Set link down");
 627
 628         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 629
 630         if (!hw->is_phyport)
 631                 return -ENOTSUP;
 632
 633         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 634                 /* Configure the physical port down */
 635                 return nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 0);
 636         else
 637                 return nfp_eth_set_configured(dev->process_private,
 638                                               hw->nfp_idx, 0);
 639 }
 640
 641 /* Reset and stop device. The device can not be restarted. */
 642 static int
 643 nfp_net_close(struct rte_eth_dev *dev)
 644 {
 645         struct nfp_net_hw *hw;
 646         struct rte_pci_device *pci_dev;
 647         int i;
 648
 649         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 650                 return 0;
 651
 652         PMD_INIT_LOG(DEBUG, "Close");
 653
 654         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 655         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 656
 657         /*
 658          * We assume that the DPDK application is stopping all the
 659          * threads/queues before calling the device close function.
 660          */
 661
 662         nfp_net_disable_queues(dev);
 663
 664         /* Clear queues */
 665         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 666                 nfp_net_reset_tx_queue(
 667                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 668         }
 669
 670         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 671                 nfp_net_reset_rx_queue(
 672                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 673         }
 674
 675         /* Only free PF resources after all physical ports have been closed */
 676         if (pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC ||
 677             pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC) {
 678                 struct nfp_pf_dev *pf_dev;
 679                 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 680
 681                 /* Mark this port as unused and free device priv resources*/
 682                 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 683                 pf_dev->ports[hw->idx] = NULL;
 684                 rte_eth_dev_release_port(dev);
 685
 686                 for (i = 0; i < pf_dev->total_phyports; i++) {
 687                         /* Check to see if ports are still in use */
 688                         if (pf_dev->ports[i])
 689                                 return 0;
 690                 }
 691
 692                 /* Now it is safe to free all PF resources */
 693                 PMD_INIT_LOG(INFO, "Freeing PF resources");
 694                 nfp_cpp_area_free(pf_dev->ctrl_area);
 695                 nfp_cpp_area_free(pf_dev->hwqueues_area);
 696                 free(pf_dev->hwinfo);
 697                 free(pf_dev->sym_tbl);
 698                 nfp_cpp_free(pf_dev->cpp);
 699                 rte_free(pf_dev);
 700         }
 701
 702         rte_intr_disable(&pci_dev->intr_handle);
 703
 704         /* unregister callback func from eal lib */
 705         rte_intr_callback_unregister(&pci_dev->intr_handle,
 706                                      nfp_net_dev_interrupt_handler,
 707                                      (void *)dev);
 708
 709         /*
 710          * The ixgbe PMD driver disables the pcie master on the
 711          * device. The i40e does not...
 712          */
 713
 714         return 0;
 715 }
 716
 717 int
 718 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 719 {
 720         uint32_t new_ctrl, update = 0;
 721         struct nfp_net_hw *hw;
 722         int ret;
 723
 724         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 725
 726         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 727
 728         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 729                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 730                 return -ENOTSUP;
 731         }
 732
 733         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 734                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 735                 return 0;
 736         }
 737
 738         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 739         update = NFP_NET_CFG_UPDATE_GEN;
 740
 741         /*
 742          * DPDK sets promiscuous mode on just after this call assuming
 743          * it can not fail ...
 744          */
 745         ret = nfp_net_reconfig(hw, new_ctrl, update);
 746         if (ret < 0)
 747                 return ret;
 748
 749         hw->ctrl = new_ctrl;
 750
 751         return 0;
 752 }
 753
 754 int
 755 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 756 {
 757         uint32_t new_ctrl, update = 0;
 758         struct nfp_net_hw *hw;
 759         int ret;
 760
 761         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 762
 763         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 764                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 765                 return 0;
 766         }
 767
 768         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 769         update = NFP_NET_CFG_UPDATE_GEN;
 770
 771         /*
 772          * DPDK sets promiscuous mode off just before this call
 773          * assuming it can not fail ...
 774          */
 775         ret = nfp_net_reconfig(hw, new_ctrl, update);
 776         if (ret < 0)
 777                 return ret;
 778
 779         hw->ctrl = new_ctrl;
 780
 781         return 0;
 782 }
 783
 784 /*
 785  * return 0 means link status changed, -1 means not changed
 786  *
 787  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 788  * status.
 789  */
 790 int
 791 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 792 {
 793         struct nfp_net_hw *hw;
 794         struct rte_eth_link link;
 795         uint32_t nn_link_status;
 796         int ret;
 797
 798         static const uint32_t ls_to_ethtool[] = {
 799                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 800                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 801                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 802                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 803                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 804                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 805                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 806                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 807         };
 808
 809         PMD_DRV_LOG(DEBUG, "Link update");
 810
 811         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 812
 813         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 814
 815         memset(&link, 0, sizeof(struct rte_eth_link));
 816
 817         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 818                 link.link_status = ETH_LINK_UP;
 819
 820         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 821
 822         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 823                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 824
 825         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 826                 link.link_speed = ETH_SPEED_NUM_NONE;
 827         else
 828                 link.link_speed = ls_to_ethtool[nn_link_status];
 829
 830         ret = rte_eth_linkstatus_set(dev, &link);
 831         if (ret == 0) {
 832                 if (link.link_status)
 833                         PMD_DRV_LOG(INFO, "NIC Link is Up");
 834                 else
 835                         PMD_DRV_LOG(INFO, "NIC Link is Down");
 836         }
 837         return ret;
 838 }
 839
 840 int
 841 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 842 {
 843         int i;
 844         struct nfp_net_hw *hw;
 845         struct rte_eth_stats nfp_dev_stats;
 846
 847         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 848
 849         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
 850
 851         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
 852
 853         /* reading per RX ring stats */
 854         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 855                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 856                         break;
 857
 858                 nfp_dev_stats.q_ipackets[i] =
 859                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
 860
 861                 nfp_dev_stats.q_ipackets[i] -=
 862                         hw->eth_stats_base.q_ipackets[i];
 863
 864                 nfp_dev_stats.q_ibytes[i] =
 865                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
 866
 867                 nfp_dev_stats.q_ibytes[i] -=
 868                         hw->eth_stats_base.q_ibytes[i];
 869         }
 870
 871         /* reading per TX ring stats */
 872         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 873                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 874                         break;
 875
 876                 nfp_dev_stats.q_opackets[i] =
 877                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
 878
 879                 nfp_dev_stats.q_opackets[i] -=
 880                         hw->eth_stats_base.q_opackets[i];
 881
 882                 nfp_dev_stats.q_obytes[i] =
 883                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
 884
 885                 nfp_dev_stats.q_obytes[i] -=
 886                         hw->eth_stats_base.q_obytes[i];
 887         }
 888
 889         nfp_dev_stats.ipackets =
 890                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
 891
 892         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
 893
 894         nfp_dev_stats.ibytes =
 895                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
 896
 897         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
 898
 899         nfp_dev_stats.opackets =
 900                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
 901
 902         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
 903
 904         nfp_dev_stats.obytes =
 905                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
 906
 907         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
 908
 909         /* reading general device stats */
 910         nfp_dev_stats.ierrors =
 911                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
 912
 913         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
 914
 915         nfp_dev_stats.oerrors =
 916                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
 917
 918         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
 919
 920         /* RX ring mbuf allocation failures */
 921         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
 922
 923         nfp_dev_stats.imissed =
 924                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
 925
 926         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
 927
 928         if (stats) {
 929                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
 930                 return 0;
 931         }
 932         return -EINVAL;
 933 }
 934
 935 int
 936 nfp_net_stats_reset(struct rte_eth_dev *dev)
 937 {
 938         int i;
 939         struct nfp_net_hw *hw;
 940
 941         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 942
 943         /*
 944          * hw->eth_stats_base records the per counter starting point.
 945          * Lets update it now
 946          */
 947
 948         /* reading per RX ring stats */
 949         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 950                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 951                         break;
 952
 953                 hw->eth_stats_base.q_ipackets[i] =
 954                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
 955
 956                 hw->eth_stats_base.q_ibytes[i] =
 957                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
 958         }
 959
 960         /* reading per TX ring stats */
 961         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 962                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 963                         break;
 964
 965                 hw->eth_stats_base.q_opackets[i] =
 966                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
 967
 968                 hw->eth_stats_base.q_obytes[i] =
 969                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
 970         }
 971
 972         hw->eth_stats_base.ipackets =
 973                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
 974
 975         hw->eth_stats_base.ibytes =
 976                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
 977
 978         hw->eth_stats_base.opackets =
 979                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
 980
 981         hw->eth_stats_base.obytes =
 982                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
 983
 984         /* reading general device stats */
 985         hw->eth_stats_base.ierrors =
 986                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
 987
 988         hw->eth_stats_base.oerrors =
 989                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
 990
 991         /* RX ring mbuf allocation failures */
 992         dev->data->rx_mbuf_alloc_failed = 0;
 993
 994         hw->eth_stats_base.imissed =
 995                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
 996
 997         return 0;
 998 }
 999
1000 int
1001 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1002 {
1003         struct nfp_net_hw *hw;
1004
1005         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006
1007         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1008         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1009         dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1010         dev_info->max_rx_pktlen = hw->max_mtu;
1011         /* Next should change when PF support is implemented */
1012         dev_info->max_mac_addrs = 1;
1013
1014         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1015                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1016
1017         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1018                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1019                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1020                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1021
1022         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1023                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1024
1025         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1026                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1027                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1028                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1029
1030         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1031                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1032
1033         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1034                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1035
1036         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1037                 .rx_thresh = {
1038                         .pthresh = DEFAULT_RX_PTHRESH,
1039                         .hthresh = DEFAULT_RX_HTHRESH,
1040                         .wthresh = DEFAULT_RX_WTHRESH,
1041                 },
1042                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1043                 .rx_drop_en = 0,
1044         };
1045
1046         dev_info->default_txconf = (struct rte_eth_txconf) {
1047                 .tx_thresh = {
1048                         .pthresh = DEFAULT_TX_PTHRESH,
1049                         .hthresh = DEFAULT_TX_HTHRESH,
1050                         .wthresh = DEFAULT_TX_WTHRESH,
1051                 },
1052                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1053                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1054         };
1055
1056         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1057                 .nb_max = NFP_NET_MAX_RX_DESC,
1058                 .nb_min = NFP_NET_MIN_RX_DESC,
1059                 .nb_align = NFP_ALIGN_RING_DESC,
1060         };
1061
1062         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1063                 .nb_max = NFP_NET_MAX_TX_DESC,
1064                 .nb_min = NFP_NET_MIN_TX_DESC,
1065                 .nb_align = NFP_ALIGN_RING_DESC,
1066                 .nb_seg_max = NFP_TX_MAX_SEG,
1067                 .nb_mtu_seg_max = NFP_TX_MAX_MTU_SEG,
1068         };
1069
1070         /* All NFP devices support jumbo frames */
1071         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1072
1073         if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
1074                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_RSS_HASH;
1075
1076                 dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1077                                                    ETH_RSS_NONFRAG_IPV4_TCP |
1078                                                    ETH_RSS_NONFRAG_IPV4_UDP |
1079                                                    ETH_RSS_IPV6 |
1080                                                    ETH_RSS_NONFRAG_IPV6_TCP |
1081                                                    ETH_RSS_NONFRAG_IPV6_UDP;
1082
1083                 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1084                 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1085         }
1086
1087         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1088                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1089                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1090
1091         return 0;
1092 }
1093
1094 const uint32_t *
1095 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1096 {
1097         static const uint32_t ptypes[] = {
1098                 /* refers to nfp_net_set_hash() */
1099                 RTE_PTYPE_INNER_L3_IPV4,
1100                 RTE_PTYPE_INNER_L3_IPV6,
1101                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1102                 RTE_PTYPE_INNER_L4_MASK,
1103                 RTE_PTYPE_UNKNOWN
1104         };
1105
1106         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1107                 return ptypes;
1108         return NULL;
1109 }
1110
1111 int
1112 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1113 {
1114         struct rte_pci_device *pci_dev;
1115         struct nfp_net_hw *hw;
1116         int base = 0;
1117
1118         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1119         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1120
1121         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1122                 base = 1;
1123
1124         /* Make sure all updates are written before un-masking */
1125         rte_wmb();
1126         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1127                       NFP_NET_CFG_ICR_UNMASKED);
1128         return 0;
1129 }
1130
1131 int
1132 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1133 {
1134         struct rte_pci_device *pci_dev;
1135         struct nfp_net_hw *hw;
1136         int base = 0;
1137
1138         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1139         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1140
1141         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1142                 base = 1;
1143
1144         /* Make sure all updates are written before un-masking */
1145         rte_wmb();
1146         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1147         return 0;
1148 }
1149
1150 static void
1151 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1152 {
1153         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1154         struct rte_eth_link link;
1155
1156         rte_eth_linkstatus_get(dev, &link);
1157         if (link.link_status)
1158                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1159                             dev->data->port_id, link.link_speed,
1160                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1161                             ? "full-duplex" : "half-duplex");
1162         else
1163                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1164                             dev->data->port_id);
1165
1166         PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
1167                     pci_dev->addr.domain, pci_dev->addr.bus,
1168                     pci_dev->addr.devid, pci_dev->addr.function);
1169 }
1170
1171 /* Interrupt configuration and handling */
1172
1173 /*
1174  * nfp_net_irq_unmask - Unmask an interrupt
1175  *
1176  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1177  * clear the ICR for the entry.
1178  */
1179 static void
1180 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1181 {
1182         struct nfp_net_hw *hw;
1183         struct rte_pci_device *pci_dev;
1184
1185         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1186         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1187
1188         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1189                 /* If MSI-X auto-masking is used, clear the entry */
1190                 rte_wmb();
1191                 rte_intr_ack(&pci_dev->intr_handle);
1192         } else {
1193                 /* Make sure all updates are written before un-masking */
1194                 rte_wmb();
1195                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1196                               NFP_NET_CFG_ICR_UNMASKED);
1197         }
1198 }
1199
1200 /*
1201  * Interrupt handler which shall be registered for alarm callback for delayed
1202  * handling specific interrupt to wait for the stable nic state. As the NIC
1203  * interrupt state is not stable for nfp after link is just down, it needs
1204  * to wait 4 seconds to get the stable status.
1205  *
1206  * @param handle   Pointer to interrupt handle.
1207  * @param param    The address of parameter (struct rte_eth_dev *)
1208  *
1209  * @return  void
1210  */
1211 static void
1212 nfp_net_dev_interrupt_delayed_handler(void *param)
1213 {
1214         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1215
1216         nfp_net_link_update(dev, 0);
1217         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1218
1219         nfp_net_dev_link_status_print(dev);
1220
1221         /* Unmasking */
1222         nfp_net_irq_unmask(dev);
1223 }
1224
1225 void
1226 nfp_net_dev_interrupt_handler(void *param)
1227 {
1228         int64_t timeout;
1229         struct rte_eth_link link;
1230         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1231
1232         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1233
1234         rte_eth_linkstatus_get(dev, &link);
1235
1236         nfp_net_link_update(dev, 0);
1237
1238         /* likely to up */
1239         if (!link.link_status) {
1240                 /* handle it 1 sec later, wait it being stable */
1241                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1242                 /* likely to down */
1243         } else {
1244                 /* handle it 4 sec later, wait it being stable */
1245                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1246         }
1247
1248         if (rte_eal_alarm_set(timeout * 1000,
1249                               nfp_net_dev_interrupt_delayed_handler,
1250                               (void *)dev) < 0) {
1251                 PMD_INIT_LOG(ERR, "Error setting alarm");
1252                 /* Unmasking */
1253                 nfp_net_irq_unmask(dev);
1254         }
1255 }
1256
1257 int
1258 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1259 {
1260         struct nfp_net_hw *hw;
1261
1262         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1263
1264         /* check that mtu is within the allowed range */
1265         if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1266                 return -EINVAL;
1267
1268         /* mtu setting is forbidden if port is started */
1269         if (dev->data->dev_started) {
1270                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1271                             dev->data->port_id);
1272                 return -EBUSY;
1273         }
1274
1275         /* switch to jumbo mode if needed */
1276         if ((uint32_t)mtu > RTE_ETHER_MTU)
1277                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1278         else
1279                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1280
1281         /* update max frame size */
1282         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1283
1284         /* writing to configuration space */
1285         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1286
1287         hw->mtu = mtu;
1288
1289         return 0;
1290 }
1291
1292 int
1293 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1294 {
1295         uint32_t new_ctrl, update;
1296         struct nfp_net_hw *hw;
1297         int ret;
1298
1299         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1300         new_ctrl = 0;
1301
1302         /* Enable vlan strip if it is not configured yet */
1303         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
1304             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
1305                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
1306
1307         /* Disable vlan strip just if it is configured */
1308         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
1309             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
1310                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
1311
1312         if (new_ctrl == 0)
1313                 return 0;
1314
1315         update = NFP_NET_CFG_UPDATE_GEN;
1316
1317         ret = nfp_net_reconfig(hw, new_ctrl, update);
1318         if (!ret)
1319                 hw->ctrl = new_ctrl;
1320
1321         return ret;
1322 }
1323
1324 static int
1325 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
1326                     struct rte_eth_rss_reta_entry64 *reta_conf,
1327                     uint16_t reta_size)
1328 {
1329         uint32_t reta, mask;
1330         int i, j;
1331         int idx, shift;
1332         struct nfp_net_hw *hw =
1333                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1334
1335         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
1336                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1337                         "(%d) doesn't match the number hardware can supported "
1338                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
1339                 return -EINVAL;
1340         }
1341
1342         /*
1343          * Update Redirection Table. There are 128 8bit-entries which can be
1344          * manage as 32 32bit-entries
1345          */
1346         for (i = 0; i < reta_size; i += 4) {
1347                 /* Handling 4 RSS entries per loop */
1348                 idx = i / RTE_RETA_GROUP_SIZE;
1349                 shift = i % RTE_RETA_GROUP_SIZE;
1350                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
1351
1352                 if (!mask)
1353                         continue;
1354
1355                 reta = 0;
1356                 /* If all 4 entries were set, don't need read RETA register */
1357                 if (mask != 0xF)
1358                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
1359
1360                 for (j = 0; j < 4; j++) {
1361                         if (!(mask & (0x1 << j)))
1362                                 continue;
1363                         if (mask != 0xF)
1364                                 /* Clearing the entry bits */
1365                                 reta &= ~(0xFF << (8 * j));
1366                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
1367                 }
1368                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
1369                               reta);
1370         }
1371         return 0;
1372 }
1373
1374 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
1375 int
1376 nfp_net_reta_update(struct rte_eth_dev *dev,
1377                     struct rte_eth_rss_reta_entry64 *reta_conf,
1378                     uint16_t reta_size)
1379 {
1380         struct nfp_net_hw *hw =
1381                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1382         uint32_t update;
1383         int ret;
1384
1385         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1386                 return -EINVAL;
1387
1388         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
1389         if (ret != 0)
1390                 return ret;
1391
1392         update = NFP_NET_CFG_UPDATE_RSS;
1393
1394         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
1395                 return -EIO;
1396
1397         return 0;
1398 }
1399
1400  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
1401 int
1402 nfp_net_reta_query(struct rte_eth_dev *dev,
1403                    struct rte_eth_rss_reta_entry64 *reta_conf,
1404                    uint16_t reta_size)
1405 {
1406         uint8_t i, j, mask;
1407         int idx, shift;
1408         uint32_t reta;
1409         struct nfp_net_hw *hw;
1410
1411         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1412
1413         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1414                 return -EINVAL;
1415
1416         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
1417                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1418                         "(%d) doesn't match the number hardware can supported "
1419                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
1420                 return -EINVAL;
1421         }
1422
1423         /*
1424          * Reading Redirection Table. There are 128 8bit-entries which can be
1425          * manage as 32 32bit-entries
1426          */
1427         for (i = 0; i < reta_size; i += 4) {
1428                 /* Handling 4 RSS entries per loop */
1429                 idx = i / RTE_RETA_GROUP_SIZE;
1430                 shift = i % RTE_RETA_GROUP_SIZE;
1431                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
1432
1433                 if (!mask)
1434                         continue;
1435
1436                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
1437                                     shift);
1438                 for (j = 0; j < 4; j++) {
1439                         if (!(mask & (0x1 << j)))
1440                                 continue;
1441                         reta_conf[idx].reta[shift + j] =
1442                                 (uint8_t)((reta >> (8 * j)) & 0xF);
1443                 }
1444         }
1445         return 0;
1446 }
1447
1448 static int
1449 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
1450                         struct rte_eth_rss_conf *rss_conf)
1451 {
1452         struct nfp_net_hw *hw;
1453         uint64_t rss_hf;
1454         uint32_t cfg_rss_ctrl = 0;
1455         uint8_t key;
1456         int i;
1457
1458         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1459
1460         /* Writing the key byte a byte */
1461         for (i = 0; i < rss_conf->rss_key_len; i++) {
1462                 memcpy(&key, &rss_conf->rss_key[i], 1);
1463                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
1464         }
1465
1466         rss_hf = rss_conf->rss_hf;
1467
1468         if (rss_hf & ETH_RSS_IPV4)
1469                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
1470
1471         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1472                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
1473
1474         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1475                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
1476
1477         if (rss_hf & ETH_RSS_IPV6)
1478                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
1479
1480         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1481                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
1482
1483         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1484                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
1485
1486         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
1487         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
1488
1489         /* configuring where to apply the RSS hash */
1490         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
1491
1492         /* Writing the key size */
1493         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
1494
1495         return 0;
1496 }
1497
1498 int
1499 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
1500                         struct rte_eth_rss_conf *rss_conf)
1501 {
1502         uint32_t update;
1503         uint64_t rss_hf;
1504         struct nfp_net_hw *hw;
1505
1506         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507
1508         rss_hf = rss_conf->rss_hf;
1509
1510         /* Checking if RSS is enabled */
1511         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
1512                 if (rss_hf != 0) { /* Enable RSS? */
1513                         PMD_DRV_LOG(ERR, "RSS unsupported");
1514                         return -EINVAL;
1515                 }
1516                 return 0; /* Nothing to do */
1517         }
1518
1519         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
1520                 PMD_DRV_LOG(ERR, "hash key too long");
1521                 return -EINVAL;
1522         }
1523
1524         nfp_net_rss_hash_write(dev, rss_conf);
1525
1526         update = NFP_NET_CFG_UPDATE_RSS;
1527
1528         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
1529                 return -EIO;
1530
1531         return 0;
1532 }
1533
1534 int
1535 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
1536                           struct rte_eth_rss_conf *rss_conf)
1537 {
1538         uint64_t rss_hf;
1539         uint32_t cfg_rss_ctrl;
1540         uint8_t key;
1541         int i;
1542         struct nfp_net_hw *hw;
1543
1544         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1545
1546         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1547                 return -EINVAL;
1548
1549         rss_hf = rss_conf->rss_hf;
1550         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
1551
1552         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
1553                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
1554
1555         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
1556                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1557
1558         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
1559                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1560
1561         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
1562                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1563
1564         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
1565                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1566
1567         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
1568                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
1569
1570         /* Propagate current RSS hash functions to caller */
1571         rss_conf->rss_hf = rss_hf;
1572
1573         /* Reading the key size */
1574         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
1575
1576         /* Reading the key byte a byte */
1577         for (i = 0; i < rss_conf->rss_key_len; i++) {
1578                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
1579                 memcpy(&rss_conf->rss_key[i], &key, 1);
1580         }
1581
1582         return 0;
1583 }
1584
1585 int
1586 nfp_net_rss_config_default(struct rte_eth_dev *dev)
1587 {
1588         struct rte_eth_conf *dev_conf;
1589         struct rte_eth_rss_conf rss_conf;
1590         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
1591         uint16_t rx_queues = dev->data->nb_rx_queues;
1592         uint16_t queue;
1593         int i, j, ret;
1594
1595         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
1596                 rx_queues);
1597
1598         nfp_reta_conf[0].mask = ~0x0;
1599         nfp_reta_conf[1].mask = ~0x0;
1600
1601         queue = 0;
1602         for (i = 0; i < 0x40; i += 8) {
1603                 for (j = i; j < (i + 8); j++) {
1604                         nfp_reta_conf[0].reta[j] = queue;
1605                         nfp_reta_conf[1].reta[j] = queue++;
1606                         queue %= rx_queues;
1607                 }
1608         }
1609         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
1610         if (ret != 0)
1611                 return ret;
1612
1613         dev_conf = &dev->data->dev_conf;
1614         if (!dev_conf) {
1615                 PMD_DRV_LOG(INFO, "wrong rss conf");
1616                 return -EINVAL;
1617         }
1618         rss_conf = dev_conf->rx_adv_conf.rss_conf;
1619
1620         ret = nfp_net_rss_hash_write(dev, &rss_conf);
1621
1622         return ret;
1623 }
1624
1625
1626 /* Initialise and register driver with DPDK Application */
1627 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
1628         .dev_configure          = nfp_net_configure,
1629         .dev_start              = nfp_net_start,
1630         .dev_stop               = nfp_net_stop,
1631         .dev_set_link_up        = nfp_net_set_link_up,
1632         .dev_set_link_down      = nfp_net_set_link_down,
1633         .dev_close              = nfp_net_close,
1634         .promiscuous_enable     = nfp_net_promisc_enable,
1635         .promiscuous_disable    = nfp_net_promisc_disable,
1636         .link_update            = nfp_net_link_update,
1637         .stats_get              = nfp_net_stats_get,
1638         .stats_reset            = nfp_net_stats_reset,
1639         .dev_infos_get          = nfp_net_infos_get,
1640         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
1641         .mtu_set                = nfp_net_dev_mtu_set,
1642         .mac_addr_set           = nfp_set_mac_addr,
1643         .vlan_offload_set       = nfp_net_vlan_offload_set,
1644         .reta_update            = nfp_net_reta_update,
1645         .reta_query             = nfp_net_reta_query,
1646         .rss_hash_update        = nfp_net_rss_hash_update,
1647         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
1648         .rx_queue_setup         = nfp_net_rx_queue_setup,
1649         .rx_queue_release       = nfp_net_rx_queue_release,
1650         .tx_queue_setup         = nfp_net_tx_queue_setup,
1651         .tx_queue_release       = nfp_net_tx_queue_release,
1652         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
1653         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
1654 };
1655
1656
1657 static int
1658 nfp_net_init(struct rte_eth_dev *eth_dev)
1659 {
1660         struct rte_pci_device *pci_dev;
1661         struct nfp_pf_dev *pf_dev;
1662         struct nfp_net_hw *hw;
1663
1664         uint64_t tx_bar_off = 0, rx_bar_off = 0;
1665         uint32_t start_q;
1666         int stride = 4;
1667         int port = 0;
1668         int err;
1669
1670         PMD_INIT_FUNC_TRACE();
1671
1672         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1673
1674         /* Use backpointer here to the PF of this eth_dev */
1675         pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(eth_dev->data->dev_private);
1676
1677         /* NFP can not handle DMA addresses requiring more than 40 bits */
1678         if (rte_mem_check_dma_mask(40)) {
1679                 RTE_LOG(ERR, PMD, "device %s can not be used:",
1680                                    pci_dev->device.name);
1681                 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
1682                 return -ENODEV;
1683         };
1684
1685         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
1686             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
1687                 port = ((struct nfp_net_hw *)eth_dev->data->dev_private)->idx;
1688                 if (port < 0 || port > 7) {
1689                         PMD_DRV_LOG(ERR, "Port value is wrong");
1690                         return -ENODEV;
1691                 }
1692
1693                 /* Use PF array of physical ports to get pointer to
1694                  * this specific port
1695                  */
1696                 hw = pf_dev->ports[port];
1697
1698                 PMD_INIT_LOG(DEBUG, "Working with physical port number: %d, "
1699                                     "NFP internal port number: %d",
1700                                     port, hw->nfp_idx);
1701
1702         } else {
1703                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1704         }
1705
1706         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
1707         eth_dev->rx_queue_count = nfp_net_rx_queue_count;
1708         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
1709         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
1710
1711         /* For secondary processes, the primary has done all the work */
1712         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1713                 return 0;
1714
1715         rte_eth_copy_pci_info(eth_dev, pci_dev);
1716
1717         hw->device_id = pci_dev->id.device_id;
1718         hw->vendor_id = pci_dev->id.vendor_id;
1719         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1720         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1721
1722         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
1723                      pci_dev->id.vendor_id, pci_dev->id.device_id,
1724                      pci_dev->addr.domain, pci_dev->addr.bus,
1725                      pci_dev->addr.devid, pci_dev->addr.function);
1726
1727         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
1728         if (hw->ctrl_bar == NULL) {
1729                 PMD_DRV_LOG(ERR,
1730                         "hw->ctrl_bar is NULL. BAR0 not configured");
1731                 return -ENODEV;
1732         }
1733
1734         if (hw->is_phyport) {
1735                 if (port == 0) {
1736                         hw->ctrl_bar = pf_dev->ctrl_bar;
1737                 } else {
1738                         if (!pf_dev->ctrl_bar)
1739                                 return -ENODEV;
1740                         /* Use port offset in pf ctrl_bar for this
1741                          * ports control bar
1742                          */
1743                         hw->ctrl_bar = pf_dev->ctrl_bar +
1744                                        (port * NFP_PF_CSR_SLICE_SIZE);
1745                 }
1746         }
1747
1748         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
1749
1750         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
1751         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
1752
1753         /* Work out where in the BAR the queues start. */
1754         switch (pci_dev->id.device_id) {
1755         case PCI_DEVICE_ID_NFP4000_PF_NIC:
1756         case PCI_DEVICE_ID_NFP6000_PF_NIC:
1757         case PCI_DEVICE_ID_NFP6000_VF_NIC:
1758                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
1759                 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
1760                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
1761                 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
1762                 break;
1763         default:
1764                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
1765                 err = -ENODEV;
1766                 goto dev_err_ctrl_map;
1767         }
1768
1769         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
1770         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
1771
1772         if (hw->is_phyport) {
1773                 hw->tx_bar = pf_dev->hw_queues + tx_bar_off;
1774                 hw->rx_bar = pf_dev->hw_queues + rx_bar_off;
1775                 eth_dev->data->dev_private = hw;
1776         } else {
1777                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
1778                              tx_bar_off;
1779                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
1780                              rx_bar_off;
1781         }
1782
1783         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
1784                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
1785
1786         nfp_net_cfg_queue_setup(hw);
1787
1788         /* Get some of the read-only fields from the config BAR */
1789         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
1790         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
1791         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
1792         hw->mtu = RTE_ETHER_MTU;
1793
1794         /* VLAN insertion is incompatible with LSOv2 */
1795         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
1796                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
1797
1798         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
1799                 hw->rx_offset = NFP_NET_RX_OFFSET;
1800         else
1801                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
1802
1803         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
1804                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
1805                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
1806
1807         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
1808                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
1809                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
1810                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
1811                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
1812                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
1813                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
1814                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
1815                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
1816                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
1817                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
1818                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
1819                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
1820                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
1821                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
1822
1823         hw->ctrl = 0;
1824
1825         hw->stride_rx = stride;
1826         hw->stride_tx = stride;
1827
1828         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
1829                      hw->max_rx_queues, hw->max_tx_queues);
1830
1831         /* Initializing spinlock for reconfigs */
1832         rte_spinlock_init(&hw->reconfig_lock);
1833
1834         /* Allocating memory for mac addr */
1835         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1836                                                RTE_ETHER_ADDR_LEN, 0);
1837         if (eth_dev->data->mac_addrs == NULL) {
1838                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
1839                 err = -ENOMEM;
1840                 goto dev_err_queues_map;
1841         }
1842
1843         if (hw->is_phyport) {
1844                 nfp_net_pf_read_mac(pf_dev, port);
1845                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
1846         }
1847
1848         if (!rte_is_valid_assigned_ether_addr(
1849                     (struct rte_ether_addr *)&hw->mac_addr)) {
1850                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
1851                                    port);
1852                 /* Using random mac addresses for VFs */
1853                 rte_eth_random_addr(&hw->mac_addr[0]);
1854                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
1855         }
1856
1857         /* Copying mac address to DPDK eth_dev struct */
1858         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
1859                         &eth_dev->data->mac_addrs[0]);
1860
1861         if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
1862                 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
1863
1864         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1865
1866         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
1867                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
1868                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1869                      pci_dev->id.device_id,
1870                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
1871                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
1872
1873         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1874                 /* Registering LSC interrupt handler */
1875                 rte_intr_callback_register(&pci_dev->intr_handle,
1876                                            nfp_net_dev_interrupt_handler,
1877                                            (void *)eth_dev);
1878                 /* Telling the firmware about the LSC interrupt entry */
1879                 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
1880                 /* Recording current stats counters values */
1881                 nfp_net_stats_reset(eth_dev);
1882         }
1883
1884         return 0;
1885
1886 dev_err_queues_map:
1887                 nfp_cpp_area_free(hw->hwqueues_area);
1888 dev_err_ctrl_map:
1889                 nfp_cpp_area_free(hw->ctrl_area);
1890
1891         return err;
1892 }
1893
1894 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
1895
1896 static int
1897 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
1898 {
1899         struct nfp_cpp *cpp = nsp->cpp;
1900         void *fw_buf;
1901         char fw_name[125];
1902         char serial[40];
1903         size_t fsize;
1904
1905         /* Looking for firmware file in order of priority */
1906
1907         /* First try to find a firmware image specific for this device */
1908         snprintf(serial, sizeof(serial),
1909                         "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
1910                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
1911                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
1912                 cpp->interface & 0xff);
1913
1914         snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
1915                         serial);
1916         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
1917         if (rte_firmware_read(fw_name, &fw_buf, &fsize) == 0)
1918                 goto load_fw;
1919
1920         /* Then try the PCI name */
1921         snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
1922                         dev->device.name);
1923         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
1924         if (rte_firmware_read(fw_name, &fw_buf, &fsize) == 0)
1925                 goto load_fw;
1926
1927         /* Finally try the card type and media */
1928         snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
1929         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
1930         if (rte_firmware_read(fw_name, &fw_buf, &fsize) < 0) {
1931                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
1932                 return -ENOENT;
1933         }
1934
1935 load_fw:
1936         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %zu",
1937                 fw_name, fsize);
1938
1939         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
1940         nfp_nsp_load_fw(nsp, fw_buf, fsize);
1941         PMD_DRV_LOG(INFO, "Done");
1942
1943         free(fw_buf);
1944         return 0;
1945 }
1946
1947 static int
1948 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
1949              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
1950 {
1951         struct nfp_nsp *nsp;
1952         const char *nfp_fw_model;
1953         char card_desc[100];
1954         int err = 0;
1955
1956         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
1957
1958         if (nfp_fw_model) {
1959                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
1960         } else {
1961                 PMD_DRV_LOG(ERR, "firmware model NOT found");
1962                 return -EIO;
1963         }
1964
1965         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
1966                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
1967                        nfp_eth_table->count);
1968                 return -EIO;
1969         }
1970
1971         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
1972                            nfp_eth_table->count);
1973
1974         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
1975
1976         snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
1977                         nfp_fw_model, nfp_eth_table->count,
1978                         nfp_eth_table->ports[0].speed / 1000);
1979
1980         nsp = nfp_nsp_open(cpp);
1981         if (!nsp) {
1982                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
1983                 return -EIO;
1984         }
1985
1986         nfp_nsp_device_soft_reset(nsp);
1987         err = nfp_fw_upload(dev, nsp, card_desc);
1988
1989         nfp_nsp_close(nsp);
1990         return err;
1991 }
1992
1993 static int nfp_init_phyports(struct nfp_pf_dev *pf_dev)
1994 {
1995         struct nfp_net_hw *hw;
1996         struct rte_eth_dev *eth_dev;
1997         struct nfp_eth_table *nfp_eth_table = NULL;
1998         int ret = 0;
1999         int i;
2000
2001         nfp_eth_table = nfp_eth_read_ports(pf_dev->cpp);
2002         if (!nfp_eth_table) {
2003                 PMD_INIT_LOG(ERR, "Error reading NFP ethernet table");
2004                 ret = -EIO;
2005                 goto error;
2006         }
2007
2008         /* Loop through all physical ports on PF */
2009         for (i = 0; i < pf_dev->total_phyports; i++) {
2010                 const unsigned int numa_node = rte_socket_id();
2011                 char port_name[RTE_ETH_NAME_MAX_LEN];
2012
2013                 snprintf(port_name, sizeof(port_name), "%s_port%d",
2014                          pf_dev->pci_dev->device.name, i);
2015
2016                 /* Allocate a eth_dev for this phyport */
2017                 eth_dev = rte_eth_dev_allocate(port_name);
2018                 if (!eth_dev) {
2019                         ret = -ENODEV;
2020                         goto port_cleanup;
2021                 }
2022
2023                 /* Allocate memory for this phyport */
2024                 eth_dev->data->dev_private =
2025                         rte_zmalloc_socket(port_name, sizeof(struct nfp_net_hw),
2026                                            RTE_CACHE_LINE_SIZE, numa_node);
2027                 if (!eth_dev->data->dev_private) {
2028                         ret = -ENOMEM;
2029                         rte_eth_dev_release_port(eth_dev);
2030                         goto port_cleanup;
2031                 }
2032
2033                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2034
2035                 /* Add this device to the PF's array of physical ports */
2036                 pf_dev->ports[i] = hw;
2037
2038                 hw->pf_dev = pf_dev;
2039                 hw->cpp = pf_dev->cpp;
2040                 hw->eth_dev = eth_dev;
2041                 hw->idx = i;
2042                 hw->nfp_idx = nfp_eth_table->ports[i].index;
2043                 hw->is_phyport = true;
2044
2045                 eth_dev->device = &pf_dev->pci_dev->device;
2046
2047                 /* ctrl/tx/rx BAR mappings and remaining init happens in
2048                  * nfp_net_init
2049                  */
2050                 ret = nfp_net_init(eth_dev);
2051
2052                 if (ret) {
2053                         ret = -ENODEV;
2054                         goto port_cleanup;
2055                 }
2056
2057                 rte_eth_dev_probing_finish(eth_dev);
2058
2059         } /* End loop, all ports on this PF */
2060         ret = 0;
2061         goto eth_table_cleanup;
2062
2063 port_cleanup:
2064         for (i = 0; i < pf_dev->total_phyports; i++) {
2065                 if (pf_dev->ports[i] && pf_dev->ports[i]->eth_dev) {
2066                         struct rte_eth_dev *tmp_dev;
2067                         tmp_dev = pf_dev->ports[i]->eth_dev;
2068                         rte_eth_dev_release_port(tmp_dev);
2069                         pf_dev->ports[i] = NULL;
2070                 }
2071         }
2072 eth_table_cleanup:
2073         free(nfp_eth_table);
2074 error:
2075         return ret;
2076 }
2077
2078 static int nfp_pf_init(struct rte_pci_device *pci_dev)
2079 {
2080         struct nfp_pf_dev *pf_dev = NULL;
2081         struct nfp_cpp *cpp;
2082         struct nfp_hwinfo *hwinfo;
2083         struct nfp_rtsym_table *sym_tbl;
2084         struct nfp_eth_table *nfp_eth_table = NULL;
2085         char name[RTE_ETH_NAME_MAX_LEN];
2086         int total_ports;
2087         int ret = -ENODEV;
2088         int err;
2089
2090         if (!pci_dev)
2091                 return ret;
2092
2093         /*
2094          * When device bound to UIO, the device could be used, by mistake,
2095          * by two DPDK apps, and the UIO driver does not avoid it. This
2096          * could lead to a serious problem when configuring the NFP CPP
2097          * interface. Here we avoid this telling to the CPP init code to
2098          * use a lock file if UIO is being used.
2099          */
2100         if (pci_dev->kdrv == RTE_PCI_KDRV_VFIO)
2101                 cpp = nfp_cpp_from_device_name(pci_dev, 0);
2102         else
2103                 cpp = nfp_cpp_from_device_name(pci_dev, 1);
2104
2105         if (!cpp) {
2106                 PMD_INIT_LOG(ERR, "A CPP handle can not be obtained");
2107                 ret = -EIO;
2108                 goto error;
2109         }
2110
2111         hwinfo = nfp_hwinfo_read(cpp);
2112         if (!hwinfo) {
2113                 PMD_INIT_LOG(ERR, "Error reading hwinfo table");
2114                 ret = -EIO;
2115                 goto error;
2116         }
2117
2118         nfp_eth_table = nfp_eth_read_ports(cpp);
2119         if (!nfp_eth_table) {
2120                 PMD_INIT_LOG(ERR, "Error reading NFP ethernet table");
2121                 ret = -EIO;
2122                 goto hwinfo_cleanup;
2123         }
2124
2125         if (nfp_fw_setup(pci_dev, cpp, nfp_eth_table, hwinfo)) {
2126                 PMD_INIT_LOG(ERR, "Error when uploading firmware");
2127                 ret = -EIO;
2128                 goto eth_table_cleanup;
2129         }
2130
2131         /* Now the symbol table should be there */
2132         sym_tbl = nfp_rtsym_table_read(cpp);
2133         if (!sym_tbl) {
2134                 PMD_INIT_LOG(ERR, "Something is wrong with the firmware"
2135                                 " symbol table");
2136                 ret = -EIO;
2137                 goto eth_table_cleanup;
2138         }
2139
2140         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
2141         if (total_ports != (int)nfp_eth_table->count) {
2142                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
2143                 ret = -EIO;
2144                 goto sym_tbl_cleanup;
2145         }
2146
2147         PMD_INIT_LOG(INFO, "Total physical ports: %d", total_ports);
2148
2149         if (total_ports <= 0 || total_ports > 8) {
2150                 PMD_INIT_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
2151                 ret = -ENODEV;
2152                 goto sym_tbl_cleanup;
2153         }
2154         /* Allocate memory for the PF "device" */
2155         snprintf(name, sizeof(name), "nfp_pf%d", 0);
2156         pf_dev = rte_zmalloc(name, sizeof(*pf_dev), 0);
2157         if (!pf_dev) {
2158                 ret = -ENOMEM;
2159                 goto sym_tbl_cleanup;
2160         }
2161
2162         /* Populate the newly created PF device */
2163         pf_dev->cpp = cpp;
2164         pf_dev->hwinfo = hwinfo;
2165         pf_dev->sym_tbl = sym_tbl;
2166         pf_dev->total_phyports = total_ports;
2167
2168         if (total_ports > 1)
2169                 pf_dev->multiport = true;
2170
2171         pf_dev->pci_dev = pci_dev;
2172
2173         /* Map the symbol table */
2174         pf_dev->ctrl_bar = nfp_rtsym_map(pf_dev->sym_tbl, "_pf0_net_bar0",
2175                                      pf_dev->total_phyports * 32768,
2176                                      &pf_dev->ctrl_area);
2177         if (!pf_dev->ctrl_bar) {
2178                 PMD_INIT_LOG(ERR, "nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2179                 ret = -EIO;
2180                 goto pf_cleanup;
2181         }
2182
2183         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", pf_dev->ctrl_bar);
2184
2185         /* configure access to tx/rx vNIC BARs */
2186         pf_dev->hw_queues = nfp_cpp_map_area(pf_dev->cpp, 0, 0,
2187                                               NFP_PCIE_QUEUE(0),
2188                                               NFP_QCP_QUEUE_AREA_SZ,
2189                                               &pf_dev->hwqueues_area);
2190         if (!pf_dev->hw_queues) {
2191                 PMD_INIT_LOG(ERR, "nfp_rtsym_map fails for net.qc");
2192                 ret = -EIO;
2193                 goto ctrl_area_cleanup;
2194         }
2195
2196         PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p", pf_dev->hw_queues);
2197
2198         /* Initialize and prep physical ports now
2199          * This will loop through all physical ports
2200          */
2201         ret = nfp_init_phyports(pf_dev);
2202         if (ret) {
2203                 PMD_INIT_LOG(ERR, "Could not create physical ports");
2204                 goto hwqueues_cleanup;
2205         }
2206
2207         /* register the CPP bridge service here for primary use */
2208         nfp_register_cpp_service(pf_dev->cpp);
2209
2210         return 0;
2211
2212 hwqueues_cleanup:
2213         nfp_cpp_area_free(pf_dev->hwqueues_area);
2214 ctrl_area_cleanup:
2215         nfp_cpp_area_free(pf_dev->ctrl_area);
2216 pf_cleanup:
2217         rte_free(pf_dev);
2218 sym_tbl_cleanup:
2219         free(sym_tbl);
2220 eth_table_cleanup:
2221         free(nfp_eth_table);
2222 hwinfo_cleanup:
2223         free(hwinfo);
2224 error:
2225         return ret;
2226 }
2227
2228 /*
2229  * When attaching to the NFP4000/6000 PF on a secondary process there
2230  * is no need to initialize the PF again. Only minimal work is required
2231  * here
2232  */
2233 static int nfp_pf_secondary_init(struct rte_pci_device *pci_dev)
2234 {
2235         struct nfp_cpp *cpp;
2236         struct nfp_rtsym_table *sym_tbl;
2237         int total_ports;
2238         int i;
2239         int err;
2240
2241         if (!pci_dev)
2242                 return -ENODEV;
2243
2244         /*
2245          * When device bound to UIO, the device could be used, by mistake,
2246          * by two DPDK apps, and the UIO driver does not avoid it. This
2247          * could lead to a serious problem when configuring the NFP CPP
2248          * interface. Here we avoid this telling to the CPP init code to
2249          * use a lock file if UIO is being used.
2250          */
2251         if (pci_dev->kdrv == RTE_PCI_KDRV_VFIO)
2252                 cpp = nfp_cpp_from_device_name(pci_dev, 0);
2253         else
2254                 cpp = nfp_cpp_from_device_name(pci_dev, 1);
2255
2256         if (!cpp) {
2257                 PMD_INIT_LOG(ERR, "A CPP handle can not be obtained");
2258                 return -EIO;
2259         }
2260
2261         /*
2262          * We don't have access to the PF created in the primary process
2263          * here so we have to read the number of ports from firmware
2264          */
2265         sym_tbl = nfp_rtsym_table_read(cpp);
2266         if (!sym_tbl) {
2267                 PMD_INIT_LOG(ERR, "Something is wrong with the firmware"
2268                                 " symbol table");
2269                 return -EIO;
2270         }
2271
2272         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
2273
2274         for (i = 0; i < total_ports; i++) {
2275                 struct rte_eth_dev *eth_dev;
2276                 char port_name[RTE_ETH_NAME_MAX_LEN];
2277
2278                 snprintf(port_name, sizeof(port_name), "%s_port%d",
2279                          pci_dev->device.name, i);
2280
2281                 PMD_DRV_LOG(DEBUG, "Secondary attaching to port %s",
2282                     port_name);
2283                 eth_dev = rte_eth_dev_attach_secondary(port_name);
2284                 if (!eth_dev) {
2285                         RTE_LOG(ERR, EAL,
2286                         "secondary process attach failed, "
2287                         "ethdev doesn't exist");
2288                         return -ENODEV;
2289                 }
2290                 eth_dev->process_private = cpp;
2291                 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2292                 eth_dev->rx_queue_count = nfp_net_rx_queue_count;
2293                 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2294                 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2295                 rte_eth_dev_probing_finish(eth_dev);
2296         }
2297
2298         /* Register the CPP bridge service for the secondary too */
2299         nfp_register_cpp_service(cpp);
2300
2301         return 0;
2302 }
2303
2304 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2305                             struct rte_pci_device *dev)
2306 {
2307         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
2308                 return nfp_pf_init(dev);
2309         else
2310                 return nfp_pf_secondary_init(dev);
2311 }
2312
2313 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
2314         {
2315                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2316                                PCI_DEVICE_ID_NFP4000_PF_NIC)
2317         },
2318         {
2319                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2320                                PCI_DEVICE_ID_NFP6000_PF_NIC)
2321         },
2322         {
2323                 .vendor_id = 0,
2324         },
2325 };
2326
2327 static int nfp_pci_uninit(struct rte_eth_dev *eth_dev)
2328 {
2329         struct rte_pci_device *pci_dev;
2330         uint16_t port_id;
2331
2332         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2333
2334         if (pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC ||
2335             pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC) {
2336                 /* Free up all physical ports under PF */
2337                 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
2338                         rte_eth_dev_close(port_id);
2339                 /*
2340                  * Ports can be closed and freed but hotplugging is not
2341                  * currently supported
2342                  */
2343                 return -ENOTSUP;
2344         }
2345
2346         /* VF cleanup, just free private port data */
2347         return nfp_net_close(eth_dev);
2348 }
2349
2350 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
2351 {
2352         return rte_eth_dev_pci_generic_remove(pci_dev, nfp_pci_uninit);
2353 }
2354
2355 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
2356         .id_table = pci_id_nfp_pf_net_map,
2357         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2358         .probe = nfp_pf_pci_probe,
2359         .remove = eth_nfp_pci_remove,
2360 };
2361
2362 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
2363 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
2364 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
2365 RTE_LOG_REGISTER_SUFFIX(nfp_logtype_init, init, NOTICE);
2366 RTE_LOG_REGISTER_SUFFIX(nfp_logtype_driver, driver, NOTICE);
2367 /*
2368  * Local variables:
2369  * c-file-style: "Linux"
2370  * indent-tabs-mode: t
2371  * End:
2372  */