2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev_driver.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
58 #include "nfpcore/nfp_cpp.h"
59 #include "nfpcore/nfp_nffw.h"
60 #include "nfpcore/nfp_hwinfo.h"
61 #include "nfpcore/nfp_mip.h"
62 #include "nfpcore/nfp_rtsym.h"
63 #include "nfpcore/nfp_nsp.h"
65 #include "nfp_net_pmd.h"
66 #include "nfp_net_logs.h"
67 #include "nfp_net_ctrl.h"
70 static void nfp_net_close(struct rte_eth_dev *dev);
71 static int nfp_net_configure(struct rte_eth_dev *dev);
72 static void nfp_net_dev_interrupt_handler(void *param);
73 static void nfp_net_dev_interrupt_delayed_handler(void *param);
74 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
75 static void nfp_net_infos_get(struct rte_eth_dev *dev,
76 struct rte_eth_dev_info *dev_info);
77 static int nfp_net_init(struct rte_eth_dev *eth_dev);
78 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
79 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
80 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
81 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
82 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
84 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
86 static void nfp_net_rx_queue_release(void *rxq);
87 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_rxconf *rx_conf,
90 struct rte_mempool *mp);
91 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
92 static void nfp_net_tx_queue_release(void *txq);
93 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
94 uint16_t nb_desc, unsigned int socket_id,
95 const struct rte_eth_txconf *tx_conf);
96 static int nfp_net_start(struct rte_eth_dev *dev);
97 static int nfp_net_stats_get(struct rte_eth_dev *dev,
98 struct rte_eth_stats *stats);
99 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
100 static void nfp_net_stop(struct rte_eth_dev *dev);
101 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
104 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
105 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
106 struct rte_eth_rss_conf *rss_conf);
107 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
108 struct rte_eth_rss_reta_entry64 *reta_conf,
110 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
111 struct rte_eth_rss_conf *rss_conf);
113 /* The offset of the queue controller queues in the PCIe Target */
114 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
116 /* Maximum value which can be added to a queue with one transaction */
117 #define NFP_QCP_MAX_ADD 0x7f
119 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
120 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
122 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
124 NFP_QCP_READ_PTR = 0,
129 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
130 * @q: Base address for queue structure
131 * @ptr: Add to the Read or Write pointer
132 * @val: Value to add to the queue pointer
134 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
137 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
141 if (ptr == NFP_QCP_READ_PTR)
142 off = NFP_QCP_QUEUE_ADD_RPTR;
144 off = NFP_QCP_QUEUE_ADD_WPTR;
146 while (val > NFP_QCP_MAX_ADD) {
147 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
148 val -= NFP_QCP_MAX_ADD;
151 nn_writel(rte_cpu_to_le_32(val), q + off);
155 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
156 * @q: Base address for queue structure
157 * @ptr: Read or Write pointer
159 static inline uint32_t
160 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
165 if (ptr == NFP_QCP_READ_PTR)
166 off = NFP_QCP_QUEUE_STS_LO;
168 off = NFP_QCP_QUEUE_STS_HI;
170 val = rte_cpu_to_le_32(nn_readl(q + off));
172 if (ptr == NFP_QCP_READ_PTR)
173 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
175 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
179 * Functions to read/write from/to Config BAR
180 * Performs any endian conversion necessary.
182 static inline uint8_t
183 nn_cfg_readb(struct nfp_net_hw *hw, int off)
185 return nn_readb(hw->ctrl_bar + off);
189 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
191 nn_writeb(val, hw->ctrl_bar + off);
194 static inline uint32_t
195 nn_cfg_readl(struct nfp_net_hw *hw, int off)
197 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
201 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
203 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
206 static inline uint64_t
207 nn_cfg_readq(struct nfp_net_hw *hw, int off)
209 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
213 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
215 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
219 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
223 if (rxq->rxbufs == NULL)
226 for (i = 0; i < rxq->rx_count; i++) {
227 if (rxq->rxbufs[i].mbuf) {
228 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
229 rxq->rxbufs[i].mbuf = NULL;
235 nfp_net_rx_queue_release(void *rx_queue)
237 struct nfp_net_rxq *rxq = rx_queue;
240 nfp_net_rx_queue_release_mbufs(rxq);
241 rte_free(rxq->rxbufs);
247 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
249 nfp_net_rx_queue_release_mbufs(rxq);
255 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
259 if (txq->txbufs == NULL)
262 for (i = 0; i < txq->tx_count; i++) {
263 if (txq->txbufs[i].mbuf) {
264 rte_pktmbuf_free(txq->txbufs[i].mbuf);
265 txq->txbufs[i].mbuf = NULL;
271 nfp_net_tx_queue_release(void *tx_queue)
273 struct nfp_net_txq *txq = tx_queue;
276 nfp_net_tx_queue_release_mbufs(txq);
277 rte_free(txq->txbufs);
283 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
285 nfp_net_tx_queue_release_mbufs(txq);
291 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
295 struct timespec wait;
297 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
300 if (hw->qcp_cfg == NULL)
301 rte_panic("Bad configuration queue pointer\n");
303 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
306 wait.tv_nsec = 1000000;
308 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
310 /* Poll update field, waiting for NFP to ack the config */
311 for (cnt = 0; ; cnt++) {
312 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
315 if (new & NFP_NET_CFG_UPDATE_ERR) {
316 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
319 if (cnt >= NFP_NET_POLL_TIMEOUT) {
320 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
321 " %dms", update, cnt);
322 rte_panic("Exiting\n");
324 nanosleep(&wait, 0); /* waiting for a 1ms */
326 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
331 * Reconfigure the NIC
332 * @nn: device to reconfigure
333 * @ctrl: The value for the ctrl field in the BAR config
334 * @update: The value for the update field in the BAR config
336 * Write the update word to the BAR and ping the reconfig queue. Then poll
337 * until the firmware has acknowledged the update by zeroing the update word.
340 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
344 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
347 rte_spinlock_lock(&hw->reconfig_lock);
349 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
350 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
354 err = __nfp_net_reconfig(hw, update);
356 rte_spinlock_unlock(&hw->reconfig_lock);
362 * Reconfig errors imply situations where they can be handled.
363 * Otherwise, rte_panic is called inside __nfp_net_reconfig
365 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
371 * Configure an Ethernet device. This function must be invoked first
372 * before any other function in the Ethernet API. This function can
373 * also be re-invoked when a device is in the stopped state.
376 nfp_net_configure(struct rte_eth_dev *dev)
378 struct rte_eth_conf *dev_conf;
379 struct rte_eth_rxmode *rxmode;
380 struct rte_eth_txmode *txmode;
381 uint32_t new_ctrl = 0;
383 struct nfp_net_hw *hw;
385 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
388 * A DPDK app sends info about how many queues to use and how
389 * those queues need to be configured. This is used by the
390 * DPDK core and it makes sure no more queues than those
391 * advertised by the driver are requested. This function is
392 * called after that internal process
395 PMD_INIT_LOG(DEBUG, "Configure");
397 dev_conf = &dev->data->dev_conf;
398 rxmode = &dev_conf->rxmode;
399 txmode = &dev_conf->txmode;
401 /* Checking TX mode */
402 if (txmode->mq_mode) {
403 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
407 /* Checking RX mode */
408 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
409 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
410 update = NFP_NET_CFG_UPDATE_RSS;
411 new_ctrl = NFP_NET_CFG_CTRL_RSS;
413 PMD_INIT_LOG(INFO, "RSS not supported");
418 if (rxmode->split_hdr_size) {
419 PMD_INIT_LOG(INFO, "rxmode does not support split header");
423 if (rxmode->hw_ip_checksum) {
424 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
425 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
427 PMD_INIT_LOG(INFO, "RXCSUM not supported");
432 if (rxmode->hw_vlan_filter) {
433 PMD_INIT_LOG(INFO, "VLAN filter not supported");
437 if (rxmode->hw_vlan_strip) {
438 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
439 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
441 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
446 if (rxmode->hw_vlan_extend) {
447 PMD_INIT_LOG(INFO, "VLAN extended not supported");
451 if (rxmode->jumbo_frame)
452 hw->mtu = rxmode->max_rx_pkt_len;
454 if (!rxmode->hw_strip_crc)
455 PMD_INIT_LOG(INFO, "HW does strip CRC and it is not configurable");
457 if (rxmode->enable_scatter) {
458 PMD_INIT_LOG(INFO, "Scatter not supported");
462 /* If next capabilities are supported, configure them by default */
465 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
466 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
469 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
470 new_ctrl |= NFP_NET_CFG_CTRL_L2BC;
473 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
474 new_ctrl |= NFP_NET_CFG_CTRL_L2MC;
476 /* TX checksum offload */
477 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
478 new_ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
481 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
482 new_ctrl |= NFP_NET_CFG_CTRL_LSO;
485 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
486 new_ctrl |= NFP_NET_CFG_CTRL_GATHER;
491 update |= NFP_NET_CFG_UPDATE_GEN;
493 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
494 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
503 nfp_net_enable_queues(struct rte_eth_dev *dev)
505 struct nfp_net_hw *hw;
506 uint64_t enabled_queues = 0;
509 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
511 /* Enabling the required TX queues in the device */
512 for (i = 0; i < dev->data->nb_tx_queues; i++)
513 enabled_queues |= (1 << i);
515 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
519 /* Enabling the required RX queues in the device */
520 for (i = 0; i < dev->data->nb_rx_queues; i++)
521 enabled_queues |= (1 << i);
523 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
527 nfp_net_disable_queues(struct rte_eth_dev *dev)
529 struct nfp_net_hw *hw;
530 uint32_t new_ctrl, update = 0;
532 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
534 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
535 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
537 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
538 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
539 NFP_NET_CFG_UPDATE_MSIX;
541 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
542 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
544 /* If an error when reconfig we avoid to change hw state */
545 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
552 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
556 for (i = 0; i < dev->data->nb_rx_queues; i++) {
557 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
564 nfp_net_params_setup(struct nfp_net_hw *hw)
566 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
567 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
571 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
573 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
576 #define ETH_ADDR_LEN 6
579 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
583 for (i = 0; i < ETH_ADDR_LEN; i++)
588 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
590 struct nfp_eth_table *nfp_eth_table;
592 nfp_eth_table = nfp_eth_read_ports(hw->cpp);
594 * hw points to port0 private data. We need hw now pointing to
598 nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
599 (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
606 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
610 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
611 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
613 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
614 memcpy(&hw->mac_addr[4], &tmp, 2);
618 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
620 uint32_t mac0 = *(uint32_t *)mac;
623 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
626 mac1 = *(uint16_t *)mac;
627 nn_writew(rte_cpu_to_be_16(mac1),
628 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
632 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
633 struct rte_intr_handle *intr_handle)
635 struct nfp_net_hw *hw;
638 if (!intr_handle->intr_vec) {
639 intr_handle->intr_vec =
640 rte_zmalloc("intr_vec",
641 dev->data->nb_rx_queues * sizeof(int), 0);
642 if (!intr_handle->intr_vec) {
643 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
644 " intr_vec", dev->data->nb_rx_queues);
649 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
651 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
652 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
653 /* UIO just supports one queue and no LSC*/
654 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
655 intr_handle->intr_vec[0] = 0;
657 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
658 for (i = 0; i < dev->data->nb_rx_queues; i++) {
660 * The first msix vector is reserved for non
663 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
664 intr_handle->intr_vec[i] = i + 1;
665 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
666 intr_handle->intr_vec[i]);
670 /* Avoiding TX interrupts */
671 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
676 nfp_net_start(struct rte_eth_dev *dev)
678 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
679 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
680 struct rte_eth_conf *dev_conf;
681 struct rte_eth_rxmode *rxmode;
682 uint32_t new_ctrl, update = 0;
683 struct nfp_net_hw *hw;
684 uint32_t intr_vector;
687 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
689 PMD_INIT_LOG(DEBUG, "Start");
691 /* Disabling queues just in case... */
692 nfp_net_disable_queues(dev);
694 /* Writing configuration parameters in the device */
695 nfp_net_params_setup(hw);
697 /* Enabling the required queues in the device */
698 nfp_net_enable_queues(dev);
700 /* check and configure queue intr-vector mapping */
701 if (dev->data->dev_conf.intr_conf.rxq != 0) {
702 if (hw->pf_multiport_enabled) {
703 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
704 "with NFP multiport PF");
707 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
709 * Better not to share LSC with RX interrupts.
710 * Unregistering LSC interrupt handler
712 rte_intr_callback_unregister(&pci_dev->intr_handle,
713 nfp_net_dev_interrupt_handler, (void *)dev);
715 if (dev->data->nb_rx_queues > 1) {
716 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
717 "supports 1 queue with UIO");
721 intr_vector = dev->data->nb_rx_queues;
722 if (rte_intr_efd_enable(intr_handle, intr_vector))
725 nfp_configure_rx_interrupt(dev, intr_handle);
726 update = NFP_NET_CFG_UPDATE_MSIX;
729 rte_intr_enable(intr_handle);
731 dev_conf = &dev->data->dev_conf;
732 rxmode = &dev_conf->rxmode;
734 /* Checking RX mode */
735 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
736 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
737 if (!nfp_net_rss_config_default(dev))
738 update |= NFP_NET_CFG_UPDATE_RSS;
740 PMD_INIT_LOG(INFO, "RSS not supported");
745 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
747 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
749 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
750 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
752 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
753 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
757 * Allocating rte mbuffs for configured rx queues.
758 * This requires queues being enabled before
760 if (nfp_net_rx_freelist_setup(dev) < 0) {
766 /* Configure the physical port up */
767 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
775 * An error returned by this function should mean the app
776 * exiting and then the system releasing all the memory
777 * allocated even memory coming from hugepages.
779 * The device could be enabled at this point with some queues
780 * ready for getting packets. This is true if the call to
781 * nfp_net_rx_freelist_setup() succeeds for some queues but
782 * fails for subsequent queues.
784 * This should make the app exiting but better if we tell the
787 nfp_net_disable_queues(dev);
792 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
794 nfp_net_stop(struct rte_eth_dev *dev)
797 struct nfp_net_hw *hw;
799 PMD_INIT_LOG(DEBUG, "Stop");
801 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
803 nfp_net_disable_queues(dev);
806 for (i = 0; i < dev->data->nb_tx_queues; i++) {
807 nfp_net_reset_tx_queue(
808 (struct nfp_net_txq *)dev->data->tx_queues[i]);
811 for (i = 0; i < dev->data->nb_rx_queues; i++) {
812 nfp_net_reset_rx_queue(
813 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
817 /* Configure the physical port down */
818 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
821 /* Reset and stop device. The device can not be restarted. */
823 nfp_net_close(struct rte_eth_dev *dev)
825 struct nfp_net_hw *hw;
826 struct rte_pci_device *pci_dev;
829 PMD_INIT_LOG(DEBUG, "Close");
831 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
832 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
835 * We assume that the DPDK application is stopping all the
836 * threads/queues before calling the device close function.
839 nfp_net_disable_queues(dev);
842 for (i = 0; i < dev->data->nb_tx_queues; i++) {
843 nfp_net_reset_tx_queue(
844 (struct nfp_net_txq *)dev->data->tx_queues[i]);
847 for (i = 0; i < dev->data->nb_rx_queues; i++) {
848 nfp_net_reset_rx_queue(
849 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
852 rte_intr_disable(&pci_dev->intr_handle);
853 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
855 /* unregister callback func from eal lib */
856 rte_intr_callback_unregister(&pci_dev->intr_handle,
857 nfp_net_dev_interrupt_handler,
861 * The ixgbe PMD driver disables the pcie master on the
862 * device. The i40e does not...
867 nfp_net_promisc_enable(struct rte_eth_dev *dev)
869 uint32_t new_ctrl, update = 0;
870 struct nfp_net_hw *hw;
872 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
874 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
876 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
877 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
881 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
882 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
886 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
887 update = NFP_NET_CFG_UPDATE_GEN;
890 * DPDK sets promiscuous mode on just after this call assuming
891 * it can not fail ...
893 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
900 nfp_net_promisc_disable(struct rte_eth_dev *dev)
902 uint32_t new_ctrl, update = 0;
903 struct nfp_net_hw *hw;
905 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
907 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
908 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
912 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
913 update = NFP_NET_CFG_UPDATE_GEN;
916 * DPDK sets promiscuous mode off just before this call
917 * assuming it can not fail ...
919 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
926 * return 0 means link status changed, -1 means not changed
928 * Wait to complete is needed as it can take up to 9 seconds to get the Link
932 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
934 struct nfp_net_hw *hw;
935 struct rte_eth_link link;
936 uint32_t nn_link_status;
939 static const uint32_t ls_to_ethtool[] = {
940 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
941 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
942 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
943 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
944 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
945 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
946 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
947 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
950 PMD_DRV_LOG(DEBUG, "Link update\n");
952 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
954 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
956 memset(&link, 0, sizeof(struct rte_eth_link));
958 if (nn_link_status & NFP_NET_CFG_STS_LINK)
959 link.link_status = ETH_LINK_UP;
961 link.link_duplex = ETH_LINK_FULL_DUPLEX;
963 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
964 NFP_NET_CFG_STS_LINK_RATE_MASK;
966 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
967 link.link_speed = ETH_SPEED_NUM_NONE;
969 link.link_speed = ls_to_ethtool[nn_link_status];
971 ret = rte_eth_linkstatus_set(dev, &link);
973 if (link.link_status)
974 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
976 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
982 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
985 struct nfp_net_hw *hw;
986 struct rte_eth_stats nfp_dev_stats;
988 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
990 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
992 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
994 /* reading per RX ring stats */
995 for (i = 0; i < dev->data->nb_rx_queues; i++) {
996 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
999 nfp_dev_stats.q_ipackets[i] =
1000 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1002 nfp_dev_stats.q_ipackets[i] -=
1003 hw->eth_stats_base.q_ipackets[i];
1005 nfp_dev_stats.q_ibytes[i] =
1006 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1008 nfp_dev_stats.q_ibytes[i] -=
1009 hw->eth_stats_base.q_ibytes[i];
1012 /* reading per TX ring stats */
1013 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1014 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1017 nfp_dev_stats.q_opackets[i] =
1018 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1020 nfp_dev_stats.q_opackets[i] -=
1021 hw->eth_stats_base.q_opackets[i];
1023 nfp_dev_stats.q_obytes[i] =
1024 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1026 nfp_dev_stats.q_obytes[i] -=
1027 hw->eth_stats_base.q_obytes[i];
1030 nfp_dev_stats.ipackets =
1031 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1033 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1035 nfp_dev_stats.ibytes =
1036 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1038 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1040 nfp_dev_stats.opackets =
1041 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1043 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1045 nfp_dev_stats.obytes =
1046 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1048 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1050 /* reading general device stats */
1051 nfp_dev_stats.ierrors =
1052 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1054 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1056 nfp_dev_stats.oerrors =
1057 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1059 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1061 /* RX ring mbuf allocation failures */
1062 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1064 nfp_dev_stats.imissed =
1065 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1067 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1070 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1077 nfp_net_stats_reset(struct rte_eth_dev *dev)
1080 struct nfp_net_hw *hw;
1082 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1085 * hw->eth_stats_base records the per counter starting point.
1086 * Lets update it now
1089 /* reading per RX ring stats */
1090 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1091 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1094 hw->eth_stats_base.q_ipackets[i] =
1095 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1097 hw->eth_stats_base.q_ibytes[i] =
1098 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1101 /* reading per TX ring stats */
1102 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1103 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1106 hw->eth_stats_base.q_opackets[i] =
1107 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1109 hw->eth_stats_base.q_obytes[i] =
1110 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1113 hw->eth_stats_base.ipackets =
1114 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1116 hw->eth_stats_base.ibytes =
1117 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1119 hw->eth_stats_base.opackets =
1120 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1122 hw->eth_stats_base.obytes =
1123 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1125 /* reading general device stats */
1126 hw->eth_stats_base.ierrors =
1127 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1129 hw->eth_stats_base.oerrors =
1130 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1132 /* RX ring mbuf allocation failures */
1133 dev->data->rx_mbuf_alloc_failed = 0;
1135 hw->eth_stats_base.imissed =
1136 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1140 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1142 struct nfp_net_hw *hw;
1144 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1146 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1147 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1148 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1149 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1150 dev_info->max_rx_pktlen = hw->max_mtu;
1151 /* Next should change when PF support is implemented */
1152 dev_info->max_mac_addrs = 1;
1154 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1155 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1157 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1158 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1159 DEV_RX_OFFLOAD_UDP_CKSUM |
1160 DEV_RX_OFFLOAD_TCP_CKSUM;
1162 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1163 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1165 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1166 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1167 DEV_TX_OFFLOAD_UDP_CKSUM |
1168 DEV_TX_OFFLOAD_TCP_CKSUM;
1170 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1172 .pthresh = DEFAULT_RX_PTHRESH,
1173 .hthresh = DEFAULT_RX_HTHRESH,
1174 .wthresh = DEFAULT_RX_WTHRESH,
1176 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1180 dev_info->default_txconf = (struct rte_eth_txconf) {
1182 .pthresh = DEFAULT_TX_PTHRESH,
1183 .hthresh = DEFAULT_TX_HTHRESH,
1184 .wthresh = DEFAULT_TX_WTHRESH,
1186 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1187 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1188 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1189 ETH_TXQ_FLAGS_NOOFFLOADS,
1192 dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1193 ETH_RSS_NONFRAG_IPV4_UDP |
1194 ETH_RSS_NONFRAG_IPV6_TCP |
1195 ETH_RSS_NONFRAG_IPV6_UDP;
1197 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1198 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1200 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1201 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1202 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1204 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1205 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1208 static const uint32_t *
1209 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1211 static const uint32_t ptypes[] = {
1212 /* refers to nfp_net_set_hash() */
1213 RTE_PTYPE_INNER_L3_IPV4,
1214 RTE_PTYPE_INNER_L3_IPV6,
1215 RTE_PTYPE_INNER_L3_IPV6_EXT,
1216 RTE_PTYPE_INNER_L4_MASK,
1220 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1226 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1228 struct nfp_net_rxq *rxq;
1229 struct nfp_net_rx_desc *rxds;
1233 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1240 * Other PMDs are just checking the DD bit in intervals of 4
1241 * descriptors and counting all four if the first has the DD
1242 * bit on. Of course, this is not accurate but can be good for
1243 * performance. But ideally that should be done in descriptors
1244 * chunks belonging to the same cache line
1247 while (count < rxq->rx_count) {
1248 rxds = &rxq->rxds[idx];
1249 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1256 if ((idx) == rxq->rx_count)
1264 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1266 struct rte_pci_device *pci_dev;
1267 struct nfp_net_hw *hw;
1270 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1273 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1276 /* Make sure all updates are written before un-masking */
1278 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1279 NFP_NET_CFG_ICR_UNMASKED);
1284 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1286 struct rte_pci_device *pci_dev;
1287 struct nfp_net_hw *hw;
1290 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1291 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1293 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1296 /* Make sure all updates are written before un-masking */
1298 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1303 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1305 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1306 struct rte_eth_link link;
1308 rte_eth_linkstatus_get(dev, &link);
1309 if (link.link_status)
1310 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1311 dev->data->port_id, link.link_speed,
1312 link.link_duplex == ETH_LINK_FULL_DUPLEX
1313 ? "full-duplex" : "half-duplex");
1315 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1316 dev->data->port_id);
1318 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1319 pci_dev->addr.domain, pci_dev->addr.bus,
1320 pci_dev->addr.devid, pci_dev->addr.function);
1323 /* Interrupt configuration and handling */
1326 * nfp_net_irq_unmask - Unmask an interrupt
1328 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1329 * clear the ICR for the entry.
1332 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1334 struct nfp_net_hw *hw;
1335 struct rte_pci_device *pci_dev;
1337 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1338 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1340 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1341 /* If MSI-X auto-masking is used, clear the entry */
1343 rte_intr_enable(&pci_dev->intr_handle);
1345 /* Make sure all updates are written before un-masking */
1347 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1348 NFP_NET_CFG_ICR_UNMASKED);
1353 nfp_net_dev_interrupt_handler(void *param)
1356 struct rte_eth_link link;
1357 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1359 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1361 rte_eth_linkstatus_get(dev, &link);
1363 nfp_net_link_update(dev, 0);
1366 if (!link.link_status) {
1367 /* handle it 1 sec later, wait it being stable */
1368 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1369 /* likely to down */
1371 /* handle it 4 sec later, wait it being stable */
1372 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1375 if (rte_eal_alarm_set(timeout * 1000,
1376 nfp_net_dev_interrupt_delayed_handler,
1378 RTE_LOG(ERR, PMD, "Error setting alarm");
1380 nfp_net_irq_unmask(dev);
1385 * Interrupt handler which shall be registered for alarm callback for delayed
1386 * handling specific interrupt to wait for the stable nic state. As the NIC
1387 * interrupt state is not stable for nfp after link is just down, it needs
1388 * to wait 4 seconds to get the stable status.
1390 * @param handle Pointer to interrupt handle.
1391 * @param param The address of parameter (struct rte_eth_dev *)
1396 nfp_net_dev_interrupt_delayed_handler(void *param)
1398 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1400 nfp_net_link_update(dev, 0);
1401 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1403 nfp_net_dev_link_status_print(dev);
1406 nfp_net_irq_unmask(dev);
1410 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1412 struct nfp_net_hw *hw;
1414 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1416 /* check that mtu is within the allowed range */
1417 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1420 /* mtu setting is forbidden if port is started */
1421 if (dev->data->dev_started) {
1422 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1423 dev->data->port_id);
1427 /* switch to jumbo mode if needed */
1428 if ((uint32_t)mtu > ETHER_MAX_LEN)
1429 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1431 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1433 /* update max frame size */
1434 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1436 /* writing to configuration space */
1437 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1445 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1446 uint16_t queue_idx, uint16_t nb_desc,
1447 unsigned int socket_id,
1448 const struct rte_eth_rxconf *rx_conf,
1449 struct rte_mempool *mp)
1451 const struct rte_memzone *tz;
1452 struct nfp_net_rxq *rxq;
1453 struct nfp_net_hw *hw;
1455 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1457 PMD_INIT_FUNC_TRACE();
1459 /* Validating number of descriptors */
1460 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1461 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1462 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1463 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1468 * Free memory prior to re-allocation if needed. This is the case after
1469 * calling nfp_net_stop
1471 if (dev->data->rx_queues[queue_idx]) {
1472 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1473 dev->data->rx_queues[queue_idx] = NULL;
1476 /* Allocating rx queue data structure */
1477 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1478 RTE_CACHE_LINE_SIZE, socket_id);
1482 /* Hw queues mapping based on firmware confifguration */
1483 rxq->qidx = queue_idx;
1484 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1485 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1486 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1487 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1490 * Tracking mbuf size for detecting a potential mbuf overflow due to
1494 rxq->mbuf_size = rxq->mem_pool->elt_size;
1495 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1496 hw->flbufsz = rxq->mbuf_size;
1498 rxq->rx_count = nb_desc;
1499 rxq->port_id = dev->data->port_id;
1500 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1501 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1503 rxq->drop_en = rx_conf->rx_drop_en;
1506 * Allocate RX ring hardware descriptors. A memzone large enough to
1507 * handle the maximum ring size is allocated in order to allow for
1508 * resizing in later calls to the queue setup function.
1510 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1511 sizeof(struct nfp_net_rx_desc) *
1512 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1516 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1517 nfp_net_rx_queue_release(rxq);
1521 /* Saving physical and virtual addresses for the RX ring */
1522 rxq->dma = (uint64_t)tz->iova;
1523 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1525 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1526 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1527 sizeof(*rxq->rxbufs) * nb_desc,
1528 RTE_CACHE_LINE_SIZE, socket_id);
1529 if (rxq->rxbufs == NULL) {
1530 nfp_net_rx_queue_release(rxq);
1534 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1535 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1537 nfp_net_reset_rx_queue(rxq);
1539 dev->data->rx_queues[queue_idx] = rxq;
1543 * Telling the HW about the physical address of the RX ring and number
1544 * of descriptors in log2 format
1546 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1547 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1553 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1555 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1559 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1562 for (i = 0; i < rxq->rx_count; i++) {
1563 struct nfp_net_rx_desc *rxd;
1564 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1567 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1568 (unsigned)rxq->qidx);
1572 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1574 rxd = &rxq->rxds[i];
1576 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1577 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1579 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1582 /* Make sure all writes are flushed before telling the hardware */
1585 /* Not advertising the whole ring as the firmware gets confused if so */
1586 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1589 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1595 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1596 uint16_t nb_desc, unsigned int socket_id,
1597 const struct rte_eth_txconf *tx_conf)
1599 const struct rte_memzone *tz;
1600 struct nfp_net_txq *txq;
1601 uint16_t tx_free_thresh;
1602 struct nfp_net_hw *hw;
1604 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606 PMD_INIT_FUNC_TRACE();
1608 /* Validating number of descriptors */
1609 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1610 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1611 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1612 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1616 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1617 tx_conf->tx_free_thresh :
1618 DEFAULT_TX_FREE_THRESH);
1620 if (tx_free_thresh > (nb_desc)) {
1622 "tx_free_thresh must be less than the number of TX "
1623 "descriptors. (tx_free_thresh=%u port=%d "
1624 "queue=%d)\n", (unsigned int)tx_free_thresh,
1625 dev->data->port_id, (int)queue_idx);
1630 * Free memory prior to re-allocation if needed. This is the case after
1631 * calling nfp_net_stop
1633 if (dev->data->tx_queues[queue_idx]) {
1634 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1636 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1637 dev->data->tx_queues[queue_idx] = NULL;
1640 /* Allocating tx queue data structure */
1641 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1642 RTE_CACHE_LINE_SIZE, socket_id);
1644 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1649 * Allocate TX ring hardware descriptors. A memzone large enough to
1650 * handle the maximum ring size is allocated in order to allow for
1651 * resizing in later calls to the queue setup function.
1653 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1654 sizeof(struct nfp_net_tx_desc) *
1655 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1658 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1659 nfp_net_tx_queue_release(txq);
1663 txq->tx_count = nb_desc;
1664 txq->tx_free_thresh = tx_free_thresh;
1665 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1666 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1667 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1669 /* queue mapping based on firmware configuration */
1670 txq->qidx = queue_idx;
1671 txq->tx_qcidx = queue_idx * hw->stride_tx;
1672 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1674 txq->port_id = dev->data->port_id;
1675 txq->txq_flags = tx_conf->txq_flags;
1677 /* Saving physical and virtual addresses for the TX ring */
1678 txq->dma = (uint64_t)tz->iova;
1679 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1681 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1682 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1683 sizeof(*txq->txbufs) * nb_desc,
1684 RTE_CACHE_LINE_SIZE, socket_id);
1685 if (txq->txbufs == NULL) {
1686 nfp_net_tx_queue_release(txq);
1689 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1690 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1692 nfp_net_reset_tx_queue(txq);
1694 dev->data->tx_queues[queue_idx] = txq;
1698 * Telling the HW about the physical address of the TX ring and number
1699 * of descriptors in log2 format
1701 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1702 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1707 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1709 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1710 struct rte_mbuf *mb)
1713 struct nfp_net_hw *hw = txq->hw;
1715 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1718 ol_flags = mb->ol_flags;
1720 if (!(ol_flags & PKT_TX_TCP_SEG))
1723 txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1724 txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1725 txd->flags = PCIE_DESC_TX_LSO;
1734 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1736 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1737 struct rte_mbuf *mb)
1740 struct nfp_net_hw *hw = txq->hw;
1742 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1745 ol_flags = mb->ol_flags;
1747 /* IPv6 does not need checksum */
1748 if (ol_flags & PKT_TX_IP_CKSUM)
1749 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1751 switch (ol_flags & PKT_TX_L4_MASK) {
1752 case PKT_TX_UDP_CKSUM:
1753 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1755 case PKT_TX_TCP_CKSUM:
1756 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1760 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1761 txd->flags |= PCIE_DESC_TX_CSUM;
1764 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1766 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1767 struct rte_mbuf *mb)
1769 struct nfp_net_hw *hw = rxq->hw;
1771 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1774 /* If IPv4 and IP checksum error, fail */
1775 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1776 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1777 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1779 /* If neither UDP nor TCP return */
1780 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1781 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1784 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1785 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1786 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1788 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1789 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1790 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1793 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1794 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1796 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1799 * nfp_net_set_hash - Set mbuf hash data
1801 * The RSS hash and hash-type are pre-pended to the packet data.
1802 * Extract and decode it and set the mbuf fields.
1805 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1806 struct rte_mbuf *mbuf)
1808 struct nfp_net_hw *hw = rxq->hw;
1809 uint8_t *meta_offset;
1812 uint32_t hash_type = 0;
1814 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1817 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1818 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1821 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1822 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1824 } else if (NFP_DESC_META_LEN(rxd)) {
1827 * <---- 32 bit ----->
1832 * ====================
1835 * Field type word contains up to 8 4bit field types
1836 * A 4bit field type refers to a data field word
1837 * A data field word can have several 4bit field types
1839 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1840 meta_offset -= NFP_DESC_META_LEN(rxd);
1841 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1843 /* NFP PMD just supports metadata for hashing */
1844 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1845 case NFP_NET_META_HASH:
1846 /* next field type is about the hash type */
1847 meta_info >>= NFP_NET_META_FIELD_SIZE;
1848 /* hash value is in the data field */
1849 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1850 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1853 /* Unsupported metadata can be a performance issue */
1860 mbuf->hash.rss = hash;
1861 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1863 switch (hash_type) {
1864 case NFP_NET_RSS_IPV4:
1865 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1867 case NFP_NET_RSS_IPV6:
1868 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1870 case NFP_NET_RSS_IPV6_EX:
1871 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1874 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1879 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1881 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1884 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1889 * There are some decissions to take:
1890 * 1) How to check DD RX descriptors bit
1891 * 2) How and when to allocate new mbufs
1893 * Current implementation checks just one single DD bit each loop. As each
1894 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1895 * a single cache line instead. Tests with this change have not shown any
1896 * performance improvement but it requires further investigation. For example,
1897 * depending on which descriptor is next, the number of descriptors could be
1898 * less than 8 for just checking those in the same cache line. This implies
1899 * extra work which could be counterproductive by itself. Indeed, last firmware
1900 * changes are just doing this: writing several descriptors with the DD bit
1901 * for saving PCIe bandwidth and DMA operations from the NFP.
1903 * Mbuf allocation is done when a new packet is received. Then the descriptor
1904 * is automatically linked with the new mbuf and the old one is given to the
1905 * user. The main drawback with this design is mbuf allocation is heavier than
1906 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1907 * cache point of view it does not seem allocating the mbuf early on as we are
1908 * doing now have any benefit at all. Again, tests with this change have not
1909 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1910 * so looking at the implications of this type of allocation should be studied
1915 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1917 struct nfp_net_rxq *rxq;
1918 struct nfp_net_rx_desc *rxds;
1919 struct nfp_net_rx_buff *rxb;
1920 struct nfp_net_hw *hw;
1921 struct rte_mbuf *mb;
1922 struct rte_mbuf *new_mb;
1928 if (unlikely(rxq == NULL)) {
1930 * DPDK just checks the queue is lower than max queues
1931 * enabled. But the queue needs to be configured
1933 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1941 while (avail < nb_pkts) {
1942 rxb = &rxq->rxbufs[rxq->rd_p];
1943 if (unlikely(rxb == NULL)) {
1944 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1948 rxds = &rxq->rxds[rxq->rd_p];
1949 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1953 * Memory barrier to ensure that we won't do other
1954 * reads before the DD bit.
1959 * We got a packet. Let's alloc a new mbuff for refilling the
1960 * free descriptor ring as soon as possible
1962 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1963 if (unlikely(new_mb == NULL)) {
1964 RTE_LOG_DP(DEBUG, PMD,
1965 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
1966 rxq->port_id, (unsigned int)rxq->qidx);
1967 nfp_net_mbuf_alloc_failed(rxq);
1974 * Grab the mbuff and refill the descriptor with the
1975 * previously allocated mbuff
1980 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1981 rxds->rxd.data_len, rxq->mbuf_size);
1983 /* Size of this segment */
1984 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1985 /* Size of the whole packet. We just support 1 segment */
1986 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1988 if (unlikely((mb->data_len + hw->rx_offset) >
1991 * This should not happen and the user has the
1992 * responsibility of avoiding it. But we have
1993 * to give some info about the error
1995 RTE_LOG_DP(ERR, PMD,
1996 "mbuf overflow likely due to the RX offset.\n"
1997 "\t\tYour mbuf size should have extra space for"
1998 " RX offset=%u bytes.\n"
1999 "\t\tCurrently you just have %u bytes available"
2000 " but the received packet is %u bytes long",
2002 rxq->mbuf_size - hw->rx_offset,
2007 /* Filling the received mbuff with packet info */
2009 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2011 mb->data_off = RTE_PKTMBUF_HEADROOM +
2012 NFP_DESC_META_LEN(rxds);
2014 /* No scatter mode supported */
2018 mb->port = rxq->port_id;
2020 /* Checking the RSS flag */
2021 nfp_net_set_hash(rxq, rxds, mb);
2023 /* Checking the checksum flag */
2024 nfp_net_rx_cksum(rxq, rxds, mb);
2026 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2027 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2028 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2029 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2032 /* Adding the mbuff to the mbuff array passed by the app */
2033 rx_pkts[avail++] = mb;
2035 /* Now resetting and updating the descriptor */
2038 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2040 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2041 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2044 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2051 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
2052 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2054 nb_hold += rxq->nb_rx_hold;
2057 * FL descriptors needs to be written before incrementing the
2058 * FL queue WR pointer
2061 if (nb_hold > rxq->rx_free_thresh) {
2062 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2063 rxq->port_id, (unsigned int)rxq->qidx,
2064 (unsigned)nb_hold, (unsigned)avail);
2065 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2068 rxq->nb_rx_hold = nb_hold;
2074 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2076 * @txq: TX queue to work with
2077 * Returns number of descriptors freed
2080 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2085 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2086 " status\n", txq->qidx);
2088 /* Work out how many packets have been sent */
2089 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2091 if (qcp_rd_p == txq->rd_p) {
2092 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2093 "packets (%u, %u)\n", txq->qidx,
2094 qcp_rd_p, txq->rd_p);
2098 if (qcp_rd_p > txq->rd_p)
2099 todo = qcp_rd_p - txq->rd_p;
2101 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2103 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2104 qcp_rd_p, txq->rd_p, txq->rd_p);
2110 if (unlikely(txq->rd_p >= txq->tx_count))
2111 txq->rd_p -= txq->tx_count;
2116 /* Leaving always free descriptors for avoiding wrapping confusion */
2118 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2120 if (txq->wr_p >= txq->rd_p)
2121 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2123 return txq->rd_p - txq->wr_p - 8;
2127 * nfp_net_txq_full - Check if the TX queue free descriptors
2128 * is below tx_free_threshold
2130 * @txq: TX queue to check
2132 * This function uses the host copy* of read/write pointers
2135 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2137 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2141 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2143 struct nfp_net_txq *txq;
2144 struct nfp_net_hw *hw;
2145 struct nfp_net_tx_desc *txds, txd;
2146 struct rte_mbuf *pkt;
2148 int pkt_size, dma_size;
2149 uint16_t free_descs, issued_descs;
2150 struct rte_mbuf **lmbuf;
2155 txds = &txq->txds[txq->wr_p];
2157 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2158 txq->qidx, txq->wr_p, nb_pkts);
2160 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2161 nfp_net_tx_free_bufs(txq);
2163 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2164 if (unlikely(free_descs == 0))
2171 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2172 txq->qidx, nb_pkts);
2173 /* Sending packets */
2174 while ((i < nb_pkts) && free_descs) {
2175 /* Grabbing the mbuf linked to the current descriptor */
2176 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2177 /* Warming the cache for releasing the mbuf later on */
2178 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2180 pkt = *(tx_pkts + i);
2182 if (unlikely((pkt->nb_segs > 1) &&
2183 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2184 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2185 rte_panic("Multisegment packet unsupported\n");
2188 /* Checking if we have enough descriptors */
2189 if (unlikely(pkt->nb_segs > free_descs))
2193 * Checksum and VLAN flags just in the first descriptor for a
2194 * multisegment packet, but TSO info needs to be in all of them.
2196 txd.data_len = pkt->pkt_len;
2197 nfp_net_tx_tso(txq, &txd, pkt);
2198 nfp_net_tx_cksum(txq, &txd, pkt);
2200 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2201 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2202 txd.flags |= PCIE_DESC_TX_VLAN;
2203 txd.vlan = pkt->vlan_tci;
2207 * mbuf data_len is the data in one segment and pkt_len data
2208 * in the whole packet. When the packet is just one segment,
2209 * then data_len = pkt_len
2211 pkt_size = pkt->pkt_len;
2214 /* Copying TSO, VLAN and cksum info */
2217 /* Releasing mbuf used by this descriptor previously*/
2219 rte_pktmbuf_free_seg(*lmbuf);
2222 * Linking mbuf with descriptor for being released
2223 * next time descriptor is used
2227 dma_size = pkt->data_len;
2228 dma_addr = rte_mbuf_data_iova(pkt);
2229 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2230 "%" PRIx64 "\n", dma_addr);
2232 /* Filling descriptors fields */
2233 txds->dma_len = dma_size;
2234 txds->data_len = txd.data_len;
2235 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2236 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2237 ASSERT(free_descs > 0);
2241 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2244 pkt_size -= dma_size;
2247 txds->offset_eop |= PCIE_DESC_TX_EOP;
2249 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2252 /* Referencing next free TX descriptor */
2253 txds = &txq->txds[txq->wr_p];
2254 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2261 /* Increment write pointers. Force memory write before we let HW know */
2263 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2269 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2271 uint32_t new_ctrl, update;
2272 struct nfp_net_hw *hw;
2275 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2278 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2279 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2280 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2281 " ETH_VLAN_EXTEND_OFFLOAD");
2283 /* Enable vlan strip if it is not configured yet */
2284 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2285 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2286 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2288 /* Disable vlan strip just if it is configured */
2289 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2290 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2291 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2296 update = NFP_NET_CFG_UPDATE_GEN;
2298 ret = nfp_net_reconfig(hw, new_ctrl, update);
2300 hw->ctrl = new_ctrl;
2306 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2307 struct rte_eth_rss_reta_entry64 *reta_conf,
2310 uint32_t reta, mask;
2313 struct nfp_net_hw *hw =
2314 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2317 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2318 "(%d) doesn't match the number hardware can supported "
2319 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2324 * Update Redirection Table. There are 128 8bit-entries which can be
2325 * manage as 32 32bit-entries
2327 for (i = 0; i < reta_size; i += 4) {
2328 /* Handling 4 RSS entries per loop */
2329 idx = i / RTE_RETA_GROUP_SIZE;
2330 shift = i % RTE_RETA_GROUP_SIZE;
2331 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2337 /* If all 4 entries were set, don't need read RETA register */
2339 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2341 for (j = 0; j < 4; j++) {
2342 if (!(mask & (0x1 << j)))
2345 /* Clearing the entry bits */
2346 reta &= ~(0xFF << (8 * j));
2347 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2349 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2355 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2357 nfp_net_reta_update(struct rte_eth_dev *dev,
2358 struct rte_eth_rss_reta_entry64 *reta_conf,
2361 struct nfp_net_hw *hw =
2362 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2369 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2373 update = NFP_NET_CFG_UPDATE_RSS;
2375 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2381 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2383 nfp_net_reta_query(struct rte_eth_dev *dev,
2384 struct rte_eth_rss_reta_entry64 *reta_conf,
2390 struct nfp_net_hw *hw;
2392 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2394 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2397 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2398 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2399 "(%d) doesn't match the number hardware can supported "
2400 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2405 * Reading Redirection Table. There are 128 8bit-entries which can be
2406 * manage as 32 32bit-entries
2408 for (i = 0; i < reta_size; i += 4) {
2409 /* Handling 4 RSS entries per loop */
2410 idx = i / RTE_RETA_GROUP_SIZE;
2411 shift = i % RTE_RETA_GROUP_SIZE;
2412 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2417 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2419 for (j = 0; j < 4; j++) {
2420 if (!(mask & (0x1 << j)))
2422 reta_conf->reta[shift + j] =
2423 (uint8_t)((reta >> (8 * j)) & 0xF);
2430 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2431 struct rte_eth_rss_conf *rss_conf)
2433 struct nfp_net_hw *hw;
2435 uint32_t cfg_rss_ctrl = 0;
2439 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441 /* Writing the key byte a byte */
2442 for (i = 0; i < rss_conf->rss_key_len; i++) {
2443 memcpy(&key, &rss_conf->rss_key[i], 1);
2444 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2447 rss_hf = rss_conf->rss_hf;
2449 if (rss_hf & ETH_RSS_IPV4)
2450 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2451 NFP_NET_CFG_RSS_IPV4_TCP |
2452 NFP_NET_CFG_RSS_IPV4_UDP;
2454 if (rss_hf & ETH_RSS_IPV6)
2455 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2456 NFP_NET_CFG_RSS_IPV6_TCP |
2457 NFP_NET_CFG_RSS_IPV6_UDP;
2459 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2460 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2462 /* configuring where to apply the RSS hash */
2463 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2465 /* Writing the key size */
2466 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2472 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2473 struct rte_eth_rss_conf *rss_conf)
2477 struct nfp_net_hw *hw;
2479 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481 rss_hf = rss_conf->rss_hf;
2483 /* Checking if RSS is enabled */
2484 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2485 if (rss_hf != 0) { /* Enable RSS? */
2486 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2489 return 0; /* Nothing to do */
2492 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2493 RTE_LOG(ERR, PMD, "hash key too long\n");
2497 nfp_net_rss_hash_write(dev, rss_conf);
2499 update = NFP_NET_CFG_UPDATE_RSS;
2501 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2508 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2509 struct rte_eth_rss_conf *rss_conf)
2512 uint32_t cfg_rss_ctrl;
2515 struct nfp_net_hw *hw;
2517 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2519 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2522 rss_hf = rss_conf->rss_hf;
2523 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2525 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2526 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2528 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2529 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2531 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2532 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2534 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2535 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2537 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2538 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2540 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2541 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2543 /* Reading the key size */
2544 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2546 /* Reading the key byte a byte */
2547 for (i = 0; i < rss_conf->rss_key_len; i++) {
2548 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2549 memcpy(&rss_conf->rss_key[i], &key, 1);
2556 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2558 struct rte_eth_conf *dev_conf;
2559 struct rte_eth_rss_conf rss_conf;
2560 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2561 uint16_t rx_queues = dev->data->nb_rx_queues;
2565 RTE_LOG(INFO, PMD, "setting default RSS conf for %u queues\n",
2568 nfp_reta_conf[0].mask = ~0x0;
2569 nfp_reta_conf[1].mask = ~0x0;
2572 for (i = 0; i < 0x40; i += 8) {
2573 for (j = i; j < (i + 8); j++) {
2574 nfp_reta_conf[0].reta[j] = queue;
2575 nfp_reta_conf[1].reta[j] = queue++;
2579 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2583 dev_conf = &dev->data->dev_conf;
2585 RTE_LOG(INFO, PMD, "wrong rss conf");
2588 rss_conf = dev_conf->rx_adv_conf.rss_conf;
2590 ret = nfp_net_rss_hash_write(dev, &rss_conf);
2596 /* Initialise and register driver with DPDK Application */
2597 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2598 .dev_configure = nfp_net_configure,
2599 .dev_start = nfp_net_start,
2600 .dev_stop = nfp_net_stop,
2601 .dev_close = nfp_net_close,
2602 .promiscuous_enable = nfp_net_promisc_enable,
2603 .promiscuous_disable = nfp_net_promisc_disable,
2604 .link_update = nfp_net_link_update,
2605 .stats_get = nfp_net_stats_get,
2606 .stats_reset = nfp_net_stats_reset,
2607 .dev_infos_get = nfp_net_infos_get,
2608 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2609 .mtu_set = nfp_net_dev_mtu_set,
2610 .vlan_offload_set = nfp_net_vlan_offload_set,
2611 .reta_update = nfp_net_reta_update,
2612 .reta_query = nfp_net_reta_query,
2613 .rss_hash_update = nfp_net_rss_hash_update,
2614 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2615 .rx_queue_setup = nfp_net_rx_queue_setup,
2616 .rx_queue_release = nfp_net_rx_queue_release,
2617 .rx_queue_count = nfp_net_rx_queue_count,
2618 .tx_queue_setup = nfp_net_tx_queue_setup,
2619 .tx_queue_release = nfp_net_tx_queue_release,
2620 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2621 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2625 * All eth_dev created got its private data, but before nfp_net_init, that
2626 * private data is referencing private data for all the PF ports. This is due
2627 * to how the vNIC bars are mapped based on first port, so all ports need info
2628 * about port 0 private data. Inside nfp_net_init the private data pointer is
2629 * changed to the right address for each port once the bars have been mapped.
2631 * This functions helps to find out which port and therefore which offset
2632 * inside the private data array to use.
2635 get_pf_port_number(char *name)
2637 char *pf_str = name;
2640 while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2645 * This should not happen at all and it would mean major
2646 * implementation fault.
2648 rte_panic("nfp_net: problem with pf device name\n");
2650 /* Expecting _portX with X within [0,7] */
2653 return (int)strtol(pf_str, NULL, 10);
2657 nfp_net_init(struct rte_eth_dev *eth_dev)
2659 struct rte_pci_device *pci_dev;
2660 struct nfp_net_hw *hw, *hwport0;
2662 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2668 PMD_INIT_FUNC_TRACE();
2670 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2672 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2673 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2674 port = get_pf_port_number(eth_dev->data->name);
2675 if (port < 0 || port > 7) {
2676 RTE_LOG(ERR, PMD, "Port value is wrong\n");
2680 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2682 /* This points to port 0 private data */
2683 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2685 /* This points to the specific port private data */
2686 hw = &hwport0[port];
2688 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2692 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2693 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2694 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2696 /* For secondary processes, the primary has done all the work */
2697 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2700 rte_eth_copy_pci_info(eth_dev, pci_dev);
2702 hw->device_id = pci_dev->id.device_id;
2703 hw->vendor_id = pci_dev->id.vendor_id;
2704 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2705 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2707 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2708 pci_dev->id.vendor_id, pci_dev->id.device_id,
2709 pci_dev->addr.domain, pci_dev->addr.bus,
2710 pci_dev->addr.devid, pci_dev->addr.function);
2712 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2713 if (hw->ctrl_bar == NULL) {
2715 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2719 if (hw->is_pf && port == 0) {
2720 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2721 hw->total_ports * 32768,
2723 if (!hw->ctrl_bar) {
2724 printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar\n");
2728 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2732 if (!hwport0->ctrl_bar)
2735 /* address based on port0 offset */
2736 hw->ctrl_bar = hwport0->ctrl_bar +
2737 (port * NFP_PF_CSR_SLICE_SIZE);
2740 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2742 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2743 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2745 /* Work out where in the BAR the queues start. */
2746 switch (pci_dev->id.device_id) {
2747 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2748 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2749 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2750 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2751 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2752 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2753 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2756 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2758 goto dev_err_ctrl_map;
2761 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2762 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2764 if (hw->is_pf && port == 0) {
2765 /* configure access to tx/rx vNIC BARs */
2766 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2768 NFP_QCP_QUEUE_AREA_SZ,
2769 &hw->hwqueues_area);
2771 if (!hwport0->hw_queues) {
2772 printf("nfp_rtsym_map fails for net.qc\n");
2774 goto dev_err_ctrl_map;
2777 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p\n",
2778 hwport0->hw_queues);
2782 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2783 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2784 eth_dev->data->dev_private = hw;
2786 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2788 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2792 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2793 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2795 nfp_net_cfg_queue_setup(hw);
2797 /* Get some of the read-only fields from the config BAR */
2798 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2799 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2800 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2801 hw->mtu = ETHER_MTU;
2803 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2804 hw->rx_offset = NFP_NET_RX_OFFSET;
2806 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2808 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2809 hw->ver, hw->max_mtu);
2810 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2811 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2812 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2813 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2814 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2815 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2816 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2817 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2818 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2819 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2820 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2821 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2825 hw->stride_rx = stride;
2826 hw->stride_tx = stride;
2828 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2829 hw->max_rx_queues, hw->max_tx_queues);
2831 /* Initializing spinlock for reconfigs */
2832 rte_spinlock_init(&hw->reconfig_lock);
2834 /* Allocating memory for mac addr */
2835 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2836 if (eth_dev->data->mac_addrs == NULL) {
2837 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2839 goto dev_err_queues_map;
2843 nfp_net_pf_read_mac(hwport0, port);
2844 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2846 nfp_net_vf_read_mac(hw);
2849 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2850 PMD_INIT_LOG(INFO, "Using random mac address for port %d\n",
2852 /* Using random mac addresses for VFs */
2853 eth_random_addr(&hw->mac_addr[0]);
2854 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2857 /* Copying mac address to DPDK eth_dev struct */
2858 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2859 ð_dev->data->mac_addrs[0]);
2861 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2862 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2863 eth_dev->data->port_id, pci_dev->id.vendor_id,
2864 pci_dev->id.device_id,
2865 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2866 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2868 /* Registering LSC interrupt handler */
2869 rte_intr_callback_register(&pci_dev->intr_handle,
2870 nfp_net_dev_interrupt_handler,
2873 /* Telling the firmware about the LSC interrupt entry */
2874 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2876 /* Recording current stats counters values */
2877 nfp_net_stats_reset(eth_dev);
2882 nfp_cpp_area_free(hw->hwqueues_area);
2884 nfp_cpp_area_free(hw->ctrl_area);
2890 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2891 struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
2892 int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
2894 struct rte_eth_dev *eth_dev;
2895 struct nfp_net_hw *hw;
2899 port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2904 sprintf(port_name, "%s_port%d", dev->device.name, port);
2906 sprintf(port_name, "%s", dev->device.name);
2908 eth_dev = rte_eth_dev_allocate(port_name);
2913 *priv = rte_zmalloc(port_name,
2914 sizeof(struct nfp_net_adapter) * ports,
2915 RTE_CACHE_LINE_SIZE);
2917 rte_eth_dev_release_port(eth_dev);
2922 eth_dev->data->dev_private = *priv;
2925 * dev_private pointing to port0 dev_private because we need
2926 * to configure vNIC bars based on port0 at nfp_net_init.
2927 * Then dev_private is adjusted per port.
2929 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2931 hw->hwinfo = hwinfo;
2932 hw->sym_tbl = sym_tbl;
2933 hw->pf_port_idx = phys_port;
2936 hw->pf_multiport_enabled = 1;
2938 hw->total_ports = ports;
2940 eth_dev->device = &dev->device;
2941 rte_eth_copy_pci_info(eth_dev, dev);
2943 ret = nfp_net_init(eth_dev);
2946 rte_eth_dev_release_port(eth_dev);
2948 rte_free(port_name);
2953 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
2956 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
2958 struct nfp_cpp *cpp = nsp->cpp;
2963 struct stat file_stat;
2966 /* Looking for firmware file in order of priority */
2968 /* First try to find a firmware image specific for this device */
2969 sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
2970 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
2971 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
2972 cpp->interface & 0xff);
2974 sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial);
2976 RTE_LOG(DEBUG, PMD, "Trying with fw file: %s\n", fw_name);
2977 fw_f = open(fw_name, O_RDONLY);
2981 /* Then try the PCI name */
2982 sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name);
2984 RTE_LOG(DEBUG, PMD, "Trying with fw file: %s\n", fw_name);
2985 fw_f = open(fw_name, O_RDONLY);
2989 /* Finally try the card type and media */
2990 sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card);
2991 RTE_LOG(DEBUG, PMD, "Trying with fw file: %s\n", fw_name);
2992 fw_f = open(fw_name, O_RDONLY);
2994 RTE_LOG(INFO, PMD, "Firmware file %s not found.", fw_name);
2999 if (fstat(fw_f, &file_stat) < 0) {
3000 RTE_LOG(INFO, PMD, "Firmware file %s size is unknown", fw_name);
3005 fsize = file_stat.st_size;
3006 RTE_LOG(INFO, PMD, "Firmware file found at %s with size: %" PRIu64 "\n",
3007 fw_name, (uint64_t)fsize);
3009 fw_buf = malloc((size_t)fsize);
3011 RTE_LOG(INFO, PMD, "malloc failed for fw buffer");
3015 memset(fw_buf, 0, fsize);
3017 bytes = read(fw_f, fw_buf, fsize);
3018 if (bytes != fsize) {
3019 RTE_LOG(INFO, PMD, "Reading fw to buffer failed.\n"
3020 "Just %" PRIu64 " of %" PRIu64 " bytes read",
3021 (uint64_t)bytes, (uint64_t)fsize);
3027 RTE_LOG(INFO, PMD, "Uploading the firmware ...");
3028 nfp_nsp_load_fw(nsp, fw_buf, bytes);
3029 RTE_LOG(INFO, PMD, "Done");
3038 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3039 struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3041 struct nfp_nsp *nsp;
3042 const char *nfp_fw_model;
3043 char card_desc[100];
3046 nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3049 RTE_LOG(INFO, PMD, "firmware model found: %s\n", nfp_fw_model);
3051 RTE_LOG(ERR, PMD, "firmware model NOT found\n");
3055 if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3056 RTE_LOG(ERR, PMD, "NFP ethernet table reports wrong ports: %u\n",
3057 nfp_eth_table->count);
3061 RTE_LOG(INFO, PMD, "NFP ethernet port table reports %u ports\n",
3062 nfp_eth_table->count);
3064 RTE_LOG(INFO, PMD, "Port speed: %u\n", nfp_eth_table->ports[0].speed);
3066 sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model,
3067 nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000);
3069 nsp = nfp_nsp_open(cpp);
3071 RTE_LOG(ERR, PMD, "NFP error when obtaining NSP handle\n");
3075 nfp_nsp_device_soft_reset(nsp);
3076 err = nfp_fw_upload(dev, nsp, card_desc);
3082 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3083 struct rte_pci_device *dev)
3085 struct nfp_cpp *cpp;
3086 struct nfp_hwinfo *hwinfo;
3087 struct nfp_rtsym_table *sym_tbl;
3088 struct nfp_eth_table *nfp_eth_table = NULL;
3098 cpp = nfp_cpp_from_device_name(dev->device.name);
3100 RTE_LOG(ERR, PMD, "A CPP handle can not be obtained");
3105 hwinfo = nfp_hwinfo_read(cpp);
3107 RTE_LOG(ERR, PMD, "Error reading hwinfo table");
3111 nfp_eth_table = nfp_eth_read_ports(cpp);
3112 if (!nfp_eth_table) {
3113 RTE_LOG(ERR, PMD, "Error reading NFP ethernet table\n");
3117 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3118 RTE_LOG(INFO, PMD, "Error when uploading firmware\n");
3123 /* Now the symbol table should be there */
3124 sym_tbl = nfp_rtsym_table_read(cpp);
3126 RTE_LOG(ERR, PMD, "Something is wrong with the firmware"
3132 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3133 if (total_ports != (int)nfp_eth_table->count) {
3134 RTE_LOG(ERR, PMD, "Inconsistent number of ports\n");
3138 PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
3140 if (total_ports <= 0 || total_ports > 8) {
3141 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
3146 for (i = 0; i < total_ports; i++) {
3147 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3148 nfp_eth_table->ports[i].index,
3155 free(nfp_eth_table);
3159 int nfp_logtype_init;
3160 int nfp_logtype_driver;
3162 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3164 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3165 PCI_DEVICE_ID_NFP4000_PF_NIC)
3168 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3169 PCI_DEVICE_ID_NFP6000_PF_NIC)
3176 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3178 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3179 PCI_DEVICE_ID_NFP6000_VF_NIC)
3186 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3187 struct rte_pci_device *pci_dev)
3189 return rte_eth_dev_pci_generic_probe(pci_dev,
3190 sizeof(struct nfp_net_adapter), nfp_net_init);
3193 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3195 struct rte_eth_dev *eth_dev;
3196 struct nfp_net_hw *hw, *hwport0;
3199 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3200 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3201 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3202 port = get_pf_port_number(eth_dev->data->name);
3204 * hotplug is not possible with multiport PF although freeing
3205 * data structures can be done for first port.
3209 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3210 hw = &hwport0[port];
3211 nfp_cpp_area_free(hw->ctrl_area);
3212 nfp_cpp_area_free(hw->hwqueues_area);
3215 nfp_cpp_free(hw->cpp);
3217 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3219 /* hotplug is not possible with multiport PF */
3220 if (hw->pf_multiport_enabled)
3222 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3225 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3226 .id_table = pci_id_nfp_pf_net_map,
3227 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3228 .probe = nfp_pf_pci_probe,
3229 .remove = eth_nfp_pci_remove,
3232 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3233 .id_table = pci_id_nfp_vf_net_map,
3234 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3235 .probe = eth_nfp_pci_probe,
3236 .remove = eth_nfp_pci_remove,
3239 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3240 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3241 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3242 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3243 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3244 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3246 RTE_INIT(nfp_init_log);
3250 nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3251 if (nfp_logtype_init >= 0)
3252 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3253 nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3254 if (nfp_logtype_driver >= 0)
3255 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3259 * c-file-style: "Linux"
3260 * indent-tabs-mode: t