drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014, 2015 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfp_nfpu.h"
  59 #include "nfp_net_pmd.h"
  60 #include "nfp_net_logs.h"
  61 #include "nfp_net_ctrl.h"
  62
  63 /* Prototypes */
  64 static void nfp_net_close(struct rte_eth_dev *dev);
  65 static int nfp_net_configure(struct rte_eth_dev *dev);
  66 static void nfp_net_dev_interrupt_handler(void *param);
  67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  70                               struct rte_eth_dev_info *dev_info);
  71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  77                                        uint16_t queue_idx);
  78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  79                                   uint16_t nb_pkts);
  80 static void nfp_net_rx_queue_release(void *rxq);
  81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  82                                   uint16_t nb_desc, unsigned int socket_id,
  83                                   const struct rte_eth_rxconf *rx_conf,
  84                                   struct rte_mempool *mp);
  85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  86 static void nfp_net_tx_queue_release(void *txq);
  87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_txconf *tx_conf);
  90 static int nfp_net_start(struct rte_eth_dev *dev);
  91 static void nfp_net_stats_get(struct rte_eth_dev *dev,
  92                               struct rte_eth_stats *stats);
  93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
  94 static void nfp_net_stop(struct rte_eth_dev *dev);
  95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  96                                   uint16_t nb_pkts);
  97
  98 /*
  99  * The offset of the queue controller queues in the PCIe Target. These
 100  * happen to be at the same offset on the NFP6000 and the NFP3200 so
 101  * we use a single macro here.
 102  */
 103 #define NFP_PCIE_QUEUE(_q)      (0x800 * ((_q) & 0xff))
 104
 105 /* Maximum value which can be added to a queue with one transaction */
 106 #define NFP_QCP_MAX_ADD 0x7f
 107
 108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 109         (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
 110
 111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 112 enum nfp_qcp_ptr {
 113         NFP_QCP_READ_PTR = 0,
 114         NFP_QCP_WRITE_PTR
 115 };
 116
 117 /*
 118  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 119  * @q: Base address for queue structure
 120  * @ptr: Add to the Read or Write pointer
 121  * @val: Value to add to the queue pointer
 122  *
 123  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 124  */
 125 static inline void
 126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 127 {
 128         uint32_t off;
 129
 130         if (ptr == NFP_QCP_READ_PTR)
 131                 off = NFP_QCP_QUEUE_ADD_RPTR;
 132         else
 133                 off = NFP_QCP_QUEUE_ADD_WPTR;
 134
 135         while (val > NFP_QCP_MAX_ADD) {
 136                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 137                 val -= NFP_QCP_MAX_ADD;
 138         }
 139
 140         nn_writel(rte_cpu_to_le_32(val), q + off);
 141 }
 142
 143 /*
 144  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 145  * @q:  Base address for queue structure
 146  * @ptr: Read or Write pointer
 147  */
 148 static inline uint32_t
 149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 150 {
 151         uint32_t off;
 152         uint32_t val;
 153
 154         if (ptr == NFP_QCP_READ_PTR)
 155                 off = NFP_QCP_QUEUE_STS_LO;
 156         else
 157                 off = NFP_QCP_QUEUE_STS_HI;
 158
 159         val = rte_cpu_to_le_32(nn_readl(q + off));
 160
 161         if (ptr == NFP_QCP_READ_PTR)
 162                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 163         else
 164                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 165 }
 166
 167 /*
 168  * Functions to read/write from/to Config BAR
 169  * Performs any endian conversion necessary.
 170  */
 171 static inline uint8_t
 172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 173 {
 174         return nn_readb(hw->ctrl_bar + off);
 175 }
 176
 177 static inline void
 178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 179 {
 180         nn_writeb(val, hw->ctrl_bar + off);
 181 }
 182
 183 static inline uint32_t
 184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 185 {
 186         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 187 }
 188
 189 static inline void
 190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 191 {
 192         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 193 }
 194
 195 static inline uint64_t
 196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 197 {
 198         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 199 }
 200
 201 static inline void
 202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 203 {
 204         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 205 }
 206
 207 /*
 208  * Atomically reads link status information from global structure rte_eth_dev.
 209  *
 210  * @param dev
 211  *   - Pointer to the structure rte_eth_dev to read from.
 212  *   - Pointer to the buffer to be saved with the link status.
 213  *
 214  * @return
 215  *   - On success, zero.
 216  *   - On failure, negative value.
 217  */
 218 static inline int
 219 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 220                                     struct rte_eth_link *link)
 221 {
 222         struct rte_eth_link *dst = link;
 223         struct rte_eth_link *src = &dev->data->dev_link;
 224
 225         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 226                                 *(uint64_t *)src) == 0)
 227                 return -1;
 228
 229         return 0;
 230 }
 231
 232 /*
 233  * Atomically writes the link status information into global
 234  * structure rte_eth_dev.
 235  *
 236  * @param dev
 237  *   - Pointer to the structure rte_eth_dev to read from.
 238  *   - Pointer to the buffer to be saved with the link status.
 239  *
 240  * @return
 241  *   - On success, zero.
 242  *   - On failure, negative value.
 243  */
 244 static inline int
 245 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 246                                      struct rte_eth_link *link)
 247 {
 248         struct rte_eth_link *dst = &dev->data->dev_link;
 249         struct rte_eth_link *src = link;
 250
 251         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 252                                 *(uint64_t *)src) == 0)
 253                 return -1;
 254
 255         return 0;
 256 }
 257
 258 static void
 259 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 260 {
 261         unsigned i;
 262
 263         if (rxq->rxbufs == NULL)
 264                 return;
 265
 266         for (i = 0; i < rxq->rx_count; i++) {
 267                 if (rxq->rxbufs[i].mbuf) {
 268                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 269                         rxq->rxbufs[i].mbuf = NULL;
 270                 }
 271         }
 272 }
 273
 274 static void
 275 nfp_net_rx_queue_release(void *rx_queue)
 276 {
 277         struct nfp_net_rxq *rxq = rx_queue;
 278
 279         if (rxq) {
 280                 nfp_net_rx_queue_release_mbufs(rxq);
 281                 rte_free(rxq->rxbufs);
 282                 rte_free(rxq);
 283         }
 284 }
 285
 286 static void
 287 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 288 {
 289         nfp_net_rx_queue_release_mbufs(rxq);
 290         rxq->rd_p = 0;
 291         rxq->nb_rx_hold = 0;
 292 }
 293
 294 static void
 295 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 296 {
 297         unsigned i;
 298
 299         if (txq->txbufs == NULL)
 300                 return;
 301
 302         for (i = 0; i < txq->tx_count; i++) {
 303                 if (txq->txbufs[i].mbuf) {
 304                         rte_pktmbuf_free(txq->txbufs[i].mbuf);
 305                         txq->txbufs[i].mbuf = NULL;
 306                 }
 307         }
 308 }
 309
 310 static void
 311 nfp_net_tx_queue_release(void *tx_queue)
 312 {
 313         struct nfp_net_txq *txq = tx_queue;
 314
 315         if (txq) {
 316                 nfp_net_tx_queue_release_mbufs(txq);
 317                 rte_free(txq->txbufs);
 318                 rte_free(txq);
 319         }
 320 }
 321
 322 static void
 323 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 324 {
 325         nfp_net_tx_queue_release_mbufs(txq);
 326         txq->wr_p = 0;
 327         txq->rd_p = 0;
 328 }
 329
 330 static int
 331 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 332 {
 333         int cnt;
 334         uint32_t new;
 335         struct timespec wait;
 336
 337         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
 338                     hw->qcp_cfg);
 339
 340         if (hw->qcp_cfg == NULL)
 341                 rte_panic("Bad configuration queue pointer\n");
 342
 343         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 344
 345         wait.tv_sec = 0;
 346         wait.tv_nsec = 1000000;
 347
 348         PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
 349
 350         /* Poll update field, waiting for NFP to ack the config */
 351         for (cnt = 0; ; cnt++) {
 352                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 353                 if (new == 0)
 354                         break;
 355                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 356                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 357                         return -1;
 358                 }
 359                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 360                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 361                                           " %dms", update, cnt);
 362                         rte_panic("Exiting\n");
 363                 }
 364                 nanosleep(&wait, 0); /* waiting for a 1ms */
 365         }
 366         PMD_DRV_LOG(DEBUG, "Ack DONE\n");
 367         return 0;
 368 }
 369
 370 /*
 371  * Reconfigure the NIC
 372  * @nn:    device to reconfigure
 373  * @ctrl:    The value for the ctrl field in the BAR config
 374  * @update:  The value for the update field in the BAR config
 375  *
 376  * Write the update word to the BAR and ping the reconfig queue. Then poll
 377  * until the firmware has acknowledged the update by zeroing the update word.
 378  */
 379 static int
 380 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 381 {
 382         uint32_t err;
 383
 384         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
 385                     ctrl, update);
 386
 387         rte_spinlock_lock(&hw->reconfig_lock);
 388
 389         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 390         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 391
 392         rte_wmb();
 393
 394         err = __nfp_net_reconfig(hw, update);
 395
 396         rte_spinlock_unlock(&hw->reconfig_lock);
 397
 398         if (!err)
 399                 return 0;
 400
 401         /*
 402          * Reconfig errors imply situations where they can be handled.
 403          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 404          */
 405         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 406                      ctrl, update);
 407         return -EIO;
 408 }
 409
 410 /*
 411  * Configure an Ethernet device. This function must be invoked first
 412  * before any other function in the Ethernet API. This function can
 413  * also be re-invoked when a device is in the stopped state.
 414  */
 415 static int
 416 nfp_net_configure(struct rte_eth_dev *dev)
 417 {
 418         struct rte_eth_conf *dev_conf;
 419         struct rte_eth_rxmode *rxmode;
 420         struct rte_eth_txmode *txmode;
 421         uint32_t new_ctrl = 0;
 422         uint32_t update = 0;
 423         struct nfp_net_hw *hw;
 424
 425         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 426
 427         /*
 428          * A DPDK app sends info about how many queues to use and how
 429          * those queues need to be configured. This is used by the
 430          * DPDK core and it makes sure no more queues than those
 431          * advertised by the driver are requested. This function is
 432          * called after that internal process
 433          */
 434
 435         PMD_INIT_LOG(DEBUG, "Configure");
 436
 437         dev_conf = &dev->data->dev_conf;
 438         rxmode = &dev_conf->rxmode;
 439         txmode = &dev_conf->txmode;
 440
 441         /* Checking TX mode */
 442         if (txmode->mq_mode) {
 443                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 444                 return -EINVAL;
 445         }
 446
 447         /* Checking RX mode */
 448         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 449                 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
 450                         update = NFP_NET_CFG_UPDATE_RSS;
 451                         new_ctrl = NFP_NET_CFG_CTRL_RSS;
 452                 } else {
 453                         PMD_INIT_LOG(INFO, "RSS not supported");
 454                         return -EINVAL;
 455                 }
 456         }
 457
 458         if (rxmode->split_hdr_size) {
 459                 PMD_INIT_LOG(INFO, "rxmode does not support split header");
 460                 return -EINVAL;
 461         }
 462
 463         if (rxmode->hw_ip_checksum) {
 464                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
 465                         new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 466                 } else {
 467                         PMD_INIT_LOG(INFO, "RXCSUM not supported");
 468                         return -EINVAL;
 469                 }
 470         }
 471
 472         if (rxmode->hw_vlan_filter) {
 473                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
 474                 return -EINVAL;
 475         }
 476
 477         if (rxmode->hw_vlan_strip) {
 478                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
 479                         new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 480                 } else {
 481                         PMD_INIT_LOG(INFO, "hw vlan strip not supported");
 482                         return -EINVAL;
 483                 }
 484         }
 485
 486         if (rxmode->hw_vlan_extend) {
 487                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
 488                 return -EINVAL;
 489         }
 490
 491         /* Supporting VLAN insertion by default */
 492         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
 493                 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 494
 495         if (rxmode->jumbo_frame)
 496                 /* this is handled in rte_eth_dev_configure */
 497
 498         if (rxmode->hw_strip_crc) {
 499                 PMD_INIT_LOG(INFO, "strip CRC not supported");
 500                 return -EINVAL;
 501         }
 502
 503         if (rxmode->enable_scatter) {
 504                 PMD_INIT_LOG(INFO, "Scatter not supported");
 505                 return -EINVAL;
 506         }
 507
 508         if (!new_ctrl)
 509                 return 0;
 510
 511         update |= NFP_NET_CFG_UPDATE_GEN;
 512
 513         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 514         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 515                 return -EIO;
 516
 517         hw->ctrl = new_ctrl;
 518
 519         return 0;
 520 }
 521
 522 static void
 523 nfp_net_enable_queues(struct rte_eth_dev *dev)
 524 {
 525         struct nfp_net_hw *hw;
 526         uint64_t enabled_queues = 0;
 527         int i;
 528
 529         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 530
 531         /* Enabling the required TX queues in the device */
 532         for (i = 0; i < dev->data->nb_tx_queues; i++)
 533                 enabled_queues |= (1 << i);
 534
 535         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 536
 537         enabled_queues = 0;
 538
 539         /* Enabling the required RX queues in the device */
 540         for (i = 0; i < dev->data->nb_rx_queues; i++)
 541                 enabled_queues |= (1 << i);
 542
 543         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 544 }
 545
 546 static void
 547 nfp_net_disable_queues(struct rte_eth_dev *dev)
 548 {
 549         struct nfp_net_hw *hw;
 550         uint32_t new_ctrl, update = 0;
 551
 552         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 553
 554         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 555         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 556
 557         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 558         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 559                  NFP_NET_CFG_UPDATE_MSIX;
 560
 561         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 562                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 563
 564         /* If an error when reconfig we avoid to change hw state */
 565         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 566                 return;
 567
 568         hw->ctrl = new_ctrl;
 569 }
 570
 571 static int
 572 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 573 {
 574         int i;
 575
 576         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 577                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 578                         return -1;
 579         }
 580         return 0;
 581 }
 582
 583 static void
 584 nfp_net_params_setup(struct nfp_net_hw *hw)
 585 {
 586         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 587         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 588 }
 589
 590 static void
 591 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 592 {
 593         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 594 }
 595
 596 static void nfp_net_read_mac(struct nfp_net_hw *hw)
 597 {
 598         uint32_t tmp;
 599
 600         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 601         memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
 602
 603         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 604         memcpy(&hw->mac_addr[4], &tmp, 2);
 605 }
 606
 607 static void
 608 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 609 {
 610         uint32_t mac0 = *(uint32_t *)mac;
 611         uint16_t mac1;
 612
 613         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 614
 615         mac += 4;
 616         mac1 = *(uint16_t *)mac;
 617         nn_writew(rte_cpu_to_be_16(mac1),
 618                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 619 }
 620
 621 static int
 622 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 623                            struct rte_intr_handle *intr_handle)
 624 {
 625         struct nfp_net_hw *hw;
 626         int i;
 627
 628         if (!intr_handle->intr_vec) {
 629                 intr_handle->intr_vec =
 630                         rte_zmalloc("intr_vec",
 631                                     dev->data->nb_rx_queues * sizeof(int), 0);
 632                 if (!intr_handle->intr_vec) {
 633                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 634                                      " intr_vec", dev->data->nb_rx_queues);
 635                         return -ENOMEM;
 636                 }
 637         }
 638
 639         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 640
 641         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 642                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 643                 /* UIO just supports one queue and no LSC*/
 644                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 645                 intr_handle->intr_vec[0] = 0;
 646         } else {
 647                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 648                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 649                         /*
 650                          * The first msix vector is reserved for non
 651                          * efd interrupts
 652                         */
 653                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 654                         intr_handle->intr_vec[i] = i + 1;
 655                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
 656                                             intr_handle->intr_vec[i]);
 657                 }
 658         }
 659
 660         /* Avoiding TX interrupts */
 661         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 662         return 0;
 663 }
 664
 665 static int
 666 nfp_net_start(struct rte_eth_dev *dev)
 667 {
 668         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 669         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 670         uint32_t new_ctrl, update = 0;
 671         struct nfp_net_hw *hw;
 672         uint32_t intr_vector;
 673         int ret;
 674
 675         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 676
 677         PMD_INIT_LOG(DEBUG, "Start");
 678
 679         /* Disabling queues just in case... */
 680         nfp_net_disable_queues(dev);
 681
 682         /* Writing configuration parameters in the device */
 683         nfp_net_params_setup(hw);
 684
 685         /* Enabling the required queues in the device */
 686         nfp_net_enable_queues(dev);
 687
 688         /* check and configure queue intr-vector mapping */
 689         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 690                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 691                         /*
 692                          * Better not to share LSC with RX interrupts.
 693                          * Unregistering LSC interrupt handler
 694                          */
 695                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 696                                 nfp_net_dev_interrupt_handler, (void *)dev);
 697
 698                         if (dev->data->nb_rx_queues > 1) {
 699                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 700                                              "supports 1 queue with UIO");
 701                                 return -EIO;
 702                         }
 703                 }
 704                 intr_vector = dev->data->nb_rx_queues;
 705                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 706                         return -1;
 707
 708                 nfp_configure_rx_interrupt(dev, intr_handle);
 709                 update = NFP_NET_CFG_UPDATE_MSIX;
 710         }
 711
 712         rte_intr_enable(intr_handle);
 713
 714         /* Enable device */
 715         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
 716
 717         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 718
 719         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 720                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 721
 722         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 723         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 724                 return -EIO;
 725
 726         /*
 727          * Allocating rte mbuffs for configured rx queues.
 728          * This requires queues being enabled before
 729          */
 730         if (nfp_net_rx_freelist_setup(dev) < 0) {
 731                 ret = -ENOMEM;
 732                 goto error;
 733         }
 734
 735         hw->ctrl = new_ctrl;
 736
 737         return 0;
 738
 739 error:
 740         /*
 741          * An error returned by this function should mean the app
 742          * exiting and then the system releasing all the memory
 743          * allocated even memory coming from hugepages.
 744          *
 745          * The device could be enabled at this point with some queues
 746          * ready for getting packets. This is true if the call to
 747          * nfp_net_rx_freelist_setup() succeeds for some queues but
 748          * fails for subsequent queues.
 749          *
 750          * This should make the app exiting but better if we tell the
 751          * device first.
 752          */
 753         nfp_net_disable_queues(dev);
 754
 755         return ret;
 756 }
 757
 758 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 759 static void
 760 nfp_net_stop(struct rte_eth_dev *dev)
 761 {
 762         int i;
 763
 764         PMD_INIT_LOG(DEBUG, "Stop");
 765
 766         nfp_net_disable_queues(dev);
 767
 768         /* Clear queues */
 769         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 770                 nfp_net_reset_tx_queue(
 771                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 772         }
 773
 774         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 775                 nfp_net_reset_rx_queue(
 776                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 777         }
 778 }
 779
 780 /* Reset and stop device. The device can not be restarted. */
 781 static void
 782 nfp_net_close(struct rte_eth_dev *dev)
 783 {
 784         struct nfp_net_hw *hw;
 785         struct rte_pci_device *pci_dev;
 786
 787         PMD_INIT_LOG(DEBUG, "Close");
 788
 789         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 790         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 791
 792         /*
 793          * We assume that the DPDK application is stopping all the
 794          * threads/queues before calling the device close function.
 795          */
 796
 797         nfp_net_stop(dev);
 798
 799         rte_intr_disable(&pci_dev->intr_handle);
 800         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 801
 802         /* unregister callback func from eal lib */
 803         rte_intr_callback_unregister(&pci_dev->intr_handle,
 804                                      nfp_net_dev_interrupt_handler,
 805                                      (void *)dev);
 806
 807         /*
 808          * The ixgbe PMD driver disables the pcie master on the
 809          * device. The i40e does not...
 810          */
 811 }
 812
 813 static void
 814 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 815 {
 816         uint32_t new_ctrl, update = 0;
 817         struct nfp_net_hw *hw;
 818
 819         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
 820
 821         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 822
 823         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 824                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 825                 return;
 826         }
 827
 828         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 829                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
 830                 return;
 831         }
 832
 833         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 834         update = NFP_NET_CFG_UPDATE_GEN;
 835
 836         /*
 837          * DPDK sets promiscuous mode on just after this call assuming
 838          * it can not fail ...
 839          */
 840         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 841                 return;
 842
 843         hw->ctrl = new_ctrl;
 844 }
 845
 846 static void
 847 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 848 {
 849         uint32_t new_ctrl, update = 0;
 850         struct nfp_net_hw *hw;
 851
 852         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 853
 854         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 855                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
 856                 return;
 857         }
 858
 859         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 860         update = NFP_NET_CFG_UPDATE_GEN;
 861
 862         /*
 863          * DPDK sets promiscuous mode off just before this call
 864          * assuming it can not fail ...
 865          */
 866         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 867                 return;
 868
 869         hw->ctrl = new_ctrl;
 870 }
 871
 872 /*
 873  * return 0 means link status changed, -1 means not changed
 874  *
 875  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 876  * status.
 877  */
 878 static int
 879 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 880 {
 881         struct nfp_net_hw *hw;
 882         struct rte_eth_link link, old;
 883         uint32_t nn_link_status;
 884
 885         static const uint32_t ls_to_ethtool[] = {
 886                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 887                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 888                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 889                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 890                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 891                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 892                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 893                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 894         };
 895
 896         PMD_DRV_LOG(DEBUG, "Link update\n");
 897
 898         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 899
 900         memset(&old, 0, sizeof(old));
 901         nfp_net_dev_atomic_read_link_status(dev, &old);
 902
 903         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 904
 905         memset(&link, 0, sizeof(struct rte_eth_link));
 906
 907         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 908                 link.link_status = ETH_LINK_UP;
 909
 910         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 911
 912         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 913                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 914
 915         if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
 916             ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
 917             (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
 918                 /* We really do not know the speed wil old firmware */
 919                 link.link_speed = ETH_SPEED_NUM_NONE;
 920         else {
 921                 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 922                         link.link_speed = ETH_SPEED_NUM_NONE;
 923                 else
 924                         link.link_speed = ls_to_ethtool[nn_link_status];
 925         }
 926
 927         if (old.link_status != link.link_status) {
 928                 nfp_net_dev_atomic_write_link_status(dev, &link);
 929                 if (link.link_status)
 930                         PMD_DRV_LOG(INFO, "NIC Link is Up\n");
 931                 else
 932                         PMD_DRV_LOG(INFO, "NIC Link is Down\n");
 933                 return 0;
 934         }
 935
 936         return -1;
 937 }
 938
 939 static void
 940 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 941 {
 942         int i;
 943         struct nfp_net_hw *hw;
 944         struct rte_eth_stats nfp_dev_stats;
 945
 946         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 947
 948         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
 949
 950         /* reading per RX ring stats */
 951         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 952                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 953                         break;
 954
 955                 nfp_dev_stats.q_ipackets[i] =
 956                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
 957
 958                 nfp_dev_stats.q_ipackets[i] -=
 959                         hw->eth_stats_base.q_ipackets[i];
 960
 961                 nfp_dev_stats.q_ibytes[i] =
 962                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
 963
 964                 nfp_dev_stats.q_ibytes[i] -=
 965                         hw->eth_stats_base.q_ibytes[i];
 966         }
 967
 968         /* reading per TX ring stats */
 969         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 970                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 971                         break;
 972
 973                 nfp_dev_stats.q_opackets[i] =
 974                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
 975
 976                 nfp_dev_stats.q_opackets[i] -=
 977                         hw->eth_stats_base.q_opackets[i];
 978
 979                 nfp_dev_stats.q_obytes[i] =
 980                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
 981
 982                 nfp_dev_stats.q_obytes[i] -=
 983                         hw->eth_stats_base.q_obytes[i];
 984         }
 985
 986         nfp_dev_stats.ipackets =
 987                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
 988
 989         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
 990
 991         nfp_dev_stats.ibytes =
 992                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
 993
 994         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
 995
 996         nfp_dev_stats.opackets =
 997                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
 998
 999         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1000
1001         nfp_dev_stats.obytes =
1002                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1003
1004         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1005
1006         /* reading general device stats */
1007         nfp_dev_stats.ierrors =
1008                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1009
1010         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1011
1012         nfp_dev_stats.oerrors =
1013                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1014
1015         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1016
1017         /* RX ring mbuf allocation failures */
1018         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1019
1020         nfp_dev_stats.imissed =
1021                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1022
1023         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1024
1025         if (stats)
1026                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1027 }
1028
1029 static void
1030 nfp_net_stats_reset(struct rte_eth_dev *dev)
1031 {
1032         int i;
1033         struct nfp_net_hw *hw;
1034
1035         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036
1037         /*
1038          * hw->eth_stats_base records the per counter starting point.
1039          * Lets update it now
1040          */
1041
1042         /* reading per RX ring stats */
1043         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1044                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1045                         break;
1046
1047                 hw->eth_stats_base.q_ipackets[i] =
1048                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1049
1050                 hw->eth_stats_base.q_ibytes[i] =
1051                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1052         }
1053
1054         /* reading per TX ring stats */
1055         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1056                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1057                         break;
1058
1059                 hw->eth_stats_base.q_opackets[i] =
1060                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1061
1062                 hw->eth_stats_base.q_obytes[i] =
1063                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1064         }
1065
1066         hw->eth_stats_base.ipackets =
1067                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1068
1069         hw->eth_stats_base.ibytes =
1070                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1071
1072         hw->eth_stats_base.opackets =
1073                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1074
1075         hw->eth_stats_base.obytes =
1076                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1077
1078         /* reading general device stats */
1079         hw->eth_stats_base.ierrors =
1080                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1081
1082         hw->eth_stats_base.oerrors =
1083                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1084
1085         /* RX ring mbuf allocation failures */
1086         dev->data->rx_mbuf_alloc_failed = 0;
1087
1088         hw->eth_stats_base.imissed =
1089                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1090 }
1091
1092 static void
1093 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1094 {
1095         struct nfp_net_hw *hw;
1096
1097         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1098
1099         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1100         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1101         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1102         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1103         dev_info->max_rx_pktlen = hw->mtu;
1104         /* Next should change when PF support is implemented */
1105         dev_info->max_mac_addrs = 1;
1106
1107         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1108                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1109
1110         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1111                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1112                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1113                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1114
1115         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1116                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1117
1118         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1119                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1120                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1121                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1122
1123         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1124                 .rx_thresh = {
1125                         .pthresh = DEFAULT_RX_PTHRESH,
1126                         .hthresh = DEFAULT_RX_HTHRESH,
1127                         .wthresh = DEFAULT_RX_WTHRESH,
1128                 },
1129                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1130                 .rx_drop_en = 0,
1131         };
1132
1133         dev_info->default_txconf = (struct rte_eth_txconf) {
1134                 .tx_thresh = {
1135                         .pthresh = DEFAULT_TX_PTHRESH,
1136                         .hthresh = DEFAULT_TX_HTHRESH,
1137                         .wthresh = DEFAULT_TX_WTHRESH,
1138                 },
1139                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1140                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1141                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1142                              ETH_TXQ_FLAGS_NOOFFLOADS,
1143         };
1144
1145         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1146         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1147
1148         dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1149                                ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1150                                ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1151
1152         if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1153                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1154 }
1155
1156 static const uint32_t *
1157 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1158 {
1159         static const uint32_t ptypes[] = {
1160                 /* refers to nfp_net_set_hash() */
1161                 RTE_PTYPE_INNER_L3_IPV4,
1162                 RTE_PTYPE_INNER_L3_IPV6,
1163                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1164                 RTE_PTYPE_INNER_L4_MASK,
1165                 RTE_PTYPE_UNKNOWN
1166         };
1167
1168         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1169                 return ptypes;
1170         return NULL;
1171 }
1172
1173 static uint32_t
1174 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1175 {
1176         struct nfp_net_rxq *rxq;
1177         struct nfp_net_rx_desc *rxds;
1178         uint32_t idx;
1179         uint32_t count;
1180
1181         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1182
1183         idx = rxq->rd_p;
1184
1185         count = 0;
1186
1187         /*
1188          * Other PMDs are just checking the DD bit in intervals of 4
1189          * descriptors and counting all four if the first has the DD
1190          * bit on. Of course, this is not accurate but can be good for
1191          * performance. But ideally that should be done in descriptors
1192          * chunks belonging to the same cache line
1193          */
1194
1195         while (count < rxq->rx_count) {
1196                 rxds = &rxq->rxds[idx];
1197                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1198                         break;
1199
1200                 count++;
1201                 idx++;
1202
1203                 /* Wrapping? */
1204                 if ((idx) == rxq->rx_count)
1205                         idx = 0;
1206         }
1207
1208         return count;
1209 }
1210
1211 static int
1212 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1213 {
1214         struct rte_pci_device *pci_dev;
1215         struct nfp_net_hw *hw;
1216         int base = 0;
1217
1218         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1219         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1220
1221         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1222                 base = 1;
1223
1224         /* Make sure all updates are written before un-masking */
1225         rte_wmb();
1226         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1227                       NFP_NET_CFG_ICR_UNMASKED);
1228         return 0;
1229 }
1230
1231 static int
1232 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1233 {
1234         struct rte_pci_device *pci_dev;
1235         struct nfp_net_hw *hw;
1236         int base = 0;
1237
1238         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1239         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1240
1241         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1242                 base = 1;
1243
1244         /* Make sure all updates are written before un-masking */
1245         rte_wmb();
1246         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1247         return 0;
1248 }
1249
1250 static void
1251 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1252 {
1253         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1254         struct rte_eth_link link;
1255
1256         memset(&link, 0, sizeof(link));
1257         nfp_net_dev_atomic_read_link_status(dev, &link);
1258         if (link.link_status)
1259                 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1260                         (int)(dev->data->port_id), (unsigned)link.link_speed,
1261                         link.link_duplex == ETH_LINK_FULL_DUPLEX
1262                         ? "full-duplex" : "half-duplex");
1263         else
1264                 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1265                         (int)(dev->data->port_id));
1266
1267         RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1268                 pci_dev->addr.domain, pci_dev->addr.bus,
1269                 pci_dev->addr.devid, pci_dev->addr.function);
1270 }
1271
1272 /* Interrupt configuration and handling */
1273
1274 /*
1275  * nfp_net_irq_unmask - Unmask an interrupt
1276  *
1277  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1278  * clear the ICR for the entry.
1279  */
1280 static void
1281 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1282 {
1283         struct nfp_net_hw *hw;
1284         struct rte_pci_device *pci_dev;
1285
1286         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1287         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1288
1289         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1290                 /* If MSI-X auto-masking is used, clear the entry */
1291                 rte_wmb();
1292                 rte_intr_enable(&pci_dev->intr_handle);
1293         } else {
1294                 /* Make sure all updates are written before un-masking */
1295                 rte_wmb();
1296                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1297                               NFP_NET_CFG_ICR_UNMASKED);
1298         }
1299 }
1300
1301 static void
1302 nfp_net_dev_interrupt_handler(void *param)
1303 {
1304         int64_t timeout;
1305         struct rte_eth_link link;
1306         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1307
1308         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1309
1310         /* get the link status */
1311         memset(&link, 0, sizeof(link));
1312         nfp_net_dev_atomic_read_link_status(dev, &link);
1313
1314         nfp_net_link_update(dev, 0);
1315
1316         /* likely to up */
1317         if (!link.link_status) {
1318                 /* handle it 1 sec later, wait it being stable */
1319                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1320                 /* likely to down */
1321         } else {
1322                 /* handle it 4 sec later, wait it being stable */
1323                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1324         }
1325
1326         if (rte_eal_alarm_set(timeout * 1000,
1327                               nfp_net_dev_interrupt_delayed_handler,
1328                               (void *)dev) < 0) {
1329                 RTE_LOG(ERR, PMD, "Error setting alarm");
1330                 /* Unmasking */
1331                 nfp_net_irq_unmask(dev);
1332         }
1333 }
1334
1335 /*
1336  * Interrupt handler which shall be registered for alarm callback for delayed
1337  * handling specific interrupt to wait for the stable nic state. As the NIC
1338  * interrupt state is not stable for nfp after link is just down, it needs
1339  * to wait 4 seconds to get the stable status.
1340  *
1341  * @param handle   Pointer to interrupt handle.
1342  * @param param    The address of parameter (struct rte_eth_dev *)
1343  *
1344  * @return  void
1345  */
1346 static void
1347 nfp_net_dev_interrupt_delayed_handler(void *param)
1348 {
1349         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1350
1351         nfp_net_link_update(dev, 0);
1352         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1353
1354         nfp_net_dev_link_status_print(dev);
1355
1356         /* Unmasking */
1357         nfp_net_irq_unmask(dev);
1358 }
1359
1360 static int
1361 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1362 {
1363         struct nfp_net_hw *hw;
1364
1365         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1366
1367         /* check that mtu is within the allowed range */
1368         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1369                 return -EINVAL;
1370
1371         /* switch to jumbo mode if needed */
1372         if ((uint32_t)mtu > ETHER_MAX_LEN)
1373                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1374         else
1375                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1376
1377         /* update max frame size */
1378         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1379
1380         /* writing to configuration space */
1381         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1382
1383         hw->mtu = mtu;
1384
1385         return 0;
1386 }
1387
1388 static int
1389 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1390                        uint16_t queue_idx, uint16_t nb_desc,
1391                        unsigned int socket_id,
1392                        const struct rte_eth_rxconf *rx_conf,
1393                        struct rte_mempool *mp)
1394 {
1395         const struct rte_memzone *tz;
1396         struct nfp_net_rxq *rxq;
1397         struct nfp_net_hw *hw;
1398
1399         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400
1401         PMD_INIT_FUNC_TRACE();
1402
1403         /* Validating number of descriptors */
1404         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1405             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1406             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1407                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1408                 return -EINVAL;
1409         }
1410
1411         /*
1412          * Free memory prior to re-allocation if needed. This is the case after
1413          * calling nfp_net_stop
1414          */
1415         if (dev->data->rx_queues[queue_idx]) {
1416                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1417                 dev->data->rx_queues[queue_idx] = NULL;
1418         }
1419
1420         /* Allocating rx queue data structure */
1421         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1422                                  RTE_CACHE_LINE_SIZE, socket_id);
1423         if (rxq == NULL)
1424                 return -ENOMEM;
1425
1426         /* Hw queues mapping based on firmware confifguration */
1427         rxq->qidx = queue_idx;
1428         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1429         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1430         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1431         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1432
1433         /*
1434          * Tracking mbuf size for detecting a potential mbuf overflow due to
1435          * RX offset
1436          */
1437         rxq->mem_pool = mp;
1438         rxq->mbuf_size = rxq->mem_pool->elt_size;
1439         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1440         hw->flbufsz = rxq->mbuf_size;
1441
1442         rxq->rx_count = nb_desc;
1443         rxq->port_id = dev->data->port_id;
1444         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1445         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1446                                   : ETHER_CRC_LEN);
1447         rxq->drop_en = rx_conf->rx_drop_en;
1448
1449         /*
1450          * Allocate RX ring hardware descriptors. A memzone large enough to
1451          * handle the maximum ring size is allocated in order to allow for
1452          * resizing in later calls to the queue setup function.
1453          */
1454         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1455                                    sizeof(struct nfp_net_rx_desc) *
1456                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1457                                    socket_id);
1458
1459         if (tz == NULL) {
1460                 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1461                 nfp_net_rx_queue_release(rxq);
1462                 return -ENOMEM;
1463         }
1464
1465         /* Saving physical and virtual addresses for the RX ring */
1466         rxq->dma = (uint64_t)tz->phys_addr;
1467         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1468
1469         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1470         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1471                                          sizeof(*rxq->rxbufs) * nb_desc,
1472                                          RTE_CACHE_LINE_SIZE, socket_id);
1473         if (rxq->rxbufs == NULL) {
1474                 nfp_net_rx_queue_release(rxq);
1475                 return -ENOMEM;
1476         }
1477
1478         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1479                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1480
1481         nfp_net_reset_rx_queue(rxq);
1482
1483         dev->data->rx_queues[queue_idx] = rxq;
1484         rxq->hw = hw;
1485
1486         /*
1487          * Telling the HW about the physical address of the RX ring and number
1488          * of descriptors in log2 format
1489          */
1490         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1491         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1492
1493         return 0;
1494 }
1495
1496 static int
1497 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1498 {
1499         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1500         uint64_t dma_addr;
1501         unsigned i;
1502
1503         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1504                    rxq->rx_count);
1505
1506         for (i = 0; i < rxq->rx_count; i++) {
1507                 struct nfp_net_rx_desc *rxd;
1508                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1509
1510                 if (mbuf == NULL) {
1511                         RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1512                                 (unsigned)rxq->qidx);
1513                         return -ENOMEM;
1514                 }
1515
1516                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1517
1518                 rxd = &rxq->rxds[i];
1519                 rxd->fld.dd = 0;
1520                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1521                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1522                 rxe[i].mbuf = mbuf;
1523                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1524         }
1525
1526         /* Make sure all writes are flushed before telling the hardware */
1527         rte_wmb();
1528
1529         /* Not advertising the whole ring as the firmware gets confused if so */
1530         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1531                    rxq->rx_count - 1);
1532
1533         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1534
1535         return 0;
1536 }
1537
1538 static int
1539 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1540                        uint16_t nb_desc, unsigned int socket_id,
1541                        const struct rte_eth_txconf *tx_conf)
1542 {
1543         const struct rte_memzone *tz;
1544         struct nfp_net_txq *txq;
1545         uint16_t tx_free_thresh;
1546         struct nfp_net_hw *hw;
1547
1548         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1549
1550         PMD_INIT_FUNC_TRACE();
1551
1552         /* Validating number of descriptors */
1553         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1554             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1555             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1556                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1557                 return -EINVAL;
1558         }
1559
1560         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1561                                     tx_conf->tx_free_thresh :
1562                                     DEFAULT_TX_FREE_THRESH);
1563
1564         if (tx_free_thresh > (nb_desc)) {
1565                 RTE_LOG(ERR, PMD,
1566                         "tx_free_thresh must be less than the number of TX "
1567                         "descriptors. (tx_free_thresh=%u port=%d "
1568                         "queue=%d)\n", (unsigned int)tx_free_thresh,
1569                         (int)dev->data->port_id, (int)queue_idx);
1570                 return -(EINVAL);
1571         }
1572
1573         /*
1574          * Free memory prior to re-allocation if needed. This is the case after
1575          * calling nfp_net_stop
1576          */
1577         if (dev->data->tx_queues[queue_idx]) {
1578                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1579                            queue_idx);
1580                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1581                 dev->data->tx_queues[queue_idx] = NULL;
1582         }
1583
1584         /* Allocating tx queue data structure */
1585         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1586                                  RTE_CACHE_LINE_SIZE, socket_id);
1587         if (txq == NULL) {
1588                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1589                 return -ENOMEM;
1590         }
1591
1592         /*
1593          * Allocate TX ring hardware descriptors. A memzone large enough to
1594          * handle the maximum ring size is allocated in order to allow for
1595          * resizing in later calls to the queue setup function.
1596          */
1597         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1598                                    sizeof(struct nfp_net_tx_desc) *
1599                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1600                                    socket_id);
1601         if (tz == NULL) {
1602                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1603                 nfp_net_tx_queue_release(txq);
1604                 return -ENOMEM;
1605         }
1606
1607         txq->tx_count = nb_desc;
1608         txq->tx_free_thresh = tx_free_thresh;
1609         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1610         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1611         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1612
1613         /* queue mapping based on firmware configuration */
1614         txq->qidx = queue_idx;
1615         txq->tx_qcidx = queue_idx * hw->stride_tx;
1616         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1617
1618         txq->port_id = dev->data->port_id;
1619         txq->txq_flags = tx_conf->txq_flags;
1620
1621         /* Saving physical and virtual addresses for the TX ring */
1622         txq->dma = (uint64_t)tz->phys_addr;
1623         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1624
1625         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1626         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1627                                          sizeof(*txq->txbufs) * nb_desc,
1628                                          RTE_CACHE_LINE_SIZE, socket_id);
1629         if (txq->txbufs == NULL) {
1630                 nfp_net_tx_queue_release(txq);
1631                 return -ENOMEM;
1632         }
1633         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1634                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1635
1636         nfp_net_reset_tx_queue(txq);
1637
1638         dev->data->tx_queues[queue_idx] = txq;
1639         txq->hw = hw;
1640
1641         /*
1642          * Telling the HW about the physical address of the TX ring and number
1643          * of descriptors in log2 format
1644          */
1645         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1646         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1647
1648         return 0;
1649 }
1650
1651 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1652 static inline void
1653 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1654                struct rte_mbuf *mb)
1655 {
1656         uint64_t ol_flags;
1657         struct nfp_net_hw *hw = txq->hw;
1658
1659         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1660                 goto clean_txd;
1661
1662         ol_flags = mb->ol_flags;
1663
1664         if (!(ol_flags & PKT_TX_TCP_SEG))
1665                 goto clean_txd;
1666
1667         txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1668         txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1669         txd->flags = PCIE_DESC_TX_LSO;
1670         return;
1671
1672 clean_txd:
1673         txd->flags = 0;
1674         txd->l4_offset = 0;
1675         txd->lso = 0;
1676 }
1677
1678 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1679 static inline void
1680 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1681                  struct rte_mbuf *mb)
1682 {
1683         uint64_t ol_flags;
1684         struct nfp_net_hw *hw = txq->hw;
1685
1686         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1687                 return;
1688
1689         ol_flags = mb->ol_flags;
1690
1691         /* IPv6 does not need checksum */
1692         if (ol_flags & PKT_TX_IP_CKSUM)
1693                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1694
1695         switch (ol_flags & PKT_TX_L4_MASK) {
1696         case PKT_TX_UDP_CKSUM:
1697                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1698                 break;
1699         case PKT_TX_TCP_CKSUM:
1700                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1701                 break;
1702         }
1703
1704         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1705                 txd->flags |= PCIE_DESC_TX_CSUM;
1706 }
1707
1708 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1709 static inline void
1710 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1711                  struct rte_mbuf *mb)
1712 {
1713         struct nfp_net_hw *hw = rxq->hw;
1714
1715         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1716                 return;
1717
1718         /* If IPv4 and IP checksum error, fail */
1719         if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1720             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1721                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1722
1723         /* If neither UDP nor TCP return */
1724         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1725             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1726                 return;
1727
1728         if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1729             !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1730                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1731
1732         if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1733             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1734                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1735 }
1736
1737 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1738 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1739
1740 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1741
1742 /*
1743  * nfp_net_set_hash - Set mbuf hash data
1744  *
1745  * The RSS hash and hash-type are pre-pended to the packet data.
1746  * Extract and decode it and set the mbuf fields.
1747  */
1748 static inline void
1749 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1750                  struct rte_mbuf *mbuf)
1751 {
1752         struct nfp_net_hw *hw = rxq->hw;
1753         uint8_t *meta_offset;
1754         uint32_t meta_info;
1755         uint32_t hash = 0;
1756         uint32_t hash_type = 0;
1757
1758         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1759                 return;
1760
1761         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1762                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1763                         return;
1764
1765                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1766                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1767
1768         } else if (NFP_DESC_META_LEN(rxd)) {
1769                 /*
1770                  * new metadata api:
1771                  * <----  32 bit  ----->
1772                  * m    field type word
1773                  * e     data field #2
1774                  * t     data field #1
1775                  * a     data field #0
1776                  * ====================
1777                  *    packet data
1778                  *
1779                  * Field type word contains up to 8 4bit field types
1780                  * A 4bit field type refers to a data field word
1781                  * A data field word can have several 4bit field types
1782                  */
1783                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1784                 meta_offset -= NFP_DESC_META_LEN(rxd);
1785                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1786                 meta_offset += 4;
1787                 /* NFP PMD just supports metadata for hashing */
1788                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1789                 case NFP_NET_META_HASH:
1790                         /* next field type is about the hash type */
1791                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1792                         /* hash value is in the data field */
1793                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1794                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1795                         break;
1796                 default:
1797                         /* Unsupported metadata can be a performance issue */
1798                         return;
1799                 }
1800         } else {
1801                 return;
1802         }
1803
1804         mbuf->hash.rss = hash;
1805         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1806
1807         switch (hash_type) {
1808         case NFP_NET_RSS_IPV4:
1809                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1810                 break;
1811         case NFP_NET_RSS_IPV6:
1812                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1813                 break;
1814         case NFP_NET_RSS_IPV6_EX:
1815                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1816                 break;
1817         default:
1818                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1819         }
1820 }
1821
1822 static inline void
1823 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1824 {
1825         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1826 }
1827
1828 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1829
1830 /*
1831  * RX path design:
1832  *
1833  * There are some decissions to take:
1834  * 1) How to check DD RX descriptors bit
1835  * 2) How and when to allocate new mbufs
1836  *
1837  * Current implementation checks just one single DD bit each loop. As each
1838  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1839  * a single cache line instead. Tests with this change have not shown any
1840  * performance improvement but it requires further investigation. For example,
1841  * depending on which descriptor is next, the number of descriptors could be
1842  * less than 8 for just checking those in the same cache line. This implies
1843  * extra work which could be counterproductive by itself. Indeed, last firmware
1844  * changes are just doing this: writing several descriptors with the DD bit
1845  * for saving PCIe bandwidth and DMA operations from the NFP.
1846  *
1847  * Mbuf allocation is done when a new packet is received. Then the descriptor
1848  * is automatically linked with the new mbuf and the old one is given to the
1849  * user. The main drawback with this design is mbuf allocation is heavier than
1850  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1851  * cache point of view it does not seem allocating the mbuf early on as we are
1852  * doing now have any benefit at all. Again, tests with this change have not
1853  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1854  * so looking at the implications of this type of allocation should be studied
1855  * deeply
1856  */
1857
1858 static uint16_t
1859 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1860 {
1861         struct nfp_net_rxq *rxq;
1862         struct nfp_net_rx_desc *rxds;
1863         struct nfp_net_rx_buff *rxb;
1864         struct nfp_net_hw *hw;
1865         struct rte_mbuf *mb;
1866         struct rte_mbuf *new_mb;
1867         uint16_t nb_hold;
1868         uint64_t dma_addr;
1869         int avail;
1870
1871         rxq = rx_queue;
1872         if (unlikely(rxq == NULL)) {
1873                 /*
1874                  * DPDK just checks the queue is lower than max queues
1875                  * enabled. But the queue needs to be configured
1876                  */
1877                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1878                 return -EINVAL;
1879         }
1880
1881         hw = rxq->hw;
1882         avail = 0;
1883         nb_hold = 0;
1884
1885         while (avail < nb_pkts) {
1886                 rxb = &rxq->rxbufs[rxq->rd_p];
1887                 if (unlikely(rxb == NULL)) {
1888                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1889                         break;
1890                 }
1891
1892                 /*
1893                  * Memory barrier to ensure that we won't do other
1894                  * reads before the DD bit.
1895                  */
1896                 rte_rmb();
1897
1898                 rxds = &rxq->rxds[rxq->rd_p];
1899                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1900                         break;
1901
1902                 /*
1903                  * We got a packet. Let's alloc a new mbuff for refilling the
1904                  * free descriptor ring as soon as possible
1905                  */
1906                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1907                 if (unlikely(new_mb == NULL)) {
1908                         RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1909                                 "queue_id=%u\n", (unsigned)rxq->port_id,
1910                                 (unsigned)rxq->qidx);
1911                         nfp_net_mbuf_alloc_failed(rxq);
1912                         break;
1913                 }
1914
1915                 nb_hold++;
1916
1917                 /*
1918                  * Grab the mbuff and refill the descriptor with the
1919                  * previously allocated mbuff
1920                  */
1921                 mb = rxb->mbuf;
1922                 rxb->mbuf = new_mb;
1923
1924                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1925                            rxds->rxd.data_len, rxq->mbuf_size);
1926
1927                 /* Size of this segment */
1928                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1929                 /* Size of the whole packet. We just support 1 segment */
1930                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1931
1932                 if (unlikely((mb->data_len + hw->rx_offset) >
1933                              rxq->mbuf_size)) {
1934                         /*
1935                          * This should not happen and the user has the
1936                          * responsibility of avoiding it. But we have
1937                          * to give some info about the error
1938                          */
1939                         RTE_LOG_DP(ERR, PMD,
1940                                 "mbuf overflow likely due to the RX offset.\n"
1941                                 "\t\tYour mbuf size should have extra space for"
1942                                 " RX offset=%u bytes.\n"
1943                                 "\t\tCurrently you just have %u bytes available"
1944                                 " but the received packet is %u bytes long",
1945                                 hw->rx_offset,
1946                                 rxq->mbuf_size - hw->rx_offset,
1947                                 mb->data_len);
1948                         return -EINVAL;
1949                 }
1950
1951                 /* Filling the received mbuff with packet info */
1952                 if (hw->rx_offset)
1953                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1954                 else
1955                         mb->data_off = RTE_PKTMBUF_HEADROOM +
1956                                        NFP_DESC_META_LEN(rxds);
1957
1958                 /* No scatter mode supported */
1959                 mb->nb_segs = 1;
1960                 mb->next = NULL;
1961
1962                 /* Checking the RSS flag */
1963                 nfp_net_set_hash(rxq, rxds, mb);
1964
1965                 /* Checking the checksum flag */
1966                 nfp_net_rx_cksum(rxq, rxds, mb);
1967
1968                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1969                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1970                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1971                         mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1972                 }
1973
1974                 /* Adding the mbuff to the mbuff array passed by the app */
1975                 rx_pkts[avail++] = mb;
1976
1977                 /* Now resetting and updating the descriptor */
1978                 rxds->vals[0] = 0;
1979                 rxds->vals[1] = 0;
1980                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1981                 rxds->fld.dd = 0;
1982                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1983                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1984
1985                 rxq->rd_p++;
1986                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
1987                         rxq->rd_p = 0;
1988         }
1989
1990         if (nb_hold == 0)
1991                 return nb_hold;
1992
1993         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received\n",
1994                    (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1995
1996         nb_hold += rxq->nb_rx_hold;
1997
1998         /*
1999          * FL descriptors needs to be written before incrementing the
2000          * FL queue WR pointer
2001          */
2002         rte_wmb();
2003         if (nb_hold > rxq->rx_free_thresh) {
2004                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2005                            (unsigned)rxq->port_id, (unsigned)rxq->qidx,
2006                            (unsigned)nb_hold, (unsigned)avail);
2007                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2008                 nb_hold = 0;
2009         }
2010         rxq->nb_rx_hold = nb_hold;
2011
2012         return avail;
2013 }
2014
2015 /*
2016  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2017  * status
2018  * @txq: TX queue to work with
2019  * Returns number of descriptors freed
2020  */
2021 int
2022 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2023 {
2024         uint32_t qcp_rd_p;
2025         int todo;
2026
2027         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2028                    " status\n", txq->qidx);
2029
2030         /* Work out how many packets have been sent */
2031         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2032
2033         if (qcp_rd_p == txq->rd_p) {
2034                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2035                            "packets (%u, %u)\n", txq->qidx,
2036                            qcp_rd_p, txq->rd_p);
2037                 return 0;
2038         }
2039
2040         if (qcp_rd_p > txq->rd_p)
2041                 todo = qcp_rd_p - txq->rd_p;
2042         else
2043                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2044
2045         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2046                    qcp_rd_p, txq->rd_p, txq->rd_p);
2047
2048         if (todo == 0)
2049                 return todo;
2050
2051         txq->rd_p += todo;
2052         if (unlikely(txq->rd_p >= txq->tx_count))
2053                 txq->rd_p -= txq->tx_count;
2054
2055         return todo;
2056 }
2057
2058 /* Leaving always free descriptors for avoiding wrapping confusion */
2059 static inline
2060 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2061 {
2062         if (txq->wr_p >= txq->rd_p)
2063                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2064         else
2065                 return txq->rd_p - txq->wr_p - 8;
2066 }
2067
2068 /*
2069  * nfp_net_txq_full - Check if the TX queue free descriptors
2070  * is below tx_free_threshold
2071  *
2072  * @txq: TX queue to check
2073  *
2074  * This function uses the host copy* of read/write pointers
2075  */
2076 static inline
2077 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2078 {
2079         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2080 }
2081
2082 static uint16_t
2083 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2084 {
2085         struct nfp_net_txq *txq;
2086         struct nfp_net_hw *hw;
2087         struct nfp_net_tx_desc *txds, txd;
2088         struct rte_mbuf *pkt;
2089         uint64_t dma_addr;
2090         int pkt_size, dma_size;
2091         uint16_t free_descs, issued_descs;
2092         struct rte_mbuf **lmbuf;
2093         int i;
2094
2095         txq = tx_queue;
2096         hw = txq->hw;
2097         txds = &txq->txds[txq->wr_p];
2098
2099         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2100                    txq->qidx, txq->wr_p, nb_pkts);
2101
2102         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2103                 nfp_net_tx_free_bufs(txq);
2104
2105         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2106         if (unlikely(free_descs == 0))
2107                 return 0;
2108
2109         pkt = *tx_pkts;
2110
2111         i = 0;
2112         issued_descs = 0;
2113         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2114                    txq->qidx, nb_pkts);
2115         /* Sending packets */
2116         while ((i < nb_pkts) && free_descs) {
2117                 /* Grabbing the mbuf linked to the current descriptor */
2118                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2119                 /* Warming the cache for releasing the mbuf later on */
2120                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2121
2122                 pkt = *(tx_pkts + i);
2123
2124                 if (unlikely((pkt->nb_segs > 1) &&
2125                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2126                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2127                         rte_panic("Multisegment packet unsupported\n");
2128                 }
2129
2130                 /* Checking if we have enough descriptors */
2131                 if (unlikely(pkt->nb_segs > free_descs))
2132                         goto xmit_end;
2133
2134                 /*
2135                  * Checksum and VLAN flags just in the first descriptor for a
2136                  * multisegment packet, but TSO info needs to be in all of them.
2137                  */
2138                 txd.data_len = pkt->pkt_len;
2139                 nfp_net_tx_tso(txq, &txd, pkt);
2140                 nfp_net_tx_cksum(txq, &txd, pkt);
2141
2142                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2143                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2144                         txd.flags |= PCIE_DESC_TX_VLAN;
2145                         txd.vlan = pkt->vlan_tci;
2146                 }
2147
2148                 /*
2149                  * mbuf data_len is the data in one segment and pkt_len data
2150                  * in the whole packet. When the packet is just one segment,
2151                  * then data_len = pkt_len
2152                  */
2153                 pkt_size = pkt->pkt_len;
2154
2155                 while (pkt) {
2156                         /* Copying TSO, VLAN and cksum info */
2157                         *txds = txd;
2158
2159                         /* Releasing mbuf used by this descriptor previously*/
2160                         if (*lmbuf)
2161                                 rte_pktmbuf_free_seg(*lmbuf);
2162
2163                         /*
2164                          * Linking mbuf with descriptor for being released
2165                          * next time descriptor is used
2166                          */
2167                         *lmbuf = pkt;
2168
2169                         dma_size = pkt->data_len;
2170                         dma_addr = rte_mbuf_data_dma_addr(pkt);
2171                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2172                                    "%" PRIx64 "\n", dma_addr);
2173
2174                         /* Filling descriptors fields */
2175                         txds->dma_len = dma_size;
2176                         txds->data_len = txd.data_len;
2177                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2178                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2179                         ASSERT(free_descs > 0);
2180                         free_descs--;
2181
2182                         txq->wr_p++;
2183                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2184                                 txq->wr_p = 0;
2185
2186                         pkt_size -= dma_size;
2187                         if (!pkt_size)
2188                                 /* End of packet */
2189                                 txds->offset_eop |= PCIE_DESC_TX_EOP;
2190                         else
2191                                 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2192
2193                         pkt = pkt->next;
2194                         /* Referencing next free TX descriptor */
2195                         txds = &txq->txds[txq->wr_p];
2196                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2197                         issued_descs++;
2198                 }
2199                 i++;
2200         }
2201
2202 xmit_end:
2203         /* Increment write pointers. Force memory write before we let HW know */
2204         rte_wmb();
2205         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2206
2207         return i;
2208 }
2209
2210 static void
2211 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2212 {
2213         uint32_t new_ctrl, update;
2214         struct nfp_net_hw *hw;
2215
2216         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217         new_ctrl = 0;
2218
2219         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2220             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2221                 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2222                         " ETH_VLAN_EXTEND_OFFLOAD");
2223
2224         /* Enable vlan strip if it is not configured yet */
2225         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2226             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2227                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2228
2229         /* Disable vlan strip just if it is configured */
2230         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2231             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2232                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2233
2234         if (new_ctrl == 0)
2235                 return;
2236
2237         update = NFP_NET_CFG_UPDATE_GEN;
2238
2239         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2240                 return;
2241
2242         hw->ctrl = new_ctrl;
2243 }
2244
2245 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2246 static int
2247 nfp_net_reta_update(struct rte_eth_dev *dev,
2248                     struct rte_eth_rss_reta_entry64 *reta_conf,
2249                     uint16_t reta_size)
2250 {
2251         uint32_t reta, mask;
2252         int i, j;
2253         int idx, shift;
2254         uint32_t update;
2255         struct nfp_net_hw *hw =
2256                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2257
2258         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2259                 return -EINVAL;
2260
2261         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2262                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2263                         "(%d) doesn't match the number hardware can supported "
2264                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2265                 return -EINVAL;
2266         }
2267
2268         /*
2269          * Update Redirection Table. There are 128 8bit-entries which can be
2270          * manage as 32 32bit-entries
2271          */
2272         for (i = 0; i < reta_size; i += 4) {
2273                 /* Handling 4 RSS entries per loop */
2274                 idx = i / RTE_RETA_GROUP_SIZE;
2275                 shift = i % RTE_RETA_GROUP_SIZE;
2276                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2277
2278                 if (!mask)
2279                         continue;
2280
2281                 reta = 0;
2282                 /* If all 4 entries were set, don't need read RETA register */
2283                 if (mask != 0xF)
2284                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2285
2286                 for (j = 0; j < 4; j++) {
2287                         if (!(mask & (0x1 << j)))
2288                                 continue;
2289                         if (mask != 0xF)
2290                                 /* Clearing the entry bits */
2291                                 reta &= ~(0xFF << (8 * j));
2292                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2293                 }
2294                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2295                               reta);
2296         }
2297
2298         update = NFP_NET_CFG_UPDATE_RSS;
2299
2300         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2301                 return -EIO;
2302
2303         return 0;
2304 }
2305
2306  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2307 static int
2308 nfp_net_reta_query(struct rte_eth_dev *dev,
2309                    struct rte_eth_rss_reta_entry64 *reta_conf,
2310                    uint16_t reta_size)
2311 {
2312         uint8_t i, j, mask;
2313         int idx, shift;
2314         uint32_t reta;
2315         struct nfp_net_hw *hw;
2316
2317         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2318
2319         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2320                 return -EINVAL;
2321
2322         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2323                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2324                         "(%d) doesn't match the number hardware can supported "
2325                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2326                 return -EINVAL;
2327         }
2328
2329         /*
2330          * Reading Redirection Table. There are 128 8bit-entries which can be
2331          * manage as 32 32bit-entries
2332          */
2333         for (i = 0; i < reta_size; i += 4) {
2334                 /* Handling 4 RSS entries per loop */
2335                 idx = i / RTE_RETA_GROUP_SIZE;
2336                 shift = i % RTE_RETA_GROUP_SIZE;
2337                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2338
2339                 if (!mask)
2340                         continue;
2341
2342                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2343                                     shift);
2344                 for (j = 0; j < 4; j++) {
2345                         if (!(mask & (0x1 << j)))
2346                                 continue;
2347                         reta_conf->reta[shift + j] =
2348                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2349                 }
2350         }
2351         return 0;
2352 }
2353
2354 static int
2355 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2356                         struct rte_eth_rss_conf *rss_conf)
2357 {
2358         uint32_t update;
2359         uint32_t cfg_rss_ctrl = 0;
2360         uint8_t key;
2361         uint64_t rss_hf;
2362         int i;
2363         struct nfp_net_hw *hw;
2364
2365         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366
2367         rss_hf = rss_conf->rss_hf;
2368
2369         /* Checking if RSS is enabled */
2370         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2371                 if (rss_hf != 0) { /* Enable RSS? */
2372                         RTE_LOG(ERR, PMD, "RSS unsupported\n");
2373                         return -EINVAL;
2374                 }
2375                 return 0; /* Nothing to do */
2376         }
2377
2378         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2379                 RTE_LOG(ERR, PMD, "hash key too long\n");
2380                 return -EINVAL;
2381         }
2382
2383         if (rss_hf & ETH_RSS_IPV4)
2384                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2385                                 NFP_NET_CFG_RSS_IPV4_TCP |
2386                                 NFP_NET_CFG_RSS_IPV4_UDP;
2387
2388         if (rss_hf & ETH_RSS_IPV6)
2389                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2390                                 NFP_NET_CFG_RSS_IPV6_TCP |
2391                                 NFP_NET_CFG_RSS_IPV6_UDP;
2392
2393         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2394         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2395
2396         /* configuring where to apply the RSS hash */
2397         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2398
2399         /* Writing the key byte a byte */
2400         for (i = 0; i < rss_conf->rss_key_len; i++) {
2401                 memcpy(&key, &rss_conf->rss_key[i], 1);
2402                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2403         }
2404
2405         /* Writing the key size */
2406         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2407
2408         update = NFP_NET_CFG_UPDATE_RSS;
2409
2410         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2411                 return -EIO;
2412
2413         return 0;
2414 }
2415
2416 static int
2417 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2418                           struct rte_eth_rss_conf *rss_conf)
2419 {
2420         uint64_t rss_hf;
2421         uint32_t cfg_rss_ctrl;
2422         uint8_t key;
2423         int i;
2424         struct nfp_net_hw *hw;
2425
2426         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427
2428         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2429                 return -EINVAL;
2430
2431         rss_hf = rss_conf->rss_hf;
2432         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2433
2434         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2435                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2436
2437         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2438                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2439
2440         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2441                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2442
2443         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2444                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2445
2446         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2447                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2448
2449         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2450                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2451
2452         /* Reading the key size */
2453         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2454
2455         /* Reading the key byte a byte */
2456         for (i = 0; i < rss_conf->rss_key_len; i++) {
2457                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2458                 memcpy(&rss_conf->rss_key[i], &key, 1);
2459         }
2460
2461         return 0;
2462 }
2463
2464 /* Initialise and register driver with DPDK Application */
2465 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2466         .dev_configure          = nfp_net_configure,
2467         .dev_start              = nfp_net_start,
2468         .dev_stop               = nfp_net_stop,
2469         .dev_close              = nfp_net_close,
2470         .promiscuous_enable     = nfp_net_promisc_enable,
2471         .promiscuous_disable    = nfp_net_promisc_disable,
2472         .link_update            = nfp_net_link_update,
2473         .stats_get              = nfp_net_stats_get,
2474         .stats_reset            = nfp_net_stats_reset,
2475         .dev_infos_get          = nfp_net_infos_get,
2476         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2477         .mtu_set                = nfp_net_dev_mtu_set,
2478         .vlan_offload_set       = nfp_net_vlan_offload_set,
2479         .reta_update            = nfp_net_reta_update,
2480         .reta_query             = nfp_net_reta_query,
2481         .rss_hash_update        = nfp_net_rss_hash_update,
2482         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2483         .rx_queue_setup         = nfp_net_rx_queue_setup,
2484         .rx_queue_release       = nfp_net_rx_queue_release,
2485         .rx_queue_count         = nfp_net_rx_queue_count,
2486         .tx_queue_setup         = nfp_net_tx_queue_setup,
2487         .tx_queue_release       = nfp_net_tx_queue_release,
2488         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2489         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2490 };
2491
2492 static int
2493 nfp_net_init(struct rte_eth_dev *eth_dev)
2494 {
2495         struct rte_pci_device *pci_dev;
2496         struct nfp_net_hw *hw;
2497
2498         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2499         uint32_t start_q;
2500         int stride = 4;
2501
2502         nspu_desc_t *nspu_desc = NULL;
2503         uint64_t bar_offset;
2504
2505         PMD_INIT_FUNC_TRACE();
2506
2507         hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2508
2509         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2510         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2511         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2512
2513         /* For secondary processes, the primary has done all the work */
2514         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2515                 return 0;
2516
2517         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2518         rte_eth_copy_pci_info(eth_dev, pci_dev);
2519         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2520
2521         hw->device_id = pci_dev->id.device_id;
2522         hw->vendor_id = pci_dev->id.vendor_id;
2523         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2524         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2525
2526         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2527                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2528                      pci_dev->addr.domain, pci_dev->addr.bus,
2529                      pci_dev->addr.devid, pci_dev->addr.function);
2530
2531         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2532         if (hw->ctrl_bar == NULL) {
2533                 RTE_LOG(ERR, PMD,
2534                         "hw->ctrl_bar is NULL. BAR0 not configured\n");
2535                 return -ENODEV;
2536         }
2537
2538         /* Is this a PF device? */
2539         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2540             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2541                 nspu_desc = hw->nspu_desc;
2542
2543                 if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
2544                         /*
2545                          * A firmware should be there after PF probe so this
2546                          * should not happen.
2547                          */
2548                         RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
2549                         return -ENODEV;
2550                 }
2551
2552                 /* vNIC PF control BAR is a subset of PF PCI device BAR */
2553                 hw->ctrl_bar += bar_offset;
2554                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2555         }
2556
2557         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2558         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2559
2560         /* Work out where in the BAR the queues start. */
2561         switch (pci_dev->id.device_id) {
2562         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2563         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2564         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2565                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2566                 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2567                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2568                 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2569                 break;
2570         default:
2571                 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2572                 return -ENODEV;
2573         }
2574
2575         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2576         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2577
2578         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2579             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2580                 /* configure access to tx/rx vNIC BARs */
2581                 nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
2582                 PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
2583                                     bar_offset);
2584                 hw->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
2585
2586                 /* vNIC PF tx/rx BARs are a subset of PF PCI device */
2587                 hw->hw_queues += bar_offset;
2588                 hw->tx_bar = hw->hw_queues + tx_bar_off;
2589                 hw->rx_bar = hw->hw_queues + rx_bar_off;
2590         } else {
2591                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2592                              tx_bar_off;
2593                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2594                              rx_bar_off;
2595         }
2596
2597         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2598                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2599
2600         nfp_net_cfg_queue_setup(hw);
2601
2602         /* Get some of the read-only fields from the config BAR */
2603         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2604         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2605         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2606         hw->mtu = hw->max_mtu;
2607
2608         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2609                 hw->rx_offset = NFP_NET_RX_OFFSET;
2610         else
2611                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2612
2613         PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2614                      hw->ver, hw->max_mtu);
2615         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
2616                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2617                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2618                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2619                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2620                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2621                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2622                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2623                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2624                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "");
2625
2626         hw->ctrl = 0;
2627
2628         hw->stride_rx = stride;
2629         hw->stride_tx = stride;
2630
2631         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2632                      hw->max_rx_queues, hw->max_tx_queues);
2633
2634         /* Initializing spinlock for reconfigs */
2635         rte_spinlock_init(&hw->reconfig_lock);
2636
2637         /* Allocating memory for mac addr */
2638         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2639         if (eth_dev->data->mac_addrs == NULL) {
2640                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2641                 return -ENOMEM;
2642         }
2643
2644         nfp_net_read_mac(hw);
2645
2646         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2647                 /* Using random mac addresses for VFs */
2648                 eth_random_addr(&hw->mac_addr[0]);
2649                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2650         }
2651
2652         /* Copying mac address to DPDK eth_dev struct */
2653         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2654                         &eth_dev->data->mac_addrs[0]);
2655
2656         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2657                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2658                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2659                      pci_dev->id.device_id,
2660                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2661                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2662
2663         /* Registering LSC interrupt handler */
2664         rte_intr_callback_register(&pci_dev->intr_handle,
2665                                    nfp_net_dev_interrupt_handler,
2666                                    (void *)eth_dev);
2667
2668         /* Telling the firmware about the LSC interrupt entry */
2669         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2670
2671         /* Recording current stats counters values */
2672         nfp_net_stats_reset(eth_dev);
2673
2674         return 0;
2675 }
2676
2677 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2678                             struct rte_pci_device *dev)
2679 {
2680         struct rte_eth_dev *eth_dev;
2681         struct nfp_net_hw *hw;
2682         nfpu_desc_t *nfpu_desc;
2683         nspu_desc_t *nspu_desc;
2684         uint64_t offset_symbol;
2685         int major, minor;
2686         int ret = -ENODEV;
2687
2688         if (!dev)
2689                 return ret;
2690
2691         nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
2692         if (!nfpu_desc)
2693                 return -ENOMEM;
2694
2695         if (nfpu_open(dev, nfpu_desc, 0) < 0) {
2696                 RTE_LOG(ERR, PMD,
2697                         "nfpu_open failed\n");
2698                 goto nfpu_error;
2699         }
2700
2701         nspu_desc = nfpu_desc->nspu;
2702
2703
2704         /* Check NSP ABI version */
2705         if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
2706                 RTE_LOG(INFO, PMD, "NFP NSP not present\n");
2707                 goto error;
2708         }
2709         PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
2710
2711         if ((major == 0) && (minor < 20)) {
2712                 RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
2713                 goto error;
2714         }
2715
2716         ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
2717                                &offset_symbol);
2718         if (ret)
2719                 goto error;
2720
2721         eth_dev = rte_eth_dev_allocate(dev->device.name);
2722         if (!eth_dev) {
2723                 ret = -ENODEV;
2724                 goto error;
2725         }
2726
2727         eth_dev->data->dev_private = rte_zmalloc("nfp_pf_port",
2728                                                  sizeof(struct nfp_net_adapter),
2729                                                  RTE_CACHE_LINE_SIZE);
2730         if (!eth_dev->data->dev_private) {
2731                 rte_eth_dev_release_port(eth_dev);
2732                 ret = -ENODEV;
2733                 goto error;
2734         }
2735
2736         hw = (struct nfp_net_hw *)(eth_dev->data->dev_private);
2737         hw->nspu_desc = nspu_desc;
2738         hw->nfpu_desc = nfpu_desc;
2739         hw->is_pf = 1;
2740
2741         eth_dev->device = &dev->device;
2742         rte_eth_copy_pci_info(eth_dev, dev);
2743
2744         ret = nfp_net_init(eth_dev);
2745
2746         if (!ret)
2747                 return 0;
2748
2749         /* something went wrong */
2750         rte_eth_dev_release_port(eth_dev);
2751
2752 error:
2753         nfpu_close(nfpu_desc);
2754 nfpu_error:
2755         rte_free(nfpu_desc);
2756
2757         return ret;
2758 }
2759
2760 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
2761         {
2762                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2763                                PCI_DEVICE_ID_NFP4000_PF_NIC)
2764         },
2765         {
2766                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2767                                PCI_DEVICE_ID_NFP6000_PF_NIC)
2768         },
2769         {
2770                 .vendor_id = 0,
2771         },
2772 };
2773
2774 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
2775         {
2776                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2777                                PCI_DEVICE_ID_NFP6000_VF_NIC)
2778         },
2779         {
2780                 .vendor_id = 0,
2781         },
2782 };
2783
2784 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2785         struct rte_pci_device *pci_dev)
2786 {
2787         return rte_eth_dev_pci_generic_probe(pci_dev,
2788                 sizeof(struct nfp_net_adapter), nfp_net_init);
2789 }
2790
2791 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
2792 {
2793         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2794 }
2795
2796 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
2797         .id_table = pci_id_nfp_pf_net_map,
2798         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2799         .probe = nfp_pf_pci_probe,
2800         .remove = eth_nfp_pci_remove,
2801 };
2802
2803 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
2804         .id_table = pci_id_nfp_vf_net_map,
2805         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2806         .probe = eth_nfp_pci_probe,
2807         .remove = eth_nfp_pci_remove,
2808 };
2809
2810 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
2811 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
2812 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
2813 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
2814 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
2815 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
2816
2817 /*
2818  * Local variables:
2819  * c-file-style: "Linux"
2820  * indent-tabs-mode: t
2821  * End:
2822  */