drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev_driver.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57 #include <rte_service_component.h>
  58
  59 #include "nfpcore/nfp_cpp.h"
  60 #include "nfpcore/nfp_nffw.h"
  61 #include "nfpcore/nfp_hwinfo.h"
  62 #include "nfpcore/nfp_mip.h"
  63 #include "nfpcore/nfp_rtsym.h"
  64 #include "nfpcore/nfp_nsp.h"
  65
  66 #include "nfp_net_pmd.h"
  67 #include "nfp_net_logs.h"
  68 #include "nfp_net_ctrl.h"
  69
  70 #include <sys/types.h>
  71 #include <sys/socket.h>
  72 #include <sys/un.h>
  73 #include <unistd.h>
  74 #include <stdio.h>
  75 #include <sys/ioctl.h>
  76 #include <errno.h>
  77
  78 /* Prototypes */
  79 static void nfp_net_close(struct rte_eth_dev *dev);
  80 static int nfp_net_configure(struct rte_eth_dev *dev);
  81 static void nfp_net_dev_interrupt_handler(void *param);
  82 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  83 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  84 static int nfp_net_infos_get(struct rte_eth_dev *dev,
  85                              struct rte_eth_dev_info *dev_info);
  86 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  87 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  88 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  89 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  90 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  91 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  92                                        uint16_t queue_idx);
  93 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  94                                   uint16_t nb_pkts);
  95 static void nfp_net_rx_queue_release(void *rxq);
  96 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  97                                   uint16_t nb_desc, unsigned int socket_id,
  98                                   const struct rte_eth_rxconf *rx_conf,
  99                                   struct rte_mempool *mp);
 100 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
 101 static void nfp_net_tx_queue_release(void *txq);
 102 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 103                                   uint16_t nb_desc, unsigned int socket_id,
 104                                   const struct rte_eth_txconf *tx_conf);
 105 static int nfp_net_start(struct rte_eth_dev *dev);
 106 static int nfp_net_stats_get(struct rte_eth_dev *dev,
 107                               struct rte_eth_stats *stats);
 108 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
 109 static void nfp_net_stop(struct rte_eth_dev *dev);
 110 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 111                                   uint16_t nb_pkts);
 112
 113 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
 114 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
 115                                    struct rte_eth_rss_conf *rss_conf);
 116 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
 117                     struct rte_eth_rss_reta_entry64 *reta_conf,
 118                     uint16_t reta_size);
 119 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
 120                         struct rte_eth_rss_conf *rss_conf);
 121 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
 122                              struct rte_ether_addr *mac_addr);
 123
 124 /* The offset of the queue controller queues in the PCIe Target */
 125 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 126
 127 /* Maximum value which can be added to a queue with one transaction */
 128 #define NFP_QCP_MAX_ADD 0x7f
 129
 130 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 131         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 132
 133 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 134 enum nfp_qcp_ptr {
 135         NFP_QCP_READ_PTR = 0,
 136         NFP_QCP_WRITE_PTR
 137 };
 138
 139 /*
 140  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 141  * @q: Base address for queue structure
 142  * @ptr: Add to the Read or Write pointer
 143  * @val: Value to add to the queue pointer
 144  *
 145  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 146  */
 147 static inline void
 148 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 149 {
 150         uint32_t off;
 151
 152         if (ptr == NFP_QCP_READ_PTR)
 153                 off = NFP_QCP_QUEUE_ADD_RPTR;
 154         else
 155                 off = NFP_QCP_QUEUE_ADD_WPTR;
 156
 157         while (val > NFP_QCP_MAX_ADD) {
 158                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 159                 val -= NFP_QCP_MAX_ADD;
 160         }
 161
 162         nn_writel(rte_cpu_to_le_32(val), q + off);
 163 }
 164
 165 /*
 166  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 167  * @q:  Base address for queue structure
 168  * @ptr: Read or Write pointer
 169  */
 170 static inline uint32_t
 171 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 172 {
 173         uint32_t off;
 174         uint32_t val;
 175
 176         if (ptr == NFP_QCP_READ_PTR)
 177                 off = NFP_QCP_QUEUE_STS_LO;
 178         else
 179                 off = NFP_QCP_QUEUE_STS_HI;
 180
 181         val = rte_cpu_to_le_32(nn_readl(q + off));
 182
 183         if (ptr == NFP_QCP_READ_PTR)
 184                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 185         else
 186                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 187 }
 188
 189 /*
 190  * Functions to read/write from/to Config BAR
 191  * Performs any endian conversion necessary.
 192  */
 193 static inline uint8_t
 194 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 195 {
 196         return nn_readb(hw->ctrl_bar + off);
 197 }
 198
 199 static inline void
 200 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 201 {
 202         nn_writeb(val, hw->ctrl_bar + off);
 203 }
 204
 205 static inline uint32_t
 206 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 207 {
 208         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 209 }
 210
 211 static inline void
 212 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 213 {
 214         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 215 }
 216
 217 static inline uint64_t
 218 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 219 {
 220         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 221 }
 222
 223 static inline void
 224 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 225 {
 226         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 227 }
 228
 229 static void
 230 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 231 {
 232         unsigned i;
 233
 234         if (rxq->rxbufs == NULL)
 235                 return;
 236
 237         for (i = 0; i < rxq->rx_count; i++) {
 238                 if (rxq->rxbufs[i].mbuf) {
 239                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 240                         rxq->rxbufs[i].mbuf = NULL;
 241                 }
 242         }
 243 }
 244
 245 static void
 246 nfp_net_rx_queue_release(void *rx_queue)
 247 {
 248         struct nfp_net_rxq *rxq = rx_queue;
 249
 250         if (rxq) {
 251                 nfp_net_rx_queue_release_mbufs(rxq);
 252                 rte_free(rxq->rxbufs);
 253                 rte_free(rxq);
 254         }
 255 }
 256
 257 static void
 258 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 259 {
 260         nfp_net_rx_queue_release_mbufs(rxq);
 261         rxq->rd_p = 0;
 262         rxq->nb_rx_hold = 0;
 263 }
 264
 265 static void
 266 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 267 {
 268         unsigned i;
 269
 270         if (txq->txbufs == NULL)
 271                 return;
 272
 273         for (i = 0; i < txq->tx_count; i++) {
 274                 if (txq->txbufs[i].mbuf) {
 275                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 276                         txq->txbufs[i].mbuf = NULL;
 277                 }
 278         }
 279 }
 280
 281 static void
 282 nfp_net_tx_queue_release(void *tx_queue)
 283 {
 284         struct nfp_net_txq *txq = tx_queue;
 285
 286         if (txq) {
 287                 nfp_net_tx_queue_release_mbufs(txq);
 288                 rte_free(txq->txbufs);
 289                 rte_free(txq);
 290         }
 291 }
 292
 293 static void
 294 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 295 {
 296         nfp_net_tx_queue_release_mbufs(txq);
 297         txq->wr_p = 0;
 298         txq->rd_p = 0;
 299 }
 300
 301 static int
 302 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 303 {
 304         int cnt;
 305         uint32_t new;
 306         struct timespec wait;
 307
 308         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 309                     hw->qcp_cfg);
 310
 311         if (hw->qcp_cfg == NULL)
 312                 rte_panic("Bad configuration queue pointer\n");
 313
 314         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 315
 316         wait.tv_sec = 0;
 317         wait.tv_nsec = 1000000;
 318
 319         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 320
 321         /* Poll update field, waiting for NFP to ack the config */
 322         for (cnt = 0; ; cnt++) {
 323                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 324                 if (new == 0)
 325                         break;
 326                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 327                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 328                         return -1;
 329                 }
 330                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 331                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 332                                           " %dms", update, cnt);
 333                         rte_panic("Exiting\n");
 334                 }
 335                 nanosleep(&wait, 0); /* waiting for a 1ms */
 336         }
 337         PMD_DRV_LOG(DEBUG, "Ack DONE");
 338         return 0;
 339 }
 340
 341 /*
 342  * Reconfigure the NIC
 343  * @nn:    device to reconfigure
 344  * @ctrl:    The value for the ctrl field in the BAR config
 345  * @update:  The value for the update field in the BAR config
 346  *
 347  * Write the update word to the BAR and ping the reconfig queue. Then poll
 348  * until the firmware has acknowledged the update by zeroing the update word.
 349  */
 350 static int
 351 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 352 {
 353         uint32_t err;
 354
 355         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 356                     ctrl, update);
 357
 358         rte_spinlock_lock(&hw->reconfig_lock);
 359
 360         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 361         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 362
 363         rte_wmb();
 364
 365         err = __nfp_net_reconfig(hw, update);
 366
 367         rte_spinlock_unlock(&hw->reconfig_lock);
 368
 369         if (!err)
 370                 return 0;
 371
 372         /*
 373          * Reconfig errors imply situations where they can be handled.
 374          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 375          */
 376         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 377                      ctrl, update);
 378         return -EIO;
 379 }
 380
 381 /*
 382  * Configure an Ethernet device. This function must be invoked first
 383  * before any other function in the Ethernet API. This function can
 384  * also be re-invoked when a device is in the stopped state.
 385  */
 386 static int
 387 nfp_net_configure(struct rte_eth_dev *dev)
 388 {
 389         struct rte_eth_conf *dev_conf;
 390         struct rte_eth_rxmode *rxmode;
 391         struct rte_eth_txmode *txmode;
 392         struct nfp_net_hw *hw;
 393
 394         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 395
 396         /*
 397          * A DPDK app sends info about how many queues to use and how
 398          * those queues need to be configured. This is used by the
 399          * DPDK core and it makes sure no more queues than those
 400          * advertised by the driver are requested. This function is
 401          * called after that internal process
 402          */
 403
 404         PMD_INIT_LOG(DEBUG, "Configure");
 405
 406         dev_conf = &dev->data->dev_conf;
 407         rxmode = &dev_conf->rxmode;
 408         txmode = &dev_conf->txmode;
 409
 410         /* Checking TX mode */
 411         if (txmode->mq_mode) {
 412                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 413                 return -EINVAL;
 414         }
 415
 416         /* Checking RX mode */
 417         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 418             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 419                 PMD_INIT_LOG(INFO, "RSS not supported");
 420                 return -EINVAL;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static void
 427 nfp_net_enable_queues(struct rte_eth_dev *dev)
 428 {
 429         struct nfp_net_hw *hw;
 430         uint64_t enabled_queues = 0;
 431         int i;
 432
 433         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 434
 435         /* Enabling the required TX queues in the device */
 436         for (i = 0; i < dev->data->nb_tx_queues; i++)
 437                 enabled_queues |= (1 << i);
 438
 439         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 440
 441         enabled_queues = 0;
 442
 443         /* Enabling the required RX queues in the device */
 444         for (i = 0; i < dev->data->nb_rx_queues; i++)
 445                 enabled_queues |= (1 << i);
 446
 447         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 448 }
 449
 450 static void
 451 nfp_net_disable_queues(struct rte_eth_dev *dev)
 452 {
 453         struct nfp_net_hw *hw;
 454         uint32_t new_ctrl, update = 0;
 455
 456         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 457
 458         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 459         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 460
 461         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 462         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 463                  NFP_NET_CFG_UPDATE_MSIX;
 464
 465         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 466                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 467
 468         /* If an error when reconfig we avoid to change hw state */
 469         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 470                 return;
 471
 472         hw->ctrl = new_ctrl;
 473 }
 474
 475 static int
 476 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 477 {
 478         int i;
 479
 480         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 481                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 482                         return -1;
 483         }
 484         return 0;
 485 }
 486
 487 static void
 488 nfp_net_params_setup(struct nfp_net_hw *hw)
 489 {
 490         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 491         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 492 }
 493
 494 static void
 495 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 496 {
 497         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 498 }
 499
 500 #define ETH_ADDR_LEN    6
 501
 502 static void
 503 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 504 {
 505         int i;
 506
 507         for (i = 0; i < ETH_ADDR_LEN; i++)
 508                 dst[i] = src[i];
 509 }
 510
 511 static int
 512 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 513 {
 514         struct nfp_eth_table *nfp_eth_table;
 515
 516         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 517         /*
 518          * hw points to port0 private data. We need hw now pointing to
 519          * right port.
 520          */
 521         hw += port;
 522         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 523                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 524
 525         free(nfp_eth_table);
 526         return 0;
 527 }
 528
 529 static void
 530 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 531 {
 532         uint32_t tmp;
 533
 534         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 535         memcpy(&hw->mac_addr[0], &tmp, 4);
 536
 537         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 538         memcpy(&hw->mac_addr[4], &tmp, 2);
 539 }
 540
 541 static void
 542 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 543 {
 544         uint32_t mac0 = *(uint32_t *)mac;
 545         uint16_t mac1;
 546
 547         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 548
 549         mac += 4;
 550         mac1 = *(uint16_t *)mac;
 551         nn_writew(rte_cpu_to_be_16(mac1),
 552                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 553 }
 554
 555 int
 556 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
 557 {
 558         struct nfp_net_hw *hw;
 559         uint32_t update, ctrl;
 560
 561         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 562         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 563             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 564                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 565                                   " port enabled");
 566                 return -EBUSY;
 567         }
 568
 569         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 570             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 571                 return -EBUSY;
 572
 573         /* Writing new MAC to the specific port BAR address */
 574         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 575
 576         /* Signal the NIC about the change */
 577         update = NFP_NET_CFG_UPDATE_MACADDR;
 578         ctrl = hw->ctrl;
 579         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 580             (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 581                 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
 582         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 583                 PMD_INIT_LOG(INFO, "MAC address update failed");
 584                 return -EIO;
 585         }
 586         return 0;
 587 }
 588
 589 static int
 590 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 591                            struct rte_intr_handle *intr_handle)
 592 {
 593         struct nfp_net_hw *hw;
 594         int i;
 595
 596         if (!intr_handle->intr_vec) {
 597                 intr_handle->intr_vec =
 598                         rte_zmalloc("intr_vec",
 599                                     dev->data->nb_rx_queues * sizeof(int), 0);
 600                 if (!intr_handle->intr_vec) {
 601                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 602                                      " intr_vec", dev->data->nb_rx_queues);
 603                         return -ENOMEM;
 604                 }
 605         }
 606
 607         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 608
 609         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 610                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 611                 /* UIO just supports one queue and no LSC*/
 612                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 613                 intr_handle->intr_vec[0] = 0;
 614         } else {
 615                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 616                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 617                         /*
 618                          * The first msix vector is reserved for non
 619                          * efd interrupts
 620                         */
 621                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 622                         intr_handle->intr_vec[i] = i + 1;
 623                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 624                                             intr_handle->intr_vec[i]);
 625                 }
 626         }
 627
 628         /* Avoiding TX interrupts */
 629         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 630         return 0;
 631 }
 632
 633 static uint32_t
 634 nfp_check_offloads(struct rte_eth_dev *dev)
 635 {
 636         struct nfp_net_hw *hw;
 637         struct rte_eth_conf *dev_conf;
 638         struct rte_eth_rxmode *rxmode;
 639         struct rte_eth_txmode *txmode;
 640         uint32_t ctrl = 0;
 641
 642         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 643
 644         dev_conf = &dev->data->dev_conf;
 645         rxmode = &dev_conf->rxmode;
 646         txmode = &dev_conf->txmode;
 647
 648         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 649                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 650                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 651         }
 652
 653         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 654                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 655                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 656         }
 657
 658         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 659                 hw->mtu = rxmode->max_rx_pkt_len;
 660
 661         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 662                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 663
 664         /* L2 broadcast */
 665         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 666                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 667
 668         /* L2 multicast */
 669         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 670                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 671
 672         /* TX checksum offload */
 673         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 674             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 675             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 676                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 677
 678         /* LSO offload */
 679         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 680                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 681                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 682                 else
 683                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 684         }
 685
 686         /* RX gather */
 687         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 688                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 689
 690         return ctrl;
 691 }
 692
 693 static int
 694 nfp_net_start(struct rte_eth_dev *dev)
 695 {
 696         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 697         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 698         uint32_t new_ctrl, update = 0;
 699         struct nfp_net_hw *hw;
 700         struct rte_eth_conf *dev_conf;
 701         struct rte_eth_rxmode *rxmode;
 702         uint32_t intr_vector;
 703         int ret;
 704
 705         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 706
 707         PMD_INIT_LOG(DEBUG, "Start");
 708
 709         /* Disabling queues just in case... */
 710         nfp_net_disable_queues(dev);
 711
 712         /* Enabling the required queues in the device */
 713         nfp_net_enable_queues(dev);
 714
 715         /* check and configure queue intr-vector mapping */
 716         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 717                 if (hw->pf_multiport_enabled) {
 718                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 719                                           "with NFP multiport PF");
 720                                 return -EINVAL;
 721                 }
 722                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 723                         /*
 724                          * Better not to share LSC with RX interrupts.
 725                          * Unregistering LSC interrupt handler
 726                          */
 727                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 728                                 nfp_net_dev_interrupt_handler, (void *)dev);
 729
 730                         if (dev->data->nb_rx_queues > 1) {
 731                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 732                                              "supports 1 queue with UIO");
 733                                 return -EIO;
 734                         }
 735                 }
 736                 intr_vector = dev->data->nb_rx_queues;
 737                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 738                         return -1;
 739
 740                 nfp_configure_rx_interrupt(dev, intr_handle);
 741                 update = NFP_NET_CFG_UPDATE_MSIX;
 742         }
 743
 744         rte_intr_enable(intr_handle);
 745
 746         new_ctrl = nfp_check_offloads(dev);
 747
 748         /* Writing configuration parameters in the device */
 749         nfp_net_params_setup(hw);
 750
 751         dev_conf = &dev->data->dev_conf;
 752         rxmode = &dev_conf->rxmode;
 753
 754         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 755                 nfp_net_rss_config_default(dev);
 756                 update |= NFP_NET_CFG_UPDATE_RSS;
 757                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 758         }
 759
 760         /* Enable device */
 761         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 762
 763         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 764
 765         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 766                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 767
 768         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 769         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 770                 return -EIO;
 771
 772         /*
 773          * Allocating rte mbufs for configured rx queues.
 774          * This requires queues being enabled before
 775          */
 776         if (nfp_net_rx_freelist_setup(dev) < 0) {
 777                 ret = -ENOMEM;
 778                 goto error;
 779         }
 780
 781         if (hw->is_pf) {
 782                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 783                         /* Configure the physical port up */
 784                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 785                 else
 786                         nfp_eth_set_configured(dev->process_private,
 787                                                hw->pf_port_idx, 1);
 788         }
 789
 790         hw->ctrl = new_ctrl;
 791
 792         return 0;
 793
 794 error:
 795         /*
 796          * An error returned by this function should mean the app
 797          * exiting and then the system releasing all the memory
 798          * allocated even memory coming from hugepages.
 799          *
 800          * The device could be enabled at this point with some queues
 801          * ready for getting packets. This is true if the call to
 802          * nfp_net_rx_freelist_setup() succeeds for some queues but
 803          * fails for subsequent queues.
 804          *
 805          * This should make the app exiting but better if we tell the
 806          * device first.
 807          */
 808         nfp_net_disable_queues(dev);
 809
 810         return ret;
 811 }
 812
 813 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 814 static void
 815 nfp_net_stop(struct rte_eth_dev *dev)
 816 {
 817         int i;
 818         struct nfp_net_hw *hw;
 819
 820         PMD_INIT_LOG(DEBUG, "Stop");
 821
 822         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 823
 824         nfp_net_disable_queues(dev);
 825
 826         /* Clear queues */
 827         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 828                 nfp_net_reset_tx_queue(
 829                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 830         }
 831
 832         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 833                 nfp_net_reset_rx_queue(
 834                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 835         }
 836
 837         if (hw->is_pf) {
 838                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 839                         /* Configure the physical port down */
 840                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 841                 else
 842                         nfp_eth_set_configured(dev->process_private,
 843                                                hw->pf_port_idx, 0);
 844         }
 845 }
 846
 847 /* Set the link up. */
 848 static int
 849 nfp_net_set_link_up(struct rte_eth_dev *dev)
 850 {
 851         struct nfp_net_hw *hw;
 852
 853         PMD_DRV_LOG(DEBUG, "Set link up");
 854
 855         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 856
 857         if (!hw->is_pf)
 858                 return -ENOTSUP;
 859
 860         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 861                 /* Configure the physical port down */
 862                 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 863         else
 864                 return nfp_eth_set_configured(dev->process_private,
 865                                               hw->pf_port_idx, 1);
 866 }
 867
 868 /* Set the link down. */
 869 static int
 870 nfp_net_set_link_down(struct rte_eth_dev *dev)
 871 {
 872         struct nfp_net_hw *hw;
 873
 874         PMD_DRV_LOG(DEBUG, "Set link down");
 875
 876         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 877
 878         if (!hw->is_pf)
 879                 return -ENOTSUP;
 880
 881         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 882                 /* Configure the physical port down */
 883                 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 884         else
 885                 return nfp_eth_set_configured(dev->process_private,
 886                                               hw->pf_port_idx, 0);
 887 }
 888
 889 /* Reset and stop device. The device can not be restarted. */
 890 static void
 891 nfp_net_close(struct rte_eth_dev *dev)
 892 {
 893         struct nfp_net_hw *hw;
 894         struct rte_pci_device *pci_dev;
 895         int i;
 896
 897         PMD_INIT_LOG(DEBUG, "Close");
 898
 899         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 900         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 901
 902         /*
 903          * We assume that the DPDK application is stopping all the
 904          * threads/queues before calling the device close function.
 905          */
 906
 907         nfp_net_disable_queues(dev);
 908
 909         /* Clear queues */
 910         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 911                 nfp_net_reset_tx_queue(
 912                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 913         }
 914
 915         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 916                 nfp_net_reset_rx_queue(
 917                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 918         }
 919
 920         rte_intr_disable(&pci_dev->intr_handle);
 921         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 922
 923         /* unregister callback func from eal lib */
 924         rte_intr_callback_unregister(&pci_dev->intr_handle,
 925                                      nfp_net_dev_interrupt_handler,
 926                                      (void *)dev);
 927
 928         /*
 929          * The ixgbe PMD driver disables the pcie master on the
 930          * device. The i40e does not...
 931          */
 932 }
 933
 934 static void
 935 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 936 {
 937         uint32_t new_ctrl, update = 0;
 938         struct nfp_net_hw *hw;
 939
 940         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 941
 942         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 943
 944         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 945                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 946                 return;
 947         }
 948
 949         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 950                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 951                 return;
 952         }
 953
 954         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 955         update = NFP_NET_CFG_UPDATE_GEN;
 956
 957         /*
 958          * DPDK sets promiscuous mode on just after this call assuming
 959          * it can not fail ...
 960          */
 961         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 962                 return;
 963
 964         hw->ctrl = new_ctrl;
 965 }
 966
 967 static void
 968 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 969 {
 970         uint32_t new_ctrl, update = 0;
 971         struct nfp_net_hw *hw;
 972
 973         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 974
 975         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 976                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 977                 return;
 978         }
 979
 980         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 981         update = NFP_NET_CFG_UPDATE_GEN;
 982
 983         /*
 984          * DPDK sets promiscuous mode off just before this call
 985          * assuming it can not fail ...
 986          */
 987         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 988                 return;
 989
 990         hw->ctrl = new_ctrl;
 991 }
 992
 993 /*
 994  * return 0 means link status changed, -1 means not changed
 995  *
 996  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 997  * status.
 998  */
 999 static int
1000 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1001 {
1002         struct nfp_net_hw *hw;
1003         struct rte_eth_link link;
1004         uint32_t nn_link_status;
1005         int ret;
1006
1007         static const uint32_t ls_to_ethtool[] = {
1008                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
1009                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
1010                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
1011                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
1012                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
1013                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
1014                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
1015                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
1016         };
1017
1018         PMD_DRV_LOG(DEBUG, "Link update");
1019
1020         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1021
1022         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1023
1024         memset(&link, 0, sizeof(struct rte_eth_link));
1025
1026         if (nn_link_status & NFP_NET_CFG_STS_LINK)
1027                 link.link_status = ETH_LINK_UP;
1028
1029         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1030
1031         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1032                          NFP_NET_CFG_STS_LINK_RATE_MASK;
1033
1034         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1035                 link.link_speed = ETH_SPEED_NUM_NONE;
1036         else
1037                 link.link_speed = ls_to_ethtool[nn_link_status];
1038
1039         ret = rte_eth_linkstatus_set(dev, &link);
1040         if (ret == 0) {
1041                 if (link.link_status)
1042                         PMD_DRV_LOG(INFO, "NIC Link is Up");
1043                 else
1044                         PMD_DRV_LOG(INFO, "NIC Link is Down");
1045         }
1046         return ret;
1047 }
1048
1049 static int
1050 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1051 {
1052         int i;
1053         struct nfp_net_hw *hw;
1054         struct rte_eth_stats nfp_dev_stats;
1055
1056         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1057
1058         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1059
1060         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1061
1062         /* reading per RX ring stats */
1063         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1064                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1065                         break;
1066
1067                 nfp_dev_stats.q_ipackets[i] =
1068                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1069
1070                 nfp_dev_stats.q_ipackets[i] -=
1071                         hw->eth_stats_base.q_ipackets[i];
1072
1073                 nfp_dev_stats.q_ibytes[i] =
1074                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1075
1076                 nfp_dev_stats.q_ibytes[i] -=
1077                         hw->eth_stats_base.q_ibytes[i];
1078         }
1079
1080         /* reading per TX ring stats */
1081         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1082                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1083                         break;
1084
1085                 nfp_dev_stats.q_opackets[i] =
1086                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1087
1088                 nfp_dev_stats.q_opackets[i] -=
1089                         hw->eth_stats_base.q_opackets[i];
1090
1091                 nfp_dev_stats.q_obytes[i] =
1092                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1093
1094                 nfp_dev_stats.q_obytes[i] -=
1095                         hw->eth_stats_base.q_obytes[i];
1096         }
1097
1098         nfp_dev_stats.ipackets =
1099                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1100
1101         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1102
1103         nfp_dev_stats.ibytes =
1104                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1105
1106         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1107
1108         nfp_dev_stats.opackets =
1109                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1110
1111         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1112
1113         nfp_dev_stats.obytes =
1114                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1115
1116         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1117
1118         /* reading general device stats */
1119         nfp_dev_stats.ierrors =
1120                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1121
1122         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1123
1124         nfp_dev_stats.oerrors =
1125                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1126
1127         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1128
1129         /* RX ring mbuf allocation failures */
1130         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1131
1132         nfp_dev_stats.imissed =
1133                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1134
1135         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1136
1137         if (stats) {
1138                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1139                 return 0;
1140         }
1141         return -EINVAL;
1142 }
1143
1144 static void
1145 nfp_net_stats_reset(struct rte_eth_dev *dev)
1146 {
1147         int i;
1148         struct nfp_net_hw *hw;
1149
1150         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1151
1152         /*
1153          * hw->eth_stats_base records the per counter starting point.
1154          * Lets update it now
1155          */
1156
1157         /* reading per RX ring stats */
1158         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1159                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1160                         break;
1161
1162                 hw->eth_stats_base.q_ipackets[i] =
1163                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1164
1165                 hw->eth_stats_base.q_ibytes[i] =
1166                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1167         }
1168
1169         /* reading per TX ring stats */
1170         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1171                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1172                         break;
1173
1174                 hw->eth_stats_base.q_opackets[i] =
1175                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1176
1177                 hw->eth_stats_base.q_obytes[i] =
1178                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1179         }
1180
1181         hw->eth_stats_base.ipackets =
1182                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1183
1184         hw->eth_stats_base.ibytes =
1185                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1186
1187         hw->eth_stats_base.opackets =
1188                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1189
1190         hw->eth_stats_base.obytes =
1191                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1192
1193         /* reading general device stats */
1194         hw->eth_stats_base.ierrors =
1195                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1196
1197         hw->eth_stats_base.oerrors =
1198                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1199
1200         /* RX ring mbuf allocation failures */
1201         dev->data->rx_mbuf_alloc_failed = 0;
1202
1203         hw->eth_stats_base.imissed =
1204                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1205 }
1206
1207 static int
1208 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1209 {
1210         struct nfp_net_hw *hw;
1211
1212         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1213
1214         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1215         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1216         dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1217         dev_info->max_rx_pktlen = hw->max_mtu;
1218         /* Next should change when PF support is implemented */
1219         dev_info->max_mac_addrs = 1;
1220
1221         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1222                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1223
1224         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1225                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1226                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1227                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1228
1229         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1230
1231         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1232                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1233
1234         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1235                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1236                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1237                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1238
1239         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1240                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1241
1242         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1243                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1244
1245         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1246                 .rx_thresh = {
1247                         .pthresh = DEFAULT_RX_PTHRESH,
1248                         .hthresh = DEFAULT_RX_HTHRESH,
1249                         .wthresh = DEFAULT_RX_WTHRESH,
1250                 },
1251                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1252                 .rx_drop_en = 0,
1253         };
1254
1255         dev_info->default_txconf = (struct rte_eth_txconf) {
1256                 .tx_thresh = {
1257                         .pthresh = DEFAULT_TX_PTHRESH,
1258                         .hthresh = DEFAULT_TX_HTHRESH,
1259                         .wthresh = DEFAULT_TX_WTHRESH,
1260                 },
1261                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1262                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1263         };
1264
1265         dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1266                                            ETH_RSS_NONFRAG_IPV4_TCP |
1267                                            ETH_RSS_NONFRAG_IPV4_UDP |
1268                                            ETH_RSS_IPV6 |
1269                                            ETH_RSS_NONFRAG_IPV6_TCP |
1270                                            ETH_RSS_NONFRAG_IPV6_UDP;
1271
1272         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1273         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1274
1275         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1276                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1277                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1278
1279         return 0;
1280 }
1281
1282 static const uint32_t *
1283 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1284 {
1285         static const uint32_t ptypes[] = {
1286                 /* refers to nfp_net_set_hash() */
1287                 RTE_PTYPE_INNER_L3_IPV4,
1288                 RTE_PTYPE_INNER_L3_IPV6,
1289                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1290                 RTE_PTYPE_INNER_L4_MASK,
1291                 RTE_PTYPE_UNKNOWN
1292         };
1293
1294         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1295                 return ptypes;
1296         return NULL;
1297 }
1298
1299 static uint32_t
1300 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1301 {
1302         struct nfp_net_rxq *rxq;
1303         struct nfp_net_rx_desc *rxds;
1304         uint32_t idx;
1305         uint32_t count;
1306
1307         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1308
1309         idx = rxq->rd_p;
1310
1311         count = 0;
1312
1313         /*
1314          * Other PMDs are just checking the DD bit in intervals of 4
1315          * descriptors and counting all four if the first has the DD
1316          * bit on. Of course, this is not accurate but can be good for
1317          * performance. But ideally that should be done in descriptors
1318          * chunks belonging to the same cache line
1319          */
1320
1321         while (count < rxq->rx_count) {
1322                 rxds = &rxq->rxds[idx];
1323                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1324                         break;
1325
1326                 count++;
1327                 idx++;
1328
1329                 /* Wrapping? */
1330                 if ((idx) == rxq->rx_count)
1331                         idx = 0;
1332         }
1333
1334         return count;
1335 }
1336
1337 static int
1338 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1339 {
1340         struct rte_pci_device *pci_dev;
1341         struct nfp_net_hw *hw;
1342         int base = 0;
1343
1344         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1345         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1346
1347         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1348                 base = 1;
1349
1350         /* Make sure all updates are written before un-masking */
1351         rte_wmb();
1352         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1353                       NFP_NET_CFG_ICR_UNMASKED);
1354         return 0;
1355 }
1356
1357 static int
1358 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1359 {
1360         struct rte_pci_device *pci_dev;
1361         struct nfp_net_hw *hw;
1362         int base = 0;
1363
1364         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1365         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1366
1367         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1368                 base = 1;
1369
1370         /* Make sure all updates are written before un-masking */
1371         rte_wmb();
1372         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1373         return 0;
1374 }
1375
1376 static void
1377 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1378 {
1379         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1380         struct rte_eth_link link;
1381
1382         rte_eth_linkstatus_get(dev, &link);
1383         if (link.link_status)
1384                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1385                             dev->data->port_id, link.link_speed,
1386                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1387                             ? "full-duplex" : "half-duplex");
1388         else
1389                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1390                             dev->data->port_id);
1391
1392         PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1393                 pci_dev->addr.domain, pci_dev->addr.bus,
1394                 pci_dev->addr.devid, pci_dev->addr.function);
1395 }
1396
1397 /* Interrupt configuration and handling */
1398
1399 /*
1400  * nfp_net_irq_unmask - Unmask an interrupt
1401  *
1402  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1403  * clear the ICR for the entry.
1404  */
1405 static void
1406 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1407 {
1408         struct nfp_net_hw *hw;
1409         struct rte_pci_device *pci_dev;
1410
1411         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1412         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1413
1414         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1415                 /* If MSI-X auto-masking is used, clear the entry */
1416                 rte_wmb();
1417                 rte_intr_ack(&pci_dev->intr_handle);
1418         } else {
1419                 /* Make sure all updates are written before un-masking */
1420                 rte_wmb();
1421                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1422                               NFP_NET_CFG_ICR_UNMASKED);
1423         }
1424 }
1425
1426 static void
1427 nfp_net_dev_interrupt_handler(void *param)
1428 {
1429         int64_t timeout;
1430         struct rte_eth_link link;
1431         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1432
1433         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1434
1435         rte_eth_linkstatus_get(dev, &link);
1436
1437         nfp_net_link_update(dev, 0);
1438
1439         /* likely to up */
1440         if (!link.link_status) {
1441                 /* handle it 1 sec later, wait it being stable */
1442                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1443                 /* likely to down */
1444         } else {
1445                 /* handle it 4 sec later, wait it being stable */
1446                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1447         }
1448
1449         if (rte_eal_alarm_set(timeout * 1000,
1450                               nfp_net_dev_interrupt_delayed_handler,
1451                               (void *)dev) < 0) {
1452                 PMD_INIT_LOG(ERR, "Error setting alarm");
1453                 /* Unmasking */
1454                 nfp_net_irq_unmask(dev);
1455         }
1456 }
1457
1458 /*
1459  * Interrupt handler which shall be registered for alarm callback for delayed
1460  * handling specific interrupt to wait for the stable nic state. As the NIC
1461  * interrupt state is not stable for nfp after link is just down, it needs
1462  * to wait 4 seconds to get the stable status.
1463  *
1464  * @param handle   Pointer to interrupt handle.
1465  * @param param    The address of parameter (struct rte_eth_dev *)
1466  *
1467  * @return  void
1468  */
1469 static void
1470 nfp_net_dev_interrupt_delayed_handler(void *param)
1471 {
1472         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1473
1474         nfp_net_link_update(dev, 0);
1475         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1476
1477         nfp_net_dev_link_status_print(dev);
1478
1479         /* Unmasking */
1480         nfp_net_irq_unmask(dev);
1481 }
1482
1483 static int
1484 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1485 {
1486         struct nfp_net_hw *hw;
1487
1488         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489
1490         /* check that mtu is within the allowed range */
1491         if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1492                 return -EINVAL;
1493
1494         /* mtu setting is forbidden if port is started */
1495         if (dev->data->dev_started) {
1496                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1497                             dev->data->port_id);
1498                 return -EBUSY;
1499         }
1500
1501         /* switch to jumbo mode if needed */
1502         if ((uint32_t)mtu > RTE_ETHER_MAX_LEN)
1503                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1504         else
1505                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1506
1507         /* update max frame size */
1508         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1509
1510         /* writing to configuration space */
1511         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1512
1513         hw->mtu = mtu;
1514
1515         return 0;
1516 }
1517
1518 static int
1519 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1520                        uint16_t queue_idx, uint16_t nb_desc,
1521                        unsigned int socket_id,
1522                        const struct rte_eth_rxconf *rx_conf,
1523                        struct rte_mempool *mp)
1524 {
1525         const struct rte_memzone *tz;
1526         struct nfp_net_rxq *rxq;
1527         struct nfp_net_hw *hw;
1528
1529         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1530
1531         PMD_INIT_FUNC_TRACE();
1532
1533         /* Validating number of descriptors */
1534         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1535             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1536             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1537                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1538                 return -EINVAL;
1539         }
1540
1541         /*
1542          * Free memory prior to re-allocation if needed. This is the case after
1543          * calling nfp_net_stop
1544          */
1545         if (dev->data->rx_queues[queue_idx]) {
1546                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1547                 dev->data->rx_queues[queue_idx] = NULL;
1548         }
1549
1550         /* Allocating rx queue data structure */
1551         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1552                                  RTE_CACHE_LINE_SIZE, socket_id);
1553         if (rxq == NULL)
1554                 return -ENOMEM;
1555
1556         /* Hw queues mapping based on firmware configuration */
1557         rxq->qidx = queue_idx;
1558         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1559         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1560         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1561         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1562
1563         /*
1564          * Tracking mbuf size for detecting a potential mbuf overflow due to
1565          * RX offset
1566          */
1567         rxq->mem_pool = mp;
1568         rxq->mbuf_size = rxq->mem_pool->elt_size;
1569         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1570         hw->flbufsz = rxq->mbuf_size;
1571
1572         rxq->rx_count = nb_desc;
1573         rxq->port_id = dev->data->port_id;
1574         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1575         rxq->drop_en = rx_conf->rx_drop_en;
1576
1577         /*
1578          * Allocate RX ring hardware descriptors. A memzone large enough to
1579          * handle the maximum ring size is allocated in order to allow for
1580          * resizing in later calls to the queue setup function.
1581          */
1582         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1583                                    sizeof(struct nfp_net_rx_desc) *
1584                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1585                                    socket_id);
1586
1587         if (tz == NULL) {
1588                 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1589                 nfp_net_rx_queue_release(rxq);
1590                 return -ENOMEM;
1591         }
1592
1593         /* Saving physical and virtual addresses for the RX ring */
1594         rxq->dma = (uint64_t)tz->iova;
1595         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1596
1597         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1598         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1599                                          sizeof(*rxq->rxbufs) * nb_desc,
1600                                          RTE_CACHE_LINE_SIZE, socket_id);
1601         if (rxq->rxbufs == NULL) {
1602                 nfp_net_rx_queue_release(rxq);
1603                 return -ENOMEM;
1604         }
1605
1606         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1607                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1608
1609         nfp_net_reset_rx_queue(rxq);
1610
1611         dev->data->rx_queues[queue_idx] = rxq;
1612         rxq->hw = hw;
1613
1614         /*
1615          * Telling the HW about the physical address of the RX ring and number
1616          * of descriptors in log2 format
1617          */
1618         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1619         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1620
1621         return 0;
1622 }
1623
1624 static int
1625 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1626 {
1627         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1628         uint64_t dma_addr;
1629         unsigned i;
1630
1631         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1632                    rxq->rx_count);
1633
1634         for (i = 0; i < rxq->rx_count; i++) {
1635                 struct nfp_net_rx_desc *rxd;
1636                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1637
1638                 if (mbuf == NULL) {
1639                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1640                                 (unsigned)rxq->qidx);
1641                         return -ENOMEM;
1642                 }
1643
1644                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1645
1646                 rxd = &rxq->rxds[i];
1647                 rxd->fld.dd = 0;
1648                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1649                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1650                 rxe[i].mbuf = mbuf;
1651                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1652         }
1653
1654         /* Make sure all writes are flushed before telling the hardware */
1655         rte_wmb();
1656
1657         /* Not advertising the whole ring as the firmware gets confused if so */
1658         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1659                    rxq->rx_count - 1);
1660
1661         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1662
1663         return 0;
1664 }
1665
1666 static int
1667 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1668                        uint16_t nb_desc, unsigned int socket_id,
1669                        const struct rte_eth_txconf *tx_conf)
1670 {
1671         const struct rte_memzone *tz;
1672         struct nfp_net_txq *txq;
1673         uint16_t tx_free_thresh;
1674         struct nfp_net_hw *hw;
1675
1676         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677
1678         PMD_INIT_FUNC_TRACE();
1679
1680         /* Validating number of descriptors */
1681         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1682             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1683             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1684                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1685                 return -EINVAL;
1686         }
1687
1688         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1689                                     tx_conf->tx_free_thresh :
1690                                     DEFAULT_TX_FREE_THRESH);
1691
1692         if (tx_free_thresh > (nb_desc)) {
1693                 PMD_DRV_LOG(ERR,
1694                         "tx_free_thresh must be less than the number of TX "
1695                         "descriptors. (tx_free_thresh=%u port=%d "
1696                         "queue=%d)", (unsigned int)tx_free_thresh,
1697                         dev->data->port_id, (int)queue_idx);
1698                 return -(EINVAL);
1699         }
1700
1701         /*
1702          * Free memory prior to re-allocation if needed. This is the case after
1703          * calling nfp_net_stop
1704          */
1705         if (dev->data->tx_queues[queue_idx]) {
1706                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1707                            queue_idx);
1708                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1709                 dev->data->tx_queues[queue_idx] = NULL;
1710         }
1711
1712         /* Allocating tx queue data structure */
1713         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1714                                  RTE_CACHE_LINE_SIZE, socket_id);
1715         if (txq == NULL) {
1716                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1717                 return -ENOMEM;
1718         }
1719
1720         /*
1721          * Allocate TX ring hardware descriptors. A memzone large enough to
1722          * handle the maximum ring size is allocated in order to allow for
1723          * resizing in later calls to the queue setup function.
1724          */
1725         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1726                                    sizeof(struct nfp_net_tx_desc) *
1727                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1728                                    socket_id);
1729         if (tz == NULL) {
1730                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1731                 nfp_net_tx_queue_release(txq);
1732                 return -ENOMEM;
1733         }
1734
1735         txq->tx_count = nb_desc;
1736         txq->tx_free_thresh = tx_free_thresh;
1737         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1738         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1739         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1740
1741         /* queue mapping based on firmware configuration */
1742         txq->qidx = queue_idx;
1743         txq->tx_qcidx = queue_idx * hw->stride_tx;
1744         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1745
1746         txq->port_id = dev->data->port_id;
1747
1748         /* Saving physical and virtual addresses for the TX ring */
1749         txq->dma = (uint64_t)tz->iova;
1750         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1751
1752         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1753         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1754                                          sizeof(*txq->txbufs) * nb_desc,
1755                                          RTE_CACHE_LINE_SIZE, socket_id);
1756         if (txq->txbufs == NULL) {
1757                 nfp_net_tx_queue_release(txq);
1758                 return -ENOMEM;
1759         }
1760         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1761                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1762
1763         nfp_net_reset_tx_queue(txq);
1764
1765         dev->data->tx_queues[queue_idx] = txq;
1766         txq->hw = hw;
1767
1768         /*
1769          * Telling the HW about the physical address of the TX ring and number
1770          * of descriptors in log2 format
1771          */
1772         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1773         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1774
1775         return 0;
1776 }
1777
1778 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1779 static inline void
1780 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1781                struct rte_mbuf *mb)
1782 {
1783         uint64_t ol_flags;
1784         struct nfp_net_hw *hw = txq->hw;
1785
1786         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1787                 goto clean_txd;
1788
1789         ol_flags = mb->ol_flags;
1790
1791         if (!(ol_flags & PKT_TX_TCP_SEG))
1792                 goto clean_txd;
1793
1794         txd->l3_offset = mb->l2_len;
1795         txd->l4_offset = mb->l2_len + mb->l3_len;
1796         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1797         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1798         txd->flags = PCIE_DESC_TX_LSO;
1799         return;
1800
1801 clean_txd:
1802         txd->flags = 0;
1803         txd->l3_offset = 0;
1804         txd->l4_offset = 0;
1805         txd->lso_hdrlen = 0;
1806         txd->mss = 0;
1807 }
1808
1809 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1810 static inline void
1811 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1812                  struct rte_mbuf *mb)
1813 {
1814         uint64_t ol_flags;
1815         struct nfp_net_hw *hw = txq->hw;
1816
1817         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1818                 return;
1819
1820         ol_flags = mb->ol_flags;
1821
1822         /* IPv6 does not need checksum */
1823         if (ol_flags & PKT_TX_IP_CKSUM)
1824                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1825
1826         switch (ol_flags & PKT_TX_L4_MASK) {
1827         case PKT_TX_UDP_CKSUM:
1828                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1829                 break;
1830         case PKT_TX_TCP_CKSUM:
1831                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1832                 break;
1833         }
1834
1835         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1836                 txd->flags |= PCIE_DESC_TX_CSUM;
1837 }
1838
1839 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1840 static inline void
1841 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1842                  struct rte_mbuf *mb)
1843 {
1844         struct nfp_net_hw *hw = rxq->hw;
1845
1846         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1847                 return;
1848
1849         /* If IPv4 and IP checksum error, fail */
1850         if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1851             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1852                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1853         else
1854                 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1855
1856         /* If neither UDP nor TCP return */
1857         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1858             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1859                 return;
1860
1861         if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1862                 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1863         else
1864                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1865 }
1866
1867 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1868 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1869
1870 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1871
1872 /*
1873  * nfp_net_set_hash - Set mbuf hash data
1874  *
1875  * The RSS hash and hash-type are pre-pended to the packet data.
1876  * Extract and decode it and set the mbuf fields.
1877  */
1878 static inline void
1879 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1880                  struct rte_mbuf *mbuf)
1881 {
1882         struct nfp_net_hw *hw = rxq->hw;
1883         uint8_t *meta_offset;
1884         uint32_t meta_info;
1885         uint32_t hash = 0;
1886         uint32_t hash_type = 0;
1887
1888         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1889                 return;
1890
1891         /* this is true for new firmwares */
1892         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1893             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1894              NFP_DESC_META_LEN(rxd))) {
1895                 /*
1896                  * new metadata api:
1897                  * <----  32 bit  ----->
1898                  * m    field type word
1899                  * e     data field #2
1900                  * t     data field #1
1901                  * a     data field #0
1902                  * ====================
1903                  *    packet data
1904                  *
1905                  * Field type word contains up to 8 4bit field types
1906                  * A 4bit field type refers to a data field word
1907                  * A data field word can have several 4bit field types
1908                  */
1909                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1910                 meta_offset -= NFP_DESC_META_LEN(rxd);
1911                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1912                 meta_offset += 4;
1913                 /* NFP PMD just supports metadata for hashing */
1914                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1915                 case NFP_NET_META_HASH:
1916                         /* next field type is about the hash type */
1917                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1918                         /* hash value is in the data field */
1919                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1920                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1921                         break;
1922                 default:
1923                         /* Unsupported metadata can be a performance issue */
1924                         return;
1925                 }
1926         } else {
1927                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1928                         return;
1929
1930                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1931                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1932         }
1933
1934         mbuf->hash.rss = hash;
1935         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1936
1937         switch (hash_type) {
1938         case NFP_NET_RSS_IPV4:
1939                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1940                 break;
1941         case NFP_NET_RSS_IPV6:
1942                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1943                 break;
1944         case NFP_NET_RSS_IPV6_EX:
1945                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1946                 break;
1947         case NFP_NET_RSS_IPV4_TCP:
1948                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1949                 break;
1950         case NFP_NET_RSS_IPV6_TCP:
1951                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1952                 break;
1953         case NFP_NET_RSS_IPV4_UDP:
1954                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1955                 break;
1956         case NFP_NET_RSS_IPV6_UDP:
1957                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1958                 break;
1959         default:
1960                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1961         }
1962 }
1963
1964 static inline void
1965 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1966 {
1967         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1968 }
1969
1970 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1971
1972 /*
1973  * RX path design:
1974  *
1975  * There are some decisions to take:
1976  * 1) How to check DD RX descriptors bit
1977  * 2) How and when to allocate new mbufs
1978  *
1979  * Current implementation checks just one single DD bit each loop. As each
1980  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1981  * a single cache line instead. Tests with this change have not shown any
1982  * performance improvement but it requires further investigation. For example,
1983  * depending on which descriptor is next, the number of descriptors could be
1984  * less than 8 for just checking those in the same cache line. This implies
1985  * extra work which could be counterproductive by itself. Indeed, last firmware
1986  * changes are just doing this: writing several descriptors with the DD bit
1987  * for saving PCIe bandwidth and DMA operations from the NFP.
1988  *
1989  * Mbuf allocation is done when a new packet is received. Then the descriptor
1990  * is automatically linked with the new mbuf and the old one is given to the
1991  * user. The main drawback with this design is mbuf allocation is heavier than
1992  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1993  * cache point of view it does not seem allocating the mbuf early on as we are
1994  * doing now have any benefit at all. Again, tests with this change have not
1995  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1996  * so looking at the implications of this type of allocation should be studied
1997  * deeply
1998  */
1999
2000 static uint16_t
2001 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2002 {
2003         struct nfp_net_rxq *rxq;
2004         struct nfp_net_rx_desc *rxds;
2005         struct nfp_net_rx_buff *rxb;
2006         struct nfp_net_hw *hw;
2007         struct rte_mbuf *mb;
2008         struct rte_mbuf *new_mb;
2009         uint16_t nb_hold;
2010         uint64_t dma_addr;
2011         int avail;
2012
2013         rxq = rx_queue;
2014         if (unlikely(rxq == NULL)) {
2015                 /*
2016                  * DPDK just checks the queue is lower than max queues
2017                  * enabled. But the queue needs to be configured
2018                  */
2019                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2020                 return -EINVAL;
2021         }
2022
2023         hw = rxq->hw;
2024         avail = 0;
2025         nb_hold = 0;
2026
2027         while (avail < nb_pkts) {
2028                 rxb = &rxq->rxbufs[rxq->rd_p];
2029                 if (unlikely(rxb == NULL)) {
2030                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2031                         break;
2032                 }
2033
2034                 rxds = &rxq->rxds[rxq->rd_p];
2035                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2036                         break;
2037
2038                 /*
2039                  * Memory barrier to ensure that we won't do other
2040                  * reads before the DD bit.
2041                  */
2042                 rte_rmb();
2043
2044                 /*
2045                  * We got a packet. Let's alloc a new mbuf for refilling the
2046                  * free descriptor ring as soon as possible
2047                  */
2048                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2049                 if (unlikely(new_mb == NULL)) {
2050                         RTE_LOG_DP(DEBUG, PMD,
2051                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2052                                 rxq->port_id, (unsigned int)rxq->qidx);
2053                         nfp_net_mbuf_alloc_failed(rxq);
2054                         break;
2055                 }
2056
2057                 nb_hold++;
2058
2059                 /*
2060                  * Grab the mbuf and refill the descriptor with the
2061                  * previously allocated mbuf
2062                  */
2063                 mb = rxb->mbuf;
2064                 rxb->mbuf = new_mb;
2065
2066                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2067                            rxds->rxd.data_len, rxq->mbuf_size);
2068
2069                 /* Size of this segment */
2070                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2071                 /* Size of the whole packet. We just support 1 segment */
2072                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2073
2074                 if (unlikely((mb->data_len + hw->rx_offset) >
2075                              rxq->mbuf_size)) {
2076                         /*
2077                          * This should not happen and the user has the
2078                          * responsibility of avoiding it. But we have
2079                          * to give some info about the error
2080                          */
2081                         RTE_LOG_DP(ERR, PMD,
2082                                 "mbuf overflow likely due to the RX offset.\n"
2083                                 "\t\tYour mbuf size should have extra space for"
2084                                 " RX offset=%u bytes.\n"
2085                                 "\t\tCurrently you just have %u bytes available"
2086                                 " but the received packet is %u bytes long",
2087                                 hw->rx_offset,
2088                                 rxq->mbuf_size - hw->rx_offset,
2089                                 mb->data_len);
2090                         return -EINVAL;
2091                 }
2092
2093                 /* Filling the received mbuf with packet info */
2094                 if (hw->rx_offset)
2095                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2096                 else
2097                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2098                                        NFP_DESC_META_LEN(rxds);
2099
2100                 /* No scatter mode supported */
2101                 mb->nb_segs = 1;
2102                 mb->next = NULL;
2103
2104                 mb->port = rxq->port_id;
2105
2106                 /* Checking the RSS flag */
2107                 nfp_net_set_hash(rxq, rxds, mb);
2108
2109                 /* Checking the checksum flag */
2110                 nfp_net_rx_cksum(rxq, rxds, mb);
2111
2112                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2113                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2114                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2115                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2116                 }
2117
2118                 /* Adding the mbuf to the mbuf array passed by the app */
2119                 rx_pkts[avail++] = mb;
2120
2121                 /* Now resetting and updating the descriptor */
2122                 rxds->vals[0] = 0;
2123                 rxds->vals[1] = 0;
2124                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2125                 rxds->fld.dd = 0;
2126                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2127                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2128
2129                 rxq->rd_p++;
2130                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2131                         rxq->rd_p = 0;
2132         }
2133
2134         if (nb_hold == 0)
2135                 return nb_hold;
2136
2137         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2138                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2139
2140         nb_hold += rxq->nb_rx_hold;
2141
2142         /*
2143          * FL descriptors needs to be written before incrementing the
2144          * FL queue WR pointer
2145          */
2146         rte_wmb();
2147         if (nb_hold > rxq->rx_free_thresh) {
2148                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2149                            rxq->port_id, (unsigned int)rxq->qidx,
2150                            (unsigned)nb_hold, (unsigned)avail);
2151                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2152                 nb_hold = 0;
2153         }
2154         rxq->nb_rx_hold = nb_hold;
2155
2156         return avail;
2157 }
2158
2159 /*
2160  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2161  * status
2162  * @txq: TX queue to work with
2163  * Returns number of descriptors freed
2164  */
2165 int
2166 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2167 {
2168         uint32_t qcp_rd_p;
2169         int todo;
2170
2171         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2172                    " status", txq->qidx);
2173
2174         /* Work out how many packets have been sent */
2175         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2176
2177         if (qcp_rd_p == txq->rd_p) {
2178                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2179                            "packets (%u, %u)", txq->qidx,
2180                            qcp_rd_p, txq->rd_p);
2181                 return 0;
2182         }
2183
2184         if (qcp_rd_p > txq->rd_p)
2185                 todo = qcp_rd_p - txq->rd_p;
2186         else
2187                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2188
2189         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2190                    qcp_rd_p, txq->rd_p, txq->rd_p);
2191
2192         if (todo == 0)
2193                 return todo;
2194
2195         txq->rd_p += todo;
2196         if (unlikely(txq->rd_p >= txq->tx_count))
2197                 txq->rd_p -= txq->tx_count;
2198
2199         return todo;
2200 }
2201
2202 /* Leaving always free descriptors for avoiding wrapping confusion */
2203 static inline
2204 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2205 {
2206         if (txq->wr_p >= txq->rd_p)
2207                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2208         else
2209                 return txq->rd_p - txq->wr_p - 8;
2210 }
2211
2212 /*
2213  * nfp_net_txq_full - Check if the TX queue free descriptors
2214  * is below tx_free_threshold
2215  *
2216  * @txq: TX queue to check
2217  *
2218  * This function uses the host copy* of read/write pointers
2219  */
2220 static inline
2221 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2222 {
2223         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2224 }
2225
2226 static uint16_t
2227 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2228 {
2229         struct nfp_net_txq *txq;
2230         struct nfp_net_hw *hw;
2231         struct nfp_net_tx_desc *txds, txd;
2232         struct rte_mbuf *pkt;
2233         uint64_t dma_addr;
2234         int pkt_size, dma_size;
2235         uint16_t free_descs, issued_descs;
2236         struct rte_mbuf **lmbuf;
2237         int i;
2238
2239         txq = tx_queue;
2240         hw = txq->hw;
2241         txds = &txq->txds[txq->wr_p];
2242
2243         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2244                    txq->qidx, txq->wr_p, nb_pkts);
2245
2246         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2247                 nfp_net_tx_free_bufs(txq);
2248
2249         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2250         if (unlikely(free_descs == 0))
2251                 return 0;
2252
2253         pkt = *tx_pkts;
2254
2255         i = 0;
2256         issued_descs = 0;
2257         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2258                    txq->qidx, nb_pkts);
2259         /* Sending packets */
2260         while ((i < nb_pkts) && free_descs) {
2261                 /* Grabbing the mbuf linked to the current descriptor */
2262                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2263                 /* Warming the cache for releasing the mbuf later on */
2264                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2265
2266                 pkt = *(tx_pkts + i);
2267
2268                 if (unlikely((pkt->nb_segs > 1) &&
2269                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2270                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2271                         rte_panic("Multisegment packet unsupported\n");
2272                 }
2273
2274                 /* Checking if we have enough descriptors */
2275                 if (unlikely(pkt->nb_segs > free_descs))
2276                         goto xmit_end;
2277
2278                 /*
2279                  * Checksum and VLAN flags just in the first descriptor for a
2280                  * multisegment packet, but TSO info needs to be in all of them.
2281                  */
2282                 txd.data_len = pkt->pkt_len;
2283                 nfp_net_tx_tso(txq, &txd, pkt);
2284                 nfp_net_tx_cksum(txq, &txd, pkt);
2285
2286                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2287                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2288                         txd.flags |= PCIE_DESC_TX_VLAN;
2289                         txd.vlan = pkt->vlan_tci;
2290                 }
2291
2292                 /*
2293                  * mbuf data_len is the data in one segment and pkt_len data
2294                  * in the whole packet. When the packet is just one segment,
2295                  * then data_len = pkt_len
2296                  */
2297                 pkt_size = pkt->pkt_len;
2298
2299                 while (pkt) {
2300                         /* Copying TSO, VLAN and cksum info */
2301                         *txds = txd;
2302
2303                         /* Releasing mbuf used by this descriptor previously*/
2304                         if (*lmbuf)
2305                                 rte_pktmbuf_free_seg(*lmbuf);
2306
2307                         /*
2308                          * Linking mbuf with descriptor for being released
2309                          * next time descriptor is used
2310                          */
2311                         *lmbuf = pkt;
2312
2313                         dma_size = pkt->data_len;
2314                         dma_addr = rte_mbuf_data_iova(pkt);
2315                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2316                                    "%" PRIx64 "", dma_addr);
2317
2318                         /* Filling descriptors fields */
2319                         txds->dma_len = dma_size;
2320                         txds->data_len = txd.data_len;
2321                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2322                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2323                         ASSERT(free_descs > 0);
2324                         free_descs--;
2325
2326                         txq->wr_p++;
2327                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2328                                 txq->wr_p = 0;
2329
2330                         pkt_size -= dma_size;
2331
2332                         /*
2333                          * Making the EOP, packets with just one segment
2334                          * the priority
2335                          */
2336                         if (likely(!pkt_size))
2337                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2338                         else
2339                                 txds->offset_eop = 0;
2340
2341                         pkt = pkt->next;
2342                         /* Referencing next free TX descriptor */
2343                         txds = &txq->txds[txq->wr_p];
2344                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2345                         issued_descs++;
2346                 }
2347                 i++;
2348         }
2349
2350 xmit_end:
2351         /* Increment write pointers. Force memory write before we let HW know */
2352         rte_wmb();
2353         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2354
2355         return i;
2356 }
2357
2358 static int
2359 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2360 {
2361         uint32_t new_ctrl, update;
2362         struct nfp_net_hw *hw;
2363         int ret;
2364
2365         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366         new_ctrl = 0;
2367
2368         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2369             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2370                 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2371                         " ETH_VLAN_EXTEND_OFFLOAD");
2372
2373         /* Enable vlan strip if it is not configured yet */
2374         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2375             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2376                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2377
2378         /* Disable vlan strip just if it is configured */
2379         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2380             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2381                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2382
2383         if (new_ctrl == 0)
2384                 return 0;
2385
2386         update = NFP_NET_CFG_UPDATE_GEN;
2387
2388         ret = nfp_net_reconfig(hw, new_ctrl, update);
2389         if (!ret)
2390                 hw->ctrl = new_ctrl;
2391
2392         return ret;
2393 }
2394
2395 static int
2396 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2397                     struct rte_eth_rss_reta_entry64 *reta_conf,
2398                     uint16_t reta_size)
2399 {
2400         uint32_t reta, mask;
2401         int i, j;
2402         int idx, shift;
2403         struct nfp_net_hw *hw =
2404                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405
2406         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2407                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2408                         "(%d) doesn't match the number hardware can supported "
2409                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2410                 return -EINVAL;
2411         }
2412
2413         /*
2414          * Update Redirection Table. There are 128 8bit-entries which can be
2415          * manage as 32 32bit-entries
2416          */
2417         for (i = 0; i < reta_size; i += 4) {
2418                 /* Handling 4 RSS entries per loop */
2419                 idx = i / RTE_RETA_GROUP_SIZE;
2420                 shift = i % RTE_RETA_GROUP_SIZE;
2421                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2422
2423                 if (!mask)
2424                         continue;
2425
2426                 reta = 0;
2427                 /* If all 4 entries were set, don't need read RETA register */
2428                 if (mask != 0xF)
2429                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2430
2431                 for (j = 0; j < 4; j++) {
2432                         if (!(mask & (0x1 << j)))
2433                                 continue;
2434                         if (mask != 0xF)
2435                                 /* Clearing the entry bits */
2436                                 reta &= ~(0xFF << (8 * j));
2437                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2438                 }
2439                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2440                               reta);
2441         }
2442         return 0;
2443 }
2444
2445 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2446 static int
2447 nfp_net_reta_update(struct rte_eth_dev *dev,
2448                     struct rte_eth_rss_reta_entry64 *reta_conf,
2449                     uint16_t reta_size)
2450 {
2451         struct nfp_net_hw *hw =
2452                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2453         uint32_t update;
2454         int ret;
2455
2456         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2457                 return -EINVAL;
2458
2459         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2460         if (ret != 0)
2461                 return ret;
2462
2463         update = NFP_NET_CFG_UPDATE_RSS;
2464
2465         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2466                 return -EIO;
2467
2468         return 0;
2469 }
2470
2471  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2472 static int
2473 nfp_net_reta_query(struct rte_eth_dev *dev,
2474                    struct rte_eth_rss_reta_entry64 *reta_conf,
2475                    uint16_t reta_size)
2476 {
2477         uint8_t i, j, mask;
2478         int idx, shift;
2479         uint32_t reta;
2480         struct nfp_net_hw *hw;
2481
2482         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2483
2484         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2485                 return -EINVAL;
2486
2487         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2488                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2489                         "(%d) doesn't match the number hardware can supported "
2490                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2491                 return -EINVAL;
2492         }
2493
2494         /*
2495          * Reading Redirection Table. There are 128 8bit-entries which can be
2496          * manage as 32 32bit-entries
2497          */
2498         for (i = 0; i < reta_size; i += 4) {
2499                 /* Handling 4 RSS entries per loop */
2500                 idx = i / RTE_RETA_GROUP_SIZE;
2501                 shift = i % RTE_RETA_GROUP_SIZE;
2502                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2503
2504                 if (!mask)
2505                         continue;
2506
2507                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2508                                     shift);
2509                 for (j = 0; j < 4; j++) {
2510                         if (!(mask & (0x1 << j)))
2511                                 continue;
2512                         reta_conf[idx].reta[shift + j] =
2513                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2514                 }
2515         }
2516         return 0;
2517 }
2518
2519 static int
2520 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2521                         struct rte_eth_rss_conf *rss_conf)
2522 {
2523         struct nfp_net_hw *hw;
2524         uint64_t rss_hf;
2525         uint32_t cfg_rss_ctrl = 0;
2526         uint8_t key;
2527         int i;
2528
2529         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2530
2531         /* Writing the key byte a byte */
2532         for (i = 0; i < rss_conf->rss_key_len; i++) {
2533                 memcpy(&key, &rss_conf->rss_key[i], 1);
2534                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2535         }
2536
2537         rss_hf = rss_conf->rss_hf;
2538
2539         if (rss_hf & ETH_RSS_IPV4)
2540                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2541
2542         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2543                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2544
2545         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2546                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2547
2548         if (rss_hf & ETH_RSS_IPV6)
2549                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2550
2551         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2552                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2553
2554         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2555                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2556
2557         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2558         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2559
2560         /* configuring where to apply the RSS hash */
2561         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2562
2563         /* Writing the key size */
2564         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2565
2566         return 0;
2567 }
2568
2569 static int
2570 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2571                         struct rte_eth_rss_conf *rss_conf)
2572 {
2573         uint32_t update;
2574         uint64_t rss_hf;
2575         struct nfp_net_hw *hw;
2576
2577         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578
2579         rss_hf = rss_conf->rss_hf;
2580
2581         /* Checking if RSS is enabled */
2582         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2583                 if (rss_hf != 0) { /* Enable RSS? */
2584                         PMD_DRV_LOG(ERR, "RSS unsupported");
2585                         return -EINVAL;
2586                 }
2587                 return 0; /* Nothing to do */
2588         }
2589
2590         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2591                 PMD_DRV_LOG(ERR, "hash key too long");
2592                 return -EINVAL;
2593         }
2594
2595         nfp_net_rss_hash_write(dev, rss_conf);
2596
2597         update = NFP_NET_CFG_UPDATE_RSS;
2598
2599         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2600                 return -EIO;
2601
2602         return 0;
2603 }
2604
2605 static int
2606 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2607                           struct rte_eth_rss_conf *rss_conf)
2608 {
2609         uint64_t rss_hf;
2610         uint32_t cfg_rss_ctrl;
2611         uint8_t key;
2612         int i;
2613         struct nfp_net_hw *hw;
2614
2615         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616
2617         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2618                 return -EINVAL;
2619
2620         rss_hf = rss_conf->rss_hf;
2621         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2622
2623         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2624                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2625
2626         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2627                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2628
2629         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2630                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2631
2632         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2633                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2634
2635         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2636                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2637
2638         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2639                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2640
2641         /* Reading the key size */
2642         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2643
2644         /* Reading the key byte a byte */
2645         for (i = 0; i < rss_conf->rss_key_len; i++) {
2646                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2647                 memcpy(&rss_conf->rss_key[i], &key, 1);
2648         }
2649
2650         return 0;
2651 }
2652
2653 static int
2654 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2655 {
2656         struct rte_eth_conf *dev_conf;
2657         struct rte_eth_rss_conf rss_conf;
2658         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2659         uint16_t rx_queues = dev->data->nb_rx_queues;
2660         uint16_t queue;
2661         int i, j, ret;
2662
2663         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2664                 rx_queues);
2665
2666         nfp_reta_conf[0].mask = ~0x0;
2667         nfp_reta_conf[1].mask = ~0x0;
2668
2669         queue = 0;
2670         for (i = 0; i < 0x40; i += 8) {
2671                 for (j = i; j < (i + 8); j++) {
2672                         nfp_reta_conf[0].reta[j] = queue;
2673                         nfp_reta_conf[1].reta[j] = queue++;
2674                         queue %= rx_queues;
2675                 }
2676         }
2677         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2678         if (ret != 0)
2679                 return ret;
2680
2681         dev_conf = &dev->data->dev_conf;
2682         if (!dev_conf) {
2683                 PMD_DRV_LOG(INFO, "wrong rss conf");
2684                 return -EINVAL;
2685         }
2686         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2687
2688         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2689
2690         return ret;
2691 }
2692
2693
2694 /* Initialise and register driver with DPDK Application */
2695 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2696         .dev_configure          = nfp_net_configure,
2697         .dev_start              = nfp_net_start,
2698         .dev_stop               = nfp_net_stop,
2699         .dev_set_link_up        = nfp_net_set_link_up,
2700         .dev_set_link_down      = nfp_net_set_link_down,
2701         .dev_close              = nfp_net_close,
2702         .promiscuous_enable     = nfp_net_promisc_enable,
2703         .promiscuous_disable    = nfp_net_promisc_disable,
2704         .link_update            = nfp_net_link_update,
2705         .stats_get              = nfp_net_stats_get,
2706         .stats_reset            = nfp_net_stats_reset,
2707         .dev_infos_get          = nfp_net_infos_get,
2708         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2709         .mtu_set                = nfp_net_dev_mtu_set,
2710         .mac_addr_set           = nfp_set_mac_addr,
2711         .vlan_offload_set       = nfp_net_vlan_offload_set,
2712         .reta_update            = nfp_net_reta_update,
2713         .reta_query             = nfp_net_reta_query,
2714         .rss_hash_update        = nfp_net_rss_hash_update,
2715         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2716         .rx_queue_setup         = nfp_net_rx_queue_setup,
2717         .rx_queue_release       = nfp_net_rx_queue_release,
2718         .rx_queue_count         = nfp_net_rx_queue_count,
2719         .tx_queue_setup         = nfp_net_tx_queue_setup,
2720         .tx_queue_release       = nfp_net_tx_queue_release,
2721         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2722         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2723 };
2724
2725 /*
2726  * All eth_dev created got its private data, but before nfp_net_init, that
2727  * private data is referencing private data for all the PF ports. This is due
2728  * to how the vNIC bars are mapped based on first port, so all ports need info
2729  * about port 0 private data. Inside nfp_net_init the private data pointer is
2730  * changed to the right address for each port once the bars have been mapped.
2731  *
2732  * This functions helps to find out which port and therefore which offset
2733  * inside the private data array to use.
2734  */
2735 static int
2736 get_pf_port_number(char *name)
2737 {
2738         char *pf_str = name;
2739         int size = 0;
2740
2741         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2742                 pf_str++;
2743
2744         if (size == 30)
2745                 /*
2746                  * This should not happen at all and it would mean major
2747                  * implementation fault.
2748                  */
2749                 rte_panic("nfp_net: problem with pf device name\n");
2750
2751         /* Expecting _portX with X within [0,7] */
2752         pf_str += 5;
2753
2754         return (int)strtol(pf_str, NULL, 10);
2755 }
2756
2757 static int
2758 nfp_net_init(struct rte_eth_dev *eth_dev)
2759 {
2760         struct rte_pci_device *pci_dev;
2761         struct nfp_net_hw *hw, *hwport0;
2762
2763         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2764         uint32_t start_q;
2765         int stride = 4;
2766         int port = 0;
2767         int err;
2768
2769         PMD_INIT_FUNC_TRACE();
2770
2771         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2772
2773         /* NFP can not handle DMA addresses requiring more than 40 bits */
2774         if (rte_mem_check_dma_mask(40)) {
2775                 RTE_LOG(ERR, PMD, "device %s can not be used:",
2776                                    pci_dev->device.name);
2777                 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2778                 return -ENODEV;
2779         };
2780
2781         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2782             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2783                 port = get_pf_port_number(eth_dev->data->name);
2784                 if (port < 0 || port > 7) {
2785                         PMD_DRV_LOG(ERR, "Port value is wrong");
2786                         return -ENODEV;
2787                 }
2788
2789                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2790
2791                 /* This points to port 0 private data */
2792                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2793
2794                 /* This points to the specific port private data */
2795                 hw = &hwport0[port];
2796         } else {
2797                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2798                 hwport0 = 0;
2799         }
2800
2801         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2802         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2803         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2804
2805         /* For secondary processes, the primary has done all the work */
2806         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2807                 return 0;
2808
2809         rte_eth_copy_pci_info(eth_dev, pci_dev);
2810
2811         hw->device_id = pci_dev->id.device_id;
2812         hw->vendor_id = pci_dev->id.vendor_id;
2813         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2814         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2815
2816         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2817                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2818                      pci_dev->addr.domain, pci_dev->addr.bus,
2819                      pci_dev->addr.devid, pci_dev->addr.function);
2820
2821         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2822         if (hw->ctrl_bar == NULL) {
2823                 PMD_DRV_LOG(ERR,
2824                         "hw->ctrl_bar is NULL. BAR0 not configured");
2825                 return -ENODEV;
2826         }
2827
2828         if (hw->is_pf && port == 0) {
2829                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2830                                              hw->total_ports * 32768,
2831                                              &hw->ctrl_area);
2832                 if (!hw->ctrl_bar) {
2833                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2834                         return -EIO;
2835                 }
2836
2837                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2838         }
2839
2840         if (port > 0) {
2841                 if (!hwport0->ctrl_bar)
2842                         return -ENODEV;
2843
2844                 /* address based on port0 offset */
2845                 hw->ctrl_bar = hwport0->ctrl_bar +
2846                                (port * NFP_PF_CSR_SLICE_SIZE);
2847         }
2848
2849         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2850
2851         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2852         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2853
2854         /* Work out where in the BAR the queues start. */
2855         switch (pci_dev->id.device_id) {
2856         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2857         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2858         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2859                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2860                 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2861                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2862                 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2863                 break;
2864         default:
2865                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2866                 err = -ENODEV;
2867                 goto dev_err_ctrl_map;
2868         }
2869
2870         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2871         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2872
2873         if (hw->is_pf && port == 0) {
2874                 /* configure access to tx/rx vNIC BARs */
2875                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2876                                                       NFP_PCIE_QUEUE(0),
2877                                                       NFP_QCP_QUEUE_AREA_SZ,
2878                                                       &hw->hwqueues_area);
2879
2880                 if (!hwport0->hw_queues) {
2881                         printf("nfp_rtsym_map fails for net.qc");
2882                         err = -EIO;
2883                         goto dev_err_ctrl_map;
2884                 }
2885
2886                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2887                                     hwport0->hw_queues);
2888         }
2889
2890         if (hw->is_pf) {
2891                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2892                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2893                 eth_dev->data->dev_private = hw;
2894         } else {
2895                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2896                              tx_bar_off;
2897                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2898                              rx_bar_off;
2899         }
2900
2901         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2902                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2903
2904         nfp_net_cfg_queue_setup(hw);
2905
2906         /* Get some of the read-only fields from the config BAR */
2907         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2908         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2909         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2910         hw->mtu = RTE_ETHER_MTU;
2911
2912         /* VLAN insertion is incompatible with LSOv2 */
2913         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2914                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2915
2916         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2917                 hw->rx_offset = NFP_NET_RX_OFFSET;
2918         else
2919                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2920
2921         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2922                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2923                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2924
2925         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2926                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2927                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2928                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2929                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2930                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2931                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2932                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2933                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2934                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2935                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2936                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2937                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2938                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2939                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2940
2941         hw->ctrl = 0;
2942
2943         hw->stride_rx = stride;
2944         hw->stride_tx = stride;
2945
2946         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2947                      hw->max_rx_queues, hw->max_tx_queues);
2948
2949         /* Initializing spinlock for reconfigs */
2950         rte_spinlock_init(&hw->reconfig_lock);
2951
2952         /* Allocating memory for mac addr */
2953         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2954                                                RTE_ETHER_ADDR_LEN, 0);
2955         if (eth_dev->data->mac_addrs == NULL) {
2956                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2957                 err = -ENOMEM;
2958                 goto dev_err_queues_map;
2959         }
2960
2961         if (hw->is_pf) {
2962                 nfp_net_pf_read_mac(hwport0, port);
2963                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2964         } else {
2965                 nfp_net_vf_read_mac(hw);
2966         }
2967
2968         if (!rte_is_valid_assigned_ether_addr(
2969                     (struct rte_ether_addr *)&hw->mac_addr)) {
2970                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2971                                    port);
2972                 /* Using random mac addresses for VFs */
2973                 rte_eth_random_addr(&hw->mac_addr[0]);
2974                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2975         }
2976
2977         /* Copying mac address to DPDK eth_dev struct */
2978         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2979                         &eth_dev->data->mac_addrs[0]);
2980
2981         if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2982                 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2983
2984         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2985                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2986                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2987                      pci_dev->id.device_id,
2988                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2989                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2990
2991         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2992                 /* Registering LSC interrupt handler */
2993                 rte_intr_callback_register(&pci_dev->intr_handle,
2994                                            nfp_net_dev_interrupt_handler,
2995                                            (void *)eth_dev);
2996                 /* Telling the firmware about the LSC interrupt entry */
2997                 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2998                 /* Recording current stats counters values */
2999                 nfp_net_stats_reset(eth_dev);
3000         }
3001
3002         return 0;
3003
3004 dev_err_queues_map:
3005                 nfp_cpp_area_free(hw->hwqueues_area);
3006 dev_err_ctrl_map:
3007                 nfp_cpp_area_free(hw->ctrl_area);
3008
3009         return err;
3010 }
3011
3012 #define NFP_CPP_MEMIO_BOUNDARY          (1 << 20)
3013
3014 /*
3015  * Serving a write request to NFP from host programs. The request
3016  * sends the write size and the CPP target. The bridge makes use
3017  * of CPP interface handler configured by the PMD setup.
3018  */
3019 static int
3020 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3021 {
3022         struct nfp_cpp_area *area;
3023         off_t offset, nfp_offset;
3024         uint32_t cpp_id, pos, len;
3025         uint32_t tmpbuf[16];
3026         size_t count, curlen, totlen = 0;
3027         int err = 0;
3028
3029         PMD_CPP_LOG(DEBUG, "%s: offset size %lu, count_size: %lu\n", __func__,
3030                 sizeof(off_t), sizeof(size_t));
3031
3032         /* Reading the count param */
3033         err = recv(sockfd, &count, sizeof(off_t), 0);
3034         if (err != sizeof(off_t))
3035                 return -EINVAL;
3036
3037         curlen = count;
3038
3039         /* Reading the offset param */
3040         err = recv(sockfd, &offset, sizeof(off_t), 0);
3041         if (err != sizeof(off_t))
3042                 return -EINVAL;
3043
3044         /* Obtain target's CPP ID and offset in target */
3045         cpp_id = (offset >> 40) << 8;
3046         nfp_offset = offset & ((1ull << 40) - 1);
3047
3048         PMD_CPP_LOG(DEBUG, "%s: count %lu and offset %ld\n", __func__, count,
3049                 offset);
3050         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %ld\n", __func__,
3051                 cpp_id, nfp_offset);
3052
3053         /* Adjust length if not aligned */
3054         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3055             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3056                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3057                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3058         }
3059
3060         while (count > 0) {
3061                 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3062                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3063                                                     nfp_offset, curlen);
3064                 if (!area) {
3065                         RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3066                         return -EIO;
3067                 }
3068
3069                 /* mapping the target */
3070                 err = nfp_cpp_area_acquire(area);
3071                 if (err < 0) {
3072                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3073                         nfp_cpp_area_free(area);
3074                         return -EIO;
3075                 }
3076
3077                 for (pos = 0; pos < curlen; pos += len) {
3078                         len = curlen - pos;
3079                         if (len > sizeof(tmpbuf))
3080                                 len = sizeof(tmpbuf);
3081
3082                         PMD_CPP_LOG(DEBUG, "%s: Receive %u of %lu\n", __func__,
3083                                            len, count);
3084                         err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3085                         if (err != (int)len) {
3086                                 RTE_LOG(ERR, PMD,
3087                                         "%s: error when receiving, %d of %lu\n",
3088                                         __func__, err, count);
3089                                 nfp_cpp_area_release(area);
3090                                 nfp_cpp_area_free(area);
3091                                 return -EIO;
3092                         }
3093                         err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3094                         if (err < 0) {
3095                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3096                                 nfp_cpp_area_release(area);
3097                                 nfp_cpp_area_free(area);
3098                                 return -EIO;
3099                         }
3100                 }
3101
3102                 nfp_offset += pos;
3103                 totlen += pos;
3104                 nfp_cpp_area_release(area);
3105                 nfp_cpp_area_free(area);
3106
3107                 count -= pos;
3108                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3109                          NFP_CPP_MEMIO_BOUNDARY : count;
3110         }
3111
3112         return 0;
3113 }
3114
3115 /*
3116  * Serving a read request to NFP from host programs. The request
3117  * sends the read size and the CPP target. The bridge makes use
3118  * of CPP interface handler configured by the PMD setup. The read
3119  * data is sent to the requester using the same socket.
3120  */
3121 static int
3122 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3123 {
3124         struct nfp_cpp_area *area;
3125         off_t offset, nfp_offset;
3126         uint32_t cpp_id, pos, len;
3127         uint32_t tmpbuf[16];
3128         size_t count, curlen, totlen = 0;
3129         int err = 0;
3130
3131         PMD_CPP_LOG(DEBUG, "%s: offset size %lu, count_size: %lu\n", __func__,
3132                 sizeof(off_t), sizeof(size_t));
3133
3134         /* Reading the count param */
3135         err = recv(sockfd, &count, sizeof(off_t), 0);
3136         if (err != sizeof(off_t))
3137                 return -EINVAL;
3138
3139         curlen = count;
3140
3141         /* Reading the offset param */
3142         err = recv(sockfd, &offset, sizeof(off_t), 0);
3143         if (err != sizeof(off_t))
3144                 return -EINVAL;
3145
3146         /* Obtain target's CPP ID and offset in target */
3147         cpp_id = (offset >> 40) << 8;
3148         nfp_offset = offset & ((1ull << 40) - 1);
3149
3150         PMD_CPP_LOG(DEBUG, "%s: count %lu and offset %ld\n", __func__, count,
3151                            offset);
3152         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %ld\n", __func__,
3153                            cpp_id, nfp_offset);
3154
3155         /* Adjust length if not aligned */
3156         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3157             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3158                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3159                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3160         }
3161
3162         while (count > 0) {
3163                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3164                                                     nfp_offset, curlen);
3165                 if (!area) {
3166                         RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3167                         return -EIO;
3168                 }
3169
3170                 err = nfp_cpp_area_acquire(area);
3171                 if (err < 0) {
3172                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3173                         nfp_cpp_area_free(area);
3174                         return -EIO;
3175                 }
3176
3177                 for (pos = 0; pos < curlen; pos += len) {
3178                         len = curlen - pos;
3179                         if (len > sizeof(tmpbuf))
3180                                 len = sizeof(tmpbuf);
3181
3182                         err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3183                         if (err < 0) {
3184                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3185                                 nfp_cpp_area_release(area);
3186                                 nfp_cpp_area_free(area);
3187                                 return -EIO;
3188                         }
3189                         PMD_CPP_LOG(DEBUG, "%s: sending %u of %lu\n", __func__,
3190                                            len, count);
3191
3192                         err = send(sockfd, tmpbuf, len, 0);
3193                         if (err != (int)len) {
3194                                 RTE_LOG(ERR, PMD,
3195                                         "%s: error when sending: %d of %lu\n",
3196                                         __func__, err, count);
3197                                 nfp_cpp_area_release(area);
3198                                 nfp_cpp_area_free(area);
3199                                 return -EIO;
3200                         }
3201                 }
3202
3203                 nfp_offset += pos;
3204                 totlen += pos;
3205                 nfp_cpp_area_release(area);
3206                 nfp_cpp_area_free(area);
3207
3208                 count -= pos;
3209                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3210                         NFP_CPP_MEMIO_BOUNDARY : count;
3211         }
3212         return 0;
3213 }
3214
3215 #define NFP_IOCTL 'n'
3216 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3217 /*
3218  * Serving a ioctl command from host NFP tools. This usually goes to
3219  * a kernel driver char driver but it is not available when the PF is
3220  * bound to the PMD. Currently just one ioctl command is served and it
3221  * does not require any CPP access at all.
3222  */
3223 static int
3224 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3225 {
3226         uint32_t cmd, ident_size, tmp;
3227         int err;
3228
3229         /* Reading now the IOCTL command */
3230         err = recv(sockfd, &cmd, 4, 0);
3231         if (err != 4) {
3232                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3233                 return -EIO;
3234         }
3235
3236         /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3237         if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3238                 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3239                 return -EINVAL;
3240         }
3241
3242         err = recv(sockfd, &ident_size, 4, 0);
3243         if (err != 4) {
3244                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3245                 return -EIO;
3246         }
3247
3248         tmp = nfp_cpp_model(cpp);
3249
3250         PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3251
3252         err = send(sockfd, &tmp, 4, 0);
3253         if (err != 4) {
3254                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3255                 return -EIO;
3256         }
3257
3258         tmp = cpp->interface;
3259
3260         PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3261
3262         err = send(sockfd, &tmp, 4, 0);
3263         if (err != 4) {
3264                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3265                 return -EIO;
3266         }
3267
3268         return 0;
3269 }
3270
3271 #define NFP_BRIDGE_OP_READ      20
3272 #define NFP_BRIDGE_OP_WRITE     30
3273 #define NFP_BRIDGE_OP_IOCTL     40
3274
3275 /*
3276  * This is the code to be executed by a service core. The CPP bridge interface
3277  * is based on a unix socket and requests usually received by a kernel char
3278  * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3279  * can be executed with a wrapper library and LD_LIBRARY being completely
3280  * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3281  * accesses.
3282  */
3283 static int32_t
3284 nfp_cpp_bridge_service_func(void *args)
3285 {
3286         struct sockaddr address;
3287         struct nfp_cpp *cpp = args;
3288         int sockfd, datafd, op, ret;
3289
3290         unlink("/tmp/nfp_cpp");
3291         sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3292         if (sockfd < 0) {
3293                 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3294                         __func__);
3295                 return -EIO;
3296         }
3297
3298         memset(&address, 0, sizeof(struct sockaddr));
3299
3300         address.sa_family = AF_UNIX;
3301         strcpy(address.sa_data, "/tmp/nfp_cpp");
3302
3303         ret = bind(sockfd, (const struct sockaddr *)&address,
3304                    sizeof(struct sockaddr));
3305         if (ret < 0) {
3306                 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3307                                   __func__, errno);
3308                 close(sockfd);
3309                 return ret;
3310         }
3311
3312         ret = listen(sockfd, 20);
3313         if (ret < 0) {
3314                 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3315                                   __func__, errno);
3316                 close(sockfd);
3317                 return ret;
3318         }
3319
3320         for (;;) {
3321                 datafd = accept(sockfd, NULL, NULL);
3322                 if (datafd < 0) {
3323                         RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3324                                           __func__, errno);
3325                         RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3326                         close(sockfd);
3327                         return -EIO;
3328                 }
3329
3330                 while (1) {
3331                         ret = recv(datafd, &op, 4, 0);
3332                         if (ret <= 0) {
3333                                 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3334                                                    __func__);
3335                                 break;
3336                         }
3337
3338                         PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3339
3340                         if (op == NFP_BRIDGE_OP_READ)
3341                                 nfp_cpp_bridge_serve_read(datafd, cpp);
3342
3343                         if (op == NFP_BRIDGE_OP_WRITE)
3344                                 nfp_cpp_bridge_serve_write(datafd, cpp);
3345
3346                         if (op == NFP_BRIDGE_OP_IOCTL)
3347                                 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3348
3349                         if (op == 0)
3350                                 break;
3351                 }
3352                 close(datafd);
3353         }
3354         close(sockfd);
3355
3356         return 0;
3357 }
3358
3359 static int
3360 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3361                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3362                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3363 {
3364         struct rte_eth_dev *eth_dev;
3365         struct nfp_net_hw *hw = NULL;
3366         char *port_name;
3367         struct rte_service_spec service;
3368         int retval;
3369
3370         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3371         if (!port_name)
3372                 return -ENOMEM;
3373
3374         if (ports > 1)
3375                 snprintf(port_name, 100, "%s_port%d", dev->device.name, port);
3376         else
3377                 strlcat(port_name, dev->device.name, 100);
3378
3379
3380         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3381                 eth_dev = rte_eth_dev_allocate(port_name);
3382                 if (!eth_dev) {
3383                         rte_free(port_name);
3384                         return -ENODEV;
3385                 }
3386                 if (port == 0) {
3387                         *priv = rte_zmalloc(port_name,
3388                                             sizeof(struct nfp_net_adapter) *
3389                                             ports, RTE_CACHE_LINE_SIZE);
3390                         if (!*priv) {
3391                                 rte_free(port_name);
3392                                 rte_eth_dev_release_port(eth_dev);
3393                                 return -ENOMEM;
3394                         }
3395                 }
3396                 eth_dev->data->dev_private = *priv;
3397
3398                 /*
3399                  * dev_private pointing to port0 dev_private because we need
3400                  * to configure vNIC bars based on port0 at nfp_net_init.
3401                  * Then dev_private is adjusted per port.
3402                  */
3403                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3404                 hw->cpp = cpp;
3405                 hw->hwinfo = hwinfo;
3406                 hw->sym_tbl = sym_tbl;
3407                 hw->pf_port_idx = phys_port;
3408                 hw->is_pf = 1;
3409                 if (ports > 1)
3410                         hw->pf_multiport_enabled = 1;
3411
3412                 hw->total_ports = ports;
3413         } else {
3414                 eth_dev = rte_eth_dev_attach_secondary(port_name);
3415                 if (!eth_dev) {
3416                         RTE_LOG(ERR, EAL, "secondary process attach failed, "
3417                                 "ethdev doesn't exist");
3418                         rte_free(port_name);
3419                         return -ENODEV;
3420                 }
3421                 eth_dev->process_private = cpp;
3422         }
3423
3424         eth_dev->device = &dev->device;
3425         rte_eth_copy_pci_info(eth_dev, dev);
3426
3427         retval = nfp_net_init(eth_dev);
3428
3429         if (retval) {
3430                 retval = -ENODEV;
3431                 goto probe_failed;
3432         } else {
3433                 rte_eth_dev_probing_finish(eth_dev);
3434         }
3435
3436         rte_free(port_name);
3437
3438         if (port == 0) {
3439                 /*
3440                  * The rte_service needs to be created just once per PMD.
3441                  * And the cpp handler needs to be linked to the service.
3442                  * Secondary processes will be used for debugging DPDK apps
3443                  * when requiring to use the CPP interface for accessing NFP
3444                  * components. And the cpp handler for secondary processes is
3445                  * available at this point.
3446                  */
3447                 memset(&service, 0, sizeof(struct rte_service_spec));
3448                 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3449                 service.callback = nfp_cpp_bridge_service_func;
3450                 service.callback_userdata = (void *)cpp;
3451
3452                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private);
3453
3454                 if (rte_service_component_register(&service,
3455                                                    &hw->nfp_cpp_service_id))
3456                         RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3457                 else
3458                         RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3459         }
3460
3461         return retval;
3462
3463 probe_failed:
3464         rte_free(port_name);
3465         /* free ports private data if primary process */
3466         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3467                 rte_free(eth_dev->data->dev_private);
3468
3469         rte_eth_dev_release_port(eth_dev);
3470
3471         return retval;
3472 }
3473
3474 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
3475
3476 static int
3477 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3478 {
3479         struct nfp_cpp *cpp = nsp->cpp;
3480         int fw_f;
3481         char *fw_buf;
3482         char fw_name[125];
3483         char serial[40];
3484         struct stat file_stat;
3485         off_t fsize, bytes;
3486
3487         /* Looking for firmware file in order of priority */
3488
3489         /* First try to find a firmware image specific for this device */
3490         snprintf(serial, sizeof(serial),
3491                         "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3492                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3493                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3494                 cpp->interface & 0xff);
3495
3496         snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3497                         serial);
3498
3499         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3500         fw_f = open(fw_name, O_RDONLY);
3501         if (fw_f >= 0)
3502                 goto read_fw;
3503
3504         /* Then try the PCI name */
3505         snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3506                         dev->device.name);
3507
3508         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3509         fw_f = open(fw_name, O_RDONLY);
3510         if (fw_f >= 0)
3511                 goto read_fw;
3512
3513         /* Finally try the card type and media */
3514         snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3515         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3516         fw_f = open(fw_name, O_RDONLY);
3517         if (fw_f < 0) {
3518                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3519                 return -ENOENT;
3520         }
3521
3522 read_fw:
3523         if (fstat(fw_f, &file_stat) < 0) {
3524                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3525                 close(fw_f);
3526                 return -ENOENT;
3527         }
3528
3529         fsize = file_stat.st_size;
3530         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3531                             fw_name, (uint64_t)fsize);
3532
3533         fw_buf = malloc((size_t)fsize);
3534         if (!fw_buf) {
3535                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3536                 close(fw_f);
3537                 return -ENOMEM;
3538         }
3539         memset(fw_buf, 0, fsize);
3540
3541         bytes = read(fw_f, fw_buf, fsize);
3542         if (bytes != fsize) {
3543                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3544                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3545                                    (uint64_t)bytes, (uint64_t)fsize);
3546                 free(fw_buf);
3547                 close(fw_f);
3548                 return -EIO;
3549         }
3550
3551         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3552         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3553         PMD_DRV_LOG(INFO, "Done");
3554
3555         free(fw_buf);
3556         close(fw_f);
3557
3558         return 0;
3559 }
3560
3561 static int
3562 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3563              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3564 {
3565         struct nfp_nsp *nsp;
3566         const char *nfp_fw_model;
3567         char card_desc[100];
3568         int err = 0;
3569
3570         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3571
3572         if (nfp_fw_model) {
3573                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3574         } else {
3575                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3576                 return -EIO;
3577         }
3578
3579         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3580                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3581                        nfp_eth_table->count);
3582                 return -EIO;
3583         }
3584
3585         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3586                            nfp_eth_table->count);
3587
3588         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3589
3590         snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3591                         nfp_fw_model, nfp_eth_table->count,
3592                         nfp_eth_table->ports[0].speed / 1000);
3593
3594         nsp = nfp_nsp_open(cpp);
3595         if (!nsp) {
3596                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3597                 return -EIO;
3598         }
3599
3600         nfp_nsp_device_soft_reset(nsp);
3601         err = nfp_fw_upload(dev, nsp, card_desc);
3602
3603         nfp_nsp_close(nsp);
3604         return err;
3605 }
3606
3607 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3608                             struct rte_pci_device *dev)
3609 {
3610         struct nfp_cpp *cpp;
3611         struct nfp_hwinfo *hwinfo;
3612         struct nfp_rtsym_table *sym_tbl;
3613         struct nfp_eth_table *nfp_eth_table = NULL;
3614         int total_ports;
3615         void *priv = 0;
3616         int ret = -ENODEV;
3617         int err;
3618         int i;
3619
3620         if (!dev)
3621                 return ret;
3622
3623         /*
3624          * When device bound to UIO, the device could be used, by mistake,
3625          * by two DPDK apps, and the UIO driver does not avoid it. This
3626          * could lead to a serious problem when configuring the NFP CPP
3627          * interface. Here we avoid this telling to the CPP init code to
3628          * use a lock file if UIO is being used.
3629          */
3630         if (dev->kdrv == RTE_KDRV_VFIO)
3631                 cpp = nfp_cpp_from_device_name(dev, 0);
3632         else
3633                 cpp = nfp_cpp_from_device_name(dev, 1);
3634
3635         if (!cpp) {
3636                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3637                 ret = -EIO;
3638                 goto error;
3639         }
3640
3641         hwinfo = nfp_hwinfo_read(cpp);
3642         if (!hwinfo) {
3643                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3644                 return -EIO;
3645         }
3646
3647         nfp_eth_table = nfp_eth_read_ports(cpp);
3648         if (!nfp_eth_table) {
3649                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3650                 return -EIO;
3651         }
3652
3653         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3654                 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3655                         PMD_DRV_LOG(INFO, "Error when uploading firmware");
3656                         ret = -EIO;
3657                         goto error;
3658                 }
3659         }
3660
3661         /* Now the symbol table should be there */
3662         sym_tbl = nfp_rtsym_table_read(cpp);
3663         if (!sym_tbl) {
3664                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3665                                 " symbol table");
3666                 ret = -EIO;
3667                 goto error;
3668         }
3669
3670         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3671         if (total_ports != (int)nfp_eth_table->count) {
3672                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3673                 ret = -EIO;
3674                 goto error;
3675         }
3676         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3677
3678         if (total_ports <= 0 || total_ports > 8) {
3679                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3680                 ret = -ENODEV;
3681                 goto error;
3682         }
3683
3684         for (i = 0; i < total_ports; i++) {
3685                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3686                                         nfp_eth_table->ports[i].index,
3687                                         sym_tbl, &priv);
3688                 if (ret)
3689                         break;
3690         }
3691
3692 error:
3693         free(nfp_eth_table);
3694         return ret;
3695 }
3696
3697 int nfp_logtype_init;
3698 int nfp_logtype_driver;
3699
3700 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3701         {
3702                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3703                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3704         },
3705         {
3706                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3707                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3708         },
3709         {
3710                 .vendor_id = 0,
3711         },
3712 };
3713
3714 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3715         {
3716                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3717                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3718         },
3719         {
3720                 .vendor_id = 0,
3721         },
3722 };
3723
3724 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3725         struct rte_pci_device *pci_dev)
3726 {
3727         return rte_eth_dev_pci_generic_probe(pci_dev,
3728                 sizeof(struct nfp_net_adapter), nfp_net_init);
3729 }
3730
3731 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3732 {
3733         struct rte_eth_dev *eth_dev;
3734         struct nfp_net_hw *hw, *hwport0;
3735         int port = 0;
3736
3737         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3738         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3739             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3740                 port = get_pf_port_number(eth_dev->data->name);
3741                 /*
3742                  * hotplug is not possible with multiport PF although freeing
3743                  * data structures can be done for first port.
3744                  */
3745                 if (port != 0)
3746                         return -ENOTSUP;
3747                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3748                 hw = &hwport0[port];
3749                 nfp_cpp_area_free(hw->ctrl_area);
3750                 nfp_cpp_area_free(hw->hwqueues_area);
3751                 free(hw->hwinfo);
3752                 free(hw->sym_tbl);
3753                 nfp_cpp_free(hw->cpp);
3754         } else {
3755                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3756         }
3757         /* hotplug is not possible with multiport PF */
3758         if (hw->pf_multiport_enabled)
3759                 return -ENOTSUP;
3760         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3761 }
3762
3763 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3764         .id_table = pci_id_nfp_pf_net_map,
3765         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3766         .probe = nfp_pf_pci_probe,
3767         .remove = eth_nfp_pci_remove,
3768 };
3769
3770 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3771         .id_table = pci_id_nfp_vf_net_map,
3772         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3773         .probe = eth_nfp_pci_probe,
3774         .remove = eth_nfp_pci_remove,
3775 };
3776
3777 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3778 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3779 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3780 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3781 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3782 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3783
3784 RTE_INIT(nfp_init_log)
3785 {
3786         nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3787         if (nfp_logtype_init >= 0)
3788                 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3789         nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3790         if (nfp_logtype_driver >= 0)
3791                 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3792 }
3793 /*
3794  * Local variables:
3795  * c-file-style: "Linux"
3796  * indent-tabs-mode: t
3797  * End:
3798  */