2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
59 #include "nfp_net_pmd.h"
60 #include "nfp_net_logs.h"
61 #include "nfp_net_ctrl.h"
64 static void nfp_net_close(struct rte_eth_dev *dev);
65 static int nfp_net_configure(struct rte_eth_dev *dev);
66 static void nfp_net_dev_interrupt_handler(void *param);
67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
70 struct rte_eth_dev_info *dev_info);
71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
80 static void nfp_net_rx_queue_release(void *rxq);
81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
82 uint16_t nb_desc, unsigned int socket_id,
83 const struct rte_eth_rxconf *rx_conf,
84 struct rte_mempool *mp);
85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
86 static void nfp_net_tx_queue_release(void *txq);
87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_txconf *tx_conf);
90 static int nfp_net_start(struct rte_eth_dev *dev);
91 static int nfp_net_stats_get(struct rte_eth_dev *dev,
92 struct rte_eth_stats *stats);
93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
94 static void nfp_net_stop(struct rte_eth_dev *dev);
95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
99 * The offset of the queue controller queues in the PCIe Target. These
100 * happen to be at the same offset on the NFP6000 and the NFP3200 so
101 * we use a single macro here.
103 #define NFP_PCIE_QUEUE(_q) (0x800 * ((_q) & 0xff))
105 /* Maximum value which can be added to a queue with one transaction */
106 #define NFP_QCP_MAX_ADD 0x7f
108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
109 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
113 NFP_QCP_READ_PTR = 0,
118 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
119 * @q: Base address for queue structure
120 * @ptr: Add to the Read or Write pointer
121 * @val: Value to add to the queue pointer
123 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
130 if (ptr == NFP_QCP_READ_PTR)
131 off = NFP_QCP_QUEUE_ADD_RPTR;
133 off = NFP_QCP_QUEUE_ADD_WPTR;
135 while (val > NFP_QCP_MAX_ADD) {
136 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
137 val -= NFP_QCP_MAX_ADD;
140 nn_writel(rte_cpu_to_le_32(val), q + off);
144 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
145 * @q: Base address for queue structure
146 * @ptr: Read or Write pointer
148 static inline uint32_t
149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
154 if (ptr == NFP_QCP_READ_PTR)
155 off = NFP_QCP_QUEUE_STS_LO;
157 off = NFP_QCP_QUEUE_STS_HI;
159 val = rte_cpu_to_le_32(nn_readl(q + off));
161 if (ptr == NFP_QCP_READ_PTR)
162 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
164 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
168 * Functions to read/write from/to Config BAR
169 * Performs any endian conversion necessary.
171 static inline uint8_t
172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
174 return nn_readb(hw->ctrl_bar + off);
178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
180 nn_writeb(val, hw->ctrl_bar + off);
183 static inline uint32_t
184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
186 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
192 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
195 static inline uint64_t
196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
198 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
204 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
208 * Atomically reads link status information from global structure rte_eth_dev.
211 * - Pointer to the structure rte_eth_dev to read from.
212 * - Pointer to the buffer to be saved with the link status.
215 * - On success, zero.
216 * - On failure, negative value.
219 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
220 struct rte_eth_link *link)
222 struct rte_eth_link *dst = link;
223 struct rte_eth_link *src = &dev->data->dev_link;
225 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
226 *(uint64_t *)src) == 0)
233 * Atomically writes the link status information into global
234 * structure rte_eth_dev.
237 * - Pointer to the structure rte_eth_dev to read from.
238 * - Pointer to the buffer to be saved with the link status.
241 * - On success, zero.
242 * - On failure, negative value.
245 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
246 struct rte_eth_link *link)
248 struct rte_eth_link *dst = &dev->data->dev_link;
249 struct rte_eth_link *src = link;
251 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
252 *(uint64_t *)src) == 0)
259 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
263 if (rxq->rxbufs == NULL)
266 for (i = 0; i < rxq->rx_count; i++) {
267 if (rxq->rxbufs[i].mbuf) {
268 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
269 rxq->rxbufs[i].mbuf = NULL;
275 nfp_net_rx_queue_release(void *rx_queue)
277 struct nfp_net_rxq *rxq = rx_queue;
280 nfp_net_rx_queue_release_mbufs(rxq);
281 rte_free(rxq->rxbufs);
287 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
289 nfp_net_rx_queue_release_mbufs(rxq);
295 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
299 if (txq->txbufs == NULL)
302 for (i = 0; i < txq->tx_count; i++) {
303 if (txq->txbufs[i].mbuf) {
304 rte_pktmbuf_free(txq->txbufs[i].mbuf);
305 txq->txbufs[i].mbuf = NULL;
311 nfp_net_tx_queue_release(void *tx_queue)
313 struct nfp_net_txq *txq = tx_queue;
316 nfp_net_tx_queue_release_mbufs(txq);
317 rte_free(txq->txbufs);
323 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
325 nfp_net_tx_queue_release_mbufs(txq);
331 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
335 struct timespec wait;
337 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
340 if (hw->qcp_cfg == NULL)
341 rte_panic("Bad configuration queue pointer\n");
343 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
346 wait.tv_nsec = 1000000;
348 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
350 /* Poll update field, waiting for NFP to ack the config */
351 for (cnt = 0; ; cnt++) {
352 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
355 if (new & NFP_NET_CFG_UPDATE_ERR) {
356 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
359 if (cnt >= NFP_NET_POLL_TIMEOUT) {
360 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
361 " %dms", update, cnt);
362 rte_panic("Exiting\n");
364 nanosleep(&wait, 0); /* waiting for a 1ms */
366 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
371 * Reconfigure the NIC
372 * @nn: device to reconfigure
373 * @ctrl: The value for the ctrl field in the BAR config
374 * @update: The value for the update field in the BAR config
376 * Write the update word to the BAR and ping the reconfig queue. Then poll
377 * until the firmware has acknowledged the update by zeroing the update word.
380 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
384 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
387 rte_spinlock_lock(&hw->reconfig_lock);
389 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
390 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
394 err = __nfp_net_reconfig(hw, update);
396 rte_spinlock_unlock(&hw->reconfig_lock);
402 * Reconfig errors imply situations where they can be handled.
403 * Otherwise, rte_panic is called inside __nfp_net_reconfig
405 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
411 * Configure an Ethernet device. This function must be invoked first
412 * before any other function in the Ethernet API. This function can
413 * also be re-invoked when a device is in the stopped state.
416 nfp_net_configure(struct rte_eth_dev *dev)
418 struct rte_eth_conf *dev_conf;
419 struct rte_eth_rxmode *rxmode;
420 struct rte_eth_txmode *txmode;
421 uint32_t new_ctrl = 0;
423 struct nfp_net_hw *hw;
425 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
428 * A DPDK app sends info about how many queues to use and how
429 * those queues need to be configured. This is used by the
430 * DPDK core and it makes sure no more queues than those
431 * advertised by the driver are requested. This function is
432 * called after that internal process
435 PMD_INIT_LOG(DEBUG, "Configure");
437 dev_conf = &dev->data->dev_conf;
438 rxmode = &dev_conf->rxmode;
439 txmode = &dev_conf->txmode;
441 /* Checking TX mode */
442 if (txmode->mq_mode) {
443 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
447 /* Checking RX mode */
448 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
449 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
450 update = NFP_NET_CFG_UPDATE_RSS;
451 new_ctrl = NFP_NET_CFG_CTRL_RSS;
453 PMD_INIT_LOG(INFO, "RSS not supported");
458 if (rxmode->split_hdr_size) {
459 PMD_INIT_LOG(INFO, "rxmode does not support split header");
463 if (rxmode->hw_ip_checksum) {
464 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
465 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
467 PMD_INIT_LOG(INFO, "RXCSUM not supported");
472 if (rxmode->hw_vlan_filter) {
473 PMD_INIT_LOG(INFO, "VLAN filter not supported");
477 if (rxmode->hw_vlan_strip) {
478 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
479 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
481 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
486 if (rxmode->hw_vlan_extend) {
487 PMD_INIT_LOG(INFO, "VLAN extended not supported");
491 if (rxmode->jumbo_frame)
492 hw->mtu = rxmode->max_rx_pkt_len;
494 if (rxmode->hw_strip_crc) {
495 PMD_INIT_LOG(INFO, "strip CRC not supported");
499 if (rxmode->enable_scatter) {
500 PMD_INIT_LOG(INFO, "Scatter not supported");
504 /* If next capabilities are supported, configure them by default */
507 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
508 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
511 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
512 new_ctrl |= NFP_NET_CFG_CTRL_L2BC;
515 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
516 new_ctrl |= NFP_NET_CFG_CTRL_L2MC;
518 /* TX checksum offload */
519 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
520 new_ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
523 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
524 new_ctrl |= NFP_NET_CFG_CTRL_LSO;
527 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
528 new_ctrl |= NFP_NET_CFG_CTRL_GATHER;
533 update |= NFP_NET_CFG_UPDATE_GEN;
535 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
536 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
545 nfp_net_enable_queues(struct rte_eth_dev *dev)
547 struct nfp_net_hw *hw;
548 uint64_t enabled_queues = 0;
551 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
553 /* Enabling the required TX queues in the device */
554 for (i = 0; i < dev->data->nb_tx_queues; i++)
555 enabled_queues |= (1 << i);
557 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
561 /* Enabling the required RX queues in the device */
562 for (i = 0; i < dev->data->nb_rx_queues; i++)
563 enabled_queues |= (1 << i);
565 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
569 nfp_net_disable_queues(struct rte_eth_dev *dev)
571 struct nfp_net_hw *hw;
572 uint32_t new_ctrl, update = 0;
574 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
576 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
577 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
579 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
580 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
581 NFP_NET_CFG_UPDATE_MSIX;
583 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
584 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
586 /* If an error when reconfig we avoid to change hw state */
587 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
594 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
598 for (i = 0; i < dev->data->nb_rx_queues; i++) {
599 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
606 nfp_net_params_setup(struct nfp_net_hw *hw)
608 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
609 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
613 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
615 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
618 #define ETH_ADDR_LEN 6
621 nfp_eth_copy_mac_reverse(uint8_t *dst, const uint8_t *src)
625 for (i = 0; i < ETH_ADDR_LEN; i++)
626 dst[ETH_ADDR_LEN - i - 1] = src[i];
630 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
632 union eth_table_entry *entry;
636 entry = hw->eth_table;
638 /* Reading NFP ethernet table obtained before */
639 for (i = 0; i < NSP_ETH_MAX_COUNT; i++) {
640 if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) {
641 /* port not in use */
651 if (i == NSP_ETH_MAX_COUNT)
655 * hw points to port0 private data. We need hw now pointing to
659 nfp_eth_copy_mac_reverse((uint8_t *)&hw->mac_addr,
660 (uint8_t *)&entry->mac_addr);
666 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
670 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
671 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
673 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
674 memcpy(&hw->mac_addr[4], &tmp, 2);
678 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
680 uint32_t mac0 = *(uint32_t *)mac;
683 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
686 mac1 = *(uint16_t *)mac;
687 nn_writew(rte_cpu_to_be_16(mac1),
688 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
692 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
693 struct rte_intr_handle *intr_handle)
695 struct nfp_net_hw *hw;
698 if (!intr_handle->intr_vec) {
699 intr_handle->intr_vec =
700 rte_zmalloc("intr_vec",
701 dev->data->nb_rx_queues * sizeof(int), 0);
702 if (!intr_handle->intr_vec) {
703 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
704 " intr_vec", dev->data->nb_rx_queues);
709 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
711 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
712 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
713 /* UIO just supports one queue and no LSC*/
714 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
715 intr_handle->intr_vec[0] = 0;
717 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
718 for (i = 0; i < dev->data->nb_rx_queues; i++) {
720 * The first msix vector is reserved for non
723 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
724 intr_handle->intr_vec[i] = i + 1;
725 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
726 intr_handle->intr_vec[i]);
730 /* Avoiding TX interrupts */
731 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
736 nfp_net_start(struct rte_eth_dev *dev)
738 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
739 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
740 uint32_t new_ctrl, update = 0;
741 struct nfp_net_hw *hw;
742 uint32_t intr_vector;
745 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
747 PMD_INIT_LOG(DEBUG, "Start");
749 /* Disabling queues just in case... */
750 nfp_net_disable_queues(dev);
752 /* Writing configuration parameters in the device */
753 nfp_net_params_setup(hw);
755 /* Enabling the required queues in the device */
756 nfp_net_enable_queues(dev);
758 /* check and configure queue intr-vector mapping */
759 if (dev->data->dev_conf.intr_conf.rxq != 0) {
760 if (hw->pf_multiport_enabled) {
761 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
762 "with NFP multiport PF");
765 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
767 * Better not to share LSC with RX interrupts.
768 * Unregistering LSC interrupt handler
770 rte_intr_callback_unregister(&pci_dev->intr_handle,
771 nfp_net_dev_interrupt_handler, (void *)dev);
773 if (dev->data->nb_rx_queues > 1) {
774 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
775 "supports 1 queue with UIO");
779 intr_vector = dev->data->nb_rx_queues;
780 if (rte_intr_efd_enable(intr_handle, intr_vector))
783 nfp_configure_rx_interrupt(dev, intr_handle);
784 update = NFP_NET_CFG_UPDATE_MSIX;
787 rte_intr_enable(intr_handle);
790 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
792 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
794 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
795 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
797 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
798 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
802 * Allocating rte mbuffs for configured rx queues.
803 * This requires queues being enabled before
805 if (nfp_net_rx_freelist_setup(dev) < 0) {
811 /* Configure the physical port up */
812 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 1);
820 * An error returned by this function should mean the app
821 * exiting and then the system releasing all the memory
822 * allocated even memory coming from hugepages.
824 * The device could be enabled at this point with some queues
825 * ready for getting packets. This is true if the call to
826 * nfp_net_rx_freelist_setup() succeeds for some queues but
827 * fails for subsequent queues.
829 * This should make the app exiting but better if we tell the
832 nfp_net_disable_queues(dev);
837 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
839 nfp_net_stop(struct rte_eth_dev *dev)
842 struct nfp_net_hw *hw;
844 PMD_INIT_LOG(DEBUG, "Stop");
846 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
848 nfp_net_disable_queues(dev);
851 for (i = 0; i < dev->data->nb_tx_queues; i++) {
852 nfp_net_reset_tx_queue(
853 (struct nfp_net_txq *)dev->data->tx_queues[i]);
856 for (i = 0; i < dev->data->nb_rx_queues; i++) {
857 nfp_net_reset_rx_queue(
858 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
862 /* Configure the physical port down */
863 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 0);
866 /* Reset and stop device. The device can not be restarted. */
868 nfp_net_close(struct rte_eth_dev *dev)
870 struct nfp_net_hw *hw;
871 struct rte_pci_device *pci_dev;
874 PMD_INIT_LOG(DEBUG, "Close");
876 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
877 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
880 * We assume that the DPDK application is stopping all the
881 * threads/queues before calling the device close function.
884 nfp_net_disable_queues(dev);
887 for (i = 0; i < dev->data->nb_tx_queues; i++) {
888 nfp_net_reset_tx_queue(
889 (struct nfp_net_txq *)dev->data->tx_queues[i]);
892 for (i = 0; i < dev->data->nb_rx_queues; i++) {
893 nfp_net_reset_rx_queue(
894 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
897 rte_intr_disable(&pci_dev->intr_handle);
898 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
900 /* unregister callback func from eal lib */
901 rte_intr_callback_unregister(&pci_dev->intr_handle,
902 nfp_net_dev_interrupt_handler,
906 * The ixgbe PMD driver disables the pcie master on the
907 * device. The i40e does not...
912 nfp_net_promisc_enable(struct rte_eth_dev *dev)
914 uint32_t new_ctrl, update = 0;
915 struct nfp_net_hw *hw;
917 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
919 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
921 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
922 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
926 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
927 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
931 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
932 update = NFP_NET_CFG_UPDATE_GEN;
935 * DPDK sets promiscuous mode on just after this call assuming
936 * it can not fail ...
938 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
945 nfp_net_promisc_disable(struct rte_eth_dev *dev)
947 uint32_t new_ctrl, update = 0;
948 struct nfp_net_hw *hw;
950 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
952 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
953 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
957 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
958 update = NFP_NET_CFG_UPDATE_GEN;
961 * DPDK sets promiscuous mode off just before this call
962 * assuming it can not fail ...
964 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
971 * return 0 means link status changed, -1 means not changed
973 * Wait to complete is needed as it can take up to 9 seconds to get the Link
977 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
979 struct nfp_net_hw *hw;
980 struct rte_eth_link link, old;
981 uint32_t nn_link_status;
983 static const uint32_t ls_to_ethtool[] = {
984 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
985 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
986 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
987 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
988 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
989 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
990 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
991 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
994 PMD_DRV_LOG(DEBUG, "Link update\n");
996 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
998 memset(&old, 0, sizeof(old));
999 nfp_net_dev_atomic_read_link_status(dev, &old);
1001 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1003 memset(&link, 0, sizeof(struct rte_eth_link));
1005 if (nn_link_status & NFP_NET_CFG_STS_LINK)
1006 link.link_status = ETH_LINK_UP;
1008 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1010 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1011 NFP_NET_CFG_STS_LINK_RATE_MASK;
1013 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1014 link.link_speed = ETH_SPEED_NUM_NONE;
1016 link.link_speed = ls_to_ethtool[nn_link_status];
1018 if (old.link_status != link.link_status) {
1019 nfp_net_dev_atomic_write_link_status(dev, &link);
1020 if (link.link_status)
1021 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
1023 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
1031 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1034 struct nfp_net_hw *hw;
1035 struct rte_eth_stats nfp_dev_stats;
1037 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1041 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1043 /* reading per RX ring stats */
1044 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1045 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1048 nfp_dev_stats.q_ipackets[i] =
1049 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1051 nfp_dev_stats.q_ipackets[i] -=
1052 hw->eth_stats_base.q_ipackets[i];
1054 nfp_dev_stats.q_ibytes[i] =
1055 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1057 nfp_dev_stats.q_ibytes[i] -=
1058 hw->eth_stats_base.q_ibytes[i];
1061 /* reading per TX ring stats */
1062 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1063 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1066 nfp_dev_stats.q_opackets[i] =
1067 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1069 nfp_dev_stats.q_opackets[i] -=
1070 hw->eth_stats_base.q_opackets[i];
1072 nfp_dev_stats.q_obytes[i] =
1073 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1075 nfp_dev_stats.q_obytes[i] -=
1076 hw->eth_stats_base.q_obytes[i];
1079 nfp_dev_stats.ipackets =
1080 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1082 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1084 nfp_dev_stats.ibytes =
1085 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1087 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1089 nfp_dev_stats.opackets =
1090 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1092 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1094 nfp_dev_stats.obytes =
1095 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1097 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1099 /* reading general device stats */
1100 nfp_dev_stats.ierrors =
1101 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1103 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1105 nfp_dev_stats.oerrors =
1106 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1108 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1110 /* RX ring mbuf allocation failures */
1111 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1113 nfp_dev_stats.imissed =
1114 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1116 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1119 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1126 nfp_net_stats_reset(struct rte_eth_dev *dev)
1129 struct nfp_net_hw *hw;
1131 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1134 * hw->eth_stats_base records the per counter starting point.
1135 * Lets update it now
1138 /* reading per RX ring stats */
1139 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1140 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1143 hw->eth_stats_base.q_ipackets[i] =
1144 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1146 hw->eth_stats_base.q_ibytes[i] =
1147 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1150 /* reading per TX ring stats */
1151 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1152 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1155 hw->eth_stats_base.q_opackets[i] =
1156 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1158 hw->eth_stats_base.q_obytes[i] =
1159 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1162 hw->eth_stats_base.ipackets =
1163 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1165 hw->eth_stats_base.ibytes =
1166 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1168 hw->eth_stats_base.opackets =
1169 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1171 hw->eth_stats_base.obytes =
1172 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1174 /* reading general device stats */
1175 hw->eth_stats_base.ierrors =
1176 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1178 hw->eth_stats_base.oerrors =
1179 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1181 /* RX ring mbuf allocation failures */
1182 dev->data->rx_mbuf_alloc_failed = 0;
1184 hw->eth_stats_base.imissed =
1185 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1189 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1191 struct nfp_net_hw *hw;
1193 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1195 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1196 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1197 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1198 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1199 dev_info->max_rx_pktlen = hw->max_mtu;
1200 /* Next should change when PF support is implemented */
1201 dev_info->max_mac_addrs = 1;
1203 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1204 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1206 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1207 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1208 DEV_RX_OFFLOAD_UDP_CKSUM |
1209 DEV_RX_OFFLOAD_TCP_CKSUM;
1211 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1212 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1214 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1215 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1216 DEV_TX_OFFLOAD_UDP_CKSUM |
1217 DEV_TX_OFFLOAD_TCP_CKSUM;
1219 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1221 .pthresh = DEFAULT_RX_PTHRESH,
1222 .hthresh = DEFAULT_RX_HTHRESH,
1223 .wthresh = DEFAULT_RX_WTHRESH,
1225 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1229 dev_info->default_txconf = (struct rte_eth_txconf) {
1231 .pthresh = DEFAULT_TX_PTHRESH,
1232 .hthresh = DEFAULT_TX_HTHRESH,
1233 .wthresh = DEFAULT_TX_WTHRESH,
1235 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1236 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1237 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1238 ETH_TXQ_FLAGS_NOOFFLOADS,
1241 dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1242 ETH_RSS_NONFRAG_IPV4_UDP |
1243 ETH_RSS_NONFRAG_IPV6_TCP |
1244 ETH_RSS_NONFRAG_IPV6_UDP;
1246 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1247 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1249 dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1250 ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1251 ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1253 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1254 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1257 static const uint32_t *
1258 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1260 static const uint32_t ptypes[] = {
1261 /* refers to nfp_net_set_hash() */
1262 RTE_PTYPE_INNER_L3_IPV4,
1263 RTE_PTYPE_INNER_L3_IPV6,
1264 RTE_PTYPE_INNER_L3_IPV6_EXT,
1265 RTE_PTYPE_INNER_L4_MASK,
1269 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1275 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1277 struct nfp_net_rxq *rxq;
1278 struct nfp_net_rx_desc *rxds;
1282 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1289 * Other PMDs are just checking the DD bit in intervals of 4
1290 * descriptors and counting all four if the first has the DD
1291 * bit on. Of course, this is not accurate but can be good for
1292 * performance. But ideally that should be done in descriptors
1293 * chunks belonging to the same cache line
1296 while (count < rxq->rx_count) {
1297 rxds = &rxq->rxds[idx];
1298 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1305 if ((idx) == rxq->rx_count)
1313 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1315 struct rte_pci_device *pci_dev;
1316 struct nfp_net_hw *hw;
1319 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1320 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1322 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1325 /* Make sure all updates are written before un-masking */
1327 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1328 NFP_NET_CFG_ICR_UNMASKED);
1333 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1335 struct rte_pci_device *pci_dev;
1336 struct nfp_net_hw *hw;
1339 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1342 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1345 /* Make sure all updates are written before un-masking */
1347 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1352 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1354 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1355 struct rte_eth_link link;
1357 memset(&link, 0, sizeof(link));
1358 nfp_net_dev_atomic_read_link_status(dev, &link);
1359 if (link.link_status)
1360 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1361 dev->data->port_id, link.link_speed,
1362 link.link_duplex == ETH_LINK_FULL_DUPLEX
1363 ? "full-duplex" : "half-duplex");
1365 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1366 dev->data->port_id);
1368 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1369 pci_dev->addr.domain, pci_dev->addr.bus,
1370 pci_dev->addr.devid, pci_dev->addr.function);
1373 /* Interrupt configuration and handling */
1376 * nfp_net_irq_unmask - Unmask an interrupt
1378 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1379 * clear the ICR for the entry.
1382 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1384 struct nfp_net_hw *hw;
1385 struct rte_pci_device *pci_dev;
1387 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1388 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1390 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1391 /* If MSI-X auto-masking is used, clear the entry */
1393 rte_intr_enable(&pci_dev->intr_handle);
1395 /* Make sure all updates are written before un-masking */
1397 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1398 NFP_NET_CFG_ICR_UNMASKED);
1403 nfp_net_dev_interrupt_handler(void *param)
1406 struct rte_eth_link link;
1407 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1409 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1411 /* get the link status */
1412 memset(&link, 0, sizeof(link));
1413 nfp_net_dev_atomic_read_link_status(dev, &link);
1415 nfp_net_link_update(dev, 0);
1418 if (!link.link_status) {
1419 /* handle it 1 sec later, wait it being stable */
1420 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1421 /* likely to down */
1423 /* handle it 4 sec later, wait it being stable */
1424 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1427 if (rte_eal_alarm_set(timeout * 1000,
1428 nfp_net_dev_interrupt_delayed_handler,
1430 RTE_LOG(ERR, PMD, "Error setting alarm");
1432 nfp_net_irq_unmask(dev);
1437 * Interrupt handler which shall be registered for alarm callback for delayed
1438 * handling specific interrupt to wait for the stable nic state. As the NIC
1439 * interrupt state is not stable for nfp after link is just down, it needs
1440 * to wait 4 seconds to get the stable status.
1442 * @param handle Pointer to interrupt handle.
1443 * @param param The address of parameter (struct rte_eth_dev *)
1448 nfp_net_dev_interrupt_delayed_handler(void *param)
1450 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1452 nfp_net_link_update(dev, 0);
1453 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1455 nfp_net_dev_link_status_print(dev);
1458 nfp_net_irq_unmask(dev);
1462 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1464 struct nfp_net_hw *hw;
1466 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1468 /* check that mtu is within the allowed range */
1469 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1472 /* mtu setting is forbidden if port is started */
1473 if (dev->data->dev_started) {
1474 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1475 dev->data->port_id);
1479 /* switch to jumbo mode if needed */
1480 if ((uint32_t)mtu > ETHER_MAX_LEN)
1481 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1483 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1485 /* update max frame size */
1486 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1488 /* writing to configuration space */
1489 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1497 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1498 uint16_t queue_idx, uint16_t nb_desc,
1499 unsigned int socket_id,
1500 const struct rte_eth_rxconf *rx_conf,
1501 struct rte_mempool *mp)
1503 const struct rte_memzone *tz;
1504 struct nfp_net_rxq *rxq;
1505 struct nfp_net_hw *hw;
1507 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1509 PMD_INIT_FUNC_TRACE();
1511 /* Validating number of descriptors */
1512 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1513 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1514 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1515 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1520 * Free memory prior to re-allocation if needed. This is the case after
1521 * calling nfp_net_stop
1523 if (dev->data->rx_queues[queue_idx]) {
1524 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1525 dev->data->rx_queues[queue_idx] = NULL;
1528 /* Allocating rx queue data structure */
1529 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1530 RTE_CACHE_LINE_SIZE, socket_id);
1534 /* Hw queues mapping based on firmware confifguration */
1535 rxq->qidx = queue_idx;
1536 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1537 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1538 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1539 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1542 * Tracking mbuf size for detecting a potential mbuf overflow due to
1546 rxq->mbuf_size = rxq->mem_pool->elt_size;
1547 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1548 hw->flbufsz = rxq->mbuf_size;
1550 rxq->rx_count = nb_desc;
1551 rxq->port_id = dev->data->port_id;
1552 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1553 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1555 rxq->drop_en = rx_conf->rx_drop_en;
1558 * Allocate RX ring hardware descriptors. A memzone large enough to
1559 * handle the maximum ring size is allocated in order to allow for
1560 * resizing in later calls to the queue setup function.
1562 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1563 sizeof(struct nfp_net_rx_desc) *
1564 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1568 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1569 nfp_net_rx_queue_release(rxq);
1573 /* Saving physical and virtual addresses for the RX ring */
1574 rxq->dma = (uint64_t)tz->iova;
1575 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1577 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1578 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1579 sizeof(*rxq->rxbufs) * nb_desc,
1580 RTE_CACHE_LINE_SIZE, socket_id);
1581 if (rxq->rxbufs == NULL) {
1582 nfp_net_rx_queue_release(rxq);
1586 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1587 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1589 nfp_net_reset_rx_queue(rxq);
1591 dev->data->rx_queues[queue_idx] = rxq;
1595 * Telling the HW about the physical address of the RX ring and number
1596 * of descriptors in log2 format
1598 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1599 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1605 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1607 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1611 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1614 for (i = 0; i < rxq->rx_count; i++) {
1615 struct nfp_net_rx_desc *rxd;
1616 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1619 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1620 (unsigned)rxq->qidx);
1624 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1626 rxd = &rxq->rxds[i];
1628 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1629 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1631 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1634 /* Make sure all writes are flushed before telling the hardware */
1637 /* Not advertising the whole ring as the firmware gets confused if so */
1638 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1641 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1647 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1648 uint16_t nb_desc, unsigned int socket_id,
1649 const struct rte_eth_txconf *tx_conf)
1651 const struct rte_memzone *tz;
1652 struct nfp_net_txq *txq;
1653 uint16_t tx_free_thresh;
1654 struct nfp_net_hw *hw;
1656 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1658 PMD_INIT_FUNC_TRACE();
1660 /* Validating number of descriptors */
1661 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1662 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1663 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1664 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1668 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1669 tx_conf->tx_free_thresh :
1670 DEFAULT_TX_FREE_THRESH);
1672 if (tx_free_thresh > (nb_desc)) {
1674 "tx_free_thresh must be less than the number of TX "
1675 "descriptors. (tx_free_thresh=%u port=%d "
1676 "queue=%d)\n", (unsigned int)tx_free_thresh,
1677 dev->data->port_id, (int)queue_idx);
1682 * Free memory prior to re-allocation if needed. This is the case after
1683 * calling nfp_net_stop
1685 if (dev->data->tx_queues[queue_idx]) {
1686 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1688 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1689 dev->data->tx_queues[queue_idx] = NULL;
1692 /* Allocating tx queue data structure */
1693 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1694 RTE_CACHE_LINE_SIZE, socket_id);
1696 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1701 * Allocate TX ring hardware descriptors. A memzone large enough to
1702 * handle the maximum ring size is allocated in order to allow for
1703 * resizing in later calls to the queue setup function.
1705 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1706 sizeof(struct nfp_net_tx_desc) *
1707 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1710 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1711 nfp_net_tx_queue_release(txq);
1715 txq->tx_count = nb_desc;
1716 txq->tx_free_thresh = tx_free_thresh;
1717 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1718 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1719 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1721 /* queue mapping based on firmware configuration */
1722 txq->qidx = queue_idx;
1723 txq->tx_qcidx = queue_idx * hw->stride_tx;
1724 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1726 txq->port_id = dev->data->port_id;
1727 txq->txq_flags = tx_conf->txq_flags;
1729 /* Saving physical and virtual addresses for the TX ring */
1730 txq->dma = (uint64_t)tz->iova;
1731 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1733 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1734 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1735 sizeof(*txq->txbufs) * nb_desc,
1736 RTE_CACHE_LINE_SIZE, socket_id);
1737 if (txq->txbufs == NULL) {
1738 nfp_net_tx_queue_release(txq);
1741 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1742 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1744 nfp_net_reset_tx_queue(txq);
1746 dev->data->tx_queues[queue_idx] = txq;
1750 * Telling the HW about the physical address of the TX ring and number
1751 * of descriptors in log2 format
1753 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1754 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1759 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1761 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1762 struct rte_mbuf *mb)
1765 struct nfp_net_hw *hw = txq->hw;
1767 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1770 ol_flags = mb->ol_flags;
1772 if (!(ol_flags & PKT_TX_TCP_SEG))
1775 txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1776 txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1777 txd->flags = PCIE_DESC_TX_LSO;
1786 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1788 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1789 struct rte_mbuf *mb)
1792 struct nfp_net_hw *hw = txq->hw;
1794 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1797 ol_flags = mb->ol_flags;
1799 /* IPv6 does not need checksum */
1800 if (ol_flags & PKT_TX_IP_CKSUM)
1801 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1803 switch (ol_flags & PKT_TX_L4_MASK) {
1804 case PKT_TX_UDP_CKSUM:
1805 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1807 case PKT_TX_TCP_CKSUM:
1808 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1812 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1813 txd->flags |= PCIE_DESC_TX_CSUM;
1816 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1818 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1819 struct rte_mbuf *mb)
1821 struct nfp_net_hw *hw = rxq->hw;
1823 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1826 /* If IPv4 and IP checksum error, fail */
1827 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1828 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1829 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1831 /* If neither UDP nor TCP return */
1832 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1833 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1836 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1837 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1838 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1840 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1841 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1842 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1845 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1846 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1848 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1851 * nfp_net_set_hash - Set mbuf hash data
1853 * The RSS hash and hash-type are pre-pended to the packet data.
1854 * Extract and decode it and set the mbuf fields.
1857 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1858 struct rte_mbuf *mbuf)
1860 struct nfp_net_hw *hw = rxq->hw;
1861 uint8_t *meta_offset;
1864 uint32_t hash_type = 0;
1866 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1869 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1870 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1873 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1874 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1876 } else if (NFP_DESC_META_LEN(rxd)) {
1879 * <---- 32 bit ----->
1884 * ====================
1887 * Field type word contains up to 8 4bit field types
1888 * A 4bit field type refers to a data field word
1889 * A data field word can have several 4bit field types
1891 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1892 meta_offset -= NFP_DESC_META_LEN(rxd);
1893 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1895 /* NFP PMD just supports metadata for hashing */
1896 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1897 case NFP_NET_META_HASH:
1898 /* next field type is about the hash type */
1899 meta_info >>= NFP_NET_META_FIELD_SIZE;
1900 /* hash value is in the data field */
1901 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1902 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1905 /* Unsupported metadata can be a performance issue */
1912 mbuf->hash.rss = hash;
1913 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1915 switch (hash_type) {
1916 case NFP_NET_RSS_IPV4:
1917 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1919 case NFP_NET_RSS_IPV6:
1920 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1922 case NFP_NET_RSS_IPV6_EX:
1923 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1926 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1931 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1933 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1936 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1941 * There are some decissions to take:
1942 * 1) How to check DD RX descriptors bit
1943 * 2) How and when to allocate new mbufs
1945 * Current implementation checks just one single DD bit each loop. As each
1946 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1947 * a single cache line instead. Tests with this change have not shown any
1948 * performance improvement but it requires further investigation. For example,
1949 * depending on which descriptor is next, the number of descriptors could be
1950 * less than 8 for just checking those in the same cache line. This implies
1951 * extra work which could be counterproductive by itself. Indeed, last firmware
1952 * changes are just doing this: writing several descriptors with the DD bit
1953 * for saving PCIe bandwidth and DMA operations from the NFP.
1955 * Mbuf allocation is done when a new packet is received. Then the descriptor
1956 * is automatically linked with the new mbuf and the old one is given to the
1957 * user. The main drawback with this design is mbuf allocation is heavier than
1958 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1959 * cache point of view it does not seem allocating the mbuf early on as we are
1960 * doing now have any benefit at all. Again, tests with this change have not
1961 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1962 * so looking at the implications of this type of allocation should be studied
1967 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1969 struct nfp_net_rxq *rxq;
1970 struct nfp_net_rx_desc *rxds;
1971 struct nfp_net_rx_buff *rxb;
1972 struct nfp_net_hw *hw;
1973 struct rte_mbuf *mb;
1974 struct rte_mbuf *new_mb;
1980 if (unlikely(rxq == NULL)) {
1982 * DPDK just checks the queue is lower than max queues
1983 * enabled. But the queue needs to be configured
1985 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1993 while (avail < nb_pkts) {
1994 rxb = &rxq->rxbufs[rxq->rd_p];
1995 if (unlikely(rxb == NULL)) {
1996 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2001 * Memory barrier to ensure that we won't do other
2002 * reads before the DD bit.
2006 rxds = &rxq->rxds[rxq->rd_p];
2007 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2011 * We got a packet. Let's alloc a new mbuff for refilling the
2012 * free descriptor ring as soon as possible
2014 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2015 if (unlikely(new_mb == NULL)) {
2016 RTE_LOG_DP(DEBUG, PMD,
2017 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2018 rxq->port_id, (unsigned int)rxq->qidx);
2019 nfp_net_mbuf_alloc_failed(rxq);
2026 * Grab the mbuff and refill the descriptor with the
2027 * previously allocated mbuff
2032 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
2033 rxds->rxd.data_len, rxq->mbuf_size);
2035 /* Size of this segment */
2036 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2037 /* Size of the whole packet. We just support 1 segment */
2038 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2040 if (unlikely((mb->data_len + hw->rx_offset) >
2043 * This should not happen and the user has the
2044 * responsibility of avoiding it. But we have
2045 * to give some info about the error
2047 RTE_LOG_DP(ERR, PMD,
2048 "mbuf overflow likely due to the RX offset.\n"
2049 "\t\tYour mbuf size should have extra space for"
2050 " RX offset=%u bytes.\n"
2051 "\t\tCurrently you just have %u bytes available"
2052 " but the received packet is %u bytes long",
2054 rxq->mbuf_size - hw->rx_offset,
2059 /* Filling the received mbuff with packet info */
2061 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2063 mb->data_off = RTE_PKTMBUF_HEADROOM +
2064 NFP_DESC_META_LEN(rxds);
2066 /* No scatter mode supported */
2070 /* Checking the RSS flag */
2071 nfp_net_set_hash(rxq, rxds, mb);
2073 /* Checking the checksum flag */
2074 nfp_net_rx_cksum(rxq, rxds, mb);
2076 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2077 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2078 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2079 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2082 /* Adding the mbuff to the mbuff array passed by the app */
2083 rx_pkts[avail++] = mb;
2085 /* Now resetting and updating the descriptor */
2088 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2090 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2091 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2094 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2101 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
2102 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2104 nb_hold += rxq->nb_rx_hold;
2107 * FL descriptors needs to be written before incrementing the
2108 * FL queue WR pointer
2111 if (nb_hold > rxq->rx_free_thresh) {
2112 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2113 rxq->port_id, (unsigned int)rxq->qidx,
2114 (unsigned)nb_hold, (unsigned)avail);
2115 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2118 rxq->nb_rx_hold = nb_hold;
2124 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2126 * @txq: TX queue to work with
2127 * Returns number of descriptors freed
2130 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2135 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2136 " status\n", txq->qidx);
2138 /* Work out how many packets have been sent */
2139 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2141 if (qcp_rd_p == txq->rd_p) {
2142 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2143 "packets (%u, %u)\n", txq->qidx,
2144 qcp_rd_p, txq->rd_p);
2148 if (qcp_rd_p > txq->rd_p)
2149 todo = qcp_rd_p - txq->rd_p;
2151 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2153 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2154 qcp_rd_p, txq->rd_p, txq->rd_p);
2160 if (unlikely(txq->rd_p >= txq->tx_count))
2161 txq->rd_p -= txq->tx_count;
2166 /* Leaving always free descriptors for avoiding wrapping confusion */
2168 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2170 if (txq->wr_p >= txq->rd_p)
2171 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2173 return txq->rd_p - txq->wr_p - 8;
2177 * nfp_net_txq_full - Check if the TX queue free descriptors
2178 * is below tx_free_threshold
2180 * @txq: TX queue to check
2182 * This function uses the host copy* of read/write pointers
2185 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2187 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2191 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2193 struct nfp_net_txq *txq;
2194 struct nfp_net_hw *hw;
2195 struct nfp_net_tx_desc *txds, txd;
2196 struct rte_mbuf *pkt;
2198 int pkt_size, dma_size;
2199 uint16_t free_descs, issued_descs;
2200 struct rte_mbuf **lmbuf;
2205 txds = &txq->txds[txq->wr_p];
2207 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2208 txq->qidx, txq->wr_p, nb_pkts);
2210 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2211 nfp_net_tx_free_bufs(txq);
2213 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2214 if (unlikely(free_descs == 0))
2221 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2222 txq->qidx, nb_pkts);
2223 /* Sending packets */
2224 while ((i < nb_pkts) && free_descs) {
2225 /* Grabbing the mbuf linked to the current descriptor */
2226 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2227 /* Warming the cache for releasing the mbuf later on */
2228 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2230 pkt = *(tx_pkts + i);
2232 if (unlikely((pkt->nb_segs > 1) &&
2233 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2234 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2235 rte_panic("Multisegment packet unsupported\n");
2238 /* Checking if we have enough descriptors */
2239 if (unlikely(pkt->nb_segs > free_descs))
2243 * Checksum and VLAN flags just in the first descriptor for a
2244 * multisegment packet, but TSO info needs to be in all of them.
2246 txd.data_len = pkt->pkt_len;
2247 nfp_net_tx_tso(txq, &txd, pkt);
2248 nfp_net_tx_cksum(txq, &txd, pkt);
2250 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2251 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2252 txd.flags |= PCIE_DESC_TX_VLAN;
2253 txd.vlan = pkt->vlan_tci;
2257 * mbuf data_len is the data in one segment and pkt_len data
2258 * in the whole packet. When the packet is just one segment,
2259 * then data_len = pkt_len
2261 pkt_size = pkt->pkt_len;
2264 /* Copying TSO, VLAN and cksum info */
2267 /* Releasing mbuf used by this descriptor previously*/
2269 rte_pktmbuf_free_seg(*lmbuf);
2272 * Linking mbuf with descriptor for being released
2273 * next time descriptor is used
2277 dma_size = pkt->data_len;
2278 dma_addr = rte_mbuf_data_iova(pkt);
2279 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2280 "%" PRIx64 "\n", dma_addr);
2282 /* Filling descriptors fields */
2283 txds->dma_len = dma_size;
2284 txds->data_len = txd.data_len;
2285 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2286 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2287 ASSERT(free_descs > 0);
2291 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2294 pkt_size -= dma_size;
2297 txds->offset_eop |= PCIE_DESC_TX_EOP;
2299 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2302 /* Referencing next free TX descriptor */
2303 txds = &txq->txds[txq->wr_p];
2304 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2311 /* Increment write pointers. Force memory write before we let HW know */
2313 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2319 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2321 uint32_t new_ctrl, update;
2322 struct nfp_net_hw *hw;
2325 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2329 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2330 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2331 " ETH_VLAN_EXTEND_OFFLOAD");
2333 /* Enable vlan strip if it is not configured yet */
2334 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2335 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2336 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2338 /* Disable vlan strip just if it is configured */
2339 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2340 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2341 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2346 update = NFP_NET_CFG_UPDATE_GEN;
2348 ret = nfp_net_reconfig(hw, new_ctrl, update);
2350 hw->ctrl = new_ctrl;
2355 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2357 nfp_net_reta_update(struct rte_eth_dev *dev,
2358 struct rte_eth_rss_reta_entry64 *reta_conf,
2361 uint32_t reta, mask;
2365 struct nfp_net_hw *hw =
2366 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2368 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2371 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2372 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2373 "(%d) doesn't match the number hardware can supported "
2374 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2379 * Update Redirection Table. There are 128 8bit-entries which can be
2380 * manage as 32 32bit-entries
2382 for (i = 0; i < reta_size; i += 4) {
2383 /* Handling 4 RSS entries per loop */
2384 idx = i / RTE_RETA_GROUP_SIZE;
2385 shift = i % RTE_RETA_GROUP_SIZE;
2386 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2392 /* If all 4 entries were set, don't need read RETA register */
2394 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2396 for (j = 0; j < 4; j++) {
2397 if (!(mask & (0x1 << j)))
2400 /* Clearing the entry bits */
2401 reta &= ~(0xFF << (8 * j));
2402 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2404 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2408 update = NFP_NET_CFG_UPDATE_RSS;
2410 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2416 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2418 nfp_net_reta_query(struct rte_eth_dev *dev,
2419 struct rte_eth_rss_reta_entry64 *reta_conf,
2425 struct nfp_net_hw *hw;
2427 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2429 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2432 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2433 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2434 "(%d) doesn't match the number hardware can supported "
2435 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2440 * Reading Redirection Table. There are 128 8bit-entries which can be
2441 * manage as 32 32bit-entries
2443 for (i = 0; i < reta_size; i += 4) {
2444 /* Handling 4 RSS entries per loop */
2445 idx = i / RTE_RETA_GROUP_SIZE;
2446 shift = i % RTE_RETA_GROUP_SIZE;
2447 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2452 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2454 for (j = 0; j < 4; j++) {
2455 if (!(mask & (0x1 << j)))
2457 reta_conf->reta[shift + j] =
2458 (uint8_t)((reta >> (8 * j)) & 0xF);
2465 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2466 struct rte_eth_rss_conf *rss_conf)
2469 uint32_t cfg_rss_ctrl = 0;
2473 struct nfp_net_hw *hw;
2475 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477 rss_hf = rss_conf->rss_hf;
2479 /* Checking if RSS is enabled */
2480 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2481 if (rss_hf != 0) { /* Enable RSS? */
2482 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2485 return 0; /* Nothing to do */
2488 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2489 RTE_LOG(ERR, PMD, "hash key too long\n");
2493 if (rss_hf & ETH_RSS_IPV4)
2494 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2495 NFP_NET_CFG_RSS_IPV4_TCP |
2496 NFP_NET_CFG_RSS_IPV4_UDP;
2498 if (rss_hf & ETH_RSS_IPV6)
2499 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2500 NFP_NET_CFG_RSS_IPV6_TCP |
2501 NFP_NET_CFG_RSS_IPV6_UDP;
2503 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2504 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2506 /* configuring where to apply the RSS hash */
2507 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2509 /* Writing the key byte a byte */
2510 for (i = 0; i < rss_conf->rss_key_len; i++) {
2511 memcpy(&key, &rss_conf->rss_key[i], 1);
2512 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2515 /* Writing the key size */
2516 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2518 update = NFP_NET_CFG_UPDATE_RSS;
2520 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2527 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2528 struct rte_eth_rss_conf *rss_conf)
2531 uint32_t cfg_rss_ctrl;
2534 struct nfp_net_hw *hw;
2536 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2541 rss_hf = rss_conf->rss_hf;
2542 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2544 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2545 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2547 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2548 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2550 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2551 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2553 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2554 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2556 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2557 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2559 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2560 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2562 /* Reading the key size */
2563 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2565 /* Reading the key byte a byte */
2566 for (i = 0; i < rss_conf->rss_key_len; i++) {
2567 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2568 memcpy(&rss_conf->rss_key[i], &key, 1);
2574 /* Initialise and register driver with DPDK Application */
2575 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2576 .dev_configure = nfp_net_configure,
2577 .dev_start = nfp_net_start,
2578 .dev_stop = nfp_net_stop,
2579 .dev_close = nfp_net_close,
2580 .promiscuous_enable = nfp_net_promisc_enable,
2581 .promiscuous_disable = nfp_net_promisc_disable,
2582 .link_update = nfp_net_link_update,
2583 .stats_get = nfp_net_stats_get,
2584 .stats_reset = nfp_net_stats_reset,
2585 .dev_infos_get = nfp_net_infos_get,
2586 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2587 .mtu_set = nfp_net_dev_mtu_set,
2588 .vlan_offload_set = nfp_net_vlan_offload_set,
2589 .reta_update = nfp_net_reta_update,
2590 .reta_query = nfp_net_reta_query,
2591 .rss_hash_update = nfp_net_rss_hash_update,
2592 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2593 .rx_queue_setup = nfp_net_rx_queue_setup,
2594 .rx_queue_release = nfp_net_rx_queue_release,
2595 .rx_queue_count = nfp_net_rx_queue_count,
2596 .tx_queue_setup = nfp_net_tx_queue_setup,
2597 .tx_queue_release = nfp_net_tx_queue_release,
2598 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2599 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2603 * All eth_dev created got its private data, but before nfp_net_init, that
2604 * private data is referencing private data for all the PF ports. This is due
2605 * to how the vNIC bars are mapped based on first port, so all ports need info
2606 * about port 0 private data. Inside nfp_net_init the private data pointer is
2607 * changed to the right address for each port once the bars have been mapped.
2609 * This functions helps to find out which port and therefore which offset
2610 * inside the private data array to use.
2613 get_pf_port_number(char *name)
2615 char *pf_str = name;
2618 while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2623 * This should not happen at all and it would mean major
2624 * implementation fault.
2626 rte_panic("nfp_net: problem with pf device name\n");
2628 /* Expecting _portX with X within [0,7] */
2631 return (int)strtol(pf_str, NULL, 10);
2635 nfp_net_init(struct rte_eth_dev *eth_dev)
2637 struct rte_pci_device *pci_dev;
2638 struct nfp_net_hw *hw, *hwport0;
2640 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2644 nspu_desc_t *nspu_desc = NULL;
2645 uint64_t bar_offset;
2648 PMD_INIT_FUNC_TRACE();
2650 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2652 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2653 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2654 port = get_pf_port_number(eth_dev->data->name);
2655 if (port < 0 || port > 7) {
2656 RTE_LOG(ERR, PMD, "Port value is wrong\n");
2660 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2662 /* This points to port 0 private data */
2663 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2665 /* This points to the specific port private data */
2666 hw = &hwport0[port];
2667 hw->pf_port_idx = port;
2669 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2673 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2674 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2675 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2677 /* For secondary processes, the primary has done all the work */
2678 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2681 rte_eth_copy_pci_info(eth_dev, pci_dev);
2683 hw->device_id = pci_dev->id.device_id;
2684 hw->vendor_id = pci_dev->id.vendor_id;
2685 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2686 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2688 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2689 pci_dev->id.vendor_id, pci_dev->id.device_id,
2690 pci_dev->addr.domain, pci_dev->addr.bus,
2691 pci_dev->addr.devid, pci_dev->addr.function);
2693 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2694 if (hw->ctrl_bar == NULL) {
2696 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2700 if (hw->is_pf && port == 0) {
2701 nspu_desc = hw->nspu_desc;
2703 if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
2705 * A firmware should be there after PF probe so this
2706 * should not happen.
2708 RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
2712 /* vNIC PF control BAR is a subset of PF PCI device BAR */
2713 hw->ctrl_bar += bar_offset;
2714 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2718 if (!hwport0->ctrl_bar)
2721 /* address based on port0 offset */
2722 hw->ctrl_bar = hwport0->ctrl_bar +
2723 (port * NFP_PF_CSR_SLICE_SIZE);
2726 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2728 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2729 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2731 /* Work out where in the BAR the queues start. */
2732 switch (pci_dev->id.device_id) {
2733 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2734 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2735 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2736 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2737 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2738 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2739 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2742 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2746 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2747 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2749 if (hw->is_pf && port == 0) {
2750 /* configure access to tx/rx vNIC BARs */
2751 nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
2752 PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
2754 hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
2756 /* vNIC PF tx/rx BARs are a subset of PF PCI device */
2757 hwport0->hw_queues += bar_offset;
2759 /* Lets seize the chance to read eth table from hw */
2760 if (nfp_nsp_eth_read_table(nspu_desc, &hw->eth_table))
2765 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2766 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2767 eth_dev->data->dev_private = hw;
2769 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2771 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2775 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2776 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2778 nfp_net_cfg_queue_setup(hw);
2780 /* Get some of the read-only fields from the config BAR */
2781 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2782 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2783 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2784 hw->mtu = ETHER_MTU;
2786 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2787 hw->rx_offset = NFP_NET_RX_OFFSET;
2789 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2791 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2792 hw->ver, hw->max_mtu);
2793 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2794 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2795 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2796 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2797 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2798 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2799 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2800 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2801 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2802 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2803 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2804 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2808 hw->stride_rx = stride;
2809 hw->stride_tx = stride;
2811 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2812 hw->max_rx_queues, hw->max_tx_queues);
2814 /* Initializing spinlock for reconfigs */
2815 rte_spinlock_init(&hw->reconfig_lock);
2817 /* Allocating memory for mac addr */
2818 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2819 if (eth_dev->data->mac_addrs == NULL) {
2820 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2825 nfp_net_pf_read_mac(hwport0, port);
2826 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2828 nfp_net_vf_read_mac(hw);
2831 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2832 /* Using random mac addresses for VFs */
2833 eth_random_addr(&hw->mac_addr[0]);
2834 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2837 /* Copying mac address to DPDK eth_dev struct */
2838 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2839 ð_dev->data->mac_addrs[0]);
2841 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2842 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2843 eth_dev->data->port_id, pci_dev->id.vendor_id,
2844 pci_dev->id.device_id,
2845 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2846 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2848 /* Registering LSC interrupt handler */
2849 rte_intr_callback_register(&pci_dev->intr_handle,
2850 nfp_net_dev_interrupt_handler,
2853 /* Telling the firmware about the LSC interrupt entry */
2854 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2856 /* Recording current stats counters values */
2857 nfp_net_stats_reset(eth_dev);
2863 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2864 nfpu_desc_t *nfpu_desc, void **priv)
2866 struct rte_eth_dev *eth_dev;
2867 struct nfp_net_hw *hw;
2871 port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2876 sprintf(port_name, "%s_port%d", dev->device.name, port);
2878 sprintf(port_name, "%s", dev->device.name);
2880 eth_dev = rte_eth_dev_allocate(port_name);
2885 *priv = rte_zmalloc(port_name,
2886 sizeof(struct nfp_net_adapter) * ports,
2887 RTE_CACHE_LINE_SIZE);
2889 rte_eth_dev_release_port(eth_dev);
2894 eth_dev->data->dev_private = *priv;
2897 * dev_private pointing to port0 dev_private because we need
2898 * to configure vNIC bars based on port0 at nfp_net_init.
2899 * Then dev_private is adjusted per port.
2901 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2902 hw->nspu_desc = nfpu_desc->nspu;
2903 hw->nfpu_desc = nfpu_desc;
2906 hw->pf_multiport_enabled = 1;
2908 eth_dev->device = &dev->device;
2909 rte_eth_copy_pci_info(eth_dev, dev);
2911 ret = nfp_net_init(eth_dev);
2914 rte_eth_dev_release_port(eth_dev);
2916 rte_free(port_name);
2921 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2922 struct rte_pci_device *dev)
2924 nfpu_desc_t *nfpu_desc;
2925 nspu_desc_t *nspu_desc;
2926 uint64_t offset_symbol;
2927 uint8_t *bar_offset;
2937 nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
2941 if (nfpu_open(dev, nfpu_desc, 0) < 0) {
2943 "nfpu_open failed\n");
2947 nspu_desc = nfpu_desc->nspu;
2950 /* Check NSP ABI version */
2951 if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
2952 RTE_LOG(INFO, PMD, "NFP NSP not present\n");
2955 PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
2957 if ((major == 0) && (minor < 20)) {
2958 RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
2962 ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
2967 bar_offset = (uint8_t *)dev->mem_resource[0].addr;
2968 bar_offset += offset_symbol;
2969 total_ports = (uint32_t)*bar_offset;
2970 PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
2972 if (total_ports <= 0 || total_ports > 8) {
2973 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
2978 for (i = 0; i < total_ports; i++) {
2979 ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv);
2987 nfpu_close(nfpu_desc);
2989 rte_free(nfpu_desc);
2994 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
2996 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2997 PCI_DEVICE_ID_NFP4000_PF_NIC)
3000 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3001 PCI_DEVICE_ID_NFP6000_PF_NIC)
3008 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3010 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3011 PCI_DEVICE_ID_NFP6000_VF_NIC)
3018 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3019 struct rte_pci_device *pci_dev)
3021 return rte_eth_dev_pci_generic_probe(pci_dev,
3022 sizeof(struct nfp_net_adapter), nfp_net_init);
3025 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3027 struct rte_eth_dev *eth_dev;
3028 struct nfp_net_hw *hw, *hwport0;
3031 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3032 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3033 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3034 port = get_pf_port_number(eth_dev->data->name);
3035 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3036 hw = &hwport0[port];
3038 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3040 /* hotplug is not possible with multiport PF */
3041 if (hw->pf_multiport_enabled)
3043 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3046 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3047 .id_table = pci_id_nfp_pf_net_map,
3048 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3049 .probe = nfp_pf_pci_probe,
3050 .remove = eth_nfp_pci_remove,
3053 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3054 .id_table = pci_id_nfp_vf_net_map,
3055 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3056 .probe = eth_nfp_pci_probe,
3057 .remove = eth_nfp_pci_remove,
3060 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3061 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3062 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3063 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3064 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3065 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3069 * c-file-style: "Linux"
3070 * indent-tabs-mode: t