2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
48 #include <sys/socket.h>
55 #include <rte_byteorder.h>
56 #include <rte_common.h>
58 #include <rte_debug.h>
59 #include <rte_ethdev.h>
61 #include <rte_ether.h>
62 #include <rte_malloc.h>
63 #include <rte_memzone.h>
64 #include <rte_mempool.h>
65 #include <rte_version.h>
66 #include <rte_string_fns.h>
67 #include <rte_alarm.h>
69 #include "nfp_net_pmd.h"
70 #include "nfp_net_logs.h"
71 #include "nfp_net_ctrl.h"
74 static void nfp_net_close(struct rte_eth_dev *dev);
75 static int nfp_net_configure(struct rte_eth_dev *dev);
76 static int nfp_net_init(struct rte_eth_dev *eth_dev);
77 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
78 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
79 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
81 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
83 static void nfp_net_rx_queue_release(void *rxq);
84 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
85 uint16_t nb_desc, unsigned int socket_id,
86 const struct rte_eth_rxconf *rx_conf,
87 struct rte_mempool *mp);
88 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
89 static void nfp_net_tx_queue_release(void *txq);
90 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
91 uint16_t nb_desc, unsigned int socket_id,
92 const struct rte_eth_txconf *tx_conf);
93 static int nfp_net_start(struct rte_eth_dev *dev);
94 static void nfp_net_stats_get(struct rte_eth_dev *dev,
95 struct rte_eth_stats *stats);
96 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
97 static void nfp_net_stop(struct rte_eth_dev *dev);
98 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
102 * The offset of the queue controller queues in the PCIe Target. These
103 * happen to be at the same offset on the NFP6000 and the NFP3200 so
104 * we use a single macro here.
106 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
108 /* Maximum value which can be added to a queue with one transaction */
109 #define NFP_QCP_MAX_ADD 0x7f
111 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
112 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
114 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
116 NFP_QCP_READ_PTR = 0,
121 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
122 * @q: Base address for queue structure
123 * @ptr: Add to the Read or Write pointer
124 * @val: Value to add to the queue pointer
126 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
129 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
133 if (ptr == NFP_QCP_READ_PTR)
134 off = NFP_QCP_QUEUE_ADD_RPTR;
136 off = NFP_QCP_QUEUE_ADD_WPTR;
138 while (val > NFP_QCP_MAX_ADD) {
139 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
140 val -= NFP_QCP_MAX_ADD;
143 nn_writel(rte_cpu_to_le_32(val), q + off);
147 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
148 * @q: Base address for queue structure
149 * @ptr: Read or Write pointer
151 static inline uint32_t
152 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
157 if (ptr == NFP_QCP_READ_PTR)
158 off = NFP_QCP_QUEUE_STS_LO;
160 off = NFP_QCP_QUEUE_STS_HI;
162 val = rte_cpu_to_le_32(nn_readl(q + off));
164 if (ptr == NFP_QCP_READ_PTR)
165 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
167 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
171 * Functions to read/write from/to Config BAR
172 * Performs any endian conversion necessary.
174 static inline uint8_t
175 nn_cfg_readb(struct nfp_net_hw *hw, int off)
177 return nn_readb(hw->ctrl_bar + off);
181 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
183 nn_writeb(val, hw->ctrl_bar + off);
186 static inline uint32_t
187 nn_cfg_readl(struct nfp_net_hw *hw, int off)
189 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
193 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
195 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
198 static inline uint64_t
199 nn_cfg_readq(struct nfp_net_hw *hw, int off)
201 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
205 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
207 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
210 /* Creating memzone for hardware rings. */
211 static const struct rte_memzone *
212 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
213 uint16_t queue_id, uint32_t ring_size, int socket_id)
215 char z_name[RTE_MEMZONE_NAMESIZE];
216 const struct rte_memzone *mz;
218 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
219 dev->driver->pci_drv.name,
220 ring_name, dev->data->port_id, queue_id);
222 mz = rte_memzone_lookup(z_name);
226 return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
231 * Atomically reads link status information from global structure rte_eth_dev.
234 * - Pointer to the structure rte_eth_dev to read from.
235 * - Pointer to the buffer to be saved with the link status.
238 * - On success, zero.
239 * - On failure, negative value.
242 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
243 struct rte_eth_link *link)
245 struct rte_eth_link *dst = link;
246 struct rte_eth_link *src = &dev->data->dev_link;
248 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
249 *(uint64_t *)src) == 0)
256 * Atomically writes the link status information into global
257 * structure rte_eth_dev.
260 * - Pointer to the structure rte_eth_dev to read from.
261 * - Pointer to the buffer to be saved with the link status.
264 * - On success, zero.
265 * - On failure, negative value.
268 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
269 struct rte_eth_link *link)
271 struct rte_eth_link *dst = &dev->data->dev_link;
272 struct rte_eth_link *src = link;
274 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
275 *(uint64_t *)src) == 0)
282 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
286 if (rxq->rxbufs == NULL)
289 for (i = 0; i < rxq->rx_count; i++) {
290 if (rxq->rxbufs[i].mbuf) {
291 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
292 rxq->rxbufs[i].mbuf = NULL;
298 nfp_net_rx_queue_release(void *rx_queue)
300 struct nfp_net_rxq *rxq = rx_queue;
303 nfp_net_rx_queue_release_mbufs(rxq);
304 rte_free(rxq->rxbufs);
310 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
312 nfp_net_rx_queue_release_mbufs(rxq);
319 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
323 if (txq->txbufs == NULL)
326 for (i = 0; i < txq->tx_count; i++) {
327 if (txq->txbufs[i].mbuf) {
328 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
329 txq->txbufs[i].mbuf = NULL;
335 nfp_net_tx_queue_release(void *tx_queue)
337 struct nfp_net_txq *txq = tx_queue;
340 nfp_net_tx_queue_release_mbufs(txq);
341 rte_free(txq->txbufs);
347 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
349 nfp_net_tx_queue_release_mbufs(txq);
356 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
360 struct timespec wait;
362 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
365 if (hw->qcp_cfg == NULL)
366 rte_panic("Bad configuration queue pointer\n");
368 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
371 wait.tv_nsec = 1000000;
373 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
375 /* Poll update field, waiting for NFP to ack the config */
376 for (cnt = 0; ; cnt++) {
377 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
380 if (new & NFP_NET_CFG_UPDATE_ERR) {
381 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x\n", new);
384 if (cnt >= NFP_NET_POLL_TIMEOUT) {
385 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
386 " %dms\n", update, cnt);
387 rte_panic("Exiting\n");
389 nanosleep(&wait, 0); /* waiting for a 1ms */
391 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
396 * Reconfigure the NIC
397 * @nn: device to reconfigure
398 * @ctrl: The value for the ctrl field in the BAR config
399 * @update: The value for the update field in the BAR config
401 * Write the update word to the BAR and ping the reconfig queue. Then poll
402 * until the firmware has acknowledged the update by zeroing the update word.
405 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
409 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
412 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
413 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
417 err = __nfp_net_reconfig(hw, update);
423 * Reconfig errors imply situations where they can be handled.
424 * Otherwise, rte_panic is called inside __nfp_net_reconfig
426 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x\n",
432 * Configure an Ethernet device. This function must be invoked first
433 * before any other function in the Ethernet API. This function can
434 * also be re-invoked when a device is in the stopped state.
437 nfp_net_configure(struct rte_eth_dev *dev)
439 struct rte_eth_conf *dev_conf;
440 struct rte_eth_rxmode *rxmode;
441 struct rte_eth_txmode *txmode;
442 uint32_t new_ctrl = 0;
444 struct nfp_net_hw *hw;
446 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
449 * A DPDK app sends info about how many queues to use and how
450 * those queues need to be configured. This is used by the
451 * DPDK core and it makes sure no more queues than those
452 * advertised by the driver are requested. This function is
453 * called after that internal process
456 PMD_INIT_LOG(DEBUG, "Configure\n");
458 dev_conf = &dev->data->dev_conf;
459 rxmode = &dev_conf->rxmode;
460 txmode = &dev_conf->txmode;
462 /* Checking TX mode */
463 if (txmode->mq_mode) {
464 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported\n");
468 /* Checking RX mode */
469 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
470 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
471 update = NFP_NET_CFG_UPDATE_RSS;
472 new_ctrl = NFP_NET_CFG_CTRL_RSS;
474 PMD_INIT_LOG(INFO, "RSS not supported\n");
479 if (rxmode->split_hdr_size) {
480 PMD_INIT_LOG(INFO, "rxmode does not support split header\n");
484 if (rxmode->hw_ip_checksum) {
485 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
486 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
488 PMD_INIT_LOG(INFO, "RXCSUM not supported\n");
493 if (rxmode->hw_vlan_filter) {
494 PMD_INIT_LOG(INFO, "VLAN filter not supported\n");
498 if (rxmode->hw_vlan_strip) {
499 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
500 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
502 PMD_INIT_LOG(INFO, "hw vlan strip not supported\n");
507 if (rxmode->hw_vlan_extend) {
508 PMD_INIT_LOG(INFO, "VLAN extended not supported\n");
512 /* Supporting VLAN insertion by default */
513 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
514 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
516 if (rxmode->jumbo_frame)
517 /* this is handled in rte_eth_dev_configure */
519 if (rxmode->hw_strip_crc) {
520 PMD_INIT_LOG(INFO, "strip CRC not supported\n");
524 if (rxmode->enable_scatter) {
525 PMD_INIT_LOG(INFO, "Scatter not supported\n");
532 update |= NFP_NET_CFG_UPDATE_GEN;
534 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
535 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
544 nfp_net_enable_queues(struct rte_eth_dev *dev)
546 struct nfp_net_hw *hw;
547 uint64_t enabled_queues = 0;
550 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
552 /* Enabling the required TX queues in the device */
553 for (i = 0; i < dev->data->nb_tx_queues; i++)
554 enabled_queues |= (1 << i);
556 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
560 /* Enabling the required RX queues in the device */
561 for (i = 0; i < dev->data->nb_rx_queues; i++)
562 enabled_queues |= (1 << i);
564 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
568 nfp_net_disable_queues(struct rte_eth_dev *dev)
570 struct nfp_net_hw *hw;
571 uint32_t new_ctrl, update = 0;
573 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
575 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
576 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
578 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
579 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
580 NFP_NET_CFG_UPDATE_MSIX;
582 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
583 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
585 /* If an error when reconfig we avoid to change hw state */
586 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
593 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
597 for (i = 0; i < dev->data->nb_rx_queues; i++) {
598 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
605 nfp_net_params_setup(struct nfp_net_hw *hw)
607 uint32_t *mac_address;
609 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
610 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
612 /* A MAC address is 8 bytes long */
613 mac_address = (uint32_t *)(hw->mac_addr);
615 nn_cfg_writel(hw, NFP_NET_CFG_MACADDR,
616 rte_cpu_to_be_32(*mac_address));
617 nn_cfg_writel(hw, NFP_NET_CFG_MACADDR + 4,
618 rte_cpu_to_be_32(*(mac_address + 4)));
622 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
624 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
628 nfp_net_start(struct rte_eth_dev *dev)
630 uint32_t new_ctrl, update = 0;
631 struct nfp_net_hw *hw;
634 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
636 PMD_INIT_LOG(DEBUG, "Start\n");
638 /* Disabling queues just in case... */
639 nfp_net_disable_queues(dev);
641 /* Writing configuration parameters in the device */
642 nfp_net_params_setup(hw);
644 /* Enabling the required queues in the device */
645 nfp_net_enable_queues(dev);
648 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE | NFP_NET_CFG_UPDATE_MSIX;
649 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
651 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
652 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
654 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
655 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
659 * Allocating rte mbuffs for configured rx queues.
660 * This requires queues being enabled before
662 if (nfp_net_rx_freelist_setup(dev) < 0) {
673 * An error returned by this function should mean the app
674 * exiting and then the system releasing all the memory
675 * allocated even memory coming from hugepages.
677 * The device could be enabled at this point with some queues
678 * ready for getting packets. This is true if the call to
679 * nfp_net_rx_freelist_setup() succeeds for some queues but
680 * fails for subsequent queues.
682 * This should make the app exiting but better if we tell the
685 nfp_net_disable_queues(dev);
690 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
692 nfp_net_stop(struct rte_eth_dev *dev)
696 PMD_INIT_LOG(DEBUG, "Stop\n");
698 nfp_net_disable_queues(dev);
701 for (i = 0; i < dev->data->nb_tx_queues; i++) {
702 nfp_net_reset_tx_queue(
703 (struct nfp_net_txq *)dev->data->tx_queues[i]);
706 for (i = 0; i < dev->data->nb_rx_queues; i++) {
707 nfp_net_reset_rx_queue(
708 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
712 /* Reset and stop device. The device can not be restarted. */
714 nfp_net_close(struct rte_eth_dev *dev)
716 struct nfp_net_hw *hw;
718 PMD_INIT_LOG(DEBUG, "Close\n");
720 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
723 * We assume that the DPDK application is stopping all the
724 * threads/queues before calling the device close function.
729 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
732 * The ixgbe PMD driver disables the pcie master on the
733 * device. The i40e does not...
738 * return 0 means link status changed, -1 means not changed
740 * Wait to complete is needed as it can take up to 9 seconds to get the Link
744 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
746 struct nfp_net_hw *hw;
747 struct rte_eth_link link, old;
748 uint32_t nn_link_status;
750 PMD_DRV_LOG(DEBUG, "Link update\n");
752 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
754 memset(&old, 0, sizeof(old));
755 nfp_net_dev_atomic_read_link_status(dev, &old);
757 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
759 memset(&link, 0, sizeof(struct rte_eth_link));
761 if (nn_link_status & NFP_NET_CFG_STS_LINK)
762 link.link_status = 1;
764 link.link_duplex = ETH_LINK_FULL_DUPLEX;
765 /* Other cards can limit the tx and rx rate per VF */
766 link.link_speed = ETH_LINK_SPEED_40G;
768 if (old.link_status != link.link_status) {
769 nfp_net_dev_atomic_write_link_status(dev, &link);
770 if (link.link_status)
771 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
773 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
781 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
784 struct nfp_net_hw *hw;
785 struct rte_eth_stats nfp_dev_stats;
787 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
789 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
791 /* reading per RX ring stats */
792 for (i = 0; i < dev->data->nb_rx_queues; i++) {
793 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
796 nfp_dev_stats.q_ipackets[i] =
797 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
799 nfp_dev_stats.q_ipackets[i] -=
800 hw->eth_stats_base.q_ipackets[i];
802 nfp_dev_stats.q_ibytes[i] =
803 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
805 nfp_dev_stats.q_ibytes[i] -=
806 hw->eth_stats_base.q_ibytes[i];
809 /* reading per TX ring stats */
810 for (i = 0; i < dev->data->nb_tx_queues; i++) {
811 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
814 nfp_dev_stats.q_opackets[i] =
815 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
817 nfp_dev_stats.q_opackets[i] -=
818 hw->eth_stats_base.q_opackets[i];
820 nfp_dev_stats.q_obytes[i] =
821 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
823 nfp_dev_stats.q_obytes[i] -=
824 hw->eth_stats_base.q_obytes[i];
827 nfp_dev_stats.ipackets =
828 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
830 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
832 nfp_dev_stats.ibytes =
833 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
835 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
837 nfp_dev_stats.opackets =
838 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
840 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
842 nfp_dev_stats.obytes =
843 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
845 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
847 nfp_dev_stats.imcasts =
848 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
850 nfp_dev_stats.imcasts -= hw->eth_stats_base.imcasts;
852 /* reading general device stats */
853 nfp_dev_stats.ierrors =
854 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
856 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
858 nfp_dev_stats.oerrors =
859 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
861 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
863 /* Multicast frames received */
864 nfp_dev_stats.imcasts =
865 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
867 nfp_dev_stats.imcasts -= hw->eth_stats_base.imcasts;
869 /* RX ring mbuf allocation failures */
870 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
872 nfp_dev_stats.imissed =
873 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
875 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
878 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
882 nfp_net_stats_reset(struct rte_eth_dev *dev)
885 struct nfp_net_hw *hw;
887 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
890 * hw->eth_stats_base records the per counter starting point.
894 /* reading per RX ring stats */
895 for (i = 0; i < dev->data->nb_rx_queues; i++) {
896 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
899 hw->eth_stats_base.q_ipackets[i] =
900 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
902 hw->eth_stats_base.q_ibytes[i] =
903 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
906 /* reading per TX ring stats */
907 for (i = 0; i < dev->data->nb_tx_queues; i++) {
908 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
911 hw->eth_stats_base.q_opackets[i] =
912 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
914 hw->eth_stats_base.q_obytes[i] =
915 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
918 hw->eth_stats_base.ipackets =
919 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
921 hw->eth_stats_base.ibytes =
922 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
924 hw->eth_stats_base.opackets =
925 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
927 hw->eth_stats_base.obytes =
928 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
930 hw->eth_stats_base.imcasts =
931 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
933 /* reading general device stats */
934 hw->eth_stats_base.ierrors =
935 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
937 hw->eth_stats_base.oerrors =
938 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
940 /* Multicast frames received */
941 hw->eth_stats_base.imcasts =
942 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
944 /* RX ring mbuf allocation failures */
945 dev->data->rx_mbuf_alloc_failed = 0;
947 hw->eth_stats_base.imissed =
948 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
952 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
954 struct nfp_net_rxq *rxq;
955 struct nfp_net_rx_desc *rxds;
959 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
962 PMD_INIT_LOG(ERR, "Bad queue: %u\n", queue_idx);
966 idx = rxq->rd_p % rxq->rx_count;
967 rxds = &rxq->rxds[idx];
972 * Other PMDs are just checking the DD bit in intervals of 4
973 * descriptors and counting all four if the first has the DD
974 * bit on. Of course, this is not accurate but can be good for
975 * perfomance. But ideally that should be done in descriptors
976 * chunks belonging to the same cache line
979 while (count < rxq->rx_count) {
980 rxds = &rxq->rxds[idx];
981 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
988 if ((idx) == rxq->rx_count)
996 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
997 uint16_t queue_idx, uint16_t nb_desc,
998 unsigned int socket_id,
999 const struct rte_eth_rxconf *rx_conf,
1000 struct rte_mempool *mp)
1002 const struct rte_memzone *tz;
1003 struct nfp_net_rxq *rxq;
1004 struct nfp_net_hw *hw;
1006 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1008 PMD_INIT_FUNC_TRACE();
1010 /* Validating number of descriptors */
1011 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1012 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1013 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1014 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1019 * Free memory prior to re-allocation if needed. This is the case after
1020 * calling nfp_net_stop
1022 if (dev->data->rx_queues[queue_idx]) {
1023 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1024 dev->data->rx_queues[queue_idx] = NULL;
1027 /* Allocating rx queue data structure */
1028 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1029 RTE_CACHE_LINE_SIZE, socket_id);
1033 /* Hw queues mapping based on firmware confifguration */
1034 rxq->qidx = queue_idx;
1035 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1036 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1037 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1038 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1041 * Tracking mbuf size for detecting a potential mbuf overflow due to
1045 rxq->mbuf_size = rxq->mem_pool->elt_size;
1046 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1047 hw->flbufsz = rxq->mbuf_size;
1049 rxq->rx_count = nb_desc;
1050 rxq->port_id = dev->data->port_id;
1051 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1052 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1054 rxq->drop_en = rx_conf->rx_drop_en;
1057 * Allocate RX ring hardware descriptors. A memzone large enough to
1058 * handle the maximum ring size is allocated in order to allow for
1059 * resizing in later calls to the queue setup function.
1061 tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1062 sizeof(struct nfp_net_rx_desc) *
1063 NFP_NET_MAX_RX_DESC, socket_id);
1066 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1067 nfp_net_rx_queue_release(rxq);
1071 /* Saving physical and virtual addresses for the RX ring */
1072 rxq->dma = (uint64_t)tz->phys_addr;
1073 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1075 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1076 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1077 sizeof(*rxq->rxbufs) * nb_desc,
1078 RTE_CACHE_LINE_SIZE, socket_id);
1079 if (rxq->rxbufs == NULL) {
1080 nfp_net_rx_queue_release(rxq);
1084 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1085 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1087 nfp_net_reset_rx_queue(rxq);
1089 dev->data->rx_queues[queue_idx] = rxq;
1093 * Telling the HW about the physical address of the RX ring and number
1094 * of descriptors in log2 format
1096 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1097 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1103 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1105 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1109 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1112 for (i = 0; i < rxq->rx_count; i++) {
1113 struct nfp_net_rx_desc *rxd;
1114 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1117 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1118 (unsigned)rxq->qidx);
1122 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1124 rxd = &rxq->rxds[i];
1126 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1127 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1129 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1134 /* Make sure all writes are flushed before telling the hardware */
1137 /* Not advertising the whole ring as the firmware gets confused if so */
1138 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1141 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1147 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1148 uint16_t nb_desc, unsigned int socket_id,
1149 const struct rte_eth_txconf *tx_conf)
1151 const struct rte_memzone *tz;
1152 struct nfp_net_txq *txq;
1153 uint16_t tx_free_thresh;
1154 struct nfp_net_hw *hw;
1156 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1158 PMD_INIT_FUNC_TRACE();
1160 /* Validating number of descriptors */
1161 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1162 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1163 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1164 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1168 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1169 tx_conf->tx_free_thresh :
1170 DEFAULT_TX_FREE_THRESH);
1172 if (tx_free_thresh > (nb_desc)) {
1174 "tx_free_thresh must be less than the number of TX "
1175 "descriptors. (tx_free_thresh=%u port=%d "
1176 "queue=%d)\n", (unsigned int)tx_free_thresh,
1177 (int)dev->data->port_id, (int)queue_idx);
1182 * Free memory prior to re-allocation if needed. This is the case after
1183 * calling nfp_net_stop
1185 if (dev->data->tx_queues[queue_idx]) {
1186 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1188 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1189 dev->data->tx_queues[queue_idx] = NULL;
1192 /* Allocating tx queue data structure */
1193 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1194 RTE_CACHE_LINE_SIZE, socket_id);
1196 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1201 * Allocate TX ring hardware descriptors. A memzone large enough to
1202 * handle the maximum ring size is allocated in order to allow for
1203 * resizing in later calls to the queue setup function.
1205 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1206 sizeof(struct nfp_net_tx_desc) *
1207 NFP_NET_MAX_TX_DESC, socket_id);
1209 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1210 nfp_net_tx_queue_release(txq);
1214 txq->tx_count = nb_desc;
1216 txq->tx_free_thresh = tx_free_thresh;
1217 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1218 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1219 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1221 /* queue mapping based on firmware configuration */
1222 txq->qidx = queue_idx;
1223 txq->tx_qcidx = queue_idx * hw->stride_tx;
1224 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1226 txq->port_id = dev->data->port_id;
1227 txq->txq_flags = tx_conf->txq_flags;
1229 /* Saving physical and virtual addresses for the TX ring */
1230 txq->dma = (uint64_t)tz->phys_addr;
1231 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1233 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1234 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1235 sizeof(*txq->txbufs) * nb_desc,
1236 RTE_CACHE_LINE_SIZE, socket_id);
1237 if (txq->txbufs == NULL) {
1238 nfp_net_tx_queue_release(txq);
1241 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1242 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1244 nfp_net_reset_tx_queue(txq);
1246 dev->data->tx_queues[queue_idx] = txq;
1250 * Telling the HW about the physical address of the TX ring and number
1251 * of descriptors in log2 format
1253 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1254 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1259 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1261 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1262 struct rte_mbuf *mb)
1265 struct nfp_net_hw *hw = txq->hw;
1267 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1270 ol_flags = mb->ol_flags;
1272 /* IPv6 does not need checksum */
1273 if (ol_flags & PKT_TX_IP_CKSUM)
1274 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1276 switch (ol_flags & PKT_TX_L4_MASK) {
1277 case PKT_TX_UDP_CKSUM:
1278 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1280 case PKT_TX_TCP_CKSUM:
1281 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1285 txd->flags |= PCIE_DESC_TX_CSUM;
1288 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1290 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1291 struct rte_mbuf *mb)
1293 struct nfp_net_hw *hw = rxq->hw;
1295 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1298 /* If IPv4 and IP checksum error, fail */
1299 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1300 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1301 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1303 /* If neither UDP nor TCP return */
1304 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1305 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1308 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1309 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1310 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1312 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1313 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1314 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1317 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1318 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1321 * nfp_net_set_hash - Set mbuf hash data
1323 * The RSS hash and hash-type are pre-pended to the packet data.
1324 * Extract and decode it and set the mbuf fields.
1327 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1328 struct rte_mbuf *mbuf)
1332 struct nfp_net_hw *hw = rxq->hw;
1334 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1337 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1340 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1341 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1344 * hash type is sharing the same word with input port info
1349 mbuf->hash.rss = hash;
1350 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1352 switch (hash_type) {
1353 case NFP_NET_RSS_IPV4:
1354 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1356 case NFP_NET_RSS_IPV6:
1357 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1359 case NFP_NET_RSS_IPV6_EX:
1360 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1363 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1367 /* nfp_net_check_port - Set mbuf in_port field */
1369 nfp_net_check_port(struct nfp_net_rx_desc *rxd, struct rte_mbuf *mbuf)
1373 if (!(rxd->rxd.flags & PCIE_DESC_RX_INGRESS_PORT)) {
1378 port = rte_be_to_cpu_32(*(uint32_t *)((uint8_t *)mbuf->buf_addr +
1379 mbuf->data_off - 8));
1382 * hash type is sharing the same word with input port info
1386 port = (uint8_t)(port >> 8);
1391 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1393 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1396 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1401 * There are some decissions to take:
1402 * 1) How to check DD RX descriptors bit
1403 * 2) How and when to allocate new mbufs
1405 * Current implementation checks just one single DD bit each loop. As each
1406 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1407 * a single cache line instead. Tests with this change have not shown any
1408 * performance improvement but it requires further investigation. For example,
1409 * depending on which descriptor is next, the number of descriptors could be
1410 * less than 8 for just checking those in the same cache line. This implies
1411 * extra work which could be counterproductive by itself. Indeed, last firmware
1412 * changes are just doing this: writing several descriptors with the DD bit
1413 * for saving PCIe bandwidth and DMA operations from the NFP.
1415 * Mbuf allocation is done when a new packet is received. Then the descriptor
1416 * is automatically linked with the new mbuf and the old one is given to the
1417 * user. The main drawback with this design is mbuf allocation is heavier than
1418 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1419 * cache point of view it does not seem allocating the mbuf early on as we are
1420 * doing now have any benefit at all. Again, tests with this change have not
1421 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1422 * so looking at the implications of this type of allocation should be studied
1427 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1429 struct nfp_net_rxq *rxq;
1430 struct nfp_net_rx_desc *rxds;
1431 struct nfp_net_rx_buff *rxb;
1432 struct nfp_net_hw *hw;
1433 struct rte_mbuf *mb;
1434 struct rte_mbuf *new_mb;
1441 if (unlikely(rxq == NULL)) {
1443 * DPDK just checks the queue is lower than max queues
1444 * enabled. But the queue needs to be configured
1446 RTE_LOG(ERR, PMD, "RX Bad queue\n");
1454 while (avail < nb_pkts) {
1455 idx = rxq->rd_p % rxq->rx_count;
1457 rxb = &rxq->rxbufs[idx];
1458 if (unlikely(rxb == NULL)) {
1459 RTE_LOG(ERR, PMD, "rxb does not exist!\n");
1464 * Memory barrier to ensure that we won't do other
1465 * reads before the DD bit.
1469 rxds = &rxq->rxds[idx];
1470 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1474 * We got a packet. Let's alloc a new mbuff for refilling the
1475 * free descriptor ring as soon as possible
1477 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1478 if (unlikely(new_mb == NULL)) {
1479 RTE_LOG(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1480 "queue_id=%u\n", (unsigned)rxq->port_id,
1481 (unsigned)rxq->qidx);
1482 nfp_net_mbuf_alloc_failed(rxq);
1489 * Grab the mbuff and refill the descriptor with the
1490 * previously allocated mbuff
1495 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1496 rxds->rxd.data_len, rxq->mbuf_size);
1498 /* Size of this segment */
1499 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1500 /* Size of the whole packet. We just support 1 segment */
1501 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1503 if (unlikely((mb->data_len + hw->rx_offset) >
1506 * This should not happen and the user has the
1507 * responsibility of avoiding it. But we have
1508 * to give some info about the error
1511 "mbuf overflow likely due to the RX offset.\n"
1512 "\t\tYour mbuf size should have extra space for"
1513 " RX offset=%u bytes.\n"
1514 "\t\tCurrently you just have %u bytes available"
1515 " but the received packet is %u bytes long",
1517 rxq->mbuf_size - hw->rx_offset,
1522 /* Filling the received mbuff with packet info */
1524 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1526 mb->data_off = RTE_PKTMBUF_HEADROOM +
1527 NFP_DESC_META_LEN(rxds);
1529 /* No scatter mode supported */
1533 /* Checking the RSS flag */
1534 nfp_net_set_hash(rxq, rxds, mb);
1536 /* Checking the checksum flag */
1537 nfp_net_rx_cksum(rxq, rxds, mb);
1539 /* Checking the port flag */
1540 nfp_net_check_port(rxds, mb);
1542 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1543 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1544 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1545 mb->ol_flags |= PKT_RX_VLAN_PKT;
1548 /* Adding the mbuff to the mbuff array passed by the app */
1549 rx_pkts[avail++] = mb;
1551 /* Now resetting and updating the descriptor */
1554 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1556 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1557 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1565 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1566 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1568 nb_hold += rxq->nb_rx_hold;
1571 * FL descriptors needs to be written before incrementing the
1572 * FL queue WR pointer
1575 if (nb_hold > rxq->rx_free_thresh) {
1576 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1577 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1578 (unsigned)nb_hold, (unsigned)avail);
1579 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1582 rxq->nb_rx_hold = nb_hold;
1588 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1590 * @txq: TX queue to work with
1591 * Returns number of descriptors freed
1594 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1599 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1600 " status\n", txq->qidx);
1602 /* Work out how many packets have been sent */
1603 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1605 if (qcp_rd_p == txq->qcp_rd_p) {
1606 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1607 "packets (%u, %u)\n", txq->qidx,
1608 qcp_rd_p, txq->qcp_rd_p);
1612 if (qcp_rd_p > txq->qcp_rd_p)
1613 todo = qcp_rd_p - txq->qcp_rd_p;
1615 todo = qcp_rd_p + txq->tx_count - txq->qcp_rd_p;
1617 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->qcp_rd_p: %u, qcp->rd_p: %u\n",
1618 qcp_rd_p, txq->qcp_rd_p, txq->rd_p);
1623 txq->qcp_rd_p += todo;
1624 txq->qcp_rd_p %= txq->tx_count;
1630 /* Leaving always free descriptors for avoiding wrapping confusion */
1631 #define NFP_FREE_TX_DESC(t) (t->tx_count - (t->wr_p - t->rd_p) - 8)
1634 * nfp_net_txq_full - Check if the TX queue free descriptors
1635 * is below tx_free_threshold
1637 * @txq: TX queue to check
1639 * This function uses the host copy* of read/write pointers
1642 int nfp_net_txq_full(struct nfp_net_txq *txq)
1644 return NFP_FREE_TX_DESC(txq) < txq->tx_free_thresh;
1648 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1650 struct nfp_net_txq *txq;
1651 struct nfp_net_hw *hw;
1652 struct nfp_net_tx_desc *txds;
1653 struct rte_mbuf *pkt;
1655 int pkt_size, dma_size;
1656 uint16_t free_descs, issued_descs;
1657 struct rte_mbuf **lmbuf;
1662 txds = &txq->txds[txq->tail];
1664 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
1665 txq->qidx, txq->tail, nb_pkts);
1667 if ((NFP_FREE_TX_DESC(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
1668 nfp_net_tx_free_bufs(txq);
1670 free_descs = (uint16_t)NFP_FREE_TX_DESC(txq);
1671 if (unlikely(free_descs == 0))
1678 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
1679 txq->qidx, nb_pkts);
1680 /* Sending packets */
1681 while ((i < nb_pkts) && free_descs) {
1682 /* Grabbing the mbuf linked to the current descriptor */
1683 lmbuf = &txq->txbufs[txq->tail].mbuf;
1684 /* Warming the cache for releasing the mbuf later on */
1685 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
1687 pkt = *(tx_pkts + i);
1689 if (unlikely((pkt->nb_segs > 1) &&
1690 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
1691 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set\n");
1692 rte_panic("Multisegment packet unsupported\n");
1695 /* Checking if we have enough descriptors */
1696 if (unlikely(pkt->nb_segs > free_descs))
1700 * Checksum and VLAN flags just in the first descriptor for a
1701 * multisegment packet
1703 nfp_net_tx_cksum(txq, txds, pkt);
1705 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
1706 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
1707 txds->flags |= PCIE_DESC_TX_VLAN;
1708 txds->vlan = pkt->vlan_tci;
1711 if (pkt->ol_flags & PKT_TX_TCP_SEG)
1712 rte_panic("TSO is not supported\n");
1715 * mbuf data_len is the data in one segment and pkt_len data
1716 * in the whole packet. When the packet is just one segment,
1717 * then data_len = pkt_len
1719 pkt_size = pkt->pkt_len;
1722 /* Releasing mbuf which was prefetched above */
1724 rte_pktmbuf_free_seg(*lmbuf);
1726 dma_size = pkt->data_len;
1727 dma_addr = RTE_MBUF_DATA_DMA_ADDR(pkt);
1728 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
1729 "%" PRIx64 "\n", dma_addr);
1731 /* Filling descriptors fields */
1732 txds->dma_len = dma_size;
1733 txds->data_len = pkt->pkt_len;
1734 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
1735 txds->dma_addr_lo = (dma_addr & 0xffffffff);
1736 ASSERT(free_descs > 0);
1740 * Linking mbuf with descriptor for being released
1741 * next time descriptor is used
1747 if (unlikely(txq->tail == txq->tx_count)) /* wrapping?*/
1750 pkt_size -= dma_size;
1753 txds->offset_eop |= PCIE_DESC_TX_EOP;
1755 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
1758 /* Referencing next free TX descriptor */
1759 txds = &txq->txds[txq->tail];
1766 /* Increment write pointers. Force memory write before we let HW know */
1768 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
1773 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
1775 nfp_net_reta_update(struct rte_eth_dev *dev,
1776 struct rte_eth_rss_reta_entry64 *reta_conf,
1779 uint32_t reta, mask;
1783 struct nfp_net_hw *hw =
1784 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1786 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1789 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
1790 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
1791 "(%d) doesn't match the number hardware can supported "
1792 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
1797 * Update Redirection Table. There are 128 8bit-entries which can be
1798 * manage as 32 32bit-entries
1800 for (i = 0; i < reta_size; i += 4) {
1801 /* Handling 4 RSS entries per loop */
1802 idx = i / RTE_RETA_GROUP_SIZE;
1803 shift = i % RTE_RETA_GROUP_SIZE;
1804 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
1810 /* If all 4 entries were set, don't need read RETA register */
1812 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
1814 for (j = 0; j < 4; j++) {
1815 if (!(mask & (0x1 << j)))
1818 /* Clearing the entry bits */
1819 reta &= ~(0xFF << (8 * j));
1820 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
1822 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
1825 update = NFP_NET_CFG_UPDATE_RSS;
1827 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
1833 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
1835 nfp_net_reta_query(struct rte_eth_dev *dev,
1836 struct rte_eth_rss_reta_entry64 *reta_conf,
1842 struct nfp_net_hw *hw;
1844 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1846 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1849 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
1850 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
1851 "(%d) doesn't match the number hardware can supported "
1852 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
1857 * Reading Redirection Table. There are 128 8bit-entries which can be
1858 * manage as 32 32bit-entries
1860 for (i = 0; i < reta_size; i += 4) {
1861 /* Handling 4 RSS entries per loop */
1862 idx = i / RTE_RETA_GROUP_SIZE;
1863 shift = i % RTE_RETA_GROUP_SIZE;
1864 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
1869 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
1870 for (j = 0; j < 4; j++) {
1871 if (!(mask & (0x1 << j)))
1873 reta_conf->reta[shift + j] =
1874 (uint8_t)((reta >> (8 * j)) & 0xF);
1881 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
1882 struct rte_eth_rss_conf *rss_conf)
1885 uint32_t cfg_rss_ctrl = 0;
1889 struct nfp_net_hw *hw;
1891 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1893 rss_hf = rss_conf->rss_hf;
1895 /* Checking if RSS is enabled */
1896 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
1897 if (rss_hf != 0) { /* Enable RSS? */
1898 RTE_LOG(ERR, PMD, "RSS unsupported\n");
1901 return 0; /* Nothing to do */
1904 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
1905 RTE_LOG(ERR, PMD, "hash key too long\n");
1909 if (rss_hf & ETH_RSS_IPV4)
1910 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
1911 NFP_NET_CFG_RSS_IPV4_TCP |
1912 NFP_NET_CFG_RSS_IPV4_UDP;
1914 if (rss_hf & ETH_RSS_IPV6)
1915 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
1916 NFP_NET_CFG_RSS_IPV6_TCP |
1917 NFP_NET_CFG_RSS_IPV6_UDP;
1919 /* configuring where to apply the RSS hash */
1920 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
1922 /* Writing the key byte a byte */
1923 for (i = 0; i < rss_conf->rss_key_len; i++) {
1924 memcpy(&key, &rss_conf->rss_key[i], 1);
1925 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
1928 /* Writing the key size */
1929 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
1931 update = NFP_NET_CFG_UPDATE_RSS;
1933 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
1940 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
1941 struct rte_eth_rss_conf *rss_conf)
1944 uint32_t cfg_rss_ctrl;
1947 struct nfp_net_hw *hw;
1949 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1954 rss_hf = rss_conf->rss_hf;
1955 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
1957 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
1958 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
1960 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
1961 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1963 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
1964 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1966 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
1967 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1969 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
1970 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1972 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
1973 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
1975 /* Reading the key size */
1976 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
1978 /* Reading the key byte a byte */
1979 for (i = 0; i < rss_conf->rss_key_len; i++) {
1980 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
1981 memcpy(&rss_conf->rss_key[i], &key, 1);
1987 /* Initialise and register driver with DPDK Application */
1988 static struct eth_dev_ops nfp_net_eth_dev_ops = {
1989 .dev_configure = nfp_net_configure,
1990 .dev_start = nfp_net_start,
1991 .dev_stop = nfp_net_stop,
1992 .dev_close = nfp_net_close,
1993 .link_update = nfp_net_link_update,
1994 .stats_get = nfp_net_stats_get,
1995 .stats_reset = nfp_net_stats_reset,
1996 .reta_update = nfp_net_reta_update,
1997 .reta_query = nfp_net_reta_query,
1998 .rss_hash_update = nfp_net_rss_hash_update,
1999 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2000 .rx_queue_setup = nfp_net_rx_queue_setup,
2001 .rx_queue_release = nfp_net_rx_queue_release,
2002 .rx_queue_count = nfp_net_rx_queue_count,
2003 .tx_queue_setup = nfp_net_tx_queue_setup,
2004 .tx_queue_release = nfp_net_tx_queue_release,
2008 nfp_net_init(struct rte_eth_dev *eth_dev)
2010 struct rte_pci_device *pci_dev;
2011 struct nfp_net_hw *hw;
2013 uint32_t tx_bar_off, rx_bar_off;
2017 PMD_INIT_FUNC_TRACE();
2019 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2021 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2022 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2023 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2025 /* For secondary processes, the primary has done all the work */
2026 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2029 pci_dev = eth_dev->pci_dev;
2030 hw->device_id = pci_dev->id.device_id;
2031 hw->vendor_id = pci_dev->id.vendor_id;
2032 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2033 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2035 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u\n",
2036 pci_dev->id.vendor_id, pci_dev->id.device_id,
2037 pci_dev->addr.domain, pci_dev->addr.bus,
2038 pci_dev->addr.devid, pci_dev->addr.function);
2040 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2041 if (hw->ctrl_bar == NULL) {
2043 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2046 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2047 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2049 /* Work out where in the BAR the queues start. */
2050 switch (pci_dev->id.device_id) {
2051 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2052 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2053 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2054 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2055 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2058 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2062 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x\n", tx_bar_off);
2063 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x\n", rx_bar_off);
2065 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2066 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2068 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p\n",
2069 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2071 nfp_net_cfg_queue_setup(hw);
2073 /* Get some of the read-only fields from the config BAR */
2074 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2075 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2076 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2077 hw->mtu = hw->max_mtu;
2079 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2080 hw->rx_offset = NFP_NET_RX_OFFSET;
2082 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2084 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d\n",
2085 hw->ver, hw->max_mtu);
2086 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s\n", hw->cap,
2087 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2088 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2089 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2090 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2091 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2092 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2093 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2094 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2095 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2097 pci_dev = eth_dev->pci_dev;
2100 hw->stride_rx = stride;
2101 hw->stride_tx = stride;
2103 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u\n",
2104 hw->max_rx_queues, hw->max_tx_queues);
2106 /* Allocating memory for mac addr */
2107 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2108 if (eth_dev->data->mac_addrs == NULL) {
2109 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2113 /* Using random mac addresses for VFs */
2114 eth_random_addr(&hw->mac_addr[0]);
2116 /* Copying mac address to DPDK eth_dev struct */
2117 ether_addr_copy(ð_dev->data->mac_addrs[0],
2118 (struct ether_addr *)hw->mac_addr);
2120 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2121 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2122 eth_dev->data->port_id, pci_dev->id.vendor_id,
2123 pci_dev->id.device_id,
2124 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2125 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2127 /* Recording current stats counters values */
2128 nfp_net_stats_reset(eth_dev);
2133 static struct rte_pci_id pci_id_nfp_net_map[] = {
2135 .vendor_id = PCI_VENDOR_ID_NETRONOME,
2136 .device_id = PCI_DEVICE_ID_NFP6000_PF_NIC,
2137 .subsystem_vendor_id = PCI_ANY_ID,
2138 .subsystem_device_id = PCI_ANY_ID,
2141 .vendor_id = PCI_VENDOR_ID_NETRONOME,
2142 .device_id = PCI_DEVICE_ID_NFP6000_VF_NIC,
2143 .subsystem_vendor_id = PCI_ANY_ID,
2144 .subsystem_device_id = PCI_ANY_ID,
2151 static struct eth_driver rte_nfp_net_pmd = {
2153 .name = "rte_nfp_net_pmd",
2154 .id_table = pci_id_nfp_net_map,
2155 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2157 .eth_dev_init = nfp_net_init,
2158 .dev_private_size = sizeof(struct nfp_net_adapter),
2162 nfp_net_pmd_init(const char *name __rte_unused,
2163 const char *params __rte_unused)
2165 PMD_INIT_FUNC_TRACE();
2166 PMD_INIT_LOG(INFO, "librte_pmd_nfp_net version %s\n",
2167 NFP_NET_PMD_VERSION);
2169 rte_eth_driver_register(&rte_nfp_net_pmd);
2173 static struct rte_driver rte_nfp_net_driver = {
2175 .init = nfp_net_pmd_init,
2178 PMD_REGISTER_DRIVER(rte_nfp_net_driver);
2182 * c-file-style: "Linux"
2183 * indent-tabs-mode: t