2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
58 #include "nfp_net_pmd.h"
59 #include "nfp_net_logs.h"
60 #include "nfp_net_ctrl.h"
63 static void nfp_net_close(struct rte_eth_dev *dev);
64 static int nfp_net_configure(struct rte_eth_dev *dev);
65 static void nfp_net_dev_interrupt_handler(void *param);
66 static void nfp_net_dev_interrupt_delayed_handler(void *param);
67 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
68 static void nfp_net_infos_get(struct rte_eth_dev *dev,
69 struct rte_eth_dev_info *dev_info);
70 static int nfp_net_init(struct rte_eth_dev *eth_dev);
71 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
72 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
73 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
74 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
75 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
77 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
79 static void nfp_net_rx_queue_release(void *rxq);
80 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
81 uint16_t nb_desc, unsigned int socket_id,
82 const struct rte_eth_rxconf *rx_conf,
83 struct rte_mempool *mp);
84 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
85 static void nfp_net_tx_queue_release(void *txq);
86 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
87 uint16_t nb_desc, unsigned int socket_id,
88 const struct rte_eth_txconf *tx_conf);
89 static int nfp_net_start(struct rte_eth_dev *dev);
90 static void nfp_net_stats_get(struct rte_eth_dev *dev,
91 struct rte_eth_stats *stats);
92 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
93 static void nfp_net_stop(struct rte_eth_dev *dev);
94 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
98 * The offset of the queue controller queues in the PCIe Target. These
99 * happen to be at the same offset on the NFP6000 and the NFP3200 so
100 * we use a single macro here.
102 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
104 /* Maximum value which can be added to a queue with one transaction */
105 #define NFP_QCP_MAX_ADD 0x7f
107 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
108 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
110 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
112 NFP_QCP_READ_PTR = 0,
117 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
118 * @q: Base address for queue structure
119 * @ptr: Add to the Read or Write pointer
120 * @val: Value to add to the queue pointer
122 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
125 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
129 if (ptr == NFP_QCP_READ_PTR)
130 off = NFP_QCP_QUEUE_ADD_RPTR;
132 off = NFP_QCP_QUEUE_ADD_WPTR;
134 while (val > NFP_QCP_MAX_ADD) {
135 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
136 val -= NFP_QCP_MAX_ADD;
139 nn_writel(rte_cpu_to_le_32(val), q + off);
143 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
144 * @q: Base address for queue structure
145 * @ptr: Read or Write pointer
147 static inline uint32_t
148 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
153 if (ptr == NFP_QCP_READ_PTR)
154 off = NFP_QCP_QUEUE_STS_LO;
156 off = NFP_QCP_QUEUE_STS_HI;
158 val = rte_cpu_to_le_32(nn_readl(q + off));
160 if (ptr == NFP_QCP_READ_PTR)
161 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
163 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
167 * Functions to read/write from/to Config BAR
168 * Performs any endian conversion necessary.
170 static inline uint8_t
171 nn_cfg_readb(struct nfp_net_hw *hw, int off)
173 return nn_readb(hw->ctrl_bar + off);
177 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
179 nn_writeb(val, hw->ctrl_bar + off);
182 static inline uint32_t
183 nn_cfg_readl(struct nfp_net_hw *hw, int off)
185 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
189 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
191 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
194 static inline uint64_t
195 nn_cfg_readq(struct nfp_net_hw *hw, int off)
197 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
201 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
203 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
207 * Atomically reads link status information from global structure rte_eth_dev.
210 * - Pointer to the structure rte_eth_dev to read from.
211 * - Pointer to the buffer to be saved with the link status.
214 * - On success, zero.
215 * - On failure, negative value.
218 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
219 struct rte_eth_link *link)
221 struct rte_eth_link *dst = link;
222 struct rte_eth_link *src = &dev->data->dev_link;
224 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
225 *(uint64_t *)src) == 0)
232 * Atomically writes the link status information into global
233 * structure rte_eth_dev.
236 * - Pointer to the structure rte_eth_dev to read from.
237 * - Pointer to the buffer to be saved with the link status.
240 * - On success, zero.
241 * - On failure, negative value.
244 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
245 struct rte_eth_link *link)
247 struct rte_eth_link *dst = &dev->data->dev_link;
248 struct rte_eth_link *src = link;
250 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
251 *(uint64_t *)src) == 0)
258 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
262 if (rxq->rxbufs == NULL)
265 for (i = 0; i < rxq->rx_count; i++) {
266 if (rxq->rxbufs[i].mbuf) {
267 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
268 rxq->rxbufs[i].mbuf = NULL;
274 nfp_net_rx_queue_release(void *rx_queue)
276 struct nfp_net_rxq *rxq = rx_queue;
279 nfp_net_rx_queue_release_mbufs(rxq);
280 rte_free(rxq->rxbufs);
286 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
288 nfp_net_rx_queue_release_mbufs(rxq);
294 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
298 if (txq->txbufs == NULL)
301 for (i = 0; i < txq->tx_count; i++) {
302 if (txq->txbufs[i].mbuf) {
303 rte_pktmbuf_free(txq->txbufs[i].mbuf);
304 txq->txbufs[i].mbuf = NULL;
310 nfp_net_tx_queue_release(void *tx_queue)
312 struct nfp_net_txq *txq = tx_queue;
315 nfp_net_tx_queue_release_mbufs(txq);
316 rte_free(txq->txbufs);
322 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
324 nfp_net_tx_queue_release_mbufs(txq);
330 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
334 struct timespec wait;
336 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
339 if (hw->qcp_cfg == NULL)
340 rte_panic("Bad configuration queue pointer\n");
342 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
345 wait.tv_nsec = 1000000;
347 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
349 /* Poll update field, waiting for NFP to ack the config */
350 for (cnt = 0; ; cnt++) {
351 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
354 if (new & NFP_NET_CFG_UPDATE_ERR) {
355 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
358 if (cnt >= NFP_NET_POLL_TIMEOUT) {
359 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
360 " %dms", update, cnt);
361 rte_panic("Exiting\n");
363 nanosleep(&wait, 0); /* waiting for a 1ms */
365 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
370 * Reconfigure the NIC
371 * @nn: device to reconfigure
372 * @ctrl: The value for the ctrl field in the BAR config
373 * @update: The value for the update field in the BAR config
375 * Write the update word to the BAR and ping the reconfig queue. Then poll
376 * until the firmware has acknowledged the update by zeroing the update word.
379 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
383 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
386 rte_spinlock_lock(&hw->reconfig_lock);
388 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
389 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
393 err = __nfp_net_reconfig(hw, update);
395 rte_spinlock_unlock(&hw->reconfig_lock);
401 * Reconfig errors imply situations where they can be handled.
402 * Otherwise, rte_panic is called inside __nfp_net_reconfig
404 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
410 * Configure an Ethernet device. This function must be invoked first
411 * before any other function in the Ethernet API. This function can
412 * also be re-invoked when a device is in the stopped state.
415 nfp_net_configure(struct rte_eth_dev *dev)
417 struct rte_eth_conf *dev_conf;
418 struct rte_eth_rxmode *rxmode;
419 struct rte_eth_txmode *txmode;
420 uint32_t new_ctrl = 0;
422 struct nfp_net_hw *hw;
424 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
427 * A DPDK app sends info about how many queues to use and how
428 * those queues need to be configured. This is used by the
429 * DPDK core and it makes sure no more queues than those
430 * advertised by the driver are requested. This function is
431 * called after that internal process
434 PMD_INIT_LOG(DEBUG, "Configure");
436 dev_conf = &dev->data->dev_conf;
437 rxmode = &dev_conf->rxmode;
438 txmode = &dev_conf->txmode;
440 /* Checking TX mode */
441 if (txmode->mq_mode) {
442 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
446 /* Checking RX mode */
447 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
448 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
449 update = NFP_NET_CFG_UPDATE_RSS;
450 new_ctrl = NFP_NET_CFG_CTRL_RSS;
452 PMD_INIT_LOG(INFO, "RSS not supported");
457 if (rxmode->split_hdr_size) {
458 PMD_INIT_LOG(INFO, "rxmode does not support split header");
462 if (rxmode->hw_ip_checksum) {
463 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
464 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
466 PMD_INIT_LOG(INFO, "RXCSUM not supported");
471 if (rxmode->hw_vlan_filter) {
472 PMD_INIT_LOG(INFO, "VLAN filter not supported");
476 if (rxmode->hw_vlan_strip) {
477 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
478 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
480 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
485 if (rxmode->hw_vlan_extend) {
486 PMD_INIT_LOG(INFO, "VLAN extended not supported");
490 /* Supporting VLAN insertion by default */
491 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
492 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
494 if (rxmode->jumbo_frame)
495 /* this is handled in rte_eth_dev_configure */
497 if (rxmode->hw_strip_crc) {
498 PMD_INIT_LOG(INFO, "strip CRC not supported");
502 if (rxmode->enable_scatter) {
503 PMD_INIT_LOG(INFO, "Scatter not supported");
510 update |= NFP_NET_CFG_UPDATE_GEN;
512 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
513 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
522 nfp_net_enable_queues(struct rte_eth_dev *dev)
524 struct nfp_net_hw *hw;
525 uint64_t enabled_queues = 0;
528 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
530 /* Enabling the required TX queues in the device */
531 for (i = 0; i < dev->data->nb_tx_queues; i++)
532 enabled_queues |= (1 << i);
534 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
538 /* Enabling the required RX queues in the device */
539 for (i = 0; i < dev->data->nb_rx_queues; i++)
540 enabled_queues |= (1 << i);
542 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
546 nfp_net_disable_queues(struct rte_eth_dev *dev)
548 struct nfp_net_hw *hw;
549 uint32_t new_ctrl, update = 0;
551 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
553 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
554 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
556 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
557 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
558 NFP_NET_CFG_UPDATE_MSIX;
560 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
561 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
563 /* If an error when reconfig we avoid to change hw state */
564 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
571 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
575 for (i = 0; i < dev->data->nb_rx_queues; i++) {
576 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
583 nfp_net_params_setup(struct nfp_net_hw *hw)
585 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
586 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
590 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
592 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
595 static void nfp_net_read_mac(struct nfp_net_hw *hw)
599 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
600 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
602 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
603 memcpy(&hw->mac_addr[4], &tmp, 2);
607 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
609 uint32_t mac0 = *(uint32_t *)mac;
612 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
615 mac1 = *(uint16_t *)mac;
616 nn_writew(rte_cpu_to_be_16(mac1),
617 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
621 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
622 struct rte_intr_handle *intr_handle)
624 struct nfp_net_hw *hw;
627 if (!intr_handle->intr_vec) {
628 intr_handle->intr_vec =
629 rte_zmalloc("intr_vec",
630 dev->data->nb_rx_queues * sizeof(int), 0);
631 if (!intr_handle->intr_vec) {
632 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
633 " intr_vec", dev->data->nb_rx_queues);
638 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
640 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
641 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
642 /* UIO just supports one queue and no LSC*/
643 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
645 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
646 for (i = 0; i < dev->data->nb_rx_queues; i++)
648 * The first msix vector is reserved for non
651 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
654 /* Avoiding TX interrupts */
655 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
660 nfp_net_start(struct rte_eth_dev *dev)
662 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
663 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
664 uint32_t new_ctrl, update = 0;
665 struct nfp_net_hw *hw;
666 uint32_t intr_vector;
669 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
671 PMD_INIT_LOG(DEBUG, "Start");
673 /* Disabling queues just in case... */
674 nfp_net_disable_queues(dev);
676 /* Writing configuration parameters in the device */
677 nfp_net_params_setup(hw);
679 /* Enabling the required queues in the device */
680 nfp_net_enable_queues(dev);
682 /* check and configure queue intr-vector mapping */
683 if (dev->data->dev_conf.intr_conf.rxq != 0) {
684 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
686 * Better not to share LSC with RX interrupts.
687 * Unregistering LSC interrupt handler
689 rte_intr_callback_unregister(&pci_dev->intr_handle,
690 nfp_net_dev_interrupt_handler, (void *)dev);
692 if (dev->data->nb_rx_queues > 1) {
693 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
694 "supports 1 queue with UIO");
698 intr_vector = dev->data->nb_rx_queues;
699 if (rte_intr_efd_enable(intr_handle, intr_vector))
703 if (rte_intr_dp_is_en(intr_handle))
704 nfp_configure_rx_interrupt(dev, intr_handle);
706 rte_intr_enable(intr_handle);
709 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
710 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
712 /* Just configuring queues interrupts when necessary */
713 if (rte_intr_dp_is_en(intr_handle))
714 update |= NFP_NET_CFG_UPDATE_MSIX;
716 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
717 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
719 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
720 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
724 * Allocating rte mbuffs for configured rx queues.
725 * This requires queues being enabled before
727 if (nfp_net_rx_freelist_setup(dev) < 0) {
738 * An error returned by this function should mean the app
739 * exiting and then the system releasing all the memory
740 * allocated even memory coming from hugepages.
742 * The device could be enabled at this point with some queues
743 * ready for getting packets. This is true if the call to
744 * nfp_net_rx_freelist_setup() succeeds for some queues but
745 * fails for subsequent queues.
747 * This should make the app exiting but better if we tell the
750 nfp_net_disable_queues(dev);
755 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
757 nfp_net_stop(struct rte_eth_dev *dev)
761 PMD_INIT_LOG(DEBUG, "Stop");
763 nfp_net_disable_queues(dev);
766 for (i = 0; i < dev->data->nb_tx_queues; i++) {
767 nfp_net_reset_tx_queue(
768 (struct nfp_net_txq *)dev->data->tx_queues[i]);
771 for (i = 0; i < dev->data->nb_rx_queues; i++) {
772 nfp_net_reset_rx_queue(
773 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
777 /* Reset and stop device. The device can not be restarted. */
779 nfp_net_close(struct rte_eth_dev *dev)
781 struct nfp_net_hw *hw;
782 struct rte_pci_device *pci_dev;
784 PMD_INIT_LOG(DEBUG, "Close");
786 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
787 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
790 * We assume that the DPDK application is stopping all the
791 * threads/queues before calling the device close function.
796 rte_intr_disable(&pci_dev->intr_handle);
797 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
799 /* unregister callback func from eal lib */
800 rte_intr_callback_unregister(&pci_dev->intr_handle,
801 nfp_net_dev_interrupt_handler,
805 * The ixgbe PMD driver disables the pcie master on the
806 * device. The i40e does not...
811 nfp_net_promisc_enable(struct rte_eth_dev *dev)
813 uint32_t new_ctrl, update = 0;
814 struct nfp_net_hw *hw;
816 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
818 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
820 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
821 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
825 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
826 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
830 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
831 update = NFP_NET_CFG_UPDATE_GEN;
834 * DPDK sets promiscuous mode on just after this call assuming
835 * it can not fail ...
837 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
844 nfp_net_promisc_disable(struct rte_eth_dev *dev)
846 uint32_t new_ctrl, update = 0;
847 struct nfp_net_hw *hw;
849 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
851 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
852 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
856 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
857 update = NFP_NET_CFG_UPDATE_GEN;
860 * DPDK sets promiscuous mode off just before this call
861 * assuming it can not fail ...
863 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
870 * return 0 means link status changed, -1 means not changed
872 * Wait to complete is needed as it can take up to 9 seconds to get the Link
876 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
878 struct nfp_net_hw *hw;
879 struct rte_eth_link link, old;
880 uint32_t nn_link_status;
882 static const uint32_t ls_to_ethtool[] = {
883 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
884 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
885 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
886 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
887 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
888 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
889 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
890 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
893 PMD_DRV_LOG(DEBUG, "Link update\n");
895 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
897 memset(&old, 0, sizeof(old));
898 nfp_net_dev_atomic_read_link_status(dev, &old);
900 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
902 memset(&link, 0, sizeof(struct rte_eth_link));
904 if (nn_link_status & NFP_NET_CFG_STS_LINK)
905 link.link_status = ETH_LINK_UP;
907 link.link_duplex = ETH_LINK_FULL_DUPLEX;
909 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
910 NFP_NET_CFG_STS_LINK_RATE_MASK;
912 if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
913 ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
914 (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
915 /* We really do not know the speed wil old firmware */
916 link.link_speed = ETH_SPEED_NUM_NONE;
918 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
919 link.link_speed = ETH_SPEED_NUM_NONE;
921 link.link_speed = ls_to_ethtool[nn_link_status];
924 if (old.link_status != link.link_status) {
925 nfp_net_dev_atomic_write_link_status(dev, &link);
926 if (link.link_status)
927 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
929 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
937 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
940 struct nfp_net_hw *hw;
941 struct rte_eth_stats nfp_dev_stats;
943 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
945 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
947 /* reading per RX ring stats */
948 for (i = 0; i < dev->data->nb_rx_queues; i++) {
949 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
952 nfp_dev_stats.q_ipackets[i] =
953 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
955 nfp_dev_stats.q_ipackets[i] -=
956 hw->eth_stats_base.q_ipackets[i];
958 nfp_dev_stats.q_ibytes[i] =
959 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
961 nfp_dev_stats.q_ibytes[i] -=
962 hw->eth_stats_base.q_ibytes[i];
965 /* reading per TX ring stats */
966 for (i = 0; i < dev->data->nb_tx_queues; i++) {
967 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
970 nfp_dev_stats.q_opackets[i] =
971 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
973 nfp_dev_stats.q_opackets[i] -=
974 hw->eth_stats_base.q_opackets[i];
976 nfp_dev_stats.q_obytes[i] =
977 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
979 nfp_dev_stats.q_obytes[i] -=
980 hw->eth_stats_base.q_obytes[i];
983 nfp_dev_stats.ipackets =
984 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
986 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
988 nfp_dev_stats.ibytes =
989 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
991 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
993 nfp_dev_stats.opackets =
994 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
996 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
998 nfp_dev_stats.obytes =
999 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1001 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1003 /* reading general device stats */
1004 nfp_dev_stats.ierrors =
1005 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1007 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1009 nfp_dev_stats.oerrors =
1010 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1012 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1014 /* RX ring mbuf allocation failures */
1015 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1017 nfp_dev_stats.imissed =
1018 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1020 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1023 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1027 nfp_net_stats_reset(struct rte_eth_dev *dev)
1030 struct nfp_net_hw *hw;
1032 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1035 * hw->eth_stats_base records the per counter starting point.
1036 * Lets update it now
1039 /* reading per RX ring stats */
1040 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1041 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1044 hw->eth_stats_base.q_ipackets[i] =
1045 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1047 hw->eth_stats_base.q_ibytes[i] =
1048 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1051 /* reading per TX ring stats */
1052 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1053 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1056 hw->eth_stats_base.q_opackets[i] =
1057 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1059 hw->eth_stats_base.q_obytes[i] =
1060 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1063 hw->eth_stats_base.ipackets =
1064 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1066 hw->eth_stats_base.ibytes =
1067 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1069 hw->eth_stats_base.opackets =
1070 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1072 hw->eth_stats_base.obytes =
1073 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1075 /* reading general device stats */
1076 hw->eth_stats_base.ierrors =
1077 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1079 hw->eth_stats_base.oerrors =
1080 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1082 /* RX ring mbuf allocation failures */
1083 dev->data->rx_mbuf_alloc_failed = 0;
1085 hw->eth_stats_base.imissed =
1086 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1090 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1092 struct nfp_net_hw *hw;
1094 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1096 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1097 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1098 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1099 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1100 dev_info->max_rx_pktlen = hw->mtu;
1101 /* Next should change when PF support is implemented */
1102 dev_info->max_mac_addrs = 1;
1104 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1105 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1107 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1108 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1109 DEV_RX_OFFLOAD_UDP_CKSUM |
1110 DEV_RX_OFFLOAD_TCP_CKSUM;
1112 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1113 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1115 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1116 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1117 DEV_TX_OFFLOAD_UDP_CKSUM |
1118 DEV_TX_OFFLOAD_TCP_CKSUM;
1120 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1122 .pthresh = DEFAULT_RX_PTHRESH,
1123 .hthresh = DEFAULT_RX_HTHRESH,
1124 .wthresh = DEFAULT_RX_WTHRESH,
1126 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1130 dev_info->default_txconf = (struct rte_eth_txconf) {
1132 .pthresh = DEFAULT_TX_PTHRESH,
1133 .hthresh = DEFAULT_TX_HTHRESH,
1134 .wthresh = DEFAULT_TX_WTHRESH,
1136 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1137 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1138 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1139 ETH_TXQ_FLAGS_NOOFFLOADS,
1142 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1143 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1145 dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1146 ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1147 ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1149 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1150 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1153 static const uint32_t *
1154 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1156 static const uint32_t ptypes[] = {
1157 /* refers to nfp_net_set_hash() */
1158 RTE_PTYPE_INNER_L3_IPV4,
1159 RTE_PTYPE_INNER_L3_IPV6,
1160 RTE_PTYPE_INNER_L3_IPV6_EXT,
1161 RTE_PTYPE_INNER_L4_MASK,
1165 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1171 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1173 struct nfp_net_rxq *rxq;
1174 struct nfp_net_rx_desc *rxds;
1178 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1185 * Other PMDs are just checking the DD bit in intervals of 4
1186 * descriptors and counting all four if the first has the DD
1187 * bit on. Of course, this is not accurate but can be good for
1188 * performance. But ideally that should be done in descriptors
1189 * chunks belonging to the same cache line
1192 while (count < rxq->rx_count) {
1193 rxds = &rxq->rxds[idx];
1194 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1201 if ((idx) == rxq->rx_count)
1209 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1211 struct rte_pci_device *pci_dev;
1212 struct nfp_net_hw *hw;
1215 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1216 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1218 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1221 /* Make sure all updates are written before un-masking */
1223 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1224 NFP_NET_CFG_ICR_UNMASKED);
1229 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1231 struct rte_pci_device *pci_dev;
1232 struct nfp_net_hw *hw;
1235 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1236 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1238 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1241 /* Make sure all updates are written before un-masking */
1243 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1248 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1250 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1251 struct rte_eth_link link;
1253 memset(&link, 0, sizeof(link));
1254 nfp_net_dev_atomic_read_link_status(dev, &link);
1255 if (link.link_status)
1256 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1257 (int)(dev->data->port_id), (unsigned)link.link_speed,
1258 link.link_duplex == ETH_LINK_FULL_DUPLEX
1259 ? "full-duplex" : "half-duplex");
1261 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1262 (int)(dev->data->port_id));
1264 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1265 pci_dev->addr.domain, pci_dev->addr.bus,
1266 pci_dev->addr.devid, pci_dev->addr.function);
1269 /* Interrupt configuration and handling */
1272 * nfp_net_irq_unmask - Unmask an interrupt
1274 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1275 * clear the ICR for the entry.
1278 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1280 struct nfp_net_hw *hw;
1281 struct rte_pci_device *pci_dev;
1283 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1286 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1287 /* If MSI-X auto-masking is used, clear the entry */
1289 rte_intr_enable(&pci_dev->intr_handle);
1291 /* Make sure all updates are written before un-masking */
1293 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1294 NFP_NET_CFG_ICR_UNMASKED);
1299 nfp_net_dev_interrupt_handler(void *param)
1302 struct rte_eth_link link;
1303 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1305 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1307 /* get the link status */
1308 memset(&link, 0, sizeof(link));
1309 nfp_net_dev_atomic_read_link_status(dev, &link);
1311 nfp_net_link_update(dev, 0);
1314 if (!link.link_status) {
1315 /* handle it 1 sec later, wait it being stable */
1316 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1317 /* likely to down */
1319 /* handle it 4 sec later, wait it being stable */
1320 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1323 if (rte_eal_alarm_set(timeout * 1000,
1324 nfp_net_dev_interrupt_delayed_handler,
1326 RTE_LOG(ERR, PMD, "Error setting alarm");
1328 nfp_net_irq_unmask(dev);
1333 * Interrupt handler which shall be registered for alarm callback for delayed
1334 * handling specific interrupt to wait for the stable nic state. As the NIC
1335 * interrupt state is not stable for nfp after link is just down, it needs
1336 * to wait 4 seconds to get the stable status.
1338 * @param handle Pointer to interrupt handle.
1339 * @param param The address of parameter (struct rte_eth_dev *)
1344 nfp_net_dev_interrupt_delayed_handler(void *param)
1346 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1348 nfp_net_link_update(dev, 0);
1349 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1351 nfp_net_dev_link_status_print(dev);
1354 nfp_net_irq_unmask(dev);
1358 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1360 struct nfp_net_hw *hw;
1362 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1364 /* check that mtu is within the allowed range */
1365 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1368 /* switch to jumbo mode if needed */
1369 if ((uint32_t)mtu > ETHER_MAX_LEN)
1370 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1372 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1374 /* update max frame size */
1375 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1377 /* writing to configuration space */
1378 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1386 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1387 uint16_t queue_idx, uint16_t nb_desc,
1388 unsigned int socket_id,
1389 const struct rte_eth_rxconf *rx_conf,
1390 struct rte_mempool *mp)
1392 const struct rte_memzone *tz;
1393 struct nfp_net_rxq *rxq;
1394 struct nfp_net_hw *hw;
1396 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1398 PMD_INIT_FUNC_TRACE();
1400 /* Validating number of descriptors */
1401 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1402 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1403 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1404 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1409 * Free memory prior to re-allocation if needed. This is the case after
1410 * calling nfp_net_stop
1412 if (dev->data->rx_queues[queue_idx]) {
1413 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1414 dev->data->rx_queues[queue_idx] = NULL;
1417 /* Allocating rx queue data structure */
1418 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1419 RTE_CACHE_LINE_SIZE, socket_id);
1423 /* Hw queues mapping based on firmware confifguration */
1424 rxq->qidx = queue_idx;
1425 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1426 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1427 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1428 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1431 * Tracking mbuf size for detecting a potential mbuf overflow due to
1435 rxq->mbuf_size = rxq->mem_pool->elt_size;
1436 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1437 hw->flbufsz = rxq->mbuf_size;
1439 rxq->rx_count = nb_desc;
1440 rxq->port_id = dev->data->port_id;
1441 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1442 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1444 rxq->drop_en = rx_conf->rx_drop_en;
1447 * Allocate RX ring hardware descriptors. A memzone large enough to
1448 * handle the maximum ring size is allocated in order to allow for
1449 * resizing in later calls to the queue setup function.
1451 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1452 sizeof(struct nfp_net_rx_desc) *
1453 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1457 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1458 nfp_net_rx_queue_release(rxq);
1462 /* Saving physical and virtual addresses for the RX ring */
1463 rxq->dma = (uint64_t)tz->phys_addr;
1464 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1466 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1467 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1468 sizeof(*rxq->rxbufs) * nb_desc,
1469 RTE_CACHE_LINE_SIZE, socket_id);
1470 if (rxq->rxbufs == NULL) {
1471 nfp_net_rx_queue_release(rxq);
1475 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1476 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1478 nfp_net_reset_rx_queue(rxq);
1480 dev->data->rx_queues[queue_idx] = rxq;
1484 * Telling the HW about the physical address of the RX ring and number
1485 * of descriptors in log2 format
1487 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1488 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1494 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1496 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1500 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1503 for (i = 0; i < rxq->rx_count; i++) {
1504 struct nfp_net_rx_desc *rxd;
1505 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1508 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1509 (unsigned)rxq->qidx);
1513 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1515 rxd = &rxq->rxds[i];
1517 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1518 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1520 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1523 /* Make sure all writes are flushed before telling the hardware */
1526 /* Not advertising the whole ring as the firmware gets confused if so */
1527 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1530 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1536 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1537 uint16_t nb_desc, unsigned int socket_id,
1538 const struct rte_eth_txconf *tx_conf)
1540 const struct rte_memzone *tz;
1541 struct nfp_net_txq *txq;
1542 uint16_t tx_free_thresh;
1543 struct nfp_net_hw *hw;
1545 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1547 PMD_INIT_FUNC_TRACE();
1549 /* Validating number of descriptors */
1550 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1551 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1552 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1553 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1557 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1558 tx_conf->tx_free_thresh :
1559 DEFAULT_TX_FREE_THRESH);
1561 if (tx_free_thresh > (nb_desc)) {
1563 "tx_free_thresh must be less than the number of TX "
1564 "descriptors. (tx_free_thresh=%u port=%d "
1565 "queue=%d)\n", (unsigned int)tx_free_thresh,
1566 (int)dev->data->port_id, (int)queue_idx);
1571 * Free memory prior to re-allocation if needed. This is the case after
1572 * calling nfp_net_stop
1574 if (dev->data->tx_queues[queue_idx]) {
1575 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1577 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1578 dev->data->tx_queues[queue_idx] = NULL;
1581 /* Allocating tx queue data structure */
1582 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1583 RTE_CACHE_LINE_SIZE, socket_id);
1585 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1590 * Allocate TX ring hardware descriptors. A memzone large enough to
1591 * handle the maximum ring size is allocated in order to allow for
1592 * resizing in later calls to the queue setup function.
1594 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1595 sizeof(struct nfp_net_tx_desc) *
1596 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1599 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1600 nfp_net_tx_queue_release(txq);
1604 txq->tx_count = nb_desc;
1605 txq->tx_free_thresh = tx_free_thresh;
1606 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1607 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1608 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1610 /* queue mapping based on firmware configuration */
1611 txq->qidx = queue_idx;
1612 txq->tx_qcidx = queue_idx * hw->stride_tx;
1613 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1615 txq->port_id = dev->data->port_id;
1616 txq->txq_flags = tx_conf->txq_flags;
1618 /* Saving physical and virtual addresses for the TX ring */
1619 txq->dma = (uint64_t)tz->phys_addr;
1620 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1622 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1623 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1624 sizeof(*txq->txbufs) * nb_desc,
1625 RTE_CACHE_LINE_SIZE, socket_id);
1626 if (txq->txbufs == NULL) {
1627 nfp_net_tx_queue_release(txq);
1630 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1631 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1633 nfp_net_reset_tx_queue(txq);
1635 dev->data->tx_queues[queue_idx] = txq;
1639 * Telling the HW about the physical address of the TX ring and number
1640 * of descriptors in log2 format
1642 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1643 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1648 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1650 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1651 struct rte_mbuf *mb)
1654 struct nfp_net_hw *hw = txq->hw;
1656 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1659 ol_flags = mb->ol_flags;
1661 if (!(ol_flags & PKT_TX_TCP_SEG))
1664 txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1665 txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1666 txd->flags = PCIE_DESC_TX_LSO;
1675 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1677 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1678 struct rte_mbuf *mb)
1681 struct nfp_net_hw *hw = txq->hw;
1683 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1686 ol_flags = mb->ol_flags;
1688 /* IPv6 does not need checksum */
1689 if (ol_flags & PKT_TX_IP_CKSUM)
1690 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1692 switch (ol_flags & PKT_TX_L4_MASK) {
1693 case PKT_TX_UDP_CKSUM:
1694 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1696 case PKT_TX_TCP_CKSUM:
1697 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1701 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1702 txd->flags |= PCIE_DESC_TX_CSUM;
1705 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1707 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1708 struct rte_mbuf *mb)
1710 struct nfp_net_hw *hw = rxq->hw;
1712 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1715 /* If IPv4 and IP checksum error, fail */
1716 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1717 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1718 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1720 /* If neither UDP nor TCP return */
1721 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1722 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1725 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1726 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1727 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1729 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1730 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1731 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1734 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1735 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1738 * nfp_net_set_hash - Set mbuf hash data
1740 * The RSS hash and hash-type are pre-pended to the packet data.
1741 * Extract and decode it and set the mbuf fields.
1744 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1745 struct rte_mbuf *mbuf)
1749 struct nfp_net_hw *hw = rxq->hw;
1751 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1754 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1757 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1758 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1760 mbuf->hash.rss = hash;
1761 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1763 switch (hash_type) {
1764 case NFP_NET_RSS_IPV4:
1765 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1767 case NFP_NET_RSS_IPV6:
1768 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1770 case NFP_NET_RSS_IPV6_EX:
1771 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1774 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1779 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1781 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1784 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1789 * There are some decissions to take:
1790 * 1) How to check DD RX descriptors bit
1791 * 2) How and when to allocate new mbufs
1793 * Current implementation checks just one single DD bit each loop. As each
1794 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1795 * a single cache line instead. Tests with this change have not shown any
1796 * performance improvement but it requires further investigation. For example,
1797 * depending on which descriptor is next, the number of descriptors could be
1798 * less than 8 for just checking those in the same cache line. This implies
1799 * extra work which could be counterproductive by itself. Indeed, last firmware
1800 * changes are just doing this: writing several descriptors with the DD bit
1801 * for saving PCIe bandwidth and DMA operations from the NFP.
1803 * Mbuf allocation is done when a new packet is received. Then the descriptor
1804 * is automatically linked with the new mbuf and the old one is given to the
1805 * user. The main drawback with this design is mbuf allocation is heavier than
1806 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1807 * cache point of view it does not seem allocating the mbuf early on as we are
1808 * doing now have any benefit at all. Again, tests with this change have not
1809 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1810 * so looking at the implications of this type of allocation should be studied
1815 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1817 struct nfp_net_rxq *rxq;
1818 struct nfp_net_rx_desc *rxds;
1819 struct nfp_net_rx_buff *rxb;
1820 struct nfp_net_hw *hw;
1821 struct rte_mbuf *mb;
1822 struct rte_mbuf *new_mb;
1828 if (unlikely(rxq == NULL)) {
1830 * DPDK just checks the queue is lower than max queues
1831 * enabled. But the queue needs to be configured
1833 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1841 while (avail < nb_pkts) {
1842 rxb = &rxq->rxbufs[rxq->rd_p];
1843 if (unlikely(rxb == NULL)) {
1844 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1849 * Memory barrier to ensure that we won't do other
1850 * reads before the DD bit.
1854 rxds = &rxq->rxds[rxq->rd_p];
1855 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1859 * We got a packet. Let's alloc a new mbuff for refilling the
1860 * free descriptor ring as soon as possible
1862 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1863 if (unlikely(new_mb == NULL)) {
1864 RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1865 "queue_id=%u\n", (unsigned)rxq->port_id,
1866 (unsigned)rxq->qidx);
1867 nfp_net_mbuf_alloc_failed(rxq);
1874 * Grab the mbuff and refill the descriptor with the
1875 * previously allocated mbuff
1880 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1881 rxds->rxd.data_len, rxq->mbuf_size);
1883 /* Size of this segment */
1884 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1885 /* Size of the whole packet. We just support 1 segment */
1886 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1888 if (unlikely((mb->data_len + hw->rx_offset) >
1891 * This should not happen and the user has the
1892 * responsibility of avoiding it. But we have
1893 * to give some info about the error
1895 RTE_LOG_DP(ERR, PMD,
1896 "mbuf overflow likely due to the RX offset.\n"
1897 "\t\tYour mbuf size should have extra space for"
1898 " RX offset=%u bytes.\n"
1899 "\t\tCurrently you just have %u bytes available"
1900 " but the received packet is %u bytes long",
1902 rxq->mbuf_size - hw->rx_offset,
1907 /* Filling the received mbuff with packet info */
1909 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1911 mb->data_off = RTE_PKTMBUF_HEADROOM +
1912 NFP_DESC_META_LEN(rxds);
1914 /* No scatter mode supported */
1918 /* Checking the RSS flag */
1919 nfp_net_set_hash(rxq, rxds, mb);
1921 /* Checking the checksum flag */
1922 nfp_net_rx_cksum(rxq, rxds, mb);
1924 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1925 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1926 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1927 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1930 /* Adding the mbuff to the mbuff array passed by the app */
1931 rx_pkts[avail++] = mb;
1933 /* Now resetting and updating the descriptor */
1936 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1938 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1939 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1942 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
1949 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1950 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1952 nb_hold += rxq->nb_rx_hold;
1955 * FL descriptors needs to be written before incrementing the
1956 * FL queue WR pointer
1959 if (nb_hold > rxq->rx_free_thresh) {
1960 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1961 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1962 (unsigned)nb_hold, (unsigned)avail);
1963 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1966 rxq->nb_rx_hold = nb_hold;
1972 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1974 * @txq: TX queue to work with
1975 * Returns number of descriptors freed
1978 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1983 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1984 " status\n", txq->qidx);
1986 /* Work out how many packets have been sent */
1987 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1989 if (qcp_rd_p == txq->rd_p) {
1990 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1991 "packets (%u, %u)\n", txq->qidx,
1992 qcp_rd_p, txq->rd_p);
1996 if (qcp_rd_p > txq->rd_p)
1997 todo = qcp_rd_p - txq->rd_p;
1999 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2001 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2002 qcp_rd_p, txq->rd_p, txq->rd_p);
2008 if (unlikely(txq->rd_p >= txq->tx_count))
2009 txq->rd_p -= txq->tx_count;
2014 /* Leaving always free descriptors for avoiding wrapping confusion */
2016 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2018 if (txq->wr_p >= txq->rd_p)
2019 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2021 return txq->rd_p - txq->wr_p - 8;
2025 * nfp_net_txq_full - Check if the TX queue free descriptors
2026 * is below tx_free_threshold
2028 * @txq: TX queue to check
2030 * This function uses the host copy* of read/write pointers
2033 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2035 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2039 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2041 struct nfp_net_txq *txq;
2042 struct nfp_net_hw *hw;
2043 struct nfp_net_tx_desc *txds, txd;
2044 struct rte_mbuf *pkt;
2046 int pkt_size, dma_size;
2047 uint16_t free_descs, issued_descs;
2048 struct rte_mbuf **lmbuf;
2053 txds = &txq->txds[txq->wr_p];
2055 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2056 txq->qidx, txq->wr_p, nb_pkts);
2058 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2059 nfp_net_tx_free_bufs(txq);
2061 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2062 if (unlikely(free_descs == 0))
2069 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2070 txq->qidx, nb_pkts);
2071 /* Sending packets */
2072 while ((i < nb_pkts) && free_descs) {
2073 /* Grabbing the mbuf linked to the current descriptor */
2074 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2075 /* Warming the cache for releasing the mbuf later on */
2076 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2078 pkt = *(tx_pkts + i);
2080 if (unlikely((pkt->nb_segs > 1) &&
2081 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2082 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2083 rte_panic("Multisegment packet unsupported\n");
2086 /* Checking if we have enough descriptors */
2087 if (unlikely(pkt->nb_segs > free_descs))
2091 * Checksum and VLAN flags just in the first descriptor for a
2092 * multisegment packet, but TSO info needs to be in all of them.
2094 txd.data_len = pkt->pkt_len;
2095 nfp_net_tx_tso(txq, &txd, pkt);
2096 nfp_net_tx_cksum(txq, &txd, pkt);
2098 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2099 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2100 txd.flags |= PCIE_DESC_TX_VLAN;
2101 txd.vlan = pkt->vlan_tci;
2105 * mbuf data_len is the data in one segment and pkt_len data
2106 * in the whole packet. When the packet is just one segment,
2107 * then data_len = pkt_len
2109 pkt_size = pkt->pkt_len;
2112 /* Copying TSO, VLAN and cksum info */
2115 /* Releasing mbuf used by this descriptor previously*/
2117 rte_pktmbuf_free_seg(*lmbuf);
2120 * Linking mbuf with descriptor for being released
2121 * next time descriptor is used
2125 dma_size = pkt->data_len;
2126 dma_addr = rte_mbuf_data_dma_addr(pkt);
2127 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2128 "%" PRIx64 "\n", dma_addr);
2130 /* Filling descriptors fields */
2131 txds->dma_len = dma_size;
2132 txds->data_len = txd.data_len;
2133 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2134 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2135 ASSERT(free_descs > 0);
2139 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2142 pkt_size -= dma_size;
2145 txds->offset_eop |= PCIE_DESC_TX_EOP;
2147 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2150 /* Referencing next free TX descriptor */
2151 txds = &txq->txds[txq->wr_p];
2152 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2159 /* Increment write pointers. Force memory write before we let HW know */
2161 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2167 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2169 uint32_t new_ctrl, update;
2170 struct nfp_net_hw *hw;
2172 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2176 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2177 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2178 " ETH_VLAN_EXTEND_OFFLOAD");
2180 /* Enable vlan strip if it is not configured yet */
2181 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2182 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2183 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2185 /* Disable vlan strip just if it is configured */
2186 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2187 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2188 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2193 update = NFP_NET_CFG_UPDATE_GEN;
2195 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2198 hw->ctrl = new_ctrl;
2201 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2203 nfp_net_reta_update(struct rte_eth_dev *dev,
2204 struct rte_eth_rss_reta_entry64 *reta_conf,
2207 uint32_t reta, mask;
2211 struct nfp_net_hw *hw =
2212 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2214 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2217 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2218 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2219 "(%d) doesn't match the number hardware can supported "
2220 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2225 * Update Redirection Table. There are 128 8bit-entries which can be
2226 * manage as 32 32bit-entries
2228 for (i = 0; i < reta_size; i += 4) {
2229 /* Handling 4 RSS entries per loop */
2230 idx = i / RTE_RETA_GROUP_SIZE;
2231 shift = i % RTE_RETA_GROUP_SIZE;
2232 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2238 /* If all 4 entries were set, don't need read RETA register */
2240 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2242 for (j = 0; j < 4; j++) {
2243 if (!(mask & (0x1 << j)))
2246 /* Clearing the entry bits */
2247 reta &= ~(0xFF << (8 * j));
2248 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2250 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2254 update = NFP_NET_CFG_UPDATE_RSS;
2256 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2262 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2264 nfp_net_reta_query(struct rte_eth_dev *dev,
2265 struct rte_eth_rss_reta_entry64 *reta_conf,
2271 struct nfp_net_hw *hw;
2273 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2275 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2278 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2279 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2280 "(%d) doesn't match the number hardware can supported "
2281 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2286 * Reading Redirection Table. There are 128 8bit-entries which can be
2287 * manage as 32 32bit-entries
2289 for (i = 0; i < reta_size; i += 4) {
2290 /* Handling 4 RSS entries per loop */
2291 idx = i / RTE_RETA_GROUP_SIZE;
2292 shift = i % RTE_RETA_GROUP_SIZE;
2293 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2298 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2300 for (j = 0; j < 4; j++) {
2301 if (!(mask & (0x1 << j)))
2303 reta_conf->reta[shift + j] =
2304 (uint8_t)((reta >> (8 * j)) & 0xF);
2311 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2312 struct rte_eth_rss_conf *rss_conf)
2315 uint32_t cfg_rss_ctrl = 0;
2319 struct nfp_net_hw *hw;
2321 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2323 rss_hf = rss_conf->rss_hf;
2325 /* Checking if RSS is enabled */
2326 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2327 if (rss_hf != 0) { /* Enable RSS? */
2328 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2331 return 0; /* Nothing to do */
2334 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2335 RTE_LOG(ERR, PMD, "hash key too long\n");
2339 if (rss_hf & ETH_RSS_IPV4)
2340 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2341 NFP_NET_CFG_RSS_IPV4_TCP |
2342 NFP_NET_CFG_RSS_IPV4_UDP;
2344 if (rss_hf & ETH_RSS_IPV6)
2345 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2346 NFP_NET_CFG_RSS_IPV6_TCP |
2347 NFP_NET_CFG_RSS_IPV6_UDP;
2349 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2350 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2352 /* configuring where to apply the RSS hash */
2353 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2355 /* Writing the key byte a byte */
2356 for (i = 0; i < rss_conf->rss_key_len; i++) {
2357 memcpy(&key, &rss_conf->rss_key[i], 1);
2358 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2361 /* Writing the key size */
2362 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2364 update = NFP_NET_CFG_UPDATE_RSS;
2366 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2373 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2374 struct rte_eth_rss_conf *rss_conf)
2377 uint32_t cfg_rss_ctrl;
2380 struct nfp_net_hw *hw;
2382 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2387 rss_hf = rss_conf->rss_hf;
2388 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2390 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2391 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2393 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2394 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2396 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2397 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2399 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2400 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2402 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2403 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2405 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2406 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2408 /* Reading the key size */
2409 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2411 /* Reading the key byte a byte */
2412 for (i = 0; i < rss_conf->rss_key_len; i++) {
2413 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2414 memcpy(&rss_conf->rss_key[i], &key, 1);
2420 /* Initialise and register driver with DPDK Application */
2421 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2422 .dev_configure = nfp_net_configure,
2423 .dev_start = nfp_net_start,
2424 .dev_stop = nfp_net_stop,
2425 .dev_close = nfp_net_close,
2426 .promiscuous_enable = nfp_net_promisc_enable,
2427 .promiscuous_disable = nfp_net_promisc_disable,
2428 .link_update = nfp_net_link_update,
2429 .stats_get = nfp_net_stats_get,
2430 .stats_reset = nfp_net_stats_reset,
2431 .dev_infos_get = nfp_net_infos_get,
2432 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2433 .mtu_set = nfp_net_dev_mtu_set,
2434 .vlan_offload_set = nfp_net_vlan_offload_set,
2435 .reta_update = nfp_net_reta_update,
2436 .reta_query = nfp_net_reta_query,
2437 .rss_hash_update = nfp_net_rss_hash_update,
2438 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2439 .rx_queue_setup = nfp_net_rx_queue_setup,
2440 .rx_queue_release = nfp_net_rx_queue_release,
2441 .rx_queue_count = nfp_net_rx_queue_count,
2442 .tx_queue_setup = nfp_net_tx_queue_setup,
2443 .tx_queue_release = nfp_net_tx_queue_release,
2444 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2445 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2449 nfp_net_init(struct rte_eth_dev *eth_dev)
2451 struct rte_pci_device *pci_dev;
2452 struct nfp_net_hw *hw;
2454 uint32_t tx_bar_off, rx_bar_off;
2458 PMD_INIT_FUNC_TRACE();
2460 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2462 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2463 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2464 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2466 /* For secondary processes, the primary has done all the work */
2467 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2470 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2471 rte_eth_copy_pci_info(eth_dev, pci_dev);
2472 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2474 hw->device_id = pci_dev->id.device_id;
2475 hw->vendor_id = pci_dev->id.vendor_id;
2476 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2477 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2479 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2480 pci_dev->id.vendor_id, pci_dev->id.device_id,
2481 pci_dev->addr.domain, pci_dev->addr.bus,
2482 pci_dev->addr.devid, pci_dev->addr.function);
2484 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2485 if (hw->ctrl_bar == NULL) {
2487 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2490 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2491 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2493 /* Work out where in the BAR the queues start. */
2494 switch (pci_dev->id.device_id) {
2495 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2496 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2497 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2498 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2499 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2502 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2506 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x", tx_bar_off);
2507 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x", rx_bar_off);
2509 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2510 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2512 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2513 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2515 nfp_net_cfg_queue_setup(hw);
2517 /* Get some of the read-only fields from the config BAR */
2518 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2519 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2520 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2521 hw->mtu = hw->max_mtu;
2523 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2524 hw->rx_offset = NFP_NET_RX_OFFSET;
2526 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2528 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2529 hw->ver, hw->max_mtu);
2530 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
2531 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2532 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2533 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2534 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2535 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2536 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2537 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2538 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2539 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2543 hw->stride_rx = stride;
2544 hw->stride_tx = stride;
2546 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2547 hw->max_rx_queues, hw->max_tx_queues);
2549 /* Initializing spinlock for reconfigs */
2550 rte_spinlock_init(&hw->reconfig_lock);
2552 /* Allocating memory for mac addr */
2553 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2554 if (eth_dev->data->mac_addrs == NULL) {
2555 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2559 nfp_net_read_mac(hw);
2561 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2562 /* Using random mac addresses for VFs */
2563 eth_random_addr(&hw->mac_addr[0]);
2564 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2567 /* Copying mac address to DPDK eth_dev struct */
2568 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2569 ð_dev->data->mac_addrs[0]);
2571 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2572 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2573 eth_dev->data->port_id, pci_dev->id.vendor_id,
2574 pci_dev->id.device_id,
2575 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2576 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2578 /* Registering LSC interrupt handler */
2579 rte_intr_callback_register(&pci_dev->intr_handle,
2580 nfp_net_dev_interrupt_handler,
2583 /* Telling the firmware about the LSC interrupt entry */
2584 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2586 /* Recording current stats counters values */
2587 nfp_net_stats_reset(eth_dev);
2592 static const struct rte_pci_id pci_id_nfp_net_map[] = {
2594 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2595 PCI_DEVICE_ID_NFP6000_PF_NIC)
2598 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2599 PCI_DEVICE_ID_NFP6000_VF_NIC)
2606 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2607 struct rte_pci_device *pci_dev)
2609 return rte_eth_dev_pci_generic_probe(pci_dev,
2610 sizeof(struct nfp_net_adapter), nfp_net_init);
2613 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
2615 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2618 static struct rte_pci_driver rte_nfp_net_pmd = {
2619 .id_table = pci_id_nfp_net_map,
2620 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2621 .probe = eth_nfp_pci_probe,
2622 .remove = eth_nfp_pci_remove,
2625 RTE_PMD_REGISTER_PCI(net_nfp, rte_nfp_net_pmd);
2626 RTE_PMD_REGISTER_PCI_TABLE(net_nfp, pci_id_nfp_net_map);
2627 RTE_PMD_REGISTER_KMOD_DEP(net_nfp, "* igb_uio | uio_pci_generic | vfio-pci");
2631 * c-file-style: "Linux"
2632 * indent-tabs-mode: t