2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
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33 * vim:shiftwidth=8:noexpandtab
35 * Netronome network device driver: Control BAR layout
37 #ifndef _NFP_NET_CTRL_H_
38 #define _NFP_NET_CTRL_H_
41 * Configuration BAR size.
43 * The configuration BAR is 8K in size, but on the NFP6000, due to
44 * THB-350, 32k needs to be reserved.
47 #define NFP_NET_CFG_BAR_SZ (32 * 1024)
49 #define NFP_NET_CFG_BAR_SZ (8 * 1024)
52 /* Offset in Freelist buffer where packet starts on RX */
53 #define NFP_NET_RX_OFFSET 32
55 /* Hash type pre-pended when a RSS hash was computed */
56 #define NFP_NET_RSS_NONE 0
57 #define NFP_NET_RSS_IPV4 1
58 #define NFP_NET_RSS_IPV6 2
59 #define NFP_NET_RSS_IPV6_EX 3
60 #define NFP_NET_RSS_IPV4_TCP 4
61 #define NFP_NET_RSS_IPV6_TCP 5
62 #define NFP_NET_RSS_IPV6_EX_TCP 6
63 #define NFP_NET_RSS_IPV4_UDP 7
64 #define NFP_NET_RSS_IPV6_UDP 8
65 #define NFP_NET_RSS_IPV6_EX_UDP 9
68 * @NFP_NET_TXR_MAX: Maximum number of TX rings
69 * @NFP_NET_TXR_MASK: Mask for TX rings
70 * @NFP_NET_RXR_MAX: Maximum number of RX rings
71 * @NFP_NET_RXR_MASK: Mask for RX rings
73 #define NFP_NET_TXR_MAX 64
74 #define NFP_NET_TXR_MASK (NFP_NET_TXR_MAX - 1)
75 #define NFP_NET_RXR_MAX 64
76 #define NFP_NET_RXR_MASK (NFP_NET_RXR_MAX - 1)
79 * Read/Write config words (0x0000 - 0x002c)
80 * @NFP_NET_CFG_CTRL: Global control
81 * @NFP_NET_CFG_UPDATE: Indicate which fields are updated
82 * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings
83 * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings
84 * @NFP_NET_CFG_MTU: Set MTU size
85 * @NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU)
86 * @NFP_NET_CFG_EXN: MSI-X table entry for exceptions
87 * @NFP_NET_CFG_LSC: MSI-X table entry for link state changes
88 * @NFP_NET_CFG_MACADDR: MAC address
91 * - define Error details in UPDATE
93 #define NFP_NET_CFG_CTRL 0x0000
94 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */
95 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */
96 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */
97 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */
98 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */
99 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */
100 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */
101 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */
102 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */
103 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */
104 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO */
105 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */
106 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS */
107 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */
108 #define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */
109 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */
110 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/
111 #define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */
112 #define NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */
113 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* Enable VXLAN */
114 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* Enable NVGRE */
115 #define NFP_NET_CFG_UPDATE 0x0004
116 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */
117 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */
118 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */
119 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */
120 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */
121 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */
122 #define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */
123 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */
124 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */
125 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */
126 #define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */
127 #define NFP_NET_CFG_TXRS_ENABLE 0x0008
128 #define NFP_NET_CFG_RXRS_ENABLE 0x0010
129 #define NFP_NET_CFG_MTU 0x0018
130 #define NFP_NET_CFG_FLBUFSZ 0x001c
131 #define NFP_NET_CFG_EXN 0x001f
132 #define NFP_NET_CFG_LSC 0x0020
133 #define NFP_NET_CFG_MACADDR 0x0024
136 * Read-only words (0x0030 - 0x0050):
137 * @NFP_NET_CFG_VERSION: Firmware version number
138 * @NFP_NET_CFG_STS: Status
139 * @NFP_NET_CFG_CAP: Capabilities (same bits as @NFP_NET_CFG_CTRL)
140 * @NFP_NET_MAX_TXRINGS: Maximum number of TX rings
141 * @NFP_NET_MAX_RXRINGS: Maximum number of RX rings
142 * @NFP_NET_MAX_MTU: Maximum support MTU
143 * @NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only)
144 * @NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only)
147 * - define more STS bits
149 #define NFP_NET_CFG_VERSION 0x0030
150 #define NFP_NET_CFG_VERSION_RESERVED_MASK (0xff << 24)
151 #define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16)
152 #define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16)
153 #define NFP_NET_CFG_VERSION_CLASS_GENERIC 0
154 #define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8)
155 #define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8)
156 #define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0)
157 #define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0)
158 #define NFP_NET_CFG_STS 0x0034
159 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */
161 #define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1
162 #define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF
163 #define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0
164 #define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1
165 #define NFP_NET_CFG_STS_LINK_RATE_1G 2
166 #define NFP_NET_CFG_STS_LINK_RATE_10G 3
167 #define NFP_NET_CFG_STS_LINK_RATE_25G 4
168 #define NFP_NET_CFG_STS_LINK_RATE_40G 5
169 #define NFP_NET_CFG_STS_LINK_RATE_50G 6
170 #define NFP_NET_CFG_STS_LINK_RATE_100G 7
171 #define NFP_NET_CFG_CAP 0x0038
172 #define NFP_NET_CFG_MAX_TXRINGS 0x003c
173 #define NFP_NET_CFG_MAX_RXRINGS 0x0040
174 #define NFP_NET_CFG_MAX_MTU 0x0044
175 /* Next two words are being used by VFs for solving THB350 issue */
176 #define NFP_NET_CFG_START_TXQ 0x0048
177 #define NFP_NET_CFG_START_RXQ 0x004c
180 * NFP-3200 workaround (0x0050 - 0x0058)
181 * @NFP_NET_CFG_SPARE_ADDR: DMA address for ME code to use (e.g. YDS-155 fix)
183 #define NFP_NET_CFG_SPARE_ADDR 0x0050
185 * NFP6000/NFP4000 - Prepend configuration
187 #define NFP_NET_CFG_RX_OFFSET 0x0050
188 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */
191 * Reuse spare address to contain the offset from the start of
192 * the host buffer where the first byte of the received frame
193 * will land. Any metadata will come prior to that offset. If the
194 * value in this field is 0, it means that that the metadata will
195 * always land starting at the first byte of the host buffer and
196 * packet data will immediately follow the metadata. As always,
197 * the RX descriptor indicates the presence or absence of metadata
198 * along with the length thereof.
200 #define NFP_NET_CFG_RX_OFFSET_ADDR 0x0050
202 #define NFP_NET_CFG_VXLAN_PORT 0x0060
203 #define NFP_NET_CFG_VXLAN_SZ 0x0008
205 /* Offload definitions */
206 #define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(uint16_t))
209 * 64B reserved for future use (0x0080 - 0x00c0)
211 #define NFP_NET_CFG_RESERVED 0x0080
212 #define NFP_NET_CFG_RESERVED_SZ 0x0040
215 * RSS configuration (0x0100 - 0x01ac):
216 * Used only when NFP_NET_CFG_CTRL_RSS is enabled
217 * @NFP_NET_CFG_RSS_CFG: RSS configuration word
218 * @NFP_NET_CFG_RSS_KEY: RSS "secret" key
219 * @NFP_NET_CFG_RSS_ITBL: RSS indirection table
221 #define NFP_NET_CFG_RSS_BASE 0x0100
222 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE
223 #define NFP_NET_CFG_RSS_MASK (0x7f)
224 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f)
225 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */
226 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */
227 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */
228 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */
229 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */
230 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */
231 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */
232 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4)
233 #define NFP_NET_CFG_RSS_KEY_SZ 0x28
234 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \
235 NFP_NET_CFG_RSS_KEY_SZ)
236 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80
239 * TX ring configuration (0x200 - 0x800)
240 * @NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration
241 * @NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries)
242 * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)
243 * @NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries)
244 * @NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries)
245 * @NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries)
246 * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries)
248 #define NFP_NET_CFG_TXR_BASE 0x0200
249 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))
250 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \
252 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x))
253 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x))
254 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x))
255 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \
259 * RX ring configuration (0x0800 - 0x0c00)
260 * @NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration
261 * @NFP_NET_CFG_RXR_ADDR: Per TX ring DMA address (8B entries)
262 * @NFP_NET_CFG_RXR_SZ: Per TX ring ring size (1B entries)
263 * @NFP_NET_CFG_RXR_VEC: Per TX ring MSI-X table entry (1B entries)
264 * @NFP_NET_CFG_RXR_PRIO: Per TX ring priority (1B entries)
265 * @NFP_NET_CFG_RXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries)
267 #define NFP_NET_CFG_RXR_BASE 0x0800
268 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))
269 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x))
270 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x))
271 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x))
272 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \
276 * Interrupt Control/Cause registers (0x0c00 - 0x0d00)
277 * These registers are only used when MSI-X auto-masking is not
278 * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index
279 * by MSI-X entry and are 1B in size. If an entry is zero, the
280 * corresponding entry is enabled. If the FW generates an interrupt,
281 * it writes a cause into the corresponding field. This also masks
282 * the MSI-X entry and the host driver must clear the register to
283 * re-enable the interrupt.
285 #define NFP_NET_CFG_ICR_BASE 0x0c00
286 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x))
287 #define NFP_NET_CFG_ICR_UNMASKED 0x0
288 #define NFP_NET_CFG_ICR_RXTX 0x1
289 #define NFP_NET_CFG_ICR_LSC 0x2
292 * General device stats (0x0d00 - 0x0d90)
293 * all counters are 64bit.
295 #define NFP_NET_CFG_STATS_BASE 0x0d00
296 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00)
297 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08)
298 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10)
299 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18)
300 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20)
301 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28)
302 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30)
303 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38)
304 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40)
306 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48)
307 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50)
308 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58)
309 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60)
310 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68)
311 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70)
312 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78)
313 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80)
314 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88)
317 * Per ring stats (0x1000 - 0x1800)
318 * options, 64bit per entry
319 * @NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count)
320 * @NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count)
322 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000
323 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \
325 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400
326 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \
329 #endif /* _NFP_NET_CTRL_H_ */
332 * c-file-style: "Linux"
333 * indent-tabs-mode: t