1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
7 * vim:shiftwidth=8:noexpandtab
9 * @file dpdk/pmd/nfp_net_pmd.h
11 * Netronome NFP_NET PMD driver
14 #ifndef _NFP_NET_PMD_H_
15 #define _NFP_NET_PMD_H_
17 #define NFP_NET_PMD_VERSION "0.1"
18 #define PCI_VENDOR_ID_NETRONOME 0x19ee
19 #define PCI_DEVICE_ID_NFP4000_PF_NIC 0x4000
20 #define PCI_DEVICE_ID_NFP6000_PF_NIC 0x6000
21 #define PCI_DEVICE_ID_NFP6000_VF_NIC 0x6003
23 /* Forward declaration */
24 struct nfp_net_adapter;
26 #define NFP_TX_MAX_SEG UINT8_MAX
27 #define NFP_TX_MAX_MTU_SEG 8
30 #define NFP_NET_CRTL_BAR 0
31 #define NFP_NET_TX_BAR 2
32 #define NFP_NET_RX_BAR 2
33 #define NFP_QCP_QUEUE_AREA_SZ 0x80000
35 /* Macros for accessing the Queue Controller Peripheral 'CSRs' */
36 #define NFP_QCP_QUEUE_OFF(_x) ((_x) * 0x800)
37 #define NFP_QCP_QUEUE_ADD_RPTR 0x0000
38 #define NFP_QCP_QUEUE_ADD_WPTR 0x0004
39 #define NFP_QCP_QUEUE_STS_LO 0x0008
40 #define NFP_QCP_QUEUE_STS_LO_READPTR_mask (0x3ffff)
41 #define NFP_QCP_QUEUE_STS_HI 0x000c
42 #define NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask (0x3ffff)
44 /* Interrupt definitions */
45 #define NFP_NET_IRQ_LSC_IDX 0
47 /* Default values for RX/TX configuration */
48 #define DEFAULT_RX_FREE_THRESH 32
49 #define DEFAULT_RX_PTHRESH 8
50 #define DEFAULT_RX_HTHRESH 8
51 #define DEFAULT_RX_WTHRESH 0
53 #define DEFAULT_TX_RS_THRESH 32
54 #define DEFAULT_TX_FREE_THRESH 32
55 #define DEFAULT_TX_PTHRESH 32
56 #define DEFAULT_TX_HTHRESH 0
57 #define DEFAULT_TX_WTHRESH 0
58 #define DEFAULT_TX_RSBIT_THRESH 32
60 /* Alignment for dma zones */
61 #define NFP_MEMZONE_ALIGN 128
64 * This is used by the reconfig protocol. It sets the maximum time waiting in
65 * milliseconds before a reconfig timeout happens.
67 #define NFP_NET_POLL_TIMEOUT 5000
69 #define NFP_QCP_QUEUE_ADDR_SZ (0x800)
71 #define NFP_NET_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
72 #define NFP_NET_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
74 /* Version number helper defines */
75 #define NFD_CFG_CLASS_VER_msk 0xff
76 #define NFD_CFG_CLASS_VER_shf 24
77 #define NFD_CFG_CLASS_VER(x) (((x) & 0xff) << 24)
78 #define NFD_CFG_CLASS_VER_of(x) (((x) >> 24) & 0xff)
79 #define NFD_CFG_CLASS_TYPE_msk 0xff
80 #define NFD_CFG_CLASS_TYPE_shf 16
81 #define NFD_CFG_CLASS_TYPE(x) (((x) & 0xff) << 16)
82 #define NFD_CFG_CLASS_TYPE_of(x) (((x) >> 16) & 0xff)
83 #define NFD_CFG_MAJOR_VERSION_msk 0xff
84 #define NFD_CFG_MAJOR_VERSION_shf 8
85 #define NFD_CFG_MAJOR_VERSION(x) (((x) & 0xff) << 8)
86 #define NFD_CFG_MAJOR_VERSION_of(x) (((x) >> 8) & 0xff)
87 #define NFD_CFG_MINOR_VERSION_msk 0xff
88 #define NFD_CFG_MINOR_VERSION_shf 0
89 #define NFD_CFG_MINOR_VERSION(x) (((x) & 0xff) << 0)
90 #define NFD_CFG_MINOR_VERSION_of(x) (((x) >> 0) & 0xff)
92 /* Number of supported physical ports */
93 #define NFP_MAX_PHYPORTS 12
95 #include <linux/types.h>
98 static inline uint8_t nn_readb(volatile const void *addr)
100 return rte_read8(addr);
103 static inline void nn_writeb(uint8_t val, volatile void *addr)
105 rte_write8(val, addr);
108 static inline uint32_t nn_readl(volatile const void *addr)
110 return rte_read32(addr);
113 static inline void nn_writel(uint32_t val, volatile void *addr)
115 rte_write32(val, addr);
118 static inline void nn_writew(uint16_t val, volatile void *addr)
120 rte_write16(val, addr);
123 static inline uint64_t nn_readq(volatile void *addr)
125 const volatile uint32_t *p = addr;
128 high = nn_readl((volatile const void *)(p + 1));
129 low = nn_readl((volatile const void *)p);
131 return low + ((uint64_t)high << 32);
134 static inline void nn_writeq(uint64_t val, volatile void *addr)
136 nn_writel(val >> 32, (volatile char *)addr + 4);
137 nn_writel(val, addr);
141 /* Backpointer to associated pci device */
142 struct rte_pci_device *pci_dev;
144 /* Array of physical ports belonging to this PF */
145 struct nfp_net_hw *ports[NFP_MAX_PHYPORTS];
147 /* Current values for control */
155 rte_spinlock_t reconfig_lock;
160 uint16_t subsystem_device_id;
161 uint16_t subsystem_vendor_id;
162 #if defined(DSTQ_SELECTION)
164 uint16_t device_function;
169 struct nfp_cpp_area *ctrl_area;
170 struct nfp_cpp_area *hwqueues_area;
171 struct nfp_cpp_area *msix_area;
174 uint8_t total_phyports;
177 union eth_table_entry *eth_table;
179 struct nfp_hwinfo *hwinfo;
180 struct nfp_rtsym_table *sym_tbl;
181 uint32_t nfp_cpp_service_id;
185 /* Backpointer to the PF this port belongs to */
186 struct nfp_pf_dev *pf_dev;
188 /* Backpointer to the eth_dev of this port*/
189 struct rte_eth_dev *eth_dev;
191 /* Info from the firmware */
198 /* Current values for control */
209 rte_spinlock_t reconfig_lock;
211 uint32_t max_tx_queues;
212 uint32_t max_rx_queues;
216 uint16_t subsystem_device_id;
217 uint16_t subsystem_vendor_id;
218 #if defined(DSTQ_SELECTION)
220 uint16_t device_function;
224 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
226 /* Records starting point for counters */
227 struct rte_eth_stats eth_stats_base;
230 struct nfp_cpp_area *ctrl_area;
231 struct nfp_cpp_area *hwqueues_area;
232 struct nfp_cpp_area *msix_area;
235 /* Sequential physical port number */
237 /* Internal port number as seen from NFP */
241 union eth_table_entry *eth_table;
243 uint32_t nfp_cpp_service_id;
246 struct nfp_net_adapter {
247 struct nfp_net_hw hw;
250 #define NFP_NET_DEV_PRIVATE_TO_HW(adapter)\
251 (&((struct nfp_net_adapter *)adapter)->hw)
253 #define NFP_NET_DEV_PRIVATE_TO_PF(dev_priv)\
254 (((struct nfp_net_hw *)dev_priv)->pf_dev)
256 #endif /* _NFP_NET_PMD_H_ */
259 * c-file-style: "Linux"
260 * indent-tabs-mode: t