11 #include <rte_byteorder.h>
14 #include "nfp_net_eth.h"
16 #define CFG_EXP_BAR_ADDR_SZ 1
17 #define CFG_EXP_BAR_MAP_TYPE 1
19 #define EXP_BAR_TARGET_SHIFT 23
20 #define EXP_BAR_LENGTH_SHIFT 27 /* 0=32, 1=64 bit increment */
21 #define EXP_BAR_MAP_TYPE_SHIFT 29 /* Bulk BAR map */
23 /* NFP target for NSP access */
24 #define NFP_NSP_TARGET 7
26 /* Expansion BARs for mapping PF vnic BARs */
27 #define NFP_NET_PF_CFG_EXP_BAR 6
28 #define NFP_NET_PF_HW_QUEUES_EXP_BAR 5
31 * This is an NFP internal address used for configuring properly an NFP
34 #define MEM_CMD_BASE_ADDR 0x8100000000
36 /* NSP interface registers */
37 #define NSP_BASE (MEM_CMD_BASE_ADDR + 0x22100)
38 #define NSP_STATUS 0x00
39 #define NSP_COMMAND 0x08
40 #define NSP_BUFFER 0x10
41 #define NSP_DEFAULT_BUF 0x18
42 #define NSP_DEFAULT_BUF_CFG 0x20
44 #define NSP_MAGIC 0xab10
45 #define NSP_STATUS_MAGIC(x) (((x) >> 48) & 0xffff)
46 #define NSP_STATUS_MAJOR(x) (int)(((x) >> 44) & 0xf)
47 #define NSP_STATUS_MINOR(x) (int)(((x) >> 32) & 0xfff)
50 #define NSP_CMD_RESET 1
51 #define NSP_CMD_FW_LOAD 6
52 #define NSP_CMD_READ_ETH_TABLE 7
53 #define NSP_CMD_WRITE_ETH_TABLE 8
54 #define NSP_CMD_GET_SYMBOL 14
56 #define NSP_BUFFER_CFG_SIZE_MASK (0xff)
58 #define NSP_REG_ADDR(d, off, reg) ((uint8_t *)(d)->mem_base + (off) + (reg))
59 #define NSP_REG_VAL(p) (*(uint64_t *)(p))
62 * An NFP expansion BAR is configured for allowing access to a specific NFP
66 * desc: struct with basic NSP addresses to work with
67 * expbar: NFP PF expansion BAR index to configure
68 * tgt: NFP target to configure access
69 * addr: NFP target address
72 * pcie_offset: NFP PCI BAR offset to work with
75 nfp_nspu_mem_bar_cfg(nspu_desc_t *desc, int expbar, int tgt,
76 uint64_t addr, uint64_t *pcie_offset)
84 * NFP CPP address to configure. This comes from NFP 6000
85 * datasheet document based on Bulk mapping.
87 x = (addr >> (barsz - 3)) << (21 - (40 - (barsz - 3)));
88 x |= CFG_EXP_BAR_MAP_TYPE << EXP_BAR_MAP_TYPE_SHIFT;
89 x |= CFG_EXP_BAR_ADDR_SZ << EXP_BAR_LENGTH_SHIFT;
90 x |= tgt << EXP_BAR_TARGET_SHIFT;
92 /* Getting expansion bar configuration register address */
93 expbar_ptr = (uint32_t *)desc->cfg_base;
94 /* Each physical PCI BAR has 8 NFP expansion BARs */
95 expbar_ptr += (desc->pcie_bar * 8) + expbar;
97 /* Writing to the expansion BAR register */
98 *expbar_ptr = (uint32_t)x;
100 /* Getting the pcie offset to work with from userspace */
101 y = addr & ((uint64_t)(1 << (barsz - 3)) - 1);
106 * Configuring an expansion bar for accessing NSP userspace interface. This
107 * function configures always the same expansion bar, which implies access to
108 * previously configured NFP target is lost.
111 nspu_xlate(nspu_desc_t *desc, uint64_t addr, uint64_t *pcie_offset)
113 nfp_nspu_mem_bar_cfg(desc, desc->exp_bar, NFP_NSP_TARGET, addr,
118 nfp_nsp_get_abi_version(nspu_desc_t *desc, int *major, int *minor)
120 uint64_t pcie_offset;
123 nspu_xlate(desc, NSP_BASE, &pcie_offset);
124 nsp_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, pcie_offset, NSP_STATUS));
126 if (NSP_STATUS_MAGIC(nsp_reg) != NSP_MAGIC)
129 *major = NSP_STATUS_MAJOR(nsp_reg);
130 *minor = NSP_STATUS_MINOR(nsp_reg);
136 nfp_nspu_init(nspu_desc_t *desc, int nfp, int pcie_bar, size_t pcie_barsz,
137 int exp_bar, void *exp_bar_cfg_base, void *exp_bar_mmap)
139 uint64_t offset, buffaddr;
143 desc->pcie_bar = pcie_bar;
144 desc->exp_bar = exp_bar;
145 desc->barsz = pcie_barsz;
146 desc->windowsz = 1 << (desc->barsz - 3);
147 desc->cfg_base = exp_bar_cfg_base;
148 desc->mem_base = exp_bar_mmap;
150 nspu_xlate(desc, NSP_BASE, &offset);
153 * Other NSPU clients can use other buffers. Let's tell NSPU we use the
156 buffaddr = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_DEFAULT_BUF));
157 NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_BUFFER)) = buffaddr;
159 /* NFP internal addresses are 40 bits. Clean all other bits here */
160 buffaddr = buffaddr & (((uint64_t)1 << 40) - 1);
161 desc->bufaddr = buffaddr;
163 /* Lets get information about the buffer */
164 nsp_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_DEFAULT_BUF_CFG));
166 /* Buffer size comes in MBs. Coversion to bytes */
167 desc->buf_size = ((size_t)nsp_reg & NSP_BUFFER_CFG_SIZE_MASK) << 20;
172 #define NSPU_NFP_BUF(addr, base, off) \
173 (*(uint64_t *)((uint8_t *)(addr)->mem_base + ((base) | (off))))
175 #define NSPU_HOST_BUF(base, off) (*(uint64_t *)((uint8_t *)(base) + (off)))
178 nspu_buff_write(nspu_desc_t *desc, void *buffer, size_t size)
180 uint64_t pcie_offset, pcie_window_base, pcie_window_offset;
181 uint64_t windowsz = desc->windowsz;
182 uint64_t buffaddr, j, i = 0;
185 if (size > desc->buf_size)
188 buffaddr = desc->bufaddr;
189 windowsz = desc->windowsz;
192 /* Expansion bar reconfiguration per window size */
193 nspu_xlate(desc, buffaddr + i, &pcie_offset);
194 pcie_window_base = pcie_offset & (~(windowsz - 1));
195 pcie_window_offset = pcie_offset & (windowsz - 1);
196 for (j = pcie_window_offset; ((j < windowsz) && (i < size));
198 NSPU_NFP_BUF(desc, pcie_window_base, j) =
199 NSPU_HOST_BUF(buffer, i);
208 nspu_buff_read(nspu_desc_t *desc, void *buffer, size_t size)
210 uint64_t pcie_offset, pcie_window_base, pcie_window_offset;
211 uint64_t windowsz, i = 0, j;
215 if (size > desc->buf_size)
218 buffaddr = desc->bufaddr;
219 windowsz = desc->windowsz;
222 /* Expansion bar reconfiguration per window size */
223 nspu_xlate(desc, buffaddr + i, &pcie_offset);
224 pcie_window_base = pcie_offset & (~(windowsz - 1));
225 pcie_window_offset = pcie_offset & (windowsz - 1);
226 for (j = pcie_window_offset; ((j < windowsz) && (i < size));
228 NSPU_HOST_BUF(buffer, i) =
229 NSPU_NFP_BUF(desc, pcie_window_base, j);
238 nspu_command(nspu_desc_t *desc, uint16_t cmd, int read, int write,
239 void *buffer, size_t rsize, size_t wsize)
241 uint64_t status, cmd_reg;
247 /* Same expansion BAR is used for different things */
248 nspu_xlate(desc, NSP_BASE, &offset);
250 status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
252 while ((status & 0x1) && (retry < retries)) {
253 status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
258 if (retry == retries)
262 ret = nspu_buff_write(desc, buffer, wsize);
266 /* Expansion BAR changes when writing the buffer */
267 nspu_xlate(desc, NSP_BASE, &offset);
270 NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND)) =
271 (uint64_t)wsize << 32 | (uint64_t)cmd << 16 | 1;
275 cmd_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND));
276 while ((cmd_reg & 0x1) && (retry < retries)) {
277 cmd_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND));
281 if (retry == retries)
285 status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
286 while ((status & 0x1) && (retry < retries)) {
287 status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
292 if (retry == retries)
295 ret = status & (0xff << 8);
300 ret = nspu_buff_read(desc, buffer, rsize);
309 nfp_fw_reset(nspu_desc_t *nspu_desc)
313 res = nspu_command(nspu_desc, NSP_CMD_RESET, 0, 0, 0, 0, 0);
316 RTE_LOG(INFO, PMD, "fw reset failed: error %d", res);
321 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
322 #define DEFAULT_FW_FILENAME "nic_dpdk_default.nffw"
325 nfp_fw_upload(nspu_desc_t *nspu_desc)
330 struct stat file_stat;
335 size = nspu_desc->buf_size;
337 sprintf(filename, "%s/%s", DEFAULT_FW_PATH, DEFAULT_FW_FILENAME);
338 fw_f = open(filename, O_RDONLY);
340 RTE_LOG(INFO, PMD, "Firmware file %s/%s not found.",
341 DEFAULT_FW_PATH, DEFAULT_FW_FILENAME);
345 fstat(fw_f, &file_stat);
347 fsize = file_stat.st_size;
348 RTE_LOG(DEBUG, PMD, "Firmware file with size: %" PRIu64 "\n",
351 if (fsize > (off_t)size) {
352 RTE_LOG(INFO, PMD, "fw file too big: %" PRIu64
353 " bytes (%" PRIu64 " max)",
354 (uint64_t)fsize, (uint64_t)size);
358 fw_buf = malloc((size_t)size);
360 RTE_LOG(INFO, PMD, "malloc failed for fw buffer");
363 memset(fw_buf, 0, size);
365 bytes = read(fw_f, fw_buf, fsize);
366 if (bytes != fsize) {
367 RTE_LOG(INFO, PMD, "Reading fw to buffer failed.\n"
368 "Just %" PRIu64 " of %" PRIu64 " bytes read.",
369 (uint64_t)bytes, (uint64_t)fsize);
374 ret = nspu_command(nspu_desc, NSP_CMD_FW_LOAD, 0, 1, fw_buf, 0, bytes);
381 /* Firmware symbol descriptor size */
382 #define NFP_SYM_DESC_LEN 40
384 #define SYMBOL_DATA(b, off) (*(int64_t *)((b) + (off)))
385 #define SYMBOL_UDATA(b, off) (*(uint64_t *)((b) + (off)))
387 /* Firmware symbols contain information about how to access what they
388 * represent. It can be as simple as an numeric variable declared at a
389 * specific NFP memory, but it can also be more complex structures and
390 * related to specific hardware functionalities or components. Target,
391 * domain and address allow to create the BAR window for accessing such
392 * hw object and size defines the length to map.
394 * A vNIC is a network interface implemented inside the NFP and using a
395 * subset of device PCI BARs. Specific firmware symbols allow to map those
396 * vNIC bars by host drivers like the NFP PMD.
398 * Accessing what the symbol represents implies to map the access through
399 * a PCI BAR window. NFP expansion BARs are used in this regard through
400 * the NSPU interface.
403 nfp_nspu_set_bar_from_symbl(nspu_desc_t *desc, const char *symbl,
404 uint32_t expbar, uint64_t *pcie_offset,
414 sym_buf = malloc(desc->buf_size);
415 strncpy(sym_buf, symbl, strlen(symbl));
416 ret = nspu_command(desc, NSP_CMD_GET_SYMBOL, 1, 1, sym_buf,
417 NFP_SYM_DESC_LEN, strlen(symbl));
419 RTE_LOG(DEBUG, PMD, "symbol resolution (%s) failed\n", symbl);
423 /* Reading symbol information */
424 type = SYMBOL_DATA(sym_buf, 0);
425 target = SYMBOL_DATA(sym_buf, 8);
426 domain = SYMBOL_DATA(sym_buf, 16);
427 addr = SYMBOL_UDATA(sym_buf, 24);
428 *size = (ssize_t)SYMBOL_UDATA(sym_buf, 32);
431 RTE_LOG(INFO, PMD, "wrong symbol type\n");
435 if (!(target == 7 || target == -7)) {
436 RTE_LOG(INFO, PMD, "wrong symbol target\n");
440 if (domain == 8 || domain == 9) {
441 RTE_LOG(INFO, PMD, "wrong symbol domain\n");
446 /* Adjusting address based on symbol location */
447 if ((domain >= 24) && (domain < 28) && (target == 7)) {
448 addr = 1ULL << 37 | addr | ((uint64_t)domain & 0x3) << 35;
450 addr = 1ULL << 39 | addr | ((uint64_t)domain & 0x3f) << 32;
455 /* Configuring NFP expansion bar for mapping specific PCI BAR window */
456 nfp_nspu_mem_bar_cfg(desc, expbar, target, addr, pcie_offset);
458 /* This is the PCI BAR offset to use by the host */
459 *pcie_offset |= ((expbar & 0x7) << (desc->barsz - 3));
467 nfp_nsp_fw_setup(nspu_desc_t *desc, const char *sym, uint64_t *pcie_offset)
469 ssize_t bar0_sym_size;
471 /* If the symbol resolution works, it implies a firmware app
474 if (!nfp_nspu_set_bar_from_symbl(desc, sym, NFP_NET_PF_CFG_EXP_BAR,
475 pcie_offset, &bar0_sym_size))
478 /* No firmware app detected or not the right one */
479 RTE_LOG(INFO, PMD, "No firmware detected. Resetting NFP...\n");
480 if (nfp_fw_reset(desc) < 0) {
481 RTE_LOG(ERR, PMD, "nfp fw reset failed\n");
485 RTE_LOG(INFO, PMD, "Reset done.\n");
486 RTE_LOG(INFO, PMD, "Uploading firmware...\n");
488 if (nfp_fw_upload(desc) < 0) {
489 RTE_LOG(ERR, PMD, "nfp fw upload failed\n");
493 RTE_LOG(INFO, PMD, "Done.\n");
495 /* Now the symbol should be there */
496 if (nfp_nspu_set_bar_from_symbl(desc, sym, NFP_NET_PF_CFG_EXP_BAR,
497 pcie_offset, &bar0_sym_size)) {
498 RTE_LOG(ERR, PMD, "nfp PF BAR symbol resolution failed\n");
506 nfp_nsp_map_ctrl_bar(nspu_desc_t *desc, uint64_t *pcie_offset)
508 ssize_t bar0_sym_size;
510 if (nfp_nspu_set_bar_from_symbl(desc, "_pf0_net_bar0",
511 NFP_NET_PF_CFG_EXP_BAR,
512 pcie_offset, &bar0_sym_size))
519 * This is a hardcoded fixed NFP internal CPP bus address for the hw queues unit
520 * inside the PCIE island.
522 #define NFP_CPP_PCIE_QUEUES ((uint64_t)(1ULL << 39) | 0x80000 | \
523 ((uint64_t)0x4 & 0x3f) << 32)
525 /* Configure a specific NFP expansion bar for accessing the vNIC rx/tx BARs */
527 nfp_nsp_map_queues_bar(nspu_desc_t *desc, uint64_t *pcie_offset)
529 nfp_nspu_mem_bar_cfg(desc, NFP_NET_PF_HW_QUEUES_EXP_BAR, 0,
530 NFP_CPP_PCIE_QUEUES, pcie_offset);
532 /* This is the pcie offset to use by the host */
533 *pcie_offset |= ((NFP_NET_PF_HW_QUEUES_EXP_BAR & 0x7) << (27 - 3));
537 nfp_nsp_eth_config(nspu_desc_t *desc, int port, int up)
539 union eth_table_entry *entries, *entry;
546 RTE_LOG(INFO, PMD, "Hw ethernet port %d configure...\n", port);
547 rte_spinlock_lock(&desc->nsp_lock);
548 entries = malloc(NSP_ETH_TABLE_SIZE);
550 rte_spinlock_unlock(&desc->nsp_lock);
554 ret = nspu_command(desc, NSP_CMD_READ_ETH_TABLE, 1, 0, entries,
555 NSP_ETH_TABLE_SIZE, 0);
557 rte_spinlock_unlock(&desc->nsp_lock);
563 for (i = 0; i < NSP_ETH_MAX_COUNT; i++) {
564 /* ports in use do not appear sequentially in the table */
565 if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) {
566 /* entry not in use */
576 if (i == NSP_ETH_MAX_COUNT) {
577 rte_spinlock_unlock(&desc->nsp_lock);
581 if (up && !(entry->state & NSP_ETH_STATE_CONFIGURED)) {
582 entry->control |= NSP_ETH_STATE_CONFIGURED;
586 if (!up && (entry->state & NSP_ETH_STATE_CONFIGURED)) {
587 entry->control &= ~NSP_ETH_STATE_CONFIGURED;
592 ret = nspu_command(desc, NSP_CMD_WRITE_ETH_TABLE, 0, 1, entries,
593 0, NSP_ETH_TABLE_SIZE);
596 "Hw ethernet port %d configure done\n", port);
599 "Hw ethernet port %d configure failed\n", port);
601 rte_spinlock_unlock(&desc->nsp_lock);