1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
9 #include "ngbe_eeprom.h"
14 * ngbe_start_hw - Prepare hardware for Tx/Rx
15 * @hw: pointer to hardware structure
17 * Starts the hardware.
19 s32 ngbe_start_hw(struct ngbe_hw *hw)
23 DEBUGFUNC("ngbe_start_hw");
25 /* Clear the VLAN filter table */
26 hw->mac.clear_vfta(hw);
28 /* Clear statistics registers */
29 hw->mac.clear_hw_cntrs(hw);
31 /* Setup flow control */
32 err = hw->mac.setup_fc(hw);
33 if (err != 0 && err != NGBE_NOT_IMPLEMENTED) {
34 DEBUGOUT("Flow control setup failed, returning %d\n", err);
38 /* Clear adapter stopped flag */
39 hw->adapter_stopped = false;
45 * ngbe_init_hw - Generic hardware initialization
46 * @hw: pointer to hardware structure
48 * Initialize the hardware by resetting the hardware, filling the bus info
49 * structure and media type, clears all on chip counters, initializes receive
50 * address registers, multicast table, VLAN filter table, calls routine to set
51 * up link and flow control settings, and leaves transmit and receive units
52 * disabled and uninitialized
54 s32 ngbe_init_hw(struct ngbe_hw *hw)
58 DEBUGFUNC("ngbe_init_hw");
60 ngbe_save_eeprom_version(hw);
62 /* Reset the hardware */
63 status = hw->mac.reset_hw(hw);
66 status = hw->mac.start_hw(hw);
70 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
76 ngbe_reset_misc_em(struct ngbe_hw *hw)
80 wr32(hw, NGBE_ISBADDRL, hw->isb_dma & 0xFFFFFFFF);
81 wr32(hw, NGBE_ISBADDRH, hw->isb_dma >> 32);
83 /* receive packets that size > 2048 */
84 wr32m(hw, NGBE_MACRXCFG,
85 NGBE_MACRXCFG_JUMBO, NGBE_MACRXCFG_JUMBO);
87 wr32m(hw, NGBE_FRMSZ, NGBE_FRMSZ_MAX_MASK,
88 NGBE_FRMSZ_MAX(NGBE_FRAME_SIZE_DFT));
90 /* clear counters on read */
91 wr32m(hw, NGBE_MACCNTCTL,
92 NGBE_MACCNTCTL_RC, NGBE_MACCNTCTL_RC);
94 wr32m(hw, NGBE_RXFCCFG,
95 NGBE_RXFCCFG_FC, NGBE_RXFCCFG_FC);
96 wr32m(hw, NGBE_TXFCCFG,
97 NGBE_TXFCCFG_FC, NGBE_TXFCCFG_FC);
99 wr32m(hw, NGBE_MACRXFLT,
100 NGBE_MACRXFLT_PROMISC, NGBE_MACRXFLT_PROMISC);
102 wr32m(hw, NGBE_RSTSTAT,
103 NGBE_RSTSTAT_TMRINIT_MASK, NGBE_RSTSTAT_TMRINIT(30));
105 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
106 wr32(hw, NGBE_MNGFLEXSEL, 0);
107 for (i = 0; i < 16; i++) {
108 wr32(hw, NGBE_MNGFLEXDWL(i), 0);
109 wr32(hw, NGBE_MNGFLEXDWH(i), 0);
110 wr32(hw, NGBE_MNGFLEXMSK(i), 0);
112 wr32(hw, NGBE_LANFLEXSEL, 0);
113 for (i = 0; i < 16; i++) {
114 wr32(hw, NGBE_LANFLEXDWL(i), 0);
115 wr32(hw, NGBE_LANFLEXDWH(i), 0);
116 wr32(hw, NGBE_LANFLEXMSK(i), 0);
119 /* set pause frame dst mac addr */
120 wr32(hw, NGBE_RXPBPFCDMACL, 0xC2000001);
121 wr32(hw, NGBE_RXPBPFCDMACH, 0x0180);
123 wr32(hw, NGBE_MDIOMODE, 0xF);
125 wr32m(hw, NGBE_GPIE, NGBE_GPIE_MSIX, NGBE_GPIE_MSIX);
127 if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
128 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
129 /* gpio0 is used to power on/off control*/
130 wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));
131 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);
134 hw->mac.init_thermal_sensor_thresh(hw);
136 /* enable mac transmitter */
137 wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_TE, NGBE_MACTXCFG_TE);
140 wr32m(hw, NGBE_MACTXCFG,
141 NGBE_MACTXCFG_SPEED_MASK, NGBE_MACTXCFG_SPEED_1G);
143 for (i = 0; i < 4; i++)
144 wr32m(hw, NGBE_IVAR(i), 0x80808080, 0);
148 * ngbe_reset_hw_em - Perform hardware reset
149 * @hw: pointer to hardware structure
151 * Resets the hardware by resetting the transmit and receive units, masks
152 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
155 s32 ngbe_reset_hw_em(struct ngbe_hw *hw)
159 DEBUGFUNC("ngbe_reset_hw_em");
161 /* Call adapter stop to disable tx/rx and clear interrupts */
162 status = hw->mac.stop_hw(hw);
166 /* Identify PHY and related function pointers */
167 status = ngbe_init_phy(hw);
172 if (!hw->phy.reset_disable)
173 hw->phy.reset_hw(hw);
175 wr32(hw, NGBE_RST, NGBE_RST_LAN(hw->bus.lan_id));
179 ngbe_reset_misc_em(hw);
180 hw->mac.clear_hw_cntrs(hw);
184 /* Store the permanent mac address */
185 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
188 * Store MAC address from RAR0, clear receive address registers, and
189 * clear the multicast table.
191 hw->mac.num_rar_entries = NGBE_EM_RAR_ENTRIES;
192 hw->mac.init_rx_addrs(hw);
198 * ngbe_clear_hw_cntrs - Generic clear hardware counters
199 * @hw: pointer to hardware structure
201 * Clears all hardware statistics counters by reading them from the hardware
202 * Statistics counters are clear on read.
204 s32 ngbe_clear_hw_cntrs(struct ngbe_hw *hw)
208 DEBUGFUNC("ngbe_clear_hw_cntrs");
211 /* don't write clear queue stats */
212 for (i = 0; i < NGBE_MAX_QP; i++) {
213 hw->qp_last[i].rx_qp_packets = 0;
214 hw->qp_last[i].tx_qp_packets = 0;
215 hw->qp_last[i].rx_qp_bytes = 0;
216 hw->qp_last[i].tx_qp_bytes = 0;
217 hw->qp_last[i].rx_qp_mc_packets = 0;
218 hw->qp_last[i].tx_qp_mc_packets = 0;
219 hw->qp_last[i].rx_qp_bc_packets = 0;
220 hw->qp_last[i].tx_qp_bc_packets = 0;
224 rd32(hw, NGBE_PBRXLNKXON);
225 rd32(hw, NGBE_PBRXLNKXOFF);
226 rd32(hw, NGBE_PBTXLNKXON);
227 rd32(hw, NGBE_PBTXLNKXOFF);
230 rd32(hw, NGBE_DMARXPKT);
231 rd32(hw, NGBE_DMATXPKT);
233 rd64(hw, NGBE_DMARXOCTL);
234 rd64(hw, NGBE_DMATXOCTL);
237 rd64(hw, NGBE_MACRXERRCRCL);
238 rd64(hw, NGBE_MACRXMPKTL);
239 rd64(hw, NGBE_MACTXMPKTL);
241 rd64(hw, NGBE_MACRXPKTL);
242 rd64(hw, NGBE_MACTXPKTL);
243 rd64(hw, NGBE_MACRXGBOCTL);
245 rd64(hw, NGBE_MACRXOCTL);
246 rd32(hw, NGBE_MACTXOCTL);
248 rd64(hw, NGBE_MACRX1TO64L);
249 rd64(hw, NGBE_MACRX65TO127L);
250 rd64(hw, NGBE_MACRX128TO255L);
251 rd64(hw, NGBE_MACRX256TO511L);
252 rd64(hw, NGBE_MACRX512TO1023L);
253 rd64(hw, NGBE_MACRX1024TOMAXL);
254 rd64(hw, NGBE_MACTX1TO64L);
255 rd64(hw, NGBE_MACTX65TO127L);
256 rd64(hw, NGBE_MACTX128TO255L);
257 rd64(hw, NGBE_MACTX256TO511L);
258 rd64(hw, NGBE_MACTX512TO1023L);
259 rd64(hw, NGBE_MACTX1024TOMAXL);
261 rd64(hw, NGBE_MACRXERRLENL);
262 rd32(hw, NGBE_MACRXOVERSIZE);
263 rd32(hw, NGBE_MACRXJABBER);
266 rd32(hw, NGBE_LSECTX_UTPKT);
267 rd32(hw, NGBE_LSECTX_ENCPKT);
268 rd32(hw, NGBE_LSECTX_PROTPKT);
269 rd32(hw, NGBE_LSECTX_ENCOCT);
270 rd32(hw, NGBE_LSECTX_PROTOCT);
271 rd32(hw, NGBE_LSECRX_UTPKT);
272 rd32(hw, NGBE_LSECRX_BTPKT);
273 rd32(hw, NGBE_LSECRX_NOSCIPKT);
274 rd32(hw, NGBE_LSECRX_UNSCIPKT);
275 rd32(hw, NGBE_LSECRX_DECOCT);
276 rd32(hw, NGBE_LSECRX_VLDOCT);
277 rd32(hw, NGBE_LSECRX_UNCHKPKT);
278 rd32(hw, NGBE_LSECRX_DLYPKT);
279 rd32(hw, NGBE_LSECRX_LATEPKT);
280 for (i = 0; i < 2; i++) {
281 rd32(hw, NGBE_LSECRX_OKPKT(i));
282 rd32(hw, NGBE_LSECRX_INVPKT(i));
283 rd32(hw, NGBE_LSECRX_BADPKT(i));
285 for (i = 0; i < 4; i++) {
286 rd32(hw, NGBE_LSECRX_INVSAPKT(i));
287 rd32(hw, NGBE_LSECRX_BADSAPKT(i));
294 * ngbe_get_mac_addr - Generic get MAC address
295 * @hw: pointer to hardware structure
296 * @mac_addr: Adapter MAC address
298 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
299 * A reset of the adapter must be performed prior to calling this function
300 * in order for the MAC address to have been loaded from the EEPROM into RAR0
302 s32 ngbe_get_mac_addr(struct ngbe_hw *hw, u8 *mac_addr)
308 DEBUGFUNC("ngbe_get_mac_addr");
310 wr32(hw, NGBE_ETHADDRIDX, 0);
311 rar_high = rd32(hw, NGBE_ETHADDRH);
312 rar_low = rd32(hw, NGBE_ETHADDRL);
314 for (i = 0; i < 2; i++)
315 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
317 for (i = 0; i < 4; i++)
318 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
324 * ngbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
325 * @hw: pointer to the HW structure
327 * Determines the LAN function id by reading memory-mapped registers and swaps
328 * the port value if requested, and set MAC instance for devices.
330 void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw)
332 struct ngbe_bus_info *bus = &hw->bus;
335 DEBUGFUNC("ngbe_set_lan_id_multi_port");
337 reg = rd32(hw, NGBE_PORTSTAT);
338 bus->lan_id = NGBE_PORTSTAT_ID(reg);
339 bus->func = bus->lan_id;
343 * ngbe_stop_hw - Generic stop Tx/Rx units
344 * @hw: pointer to hardware structure
346 * Sets the adapter_stopped flag within ngbe_hw struct. Clears interrupts,
347 * disables transmit and receive units. The adapter_stopped flag is used by
348 * the shared code and drivers to determine if the adapter is in a stopped
349 * state and should not touch the hardware.
351 s32 ngbe_stop_hw(struct ngbe_hw *hw)
356 DEBUGFUNC("ngbe_stop_hw");
359 * Set the adapter_stopped flag so other driver functions stop touching
362 hw->adapter_stopped = true;
364 /* Disable the receive unit */
367 /* Clear interrupt mask to stop interrupts from being generated */
368 wr32(hw, NGBE_IENMISC, 0);
369 wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK);
371 /* Clear any pending interrupts, flush previous writes */
372 wr32(hw, NGBE_ICRMISC, NGBE_ICRMISC_MASK);
373 wr32(hw, NGBE_ICR(0), NGBE_ICR_MASK);
375 /* Disable the transmit unit. Each queue must be disabled. */
376 for (i = 0; i < hw->mac.max_tx_queues; i++)
377 wr32(hw, NGBE_TXCFG(i), NGBE_TXCFG_FLUSH);
379 /* Disable the receive unit by stopping each queue */
380 for (i = 0; i < hw->mac.max_rx_queues; i++) {
381 reg_val = rd32(hw, NGBE_RXCFG(i));
382 reg_val &= ~NGBE_RXCFG_ENA;
383 wr32(hw, NGBE_RXCFG(i), reg_val);
386 /* flush all queues disables */
394 * ngbe_led_on - Turns on the software controllable LEDs.
395 * @hw: pointer to hardware structure
396 * @index: led number to turn on
398 s32 ngbe_led_on(struct ngbe_hw *hw, u32 index)
400 u32 led_reg = rd32(hw, NGBE_LEDCTL);
402 DEBUGFUNC("ngbe_led_on");
405 return NGBE_ERR_PARAM;
407 /* To turn on the LED, set mode to ON. */
408 led_reg |= NGBE_LEDCTL_100M;
409 wr32(hw, NGBE_LEDCTL, led_reg);
416 * ngbe_led_off - Turns off the software controllable LEDs.
417 * @hw: pointer to hardware structure
418 * @index: led number to turn off
420 s32 ngbe_led_off(struct ngbe_hw *hw, u32 index)
422 u32 led_reg = rd32(hw, NGBE_LEDCTL);
424 DEBUGFUNC("ngbe_led_off");
427 return NGBE_ERR_PARAM;
429 /* To turn off the LED, set mode to OFF. */
430 led_reg &= ~NGBE_LEDCTL_100M;
431 wr32(hw, NGBE_LEDCTL, led_reg);
438 * ngbe_validate_mac_addr - Validate MAC address
439 * @mac_addr: pointer to MAC address.
441 * Tests a MAC address to ensure it is a valid Individual Address.
443 s32 ngbe_validate_mac_addr(u8 *mac_addr)
447 DEBUGFUNC("ngbe_validate_mac_addr");
449 /* Make sure it is not a multicast address */
450 if (NGBE_IS_MULTICAST((struct rte_ether_addr *)mac_addr)) {
451 status = NGBE_ERR_INVALID_MAC_ADDR;
452 /* Not a broadcast address */
453 } else if (NGBE_IS_BROADCAST((struct rte_ether_addr *)mac_addr)) {
454 status = NGBE_ERR_INVALID_MAC_ADDR;
455 /* Reject the zero address */
456 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
457 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
458 status = NGBE_ERR_INVALID_MAC_ADDR;
464 * ngbe_set_rar - Set Rx address register
465 * @hw: pointer to hardware structure
466 * @index: Receive address register to write
467 * @addr: Address to put into receive address register
468 * @vmdq: VMDq "set" or "pool" index
469 * @enable_addr: set flag that address is active
471 * Puts an ethernet address into a receive address register.
473 s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
476 u32 rar_low, rar_high;
477 u32 rar_entries = hw->mac.num_rar_entries;
479 DEBUGFUNC("ngbe_set_rar");
481 /* Make sure we are using a valid rar index range */
482 if (index >= rar_entries) {
483 DEBUGOUT("RAR index %d is out of range.\n", index);
484 return NGBE_ERR_INVALID_ARGUMENT;
487 /* setup VMDq pool selection before this RAR gets enabled */
488 hw->mac.set_vmdq(hw, index, vmdq);
491 * HW expects these in little endian so we reverse the byte
492 * order from network order (big endian) to little endian
494 rar_low = NGBE_ETHADDRL_AD0(addr[5]) |
495 NGBE_ETHADDRL_AD1(addr[4]) |
496 NGBE_ETHADDRL_AD2(addr[3]) |
497 NGBE_ETHADDRL_AD3(addr[2]);
499 * Some parts put the VMDq setting in the extra RAH bits,
500 * so save everything except the lower 16 bits that hold part
501 * of the address and the address valid bit.
503 rar_high = rd32(hw, NGBE_ETHADDRH);
504 rar_high &= ~NGBE_ETHADDRH_AD_MASK;
505 rar_high |= (NGBE_ETHADDRH_AD4(addr[1]) |
506 NGBE_ETHADDRH_AD5(addr[0]));
508 rar_high &= ~NGBE_ETHADDRH_VLD;
509 if (enable_addr != 0)
510 rar_high |= NGBE_ETHADDRH_VLD;
512 wr32(hw, NGBE_ETHADDRIDX, index);
513 wr32(hw, NGBE_ETHADDRL, rar_low);
514 wr32(hw, NGBE_ETHADDRH, rar_high);
520 * ngbe_clear_rar - Remove Rx address register
521 * @hw: pointer to hardware structure
522 * @index: Receive address register to write
524 * Clears an ethernet address from a receive address register.
526 s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index)
529 u32 rar_entries = hw->mac.num_rar_entries;
531 DEBUGFUNC("ngbe_clear_rar");
533 /* Make sure we are using a valid rar index range */
534 if (index >= rar_entries) {
535 DEBUGOUT("RAR index %d is out of range.\n", index);
536 return NGBE_ERR_INVALID_ARGUMENT;
540 * Some parts put the VMDq setting in the extra RAH bits,
541 * so save everything except the lower 16 bits that hold part
542 * of the address and the address valid bit.
544 wr32(hw, NGBE_ETHADDRIDX, index);
545 rar_high = rd32(hw, NGBE_ETHADDRH);
546 rar_high &= ~(NGBE_ETHADDRH_AD_MASK | NGBE_ETHADDRH_VLD);
548 wr32(hw, NGBE_ETHADDRL, 0);
549 wr32(hw, NGBE_ETHADDRH, rar_high);
551 /* clear VMDq pool/queue selection for this RAR */
552 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
558 * ngbe_init_rx_addrs - Initializes receive address filters.
559 * @hw: pointer to hardware structure
561 * Places the MAC address in receive address register 0 and clears the rest
562 * of the receive address registers. Clears the multicast table. Assumes
563 * the receiver is in reset when the routine is called.
565 s32 ngbe_init_rx_addrs(struct ngbe_hw *hw)
569 u32 rar_entries = hw->mac.num_rar_entries;
571 DEBUGFUNC("ngbe_init_rx_addrs");
574 * If the current mac address is valid, assume it is a software override
575 * to the permanent address.
576 * Otherwise, use the permanent address from the eeprom.
578 if (ngbe_validate_mac_addr(hw->mac.addr) ==
579 NGBE_ERR_INVALID_MAC_ADDR) {
580 /* Get the MAC address from the RAR0 for later reference */
581 hw->mac.get_mac_addr(hw, hw->mac.addr);
583 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
584 hw->mac.addr[0], hw->mac.addr[1],
586 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
587 hw->mac.addr[4], hw->mac.addr[5]);
589 /* Setup the receive address. */
590 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
591 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
592 hw->mac.addr[0], hw->mac.addr[1],
594 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
595 hw->mac.addr[4], hw->mac.addr[5]);
597 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
600 /* clear VMDq pool/queue selection for RAR 0 */
601 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
603 /* Zero out the other receive addresses. */
604 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
605 for (i = 1; i < rar_entries; i++) {
606 wr32(hw, NGBE_ETHADDRIDX, i);
607 wr32(hw, NGBE_ETHADDRL, 0);
608 wr32(hw, NGBE_ETHADDRH, 0);
612 hw->addr_ctrl.mta_in_use = 0;
613 psrctl = rd32(hw, NGBE_PSRCTL);
614 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
615 psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
616 wr32(hw, NGBE_PSRCTL, psrctl);
618 DEBUGOUT(" Clearing MTA\n");
619 for (i = 0; i < hw->mac.mcft_size; i++)
620 wr32(hw, NGBE_MCADDRTBL(i), 0);
622 ngbe_init_uta_tables(hw);
628 * ngbe_mta_vector - Determines bit-vector in multicast table to set
629 * @hw: pointer to hardware structure
630 * @mc_addr: the multicast address
632 * Extracts the 12 bits, from a multicast address, to determine which
633 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
634 * incoming rx multicast addresses, to determine the bit-vector to check in
635 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
636 * by the MO field of the PSRCTRL. The MO field is set during initialization
639 static s32 ngbe_mta_vector(struct ngbe_hw *hw, u8 *mc_addr)
643 DEBUGFUNC("ngbe_mta_vector");
645 switch (hw->mac.mc_filter_type) {
646 case 0: /* use bits [47:36] of the address */
647 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
649 case 1: /* use bits [46:35] of the address */
650 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
652 case 2: /* use bits [45:34] of the address */
653 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
655 case 3: /* use bits [43:32] of the address */
656 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
658 default: /* Invalid mc_filter_type */
659 DEBUGOUT("MC filter type param set incorrectly\n");
664 /* vector can only be 12-bits or boundary will be exceeded */
670 * ngbe_set_mta - Set bit-vector in multicast table
671 * @hw: pointer to hardware structure
672 * @mc_addr: Multicast address
674 * Sets the bit-vector in the multicast table.
676 void ngbe_set_mta(struct ngbe_hw *hw, u8 *mc_addr)
682 DEBUGFUNC("ngbe_set_mta");
684 hw->addr_ctrl.mta_in_use++;
686 vector = ngbe_mta_vector(hw, mc_addr);
687 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
690 * The MTA is a register array of 128 32-bit registers. It is treated
691 * like an array of 4096 bits. We want to set bit
692 * BitArray[vector_value]. So we figure out what register the bit is
693 * in, read it, OR in the new bit, then write back the new value. The
694 * register is determined by the upper 7 bits of the vector value and
695 * the bit within that register are determined by the lower 5 bits of
698 vector_reg = (vector >> 5) & 0x7F;
699 vector_bit = vector & 0x1F;
700 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
704 * ngbe_update_mc_addr_list - Updates MAC list of multicast addresses
705 * @hw: pointer to hardware structure
706 * @mc_addr_list: the list of new multicast addresses
707 * @mc_addr_count: number of addresses
708 * @next: iterator function to walk the multicast address list
709 * @clear: flag, when set clears the table beforehand
711 * When the clear flag is set, the given list replaces any existing list.
712 * Hashes the given addresses into the multicast table.
714 s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list,
715 u32 mc_addr_count, ngbe_mc_addr_itr next,
721 DEBUGFUNC("ngbe_update_mc_addr_list");
724 * Set the new number of MC addresses that we are being requested to
727 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
728 hw->addr_ctrl.mta_in_use = 0;
730 /* Clear mta_shadow */
732 DEBUGOUT(" Clearing MTA\n");
733 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
736 /* Update mta_shadow */
737 for (i = 0; i < mc_addr_count; i++) {
738 DEBUGOUT(" Adding the multicast addresses:\n");
739 ngbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
743 for (i = 0; i < hw->mac.mcft_size; i++)
744 wr32a(hw, NGBE_MCADDRTBL(0), i,
745 hw->mac.mta_shadow[i]);
747 if (hw->addr_ctrl.mta_in_use > 0) {
748 u32 psrctl = rd32(hw, NGBE_PSRCTL);
749 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
750 psrctl |= NGBE_PSRCTL_MCHFENA |
751 NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
752 wr32(hw, NGBE_PSRCTL, psrctl);
755 DEBUGOUT("ngbe update mc addr list complete\n");
760 * ngbe_setup_fc_em - Set up flow control
761 * @hw: pointer to hardware structure
763 * Called at init time to set up flow control.
765 s32 ngbe_setup_fc_em(struct ngbe_hw *hw)
770 DEBUGFUNC("ngbe_setup_fc");
772 /* Validate the requested mode */
773 if (hw->fc.strict_ieee && hw->fc.requested_mode == ngbe_fc_rx_pause) {
774 DEBUGOUT("ngbe_fc_rx_pause not valid in strict IEEE mode\n");
775 err = NGBE_ERR_INVALID_LINK_SETTINGS;
780 * 1gig parts do not have a word in the EEPROM to determine the
781 * default flow control setting, so we explicitly set it to full.
783 if (hw->fc.requested_mode == ngbe_fc_default)
784 hw->fc.requested_mode = ngbe_fc_full;
787 * The possible values of fc.requested_mode are:
788 * 0: Flow control is completely disabled
789 * 1: Rx flow control is enabled (we can receive pause frames,
790 * but not send pause frames).
791 * 2: Tx flow control is enabled (we can send pause frames but
792 * we do not support receiving pause frames).
793 * 3: Both Rx and Tx flow control (symmetric) are enabled.
796 switch (hw->fc.requested_mode) {
798 /* Flow control completely disabled by software override. */
800 case ngbe_fc_tx_pause:
802 * Tx Flow control is enabled, and Rx Flow control is
803 * disabled by software override.
805 if (hw->phy.type == ngbe_phy_mvl_sfi ||
806 hw->phy.type == ngbe_phy_yt8521s_sfi)
807 reg_cu |= MVL_FANA_ASM_PAUSE;
809 reg_cu |= 0x800; /*need to merge rtl and mvl on page 0*/
811 case ngbe_fc_rx_pause:
813 * Rx Flow control is enabled and Tx Flow control is
814 * disabled by software override. Since there really
815 * isn't a way to advertise that we are capable of RX
816 * Pause ONLY, we will advertise that we support both
817 * symmetric and asymmetric Rx PAUSE, as such we fall
818 * through to the fc_full statement. Later, we will
819 * disable the adapter's ability to send PAUSE frames.
822 /* Flow control (both Rx and Tx) is enabled by SW override. */
823 if (hw->phy.type == ngbe_phy_mvl_sfi ||
824 hw->phy.type == ngbe_phy_yt8521s_sfi)
825 reg_cu |= MVL_FANA_SYM_PAUSE;
827 reg_cu |= 0xC00; /*need to merge rtl and mvl on page 0*/
830 DEBUGOUT("Flow control param set incorrectly\n");
831 err = NGBE_ERR_CONFIG;
835 err = hw->phy.set_pause_adv(hw, reg_cu);
842 * ngbe_fc_enable - Enable flow control
843 * @hw: pointer to hardware structure
845 * Enable flow control according to the current settings.
847 s32 ngbe_fc_enable(struct ngbe_hw *hw)
850 u32 mflcn_reg, fccfg_reg;
854 DEBUGFUNC("ngbe_fc_enable");
856 /* Validate the water mark configuration */
857 if (!hw->fc.pause_time) {
858 err = NGBE_ERR_INVALID_LINK_SETTINGS;
862 /* Low water mark of zero causes XOFF floods */
863 if ((hw->fc.current_mode & ngbe_fc_tx_pause) && hw->fc.high_water) {
864 if (!hw->fc.low_water ||
865 hw->fc.low_water >= hw->fc.high_water) {
866 DEBUGOUT("Invalid water mark configuration\n");
867 err = NGBE_ERR_INVALID_LINK_SETTINGS;
872 /* Negotiate the fc mode to use */
873 hw->mac.fc_autoneg(hw);
875 /* Disable any previous flow control settings */
876 mflcn_reg = rd32(hw, NGBE_RXFCCFG);
877 mflcn_reg &= ~NGBE_RXFCCFG_FC;
879 fccfg_reg = rd32(hw, NGBE_TXFCCFG);
880 fccfg_reg &= ~NGBE_TXFCCFG_FC;
882 * The possible values of fc.current_mode are:
883 * 0: Flow control is completely disabled
884 * 1: Rx flow control is enabled (we can receive pause frames,
885 * but not send pause frames).
886 * 2: Tx flow control is enabled (we can send pause frames but
887 * we do not support receiving pause frames).
888 * 3: Both Rx and Tx flow control (symmetric) are enabled.
891 switch (hw->fc.current_mode) {
894 * Flow control is disabled by software override or autoneg.
895 * The code below will actually disable it in the HW.
898 case ngbe_fc_rx_pause:
900 * Rx Flow control is enabled and Tx Flow control is
901 * disabled by software override. Since there really
902 * isn't a way to advertise that we are capable of RX
903 * Pause ONLY, we will advertise that we support both
904 * symmetric and asymmetric Rx PAUSE. Later, we will
905 * disable the adapter's ability to send PAUSE frames.
907 mflcn_reg |= NGBE_RXFCCFG_FC;
909 case ngbe_fc_tx_pause:
911 * Tx Flow control is enabled, and Rx Flow control is
912 * disabled by software override.
914 fccfg_reg |= NGBE_TXFCCFG_FC;
917 /* Flow control (both Rx and Tx) is enabled by SW override. */
918 mflcn_reg |= NGBE_RXFCCFG_FC;
919 fccfg_reg |= NGBE_TXFCCFG_FC;
922 DEBUGOUT("Flow control param set incorrectly\n");
923 err = NGBE_ERR_CONFIG;
927 /* Set 802.3x based flow control settings. */
928 wr32(hw, NGBE_RXFCCFG, mflcn_reg);
929 wr32(hw, NGBE_TXFCCFG, fccfg_reg);
931 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
932 if ((hw->fc.current_mode & ngbe_fc_tx_pause) &&
934 fcrtl = NGBE_FCWTRLO_TH(hw->fc.low_water) |
936 fcrth = NGBE_FCWTRHI_TH(hw->fc.high_water) |
940 * In order to prevent Tx hangs when the internal Tx
941 * switch is enabled we must set the high water mark
942 * to the Rx packet buffer size - 24KB. This allows
943 * the Tx switch to function even under heavy Rx
947 fcrth = rd32(hw, NGBE_PBRXSIZE) - 24576;
949 wr32(hw, NGBE_FCWTRLO, fcrtl);
950 wr32(hw, NGBE_FCWTRHI, fcrth);
952 /* Configure pause time */
953 pause_time = NGBE_RXFCFSH_TIME(hw->fc.pause_time);
954 wr32(hw, NGBE_FCXOFFTM, pause_time * 0x00010000);
956 /* Configure flow control refresh threshold value */
957 wr32(hw, NGBE_RXFCRFSH, hw->fc.pause_time / 2);
964 * ngbe_negotiate_fc - Negotiate flow control
965 * @hw: pointer to hardware structure
966 * @adv_reg: flow control advertised settings
967 * @lp_reg: link partner's flow control settings
968 * @adv_sym: symmetric pause bit in advertisement
969 * @adv_asm: asymmetric pause bit in advertisement
970 * @lp_sym: symmetric pause bit in link partner advertisement
971 * @lp_asm: asymmetric pause bit in link partner advertisement
973 * Find the intersection between advertised settings and link partner's
974 * advertised settings
976 s32 ngbe_negotiate_fc(struct ngbe_hw *hw, u32 adv_reg, u32 lp_reg,
977 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
979 if ((!(adv_reg)) || (!(lp_reg))) {
980 DEBUGOUT("Local or link partner's advertised flow control "
981 "settings are NULL. Local: %x, link partner: %x\n",
983 return NGBE_ERR_FC_NOT_NEGOTIATED;
986 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
988 * Now we need to check if the user selected Rx ONLY
989 * of pause frames. In this case, we had to advertise
990 * FULL flow control because we could not advertise RX
991 * ONLY. Hence, we must now check to see if we need to
992 * turn OFF the TRANSMISSION of PAUSE frames.
994 if (hw->fc.requested_mode == ngbe_fc_full) {
995 hw->fc.current_mode = ngbe_fc_full;
996 DEBUGOUT("Flow Control = FULL.\n");
998 hw->fc.current_mode = ngbe_fc_rx_pause;
999 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
1001 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1002 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1003 hw->fc.current_mode = ngbe_fc_tx_pause;
1004 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1005 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1006 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1007 hw->fc.current_mode = ngbe_fc_rx_pause;
1008 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1010 hw->fc.current_mode = ngbe_fc_none;
1011 DEBUGOUT("Flow Control = NONE.\n");
1017 * ngbe_fc_autoneg_em - Enable flow control IEEE clause 37
1018 * @hw: pointer to hardware structure
1020 * Enable flow control according to IEEE clause 37.
1022 STATIC s32 ngbe_fc_autoneg_em(struct ngbe_hw *hw)
1024 u8 technology_ability_reg = 0;
1025 u8 lp_technology_ability_reg = 0;
1027 hw->phy.get_adv_pause(hw, &technology_ability_reg);
1028 hw->phy.get_lp_adv_pause(hw, &lp_technology_ability_reg);
1030 return ngbe_negotiate_fc(hw, (u32)technology_ability_reg,
1031 (u32)lp_technology_ability_reg,
1032 NGBE_TAF_SYM_PAUSE, NGBE_TAF_ASM_PAUSE,
1033 NGBE_TAF_SYM_PAUSE, NGBE_TAF_ASM_PAUSE);
1037 * ngbe_fc_autoneg - Configure flow control
1038 * @hw: pointer to hardware structure
1040 * Compares our advertised flow control capabilities to those advertised by
1041 * our link partner, and determines the proper flow control mode to use.
1043 void ngbe_fc_autoneg(struct ngbe_hw *hw)
1045 s32 err = NGBE_ERR_FC_NOT_NEGOTIATED;
1049 DEBUGFUNC("ngbe_fc_autoneg");
1052 * AN should have completed when the cable was plugged in.
1053 * Look for reasons to bail out. Bail out if:
1054 * - FC autoneg is disabled, or if
1057 if (hw->fc.disable_fc_autoneg) {
1058 DEBUGOUT("Flow control autoneg is disabled");
1062 hw->mac.check_link(hw, &speed, &link_up, false);
1064 DEBUGOUT("The link is down");
1068 err = ngbe_fc_autoneg_em(hw);
1072 hw->fc.fc_was_autonegged = true;
1074 hw->fc.fc_was_autonegged = false;
1075 hw->fc.current_mode = hw->fc.requested_mode;
1080 * ngbe_acquire_swfw_sync - Acquire SWFW semaphore
1081 * @hw: pointer to hardware structure
1082 * @mask: Mask to specify which semaphore to acquire
1084 * Acquires the SWFW semaphore through the MNGSEM register for the specified
1085 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1087 s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask)
1090 u32 swmask = NGBE_MNGSEM_SW(mask);
1091 u32 fwmask = NGBE_MNGSEM_FW(mask);
1095 DEBUGFUNC("ngbe_acquire_swfw_sync");
1097 for (i = 0; i < timeout; i++) {
1099 * SW NVM semaphore bit is used for access to all
1100 * SW_FW_SYNC bits (not just NVM)
1102 if (ngbe_get_eeprom_semaphore(hw))
1103 return NGBE_ERR_SWFW_SYNC;
1105 mngsem = rd32(hw, NGBE_MNGSEM);
1106 if (mngsem & (fwmask | swmask)) {
1107 /* Resource is currently in use by FW or SW */
1108 ngbe_release_eeprom_semaphore(hw);
1112 wr32(hw, NGBE_MNGSEM, mngsem);
1113 ngbe_release_eeprom_semaphore(hw);
1118 /* If time expired clear the bits holding the lock and retry */
1119 if (mngsem & (fwmask | swmask))
1120 ngbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
1123 return NGBE_ERR_SWFW_SYNC;
1127 * ngbe_release_swfw_sync - Release SWFW semaphore
1128 * @hw: pointer to hardware structure
1129 * @mask: Mask to specify which semaphore to release
1131 * Releases the SWFW semaphore through the MNGSEM register for the specified
1132 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1134 void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask)
1139 DEBUGFUNC("ngbe_release_swfw_sync");
1141 ngbe_get_eeprom_semaphore(hw);
1143 mngsem = rd32(hw, NGBE_MNGSEM);
1145 wr32(hw, NGBE_MNGSEM, mngsem);
1147 ngbe_release_eeprom_semaphore(hw);
1151 * ngbe_disable_sec_rx_path - Stops the receive data path
1152 * @hw: pointer to hardware structure
1154 * Stops the receive data path and waits for the HW to internally empty
1155 * the Rx security block
1157 s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw)
1159 #define NGBE_MAX_SECRX_POLL 4000
1164 DEBUGFUNC("ngbe_disable_sec_rx_path");
1167 secrxreg = rd32(hw, NGBE_SECRXCTL);
1168 secrxreg |= NGBE_SECRXCTL_XDSA;
1169 wr32(hw, NGBE_SECRXCTL, secrxreg);
1170 for (i = 0; i < NGBE_MAX_SECRX_POLL; i++) {
1171 secrxreg = rd32(hw, NGBE_SECRXSTAT);
1172 if (!(secrxreg & NGBE_SECRXSTAT_RDY))
1173 /* Use interrupt-safe sleep just in case */
1179 /* For informational purposes only */
1180 if (i >= NGBE_MAX_SECRX_POLL)
1181 DEBUGOUT("Rx unit being enabled before security "
1182 "path fully disabled. Continuing with init.\n");
1188 * ngbe_enable_sec_rx_path - Enables the receive data path
1189 * @hw: pointer to hardware structure
1191 * Enables the receive data path.
1193 s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw)
1197 DEBUGFUNC("ngbe_enable_sec_rx_path");
1199 secrxreg = rd32(hw, NGBE_SECRXCTL);
1200 secrxreg &= ~NGBE_SECRXCTL_XDSA;
1201 wr32(hw, NGBE_SECRXCTL, secrxreg);
1208 * ngbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
1209 * @hw: pointer to hardware struct
1210 * @rar: receive address register index to disassociate
1211 * @vmdq: VMDq pool index to remove from the rar
1213 s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
1216 u32 rar_entries = hw->mac.num_rar_entries;
1218 DEBUGFUNC("ngbe_clear_vmdq");
1220 /* Make sure we are using a valid rar index range */
1221 if (rar >= rar_entries) {
1222 DEBUGOUT("RAR index %d is out of range.\n", rar);
1223 return NGBE_ERR_INVALID_ARGUMENT;
1226 wr32(hw, NGBE_ETHADDRIDX, rar);
1227 mpsar = rd32(hw, NGBE_ETHADDRASS);
1229 if (NGBE_REMOVED(hw->hw_addr))
1235 mpsar &= ~(1 << vmdq);
1236 wr32(hw, NGBE_ETHADDRASS, mpsar);
1238 /* was that the last pool using this rar? */
1239 if (mpsar == 0 && rar != 0)
1240 hw->mac.clear_rar(hw, rar);
1246 * ngbe_set_vmdq - Associate a VMDq pool index with a rx address
1247 * @hw: pointer to hardware struct
1248 * @rar: receive address register index to associate with a VMDq index
1249 * @vmdq: VMDq pool index
1251 s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
1254 u32 rar_entries = hw->mac.num_rar_entries;
1256 DEBUGFUNC("ngbe_set_vmdq");
1258 /* Make sure we are using a valid rar index range */
1259 if (rar >= rar_entries) {
1260 DEBUGOUT("RAR index %d is out of range.\n", rar);
1261 return NGBE_ERR_INVALID_ARGUMENT;
1264 wr32(hw, NGBE_ETHADDRIDX, rar);
1266 mpsar = rd32(hw, NGBE_ETHADDRASS);
1268 wr32(hw, NGBE_ETHADDRASS, mpsar);
1274 * ngbe_init_uta_tables - Initialize the Unicast Table Array
1275 * @hw: pointer to hardware structure
1277 s32 ngbe_init_uta_tables(struct ngbe_hw *hw)
1281 DEBUGFUNC("ngbe_init_uta_tables");
1282 DEBUGOUT(" Clearing UTA\n");
1284 for (i = 0; i < 128; i++)
1285 wr32(hw, NGBE_UCADDRTBL(i), 0);
1291 * ngbe_find_vlvf_slot - find the vlanid or the first empty slot
1292 * @hw: pointer to hardware structure
1293 * @vlan: VLAN id to write to VLAN filter
1294 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1298 * return the VLVF index where this VLAN id should be placed
1301 s32 ngbe_find_vlvf_slot(struct ngbe_hw *hw, u32 vlan, bool vlvf_bypass)
1303 s32 regindex, first_empty_slot;
1306 /* short cut the special case */
1310 /* if vlvf_bypass is set we don't want to use an empty slot, we
1311 * will simply bypass the VLVF if there are no entries present in the
1312 * VLVF that contain our VLAN
1314 first_empty_slot = vlvf_bypass ? NGBE_ERR_NO_SPACE : 0;
1316 /* add VLAN enable bit for comparison */
1317 vlan |= NGBE_PSRVLAN_EA;
1319 /* Search for the vlan id in the VLVF entries. Save off the first empty
1320 * slot found along the way.
1322 * pre-decrement loop covering (NGBE_NUM_POOL - 1) .. 1
1324 for (regindex = NGBE_NUM_POOL; --regindex;) {
1325 wr32(hw, NGBE_PSRVLANIDX, regindex);
1326 bits = rd32(hw, NGBE_PSRVLAN);
1329 if (!first_empty_slot && !bits)
1330 first_empty_slot = regindex;
1333 /* If we are here then we didn't find the VLAN. Return first empty
1334 * slot we found during our search, else error.
1336 if (!first_empty_slot)
1337 DEBUGOUT("No space in VLVF.\n");
1339 return first_empty_slot ? first_empty_slot : NGBE_ERR_NO_SPACE;
1343 * ngbe_set_vfta - Set VLAN filter table
1344 * @hw: pointer to hardware structure
1345 * @vlan: VLAN id to write to VLAN filter
1346 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1347 * @vlan_on: boolean flag to turn on/off VLAN
1348 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1350 * Turn on/off specified VLAN in the VLAN filter table.
1352 s32 ngbe_set_vfta(struct ngbe_hw *hw, u32 vlan, u32 vind,
1353 bool vlan_on, bool vlvf_bypass)
1355 u32 regidx, vfta_delta, vfta;
1358 DEBUGFUNC("ngbe_set_vfta");
1360 if (vlan > 4095 || vind > 63)
1361 return NGBE_ERR_PARAM;
1364 * this is a 2 part operation - first the VFTA, then the
1365 * VLVF and VLVFB if VT Mode is set
1366 * We don't write the VFTA until we know the VLVF part succeeded.
1370 * The VFTA is a bitstring made up of 128 32-bit registers
1371 * that enable the particular VLAN id, much like the MTA:
1372 * bits[11-5]: which register
1373 * bits[4-0]: which bit in the register
1376 vfta_delta = 1 << (vlan % 32);
1377 vfta = rd32(hw, NGBE_VLANTBL(regidx));
1380 * vfta_delta represents the difference between the current value
1381 * of vfta and the value we want in the register. Since the diff
1382 * is an XOR mask we can just update the vfta using an XOR
1384 vfta_delta &= vlan_on ? ~vfta : vfta;
1388 * Call ngbe_set_vlvf to set VLVFB and VLVF
1390 err = ngbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1399 /* Update VFTA now that we are ready for traffic */
1401 wr32(hw, NGBE_VLANTBL(regidx), vfta);
1407 * ngbe_set_vlvf - Set VLAN Pool Filter
1408 * @hw: pointer to hardware structure
1409 * @vlan: VLAN id to write to VLAN filter
1410 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1411 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1412 * @vfta_delta: pointer to the difference between the current value
1413 * of PSRVLANPLM and the desired value
1414 * @vfta: the desired value of the VFTA
1415 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1417 * Turn on/off specified bit in VLVF table.
1419 s32 ngbe_set_vlvf(struct ngbe_hw *hw, u32 vlan, u32 vind,
1420 bool vlan_on, u32 *vfta_delta, u32 vfta,
1427 DEBUGFUNC("ngbe_set_vlvf");
1429 if (vlan > 4095 || vind > 63)
1430 return NGBE_ERR_PARAM;
1432 /* If VT Mode is set
1434 * make sure the vlan is in PSRVLAN
1435 * set the vind bit in the matching PSRVLANPLM
1437 * clear the pool bit and possibly the vind
1439 portctl = rd32(hw, NGBE_PORTCTL);
1440 if (!(portctl & NGBE_PORTCTL_NUMVT_MASK))
1443 vlvf_index = ngbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1447 wr32(hw, NGBE_PSRVLANIDX, vlvf_index);
1448 bits = rd32(hw, NGBE_PSRVLANPLM(vind / 32));
1450 /* set the pool bit */
1451 bits |= 1 << (vind % 32);
1455 /* clear the pool bit */
1456 bits ^= 1 << (vind % 32);
1459 !rd32(hw, NGBE_PSRVLANPLM(vind / 32))) {
1460 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1461 * we run the risk of stray packets leaking into
1462 * the PF via the default pool
1465 wr32(hw, NGBE_PSRVLANPLM(vlan / 32), vfta);
1467 /* disable VLVF and clear remaining bit from pool */
1468 wr32(hw, NGBE_PSRVLAN, 0);
1469 wr32(hw, NGBE_PSRVLANPLM(vind / 32), 0);
1474 /* If there are still bits set in the PSRVLANPLM registers
1475 * for the VLAN ID indicated we need to see if the
1476 * caller is requesting that we clear the PSRVLANPLM entry bit.
1477 * If the caller has requested that we clear the PSRVLANPLM
1478 * entry bit but there are still pools/VFs using this VLAN
1479 * ID entry then ignore the request. We're not worried
1480 * about the case where we're turning the PSRVLANPLM VLAN ID
1481 * entry bit on, only when requested to turn it off as
1482 * there may be multiple pools and/or VFs using the
1483 * VLAN ID entry. In that case we cannot clear the
1484 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1485 * been cleared. This will be indicated by "bits" being
1491 /* record pool change and enable VLAN ID if not already enabled */
1492 wr32(hw, NGBE_PSRVLANPLM(vind / 32), bits);
1493 wr32(hw, NGBE_PSRVLAN, NGBE_PSRVLAN_EA | vlan);
1499 * ngbe_clear_vfta - Clear VLAN filter table
1500 * @hw: pointer to hardware structure
1502 * Clears the VLAN filer table, and the VMDq index associated with the filter
1504 s32 ngbe_clear_vfta(struct ngbe_hw *hw)
1508 DEBUGFUNC("ngbe_clear_vfta");
1510 for (offset = 0; offset < hw->mac.vft_size; offset++)
1511 wr32(hw, NGBE_VLANTBL(offset), 0);
1513 for (offset = 0; offset < NGBE_NUM_POOL; offset++) {
1514 wr32(hw, NGBE_PSRVLANIDX, offset);
1515 wr32(hw, NGBE_PSRVLAN, 0);
1516 wr32(hw, NGBE_PSRVLANPLM(0), 0);
1523 * ngbe_check_mac_link_em - Determine link and speed status
1524 * @hw: pointer to hardware structure
1525 * @speed: pointer to link speed
1526 * @link_up: true when link is up
1527 * @link_up_wait_to_complete: bool used to wait for link up or not
1529 * Reads the links register to determine if link is up and the current speed
1531 s32 ngbe_check_mac_link_em(struct ngbe_hw *hw, u32 *speed,
1532 bool *link_up, bool link_up_wait_to_complete)
1537 DEBUGFUNC("ngbe_check_mac_link_em");
1539 reg = rd32(hw, NGBE_GPIOINTSTAT);
1540 wr32(hw, NGBE_GPIOEOI, reg);
1542 if (link_up_wait_to_complete) {
1543 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1544 status = hw->phy.check_link(hw, speed, link_up);
1550 status = hw->phy.check_link(hw, speed, link_up);
1556 s32 ngbe_get_link_capabilities_em(struct ngbe_hw *hw,
1564 hw->mac.autoneg = *autoneg;
1566 switch (hw->sub_device_id) {
1567 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
1568 *speed = NGBE_LINK_SPEED_1GB_FULL |
1569 NGBE_LINK_SPEED_100M_FULL |
1570 NGBE_LINK_SPEED_10M_FULL;
1579 s32 ngbe_setup_mac_link_em(struct ngbe_hw *hw,
1581 bool autoneg_wait_to_complete)
1587 /* Setup the PHY according to input speed */
1588 status = hw->phy.setup_link(hw, speed, autoneg_wait_to_complete);
1594 * ngbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
1595 * @hw: pointer to hardware structure
1596 * @enable: enable or disable switch for MAC anti-spoofing
1597 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
1600 void ngbe_set_mac_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf)
1604 pfvfspoof = rd32(hw, NGBE_POOLTXASMAC);
1606 pfvfspoof |= (1 << vf);
1608 pfvfspoof &= ~(1 << vf);
1609 wr32(hw, NGBE_POOLTXASMAC, pfvfspoof);
1613 * ngbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
1614 * @hw: pointer to hardware structure
1615 * @enable: enable or disable switch for VLAN anti-spoofing
1616 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
1619 void ngbe_set_vlan_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf)
1623 pfvfspoof = rd32(hw, NGBE_POOLTXASVLAN);
1625 pfvfspoof |= (1 << vf);
1627 pfvfspoof &= ~(1 << vf);
1628 wr32(hw, NGBE_POOLTXASVLAN, pfvfspoof);
1632 * ngbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1633 * @hw: pointer to hardware structure
1635 * Inits the thermal sensor thresholds according to the NVM map
1636 * and save off the threshold and location values into mac.thermal_sensor_data
1638 s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw)
1640 struct ngbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1642 DEBUGFUNC("ngbe_init_thermal_sensor_thresh");
1644 memset(data, 0, sizeof(struct ngbe_thermal_sensor_data));
1646 if (hw->bus.lan_id != 0)
1647 return NGBE_NOT_IMPLEMENTED;
1649 wr32(hw, NGBE_TSINTR,
1650 NGBE_TSINTR_AEN | NGBE_TSINTR_DEN);
1651 wr32(hw, NGBE_TSEN, NGBE_TSEN_ENA);
1654 data->sensor[0].alarm_thresh = 115;
1655 wr32(hw, NGBE_TSATHRE, 0x344);
1656 data->sensor[0].dalarm_thresh = 110;
1657 wr32(hw, NGBE_TSDTHRE, 0x330);
1662 s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw)
1667 DEBUGFUNC("ngbe_mac_check_overtemp");
1669 /* Check that the LASI temp alarm status was triggered */
1670 ts_state = rd32(hw, NGBE_TSALM);
1672 if (ts_state & NGBE_TSALM_HI)
1673 status = NGBE_ERR_UNDERTEMP;
1674 else if (ts_state & NGBE_TSALM_LO)
1675 status = NGBE_ERR_OVERTEMP;
1680 void ngbe_disable_rx(struct ngbe_hw *hw)
1684 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
1685 if (pfdtxgswc & NGBE_PSRCTL_LBENA) {
1686 pfdtxgswc &= ~NGBE_PSRCTL_LBENA;
1687 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
1688 hw->mac.set_lben = true;
1690 hw->mac.set_lben = false;
1693 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0);
1694 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, 0);
1697 void ngbe_enable_rx(struct ngbe_hw *hw)
1701 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, NGBE_MACRXCFG_ENA);
1702 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, NGBE_PBRXCTL_ENA);
1704 if (hw->mac.set_lben) {
1705 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
1706 pfdtxgswc |= NGBE_PSRCTL_LBENA;
1707 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
1708 hw->mac.set_lben = false;
1713 * ngbe_set_mac_type - Sets MAC type
1714 * @hw: pointer to the HW structure
1716 * This function sets the mac type of the adapter based on the
1717 * vendor ID and device ID stored in the hw structure.
1719 s32 ngbe_set_mac_type(struct ngbe_hw *hw)
1723 DEBUGFUNC("ngbe_set_mac_type");
1725 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
1726 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
1727 return NGBE_ERR_DEVICE_NOT_SUPPORTED;
1730 switch (hw->sub_device_id) {
1731 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
1732 case NGBE_SUB_DEV_ID_EM_MVL_RGMII:
1733 hw->phy.media_type = ngbe_media_type_copper;
1734 hw->mac.type = ngbe_mac_em;
1736 case NGBE_SUB_DEV_ID_EM_MVL_SFP:
1737 case NGBE_SUB_DEV_ID_EM_YT8521S_SFP:
1738 hw->phy.media_type = ngbe_media_type_fiber;
1739 hw->mac.type = ngbe_mac_em;
1741 case NGBE_SUB_DEV_ID_EM_VF:
1742 hw->phy.media_type = ngbe_media_type_virtual;
1743 hw->mac.type = ngbe_mac_em_vf;
1746 err = NGBE_ERR_DEVICE_NOT_SUPPORTED;
1747 hw->phy.media_type = ngbe_media_type_unknown;
1748 hw->mac.type = ngbe_mac_unknown;
1749 DEBUGOUT("Unsupported device id: %x", hw->device_id);
1753 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
1754 hw->mac.type, hw->phy.media_type, err);
1759 * ngbe_enable_rx_dma - Enable the Rx DMA unit
1760 * @hw: pointer to hardware structure
1761 * @regval: register value to write to RXCTRL
1763 * Enables the Rx DMA unit
1765 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)
1767 DEBUGFUNC("ngbe_enable_rx_dma");
1770 * Workaround silicon errata when enabling the Rx datapath.
1771 * If traffic is incoming before we enable the Rx unit, it could hang
1772 * the Rx DMA unit. Therefore, make sure the security engine is
1773 * completely disabled prior to enabling the Rx unit.
1776 hw->mac.disable_sec_rx_path(hw);
1778 if (regval & NGBE_PBRXCTL_ENA)
1781 ngbe_disable_rx(hw);
1783 hw->mac.enable_sec_rx_path(hw);
1788 void ngbe_map_device_id(struct ngbe_hw *hw)
1790 u16 oem = hw->sub_system_id & NGBE_OEM_MASK;
1791 u16 internal = hw->sub_system_id & NGBE_INTERNAL_MASK;
1794 /* move subsystem_device_id to device_id */
1795 switch (hw->device_id) {
1796 case NGBE_DEV_ID_EM_WX1860AL_W_VF:
1797 case NGBE_DEV_ID_EM_WX1860A2_VF:
1798 case NGBE_DEV_ID_EM_WX1860A2S_VF:
1799 case NGBE_DEV_ID_EM_WX1860A4_VF:
1800 case NGBE_DEV_ID_EM_WX1860A4S_VF:
1801 case NGBE_DEV_ID_EM_WX1860AL2_VF:
1802 case NGBE_DEV_ID_EM_WX1860AL2S_VF:
1803 case NGBE_DEV_ID_EM_WX1860AL4_VF:
1804 case NGBE_DEV_ID_EM_WX1860AL4S_VF:
1805 case NGBE_DEV_ID_EM_WX1860NCSI_VF:
1806 case NGBE_DEV_ID_EM_WX1860A1_VF:
1807 case NGBE_DEV_ID_EM_WX1860A1L_VF:
1808 hw->device_id = NGBE_DEV_ID_EM_VF;
1809 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_VF;
1812 case NGBE_DEV_ID_EM_WX1860AL_W:
1813 case NGBE_DEV_ID_EM_WX1860A2:
1814 case NGBE_DEV_ID_EM_WX1860A2S:
1815 case NGBE_DEV_ID_EM_WX1860A4:
1816 case NGBE_DEV_ID_EM_WX1860A4S:
1817 case NGBE_DEV_ID_EM_WX1860AL2:
1818 case NGBE_DEV_ID_EM_WX1860AL2S:
1819 case NGBE_DEV_ID_EM_WX1860AL4:
1820 case NGBE_DEV_ID_EM_WX1860AL4S:
1821 case NGBE_DEV_ID_EM_WX1860NCSI:
1822 case NGBE_DEV_ID_EM_WX1860A1:
1823 case NGBE_DEV_ID_EM_WX1860A1L:
1824 hw->device_id = NGBE_DEV_ID_EM;
1825 if (oem == NGBE_LY_M88E1512_SFP ||
1826 internal == NGBE_INTERNAL_SFP)
1827 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_SFP;
1828 else if (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45)
1829 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_RGMII;
1830 else if (oem == NGBE_YT8521S_SFP ||
1831 oem == NGBE_LY_YT8521S_SFP)
1832 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_YT8521S_SFP;
1834 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_SGMII;
1842 * ngbe_init_ops_pf - Inits func ptrs and MAC type
1843 * @hw: pointer to hardware structure
1845 * Initialize the function pointers and assign the MAC type.
1846 * Does not touch the hardware.
1848 s32 ngbe_init_ops_pf(struct ngbe_hw *hw)
1850 struct ngbe_bus_info *bus = &hw->bus;
1851 struct ngbe_mac_info *mac = &hw->mac;
1852 struct ngbe_phy_info *phy = &hw->phy;
1853 struct ngbe_rom_info *rom = &hw->rom;
1854 struct ngbe_mbx_info *mbx = &hw->mbx;
1856 DEBUGFUNC("ngbe_init_ops_pf");
1859 bus->set_lan_id = ngbe_set_lan_id_multi_port;
1862 phy->identify = ngbe_identify_phy;
1863 phy->read_reg = ngbe_read_phy_reg;
1864 phy->write_reg = ngbe_write_phy_reg;
1865 phy->read_reg_unlocked = ngbe_read_phy_reg_mdi;
1866 phy->write_reg_unlocked = ngbe_write_phy_reg_mdi;
1867 phy->reset_hw = ngbe_reset_phy;
1870 mac->init_hw = ngbe_init_hw;
1871 mac->reset_hw = ngbe_reset_hw_em;
1872 mac->start_hw = ngbe_start_hw;
1873 mac->clear_hw_cntrs = ngbe_clear_hw_cntrs;
1874 mac->enable_rx_dma = ngbe_enable_rx_dma;
1875 mac->get_mac_addr = ngbe_get_mac_addr;
1876 mac->stop_hw = ngbe_stop_hw;
1877 mac->acquire_swfw_sync = ngbe_acquire_swfw_sync;
1878 mac->release_swfw_sync = ngbe_release_swfw_sync;
1880 mac->disable_sec_rx_path = ngbe_disable_sec_rx_path;
1881 mac->enable_sec_rx_path = ngbe_enable_sec_rx_path;
1884 mac->led_on = ngbe_led_on;
1885 mac->led_off = ngbe_led_off;
1887 /* RAR, VLAN, Multicast */
1888 mac->set_rar = ngbe_set_rar;
1889 mac->clear_rar = ngbe_clear_rar;
1890 mac->init_rx_addrs = ngbe_init_rx_addrs;
1891 mac->update_mc_addr_list = ngbe_update_mc_addr_list;
1892 mac->set_vmdq = ngbe_set_vmdq;
1893 mac->clear_vmdq = ngbe_clear_vmdq;
1894 mac->set_vfta = ngbe_set_vfta;
1895 mac->set_vlvf = ngbe_set_vlvf;
1896 mac->clear_vfta = ngbe_clear_vfta;
1897 mac->set_mac_anti_spoofing = ngbe_set_mac_anti_spoofing;
1898 mac->set_vlan_anti_spoofing = ngbe_set_vlan_anti_spoofing;
1901 mac->fc_enable = ngbe_fc_enable;
1902 mac->fc_autoneg = ngbe_fc_autoneg;
1903 mac->setup_fc = ngbe_setup_fc_em;
1906 mac->get_link_capabilities = ngbe_get_link_capabilities_em;
1907 mac->check_link = ngbe_check_mac_link_em;
1908 mac->setup_link = ngbe_setup_mac_link_em;
1910 /* Manageability interface */
1911 mac->init_thermal_sensor_thresh = ngbe_init_thermal_sensor_thresh;
1912 mac->check_overtemp = ngbe_mac_check_overtemp;
1914 mbx->init_params = ngbe_init_mbx_params_pf;
1915 mbx->read = ngbe_read_mbx_pf;
1916 mbx->write = ngbe_write_mbx_pf;
1917 mbx->check_for_msg = ngbe_check_for_msg_pf;
1918 mbx->check_for_ack = ngbe_check_for_ack_pf;
1919 mbx->check_for_rst = ngbe_check_for_rst_pf;
1922 rom->init_params = ngbe_init_eeprom_params;
1923 rom->readw_buffer = ngbe_ee_readw_buffer;
1924 rom->read32 = ngbe_ee_read32;
1925 rom->writew_buffer = ngbe_ee_writew_buffer;
1926 rom->validate_checksum = ngbe_validate_eeprom_checksum_em;
1928 mac->mcft_size = NGBE_EM_MC_TBL_SIZE;
1929 mac->vft_size = NGBE_EM_VFT_TBL_SIZE;
1930 mac->num_rar_entries = NGBE_EM_RAR_ENTRIES;
1931 mac->max_rx_queues = NGBE_EM_MAX_RX_QUEUES;
1932 mac->max_tx_queues = NGBE_EM_MAX_TX_QUEUES;
1934 mac->default_speeds = NGBE_LINK_SPEED_10M_FULL |
1935 NGBE_LINK_SPEED_100M_FULL |
1936 NGBE_LINK_SPEED_1GB_FULL;
1942 * ngbe_init_shared_code - Initialize the shared code
1943 * @hw: pointer to hardware structure
1945 * This will assign function pointers and assign the MAC type and PHY code.
1946 * Does not touch the hardware. This function must be called prior to any
1947 * other function in the shared code. The ngbe_hw structure should be
1948 * memset to 0 prior to calling this function. The following fields in
1949 * hw structure should be filled in prior to calling this function:
1950 * hw_addr, back, device_id, vendor_id, subsystem_device_id
1952 s32 ngbe_init_shared_code(struct ngbe_hw *hw)
1956 DEBUGFUNC("ngbe_init_shared_code");
1961 ngbe_set_mac_type(hw);
1963 ngbe_init_ops_dummy(hw);
1964 switch (hw->mac.type) {
1966 ngbe_init_ops_pf(hw);
1969 status = NGBE_ERR_DEVICE_NOT_SUPPORTED;
1972 hw->mac.max_link_up_time = NGBE_LINK_UP_TIME;
1974 hw->bus.set_lan_id(hw);