1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
8 #include "ngbe_eeprom.h"
13 * ngbe_start_hw - Prepare hardware for Tx/Rx
14 * @hw: pointer to hardware structure
16 * Starts the hardware.
18 s32 ngbe_start_hw(struct ngbe_hw *hw)
20 DEBUGFUNC("ngbe_start_hw");
22 /* Clear adapter stopped flag */
23 hw->adapter_stopped = false;
29 * ngbe_init_hw - Generic hardware initialization
30 * @hw: pointer to hardware structure
32 * Initialize the hardware by resetting the hardware, filling the bus info
33 * structure and media type, clears all on chip counters, initializes receive
34 * address registers, multicast table, VLAN filter table, calls routine to set
35 * up link and flow control settings, and leaves transmit and receive units
36 * disabled and uninitialized
38 s32 ngbe_init_hw(struct ngbe_hw *hw)
42 DEBUGFUNC("ngbe_init_hw");
44 /* Reset the hardware */
45 status = hw->mac.reset_hw(hw);
48 status = hw->mac.start_hw(hw);
52 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
58 ngbe_reset_misc_em(struct ngbe_hw *hw)
62 wr32(hw, NGBE_ISBADDRL, hw->isb_dma & 0xFFFFFFFF);
63 wr32(hw, NGBE_ISBADDRH, hw->isb_dma >> 32);
65 /* receive packets that size > 2048 */
66 wr32m(hw, NGBE_MACRXCFG,
67 NGBE_MACRXCFG_JUMBO, NGBE_MACRXCFG_JUMBO);
69 wr32m(hw, NGBE_FRMSZ, NGBE_FRMSZ_MAX_MASK,
70 NGBE_FRMSZ_MAX(NGBE_FRAME_SIZE_DFT));
72 /* clear counters on read */
73 wr32m(hw, NGBE_MACCNTCTL,
74 NGBE_MACCNTCTL_RC, NGBE_MACCNTCTL_RC);
76 wr32m(hw, NGBE_RXFCCFG,
77 NGBE_RXFCCFG_FC, NGBE_RXFCCFG_FC);
78 wr32m(hw, NGBE_TXFCCFG,
79 NGBE_TXFCCFG_FC, NGBE_TXFCCFG_FC);
81 wr32m(hw, NGBE_MACRXFLT,
82 NGBE_MACRXFLT_PROMISC, NGBE_MACRXFLT_PROMISC);
84 wr32m(hw, NGBE_RSTSTAT,
85 NGBE_RSTSTAT_TMRINIT_MASK, NGBE_RSTSTAT_TMRINIT(30));
87 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
88 wr32(hw, NGBE_MNGFLEXSEL, 0);
89 for (i = 0; i < 16; i++) {
90 wr32(hw, NGBE_MNGFLEXDWL(i), 0);
91 wr32(hw, NGBE_MNGFLEXDWH(i), 0);
92 wr32(hw, NGBE_MNGFLEXMSK(i), 0);
94 wr32(hw, NGBE_LANFLEXSEL, 0);
95 for (i = 0; i < 16; i++) {
96 wr32(hw, NGBE_LANFLEXDWL(i), 0);
97 wr32(hw, NGBE_LANFLEXDWH(i), 0);
98 wr32(hw, NGBE_LANFLEXMSK(i), 0);
101 /* set pause frame dst mac addr */
102 wr32(hw, NGBE_RXPBPFCDMACL, 0xC2000001);
103 wr32(hw, NGBE_RXPBPFCDMACH, 0x0180);
105 wr32(hw, NGBE_MDIOMODE, 0xF);
107 wr32m(hw, NGBE_GPIE, NGBE_GPIE_MSIX, NGBE_GPIE_MSIX);
109 if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
110 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
111 /* gpio0 is used to power on/off control*/
112 wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));
113 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);
116 hw->mac.init_thermal_sensor_thresh(hw);
118 /* enable mac transmitter */
119 wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_TE, NGBE_MACTXCFG_TE);
122 wr32m(hw, NGBE_MACTXCFG,
123 NGBE_MACTXCFG_SPEED_MASK, NGBE_MACTXCFG_SPEED_1G);
125 for (i = 0; i < 4; i++)
126 wr32m(hw, NGBE_IVAR(i), 0x80808080, 0);
130 * ngbe_reset_hw_em - Perform hardware reset
131 * @hw: pointer to hardware structure
133 * Resets the hardware by resetting the transmit and receive units, masks
134 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
137 s32 ngbe_reset_hw_em(struct ngbe_hw *hw)
141 DEBUGFUNC("ngbe_reset_hw_em");
143 /* Call adapter stop to disable tx/rx and clear interrupts */
144 status = hw->mac.stop_hw(hw);
148 /* Identify PHY and related function pointers */
149 status = ngbe_init_phy(hw);
154 if (!hw->phy.reset_disable)
155 hw->phy.reset_hw(hw);
157 wr32(hw, NGBE_RST, NGBE_RST_LAN(hw->bus.lan_id));
161 ngbe_reset_misc_em(hw);
165 /* Store the permanent mac address */
166 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
169 * Store MAC address from RAR0, clear receive address registers, and
170 * clear the multicast table.
172 hw->mac.num_rar_entries = NGBE_EM_RAR_ENTRIES;
173 hw->mac.init_rx_addrs(hw);
179 * ngbe_get_mac_addr - Generic get MAC address
180 * @hw: pointer to hardware structure
181 * @mac_addr: Adapter MAC address
183 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
184 * A reset of the adapter must be performed prior to calling this function
185 * in order for the MAC address to have been loaded from the EEPROM into RAR0
187 s32 ngbe_get_mac_addr(struct ngbe_hw *hw, u8 *mac_addr)
193 DEBUGFUNC("ngbe_get_mac_addr");
195 wr32(hw, NGBE_ETHADDRIDX, 0);
196 rar_high = rd32(hw, NGBE_ETHADDRH);
197 rar_low = rd32(hw, NGBE_ETHADDRL);
199 for (i = 0; i < 2; i++)
200 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
202 for (i = 0; i < 4; i++)
203 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
209 * ngbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
210 * @hw: pointer to the HW structure
212 * Determines the LAN function id by reading memory-mapped registers and swaps
213 * the port value if requested, and set MAC instance for devices.
215 void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw)
217 struct ngbe_bus_info *bus = &hw->bus;
220 DEBUGFUNC("ngbe_set_lan_id_multi_port");
222 reg = rd32(hw, NGBE_PORTSTAT);
223 bus->lan_id = NGBE_PORTSTAT_ID(reg);
224 bus->func = bus->lan_id;
228 * ngbe_stop_hw - Generic stop Tx/Rx units
229 * @hw: pointer to hardware structure
231 * Sets the adapter_stopped flag within ngbe_hw struct. Clears interrupts,
232 * disables transmit and receive units. The adapter_stopped flag is used by
233 * the shared code and drivers to determine if the adapter is in a stopped
234 * state and should not touch the hardware.
236 s32 ngbe_stop_hw(struct ngbe_hw *hw)
241 DEBUGFUNC("ngbe_stop_hw");
244 * Set the adapter_stopped flag so other driver functions stop touching
247 hw->adapter_stopped = true;
249 /* Disable the receive unit */
252 /* Clear interrupt mask to stop interrupts from being generated */
253 wr32(hw, NGBE_IENMISC, 0);
254 wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK);
256 /* Clear any pending interrupts, flush previous writes */
257 wr32(hw, NGBE_ICRMISC, NGBE_ICRMISC_MASK);
258 wr32(hw, NGBE_ICR(0), NGBE_ICR_MASK);
260 /* Disable the transmit unit. Each queue must be disabled. */
261 for (i = 0; i < hw->mac.max_tx_queues; i++)
262 wr32(hw, NGBE_TXCFG(i), NGBE_TXCFG_FLUSH);
264 /* Disable the receive unit by stopping each queue */
265 for (i = 0; i < hw->mac.max_rx_queues; i++) {
266 reg_val = rd32(hw, NGBE_RXCFG(i));
267 reg_val &= ~NGBE_RXCFG_ENA;
268 wr32(hw, NGBE_RXCFG(i), reg_val);
271 /* flush all queues disables */
279 * ngbe_validate_mac_addr - Validate MAC address
280 * @mac_addr: pointer to MAC address.
282 * Tests a MAC address to ensure it is a valid Individual Address.
284 s32 ngbe_validate_mac_addr(u8 *mac_addr)
288 DEBUGFUNC("ngbe_validate_mac_addr");
290 /* Make sure it is not a multicast address */
291 if (NGBE_IS_MULTICAST((struct rte_ether_addr *)mac_addr)) {
292 status = NGBE_ERR_INVALID_MAC_ADDR;
293 /* Not a broadcast address */
294 } else if (NGBE_IS_BROADCAST((struct rte_ether_addr *)mac_addr)) {
295 status = NGBE_ERR_INVALID_MAC_ADDR;
296 /* Reject the zero address */
297 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
298 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
299 status = NGBE_ERR_INVALID_MAC_ADDR;
305 * ngbe_set_rar - Set Rx address register
306 * @hw: pointer to hardware structure
307 * @index: Receive address register to write
308 * @addr: Address to put into receive address register
309 * @vmdq: VMDq "set" or "pool" index
310 * @enable_addr: set flag that address is active
312 * Puts an ethernet address into a receive address register.
314 s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
317 u32 rar_low, rar_high;
318 u32 rar_entries = hw->mac.num_rar_entries;
320 DEBUGFUNC("ngbe_set_rar");
322 /* Make sure we are using a valid rar index range */
323 if (index >= rar_entries) {
324 DEBUGOUT("RAR index %d is out of range.\n", index);
325 return NGBE_ERR_INVALID_ARGUMENT;
328 /* setup VMDq pool selection before this RAR gets enabled */
329 hw->mac.set_vmdq(hw, index, vmdq);
332 * HW expects these in little endian so we reverse the byte
333 * order from network order (big endian) to little endian
335 rar_low = NGBE_ETHADDRL_AD0(addr[5]) |
336 NGBE_ETHADDRL_AD1(addr[4]) |
337 NGBE_ETHADDRL_AD2(addr[3]) |
338 NGBE_ETHADDRL_AD3(addr[2]);
340 * Some parts put the VMDq setting in the extra RAH bits,
341 * so save everything except the lower 16 bits that hold part
342 * of the address and the address valid bit.
344 rar_high = rd32(hw, NGBE_ETHADDRH);
345 rar_high &= ~NGBE_ETHADDRH_AD_MASK;
346 rar_high |= (NGBE_ETHADDRH_AD4(addr[1]) |
347 NGBE_ETHADDRH_AD5(addr[0]));
349 rar_high &= ~NGBE_ETHADDRH_VLD;
350 if (enable_addr != 0)
351 rar_high |= NGBE_ETHADDRH_VLD;
353 wr32(hw, NGBE_ETHADDRIDX, index);
354 wr32(hw, NGBE_ETHADDRL, rar_low);
355 wr32(hw, NGBE_ETHADDRH, rar_high);
361 * ngbe_clear_rar - Remove Rx address register
362 * @hw: pointer to hardware structure
363 * @index: Receive address register to write
365 * Clears an ethernet address from a receive address register.
367 s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index)
370 u32 rar_entries = hw->mac.num_rar_entries;
372 DEBUGFUNC("ngbe_clear_rar");
374 /* Make sure we are using a valid rar index range */
375 if (index >= rar_entries) {
376 DEBUGOUT("RAR index %d is out of range.\n", index);
377 return NGBE_ERR_INVALID_ARGUMENT;
381 * Some parts put the VMDq setting in the extra RAH bits,
382 * so save everything except the lower 16 bits that hold part
383 * of the address and the address valid bit.
385 wr32(hw, NGBE_ETHADDRIDX, index);
386 rar_high = rd32(hw, NGBE_ETHADDRH);
387 rar_high &= ~(NGBE_ETHADDRH_AD_MASK | NGBE_ETHADDRH_VLD);
389 wr32(hw, NGBE_ETHADDRL, 0);
390 wr32(hw, NGBE_ETHADDRH, rar_high);
392 /* clear VMDq pool/queue selection for this RAR */
393 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
399 * ngbe_init_rx_addrs - Initializes receive address filters.
400 * @hw: pointer to hardware structure
402 * Places the MAC address in receive address register 0 and clears the rest
403 * of the receive address registers. Clears the multicast table. Assumes
404 * the receiver is in reset when the routine is called.
406 s32 ngbe_init_rx_addrs(struct ngbe_hw *hw)
410 u32 rar_entries = hw->mac.num_rar_entries;
412 DEBUGFUNC("ngbe_init_rx_addrs");
415 * If the current mac address is valid, assume it is a software override
416 * to the permanent address.
417 * Otherwise, use the permanent address from the eeprom.
419 if (ngbe_validate_mac_addr(hw->mac.addr) ==
420 NGBE_ERR_INVALID_MAC_ADDR) {
421 /* Get the MAC address from the RAR0 for later reference */
422 hw->mac.get_mac_addr(hw, hw->mac.addr);
424 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
425 hw->mac.addr[0], hw->mac.addr[1],
427 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
428 hw->mac.addr[4], hw->mac.addr[5]);
430 /* Setup the receive address. */
431 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
432 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
433 hw->mac.addr[0], hw->mac.addr[1],
435 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
436 hw->mac.addr[4], hw->mac.addr[5]);
438 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
441 /* clear VMDq pool/queue selection for RAR 0 */
442 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
444 /* Zero out the other receive addresses. */
445 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
446 for (i = 1; i < rar_entries; i++) {
447 wr32(hw, NGBE_ETHADDRIDX, i);
448 wr32(hw, NGBE_ETHADDRL, 0);
449 wr32(hw, NGBE_ETHADDRH, 0);
453 hw->addr_ctrl.mta_in_use = 0;
454 psrctl = rd32(hw, NGBE_PSRCTL);
455 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
456 psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
457 wr32(hw, NGBE_PSRCTL, psrctl);
459 DEBUGOUT(" Clearing MTA\n");
460 for (i = 0; i < hw->mac.mcft_size; i++)
461 wr32(hw, NGBE_MCADDRTBL(i), 0);
463 ngbe_init_uta_tables(hw);
469 * ngbe_acquire_swfw_sync - Acquire SWFW semaphore
470 * @hw: pointer to hardware structure
471 * @mask: Mask to specify which semaphore to acquire
473 * Acquires the SWFW semaphore through the MNGSEM register for the specified
474 * function (CSR, PHY0, PHY1, EEPROM, Flash)
476 s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask)
479 u32 swmask = NGBE_MNGSEM_SW(mask);
480 u32 fwmask = NGBE_MNGSEM_FW(mask);
484 DEBUGFUNC("ngbe_acquire_swfw_sync");
486 for (i = 0; i < timeout; i++) {
488 * SW NVM semaphore bit is used for access to all
489 * SW_FW_SYNC bits (not just NVM)
491 if (ngbe_get_eeprom_semaphore(hw))
492 return NGBE_ERR_SWFW_SYNC;
494 mngsem = rd32(hw, NGBE_MNGSEM);
495 if (mngsem & (fwmask | swmask)) {
496 /* Resource is currently in use by FW or SW */
497 ngbe_release_eeprom_semaphore(hw);
501 wr32(hw, NGBE_MNGSEM, mngsem);
502 ngbe_release_eeprom_semaphore(hw);
507 /* If time expired clear the bits holding the lock and retry */
508 if (mngsem & (fwmask | swmask))
509 ngbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
512 return NGBE_ERR_SWFW_SYNC;
516 * ngbe_release_swfw_sync - Release SWFW semaphore
517 * @hw: pointer to hardware structure
518 * @mask: Mask to specify which semaphore to release
520 * Releases the SWFW semaphore through the MNGSEM register for the specified
521 * function (CSR, PHY0, PHY1, EEPROM, Flash)
523 void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask)
528 DEBUGFUNC("ngbe_release_swfw_sync");
530 ngbe_get_eeprom_semaphore(hw);
532 mngsem = rd32(hw, NGBE_MNGSEM);
534 wr32(hw, NGBE_MNGSEM, mngsem);
536 ngbe_release_eeprom_semaphore(hw);
540 * ngbe_disable_sec_rx_path - Stops the receive data path
541 * @hw: pointer to hardware structure
543 * Stops the receive data path and waits for the HW to internally empty
544 * the Rx security block
546 s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw)
548 #define NGBE_MAX_SECRX_POLL 4000
553 DEBUGFUNC("ngbe_disable_sec_rx_path");
556 secrxreg = rd32(hw, NGBE_SECRXCTL);
557 secrxreg |= NGBE_SECRXCTL_XDSA;
558 wr32(hw, NGBE_SECRXCTL, secrxreg);
559 for (i = 0; i < NGBE_MAX_SECRX_POLL; i++) {
560 secrxreg = rd32(hw, NGBE_SECRXSTAT);
561 if (!(secrxreg & NGBE_SECRXSTAT_RDY))
562 /* Use interrupt-safe sleep just in case */
568 /* For informational purposes only */
569 if (i >= NGBE_MAX_SECRX_POLL)
570 DEBUGOUT("Rx unit being enabled before security "
571 "path fully disabled. Continuing with init.\n");
577 * ngbe_enable_sec_rx_path - Enables the receive data path
578 * @hw: pointer to hardware structure
580 * Enables the receive data path.
582 s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw)
586 DEBUGFUNC("ngbe_enable_sec_rx_path");
588 secrxreg = rd32(hw, NGBE_SECRXCTL);
589 secrxreg &= ~NGBE_SECRXCTL_XDSA;
590 wr32(hw, NGBE_SECRXCTL, secrxreg);
597 * ngbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
598 * @hw: pointer to hardware struct
599 * @rar: receive address register index to disassociate
600 * @vmdq: VMDq pool index to remove from the rar
602 s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
605 u32 rar_entries = hw->mac.num_rar_entries;
607 DEBUGFUNC("ngbe_clear_vmdq");
609 /* Make sure we are using a valid rar index range */
610 if (rar >= rar_entries) {
611 DEBUGOUT("RAR index %d is out of range.\n", rar);
612 return NGBE_ERR_INVALID_ARGUMENT;
615 wr32(hw, NGBE_ETHADDRIDX, rar);
616 mpsar = rd32(hw, NGBE_ETHADDRASS);
618 if (NGBE_REMOVED(hw->hw_addr))
624 mpsar &= ~(1 << vmdq);
625 wr32(hw, NGBE_ETHADDRASS, mpsar);
627 /* was that the last pool using this rar? */
628 if (mpsar == 0 && rar != 0)
629 hw->mac.clear_rar(hw, rar);
635 * ngbe_set_vmdq - Associate a VMDq pool index with a rx address
636 * @hw: pointer to hardware struct
637 * @rar: receive address register index to associate with a VMDq index
638 * @vmdq: VMDq pool index
640 s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
643 u32 rar_entries = hw->mac.num_rar_entries;
645 DEBUGFUNC("ngbe_set_vmdq");
647 /* Make sure we are using a valid rar index range */
648 if (rar >= rar_entries) {
649 DEBUGOUT("RAR index %d is out of range.\n", rar);
650 return NGBE_ERR_INVALID_ARGUMENT;
653 wr32(hw, NGBE_ETHADDRIDX, rar);
655 mpsar = rd32(hw, NGBE_ETHADDRASS);
657 wr32(hw, NGBE_ETHADDRASS, mpsar);
663 * ngbe_init_uta_tables - Initialize the Unicast Table Array
664 * @hw: pointer to hardware structure
666 s32 ngbe_init_uta_tables(struct ngbe_hw *hw)
670 DEBUGFUNC("ngbe_init_uta_tables");
671 DEBUGOUT(" Clearing UTA\n");
673 for (i = 0; i < 128; i++)
674 wr32(hw, NGBE_UCADDRTBL(i), 0);
680 * ngbe_check_mac_link_em - Determine link and speed status
681 * @hw: pointer to hardware structure
682 * @speed: pointer to link speed
683 * @link_up: true when link is up
684 * @link_up_wait_to_complete: bool used to wait for link up or not
686 * Reads the links register to determine if link is up and the current speed
688 s32 ngbe_check_mac_link_em(struct ngbe_hw *hw, u32 *speed,
689 bool *link_up, bool link_up_wait_to_complete)
694 DEBUGFUNC("ngbe_check_mac_link_em");
696 reg = rd32(hw, NGBE_GPIOINTSTAT);
697 wr32(hw, NGBE_GPIOEOI, reg);
699 if (link_up_wait_to_complete) {
700 for (i = 0; i < hw->mac.max_link_up_time; i++) {
701 status = hw->phy.check_link(hw, speed, link_up);
707 status = hw->phy.check_link(hw, speed, link_up);
713 s32 ngbe_get_link_capabilities_em(struct ngbe_hw *hw,
721 hw->mac.autoneg = *autoneg;
723 switch (hw->sub_device_id) {
724 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
725 *speed = NGBE_LINK_SPEED_1GB_FULL |
726 NGBE_LINK_SPEED_100M_FULL |
727 NGBE_LINK_SPEED_10M_FULL;
736 s32 ngbe_setup_mac_link_em(struct ngbe_hw *hw,
738 bool autoneg_wait_to_complete)
744 /* Setup the PHY according to input speed */
745 status = hw->phy.setup_link(hw, speed, autoneg_wait_to_complete);
751 * ngbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
752 * @hw: pointer to hardware structure
754 * Inits the thermal sensor thresholds according to the NVM map
755 * and save off the threshold and location values into mac.thermal_sensor_data
757 s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw)
759 struct ngbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
761 DEBUGFUNC("ngbe_init_thermal_sensor_thresh");
763 memset(data, 0, sizeof(struct ngbe_thermal_sensor_data));
765 if (hw->bus.lan_id != 0)
766 return NGBE_NOT_IMPLEMENTED;
768 wr32(hw, NGBE_TSINTR,
769 NGBE_TSINTR_AEN | NGBE_TSINTR_DEN);
770 wr32(hw, NGBE_TSEN, NGBE_TSEN_ENA);
773 data->sensor[0].alarm_thresh = 115;
774 wr32(hw, NGBE_TSATHRE, 0x344);
775 data->sensor[0].dalarm_thresh = 110;
776 wr32(hw, NGBE_TSDTHRE, 0x330);
781 s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw)
786 DEBUGFUNC("ngbe_mac_check_overtemp");
788 /* Check that the LASI temp alarm status was triggered */
789 ts_state = rd32(hw, NGBE_TSALM);
791 if (ts_state & NGBE_TSALM_HI)
792 status = NGBE_ERR_UNDERTEMP;
793 else if (ts_state & NGBE_TSALM_LO)
794 status = NGBE_ERR_OVERTEMP;
799 void ngbe_disable_rx(struct ngbe_hw *hw)
803 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
804 if (pfdtxgswc & NGBE_PSRCTL_LBENA) {
805 pfdtxgswc &= ~NGBE_PSRCTL_LBENA;
806 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
807 hw->mac.set_lben = true;
809 hw->mac.set_lben = false;
812 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0);
813 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, 0);
816 void ngbe_enable_rx(struct ngbe_hw *hw)
820 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, NGBE_MACRXCFG_ENA);
821 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, NGBE_PBRXCTL_ENA);
823 if (hw->mac.set_lben) {
824 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
825 pfdtxgswc |= NGBE_PSRCTL_LBENA;
826 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
827 hw->mac.set_lben = false;
832 * ngbe_set_mac_type - Sets MAC type
833 * @hw: pointer to the HW structure
835 * This function sets the mac type of the adapter based on the
836 * vendor ID and device ID stored in the hw structure.
838 s32 ngbe_set_mac_type(struct ngbe_hw *hw)
842 DEBUGFUNC("ngbe_set_mac_type");
844 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
845 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
846 return NGBE_ERR_DEVICE_NOT_SUPPORTED;
849 switch (hw->sub_device_id) {
850 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
851 case NGBE_SUB_DEV_ID_EM_MVL_RGMII:
852 hw->phy.media_type = ngbe_media_type_copper;
853 hw->mac.type = ngbe_mac_em;
855 case NGBE_SUB_DEV_ID_EM_MVL_SFP:
856 case NGBE_SUB_DEV_ID_EM_YT8521S_SFP:
857 hw->phy.media_type = ngbe_media_type_fiber;
858 hw->mac.type = ngbe_mac_em;
860 case NGBE_SUB_DEV_ID_EM_VF:
861 hw->phy.media_type = ngbe_media_type_virtual;
862 hw->mac.type = ngbe_mac_em_vf;
865 err = NGBE_ERR_DEVICE_NOT_SUPPORTED;
866 hw->phy.media_type = ngbe_media_type_unknown;
867 hw->mac.type = ngbe_mac_unknown;
868 DEBUGOUT("Unsupported device id: %x", hw->device_id);
872 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
873 hw->mac.type, hw->phy.media_type, err);
878 * ngbe_enable_rx_dma - Enable the Rx DMA unit
879 * @hw: pointer to hardware structure
880 * @regval: register value to write to RXCTRL
882 * Enables the Rx DMA unit
884 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)
886 DEBUGFUNC("ngbe_enable_rx_dma");
889 * Workaround silicon errata when enabling the Rx datapath.
890 * If traffic is incoming before we enable the Rx unit, it could hang
891 * the Rx DMA unit. Therefore, make sure the security engine is
892 * completely disabled prior to enabling the Rx unit.
895 hw->mac.disable_sec_rx_path(hw);
897 if (regval & NGBE_PBRXCTL_ENA)
902 hw->mac.enable_sec_rx_path(hw);
907 void ngbe_map_device_id(struct ngbe_hw *hw)
909 u16 oem = hw->sub_system_id & NGBE_OEM_MASK;
910 u16 internal = hw->sub_system_id & NGBE_INTERNAL_MASK;
913 /* move subsystem_device_id to device_id */
914 switch (hw->device_id) {
915 case NGBE_DEV_ID_EM_WX1860AL_W_VF:
916 case NGBE_DEV_ID_EM_WX1860A2_VF:
917 case NGBE_DEV_ID_EM_WX1860A2S_VF:
918 case NGBE_DEV_ID_EM_WX1860A4_VF:
919 case NGBE_DEV_ID_EM_WX1860A4S_VF:
920 case NGBE_DEV_ID_EM_WX1860AL2_VF:
921 case NGBE_DEV_ID_EM_WX1860AL2S_VF:
922 case NGBE_DEV_ID_EM_WX1860AL4_VF:
923 case NGBE_DEV_ID_EM_WX1860AL4S_VF:
924 case NGBE_DEV_ID_EM_WX1860NCSI_VF:
925 case NGBE_DEV_ID_EM_WX1860A1_VF:
926 case NGBE_DEV_ID_EM_WX1860A1L_VF:
927 hw->device_id = NGBE_DEV_ID_EM_VF;
928 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_VF;
931 case NGBE_DEV_ID_EM_WX1860AL_W:
932 case NGBE_DEV_ID_EM_WX1860A2:
933 case NGBE_DEV_ID_EM_WX1860A2S:
934 case NGBE_DEV_ID_EM_WX1860A4:
935 case NGBE_DEV_ID_EM_WX1860A4S:
936 case NGBE_DEV_ID_EM_WX1860AL2:
937 case NGBE_DEV_ID_EM_WX1860AL2S:
938 case NGBE_DEV_ID_EM_WX1860AL4:
939 case NGBE_DEV_ID_EM_WX1860AL4S:
940 case NGBE_DEV_ID_EM_WX1860NCSI:
941 case NGBE_DEV_ID_EM_WX1860A1:
942 case NGBE_DEV_ID_EM_WX1860A1L:
943 hw->device_id = NGBE_DEV_ID_EM;
944 if (oem == NGBE_LY_M88E1512_SFP ||
945 internal == NGBE_INTERNAL_SFP)
946 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_SFP;
947 else if (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45)
948 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_RGMII;
949 else if (oem == NGBE_YT8521S_SFP ||
950 oem == NGBE_LY_YT8521S_SFP)
951 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_YT8521S_SFP;
953 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_SGMII;
961 * ngbe_init_ops_pf - Inits func ptrs and MAC type
962 * @hw: pointer to hardware structure
964 * Initialize the function pointers and assign the MAC type.
965 * Does not touch the hardware.
967 s32 ngbe_init_ops_pf(struct ngbe_hw *hw)
969 struct ngbe_bus_info *bus = &hw->bus;
970 struct ngbe_mac_info *mac = &hw->mac;
971 struct ngbe_phy_info *phy = &hw->phy;
972 struct ngbe_rom_info *rom = &hw->rom;
974 DEBUGFUNC("ngbe_init_ops_pf");
977 bus->set_lan_id = ngbe_set_lan_id_multi_port;
980 phy->identify = ngbe_identify_phy;
981 phy->read_reg = ngbe_read_phy_reg;
982 phy->write_reg = ngbe_write_phy_reg;
983 phy->read_reg_unlocked = ngbe_read_phy_reg_mdi;
984 phy->write_reg_unlocked = ngbe_write_phy_reg_mdi;
985 phy->reset_hw = ngbe_reset_phy;
988 mac->init_hw = ngbe_init_hw;
989 mac->reset_hw = ngbe_reset_hw_em;
990 mac->start_hw = ngbe_start_hw;
991 mac->enable_rx_dma = ngbe_enable_rx_dma;
992 mac->get_mac_addr = ngbe_get_mac_addr;
993 mac->stop_hw = ngbe_stop_hw;
994 mac->acquire_swfw_sync = ngbe_acquire_swfw_sync;
995 mac->release_swfw_sync = ngbe_release_swfw_sync;
997 mac->disable_sec_rx_path = ngbe_disable_sec_rx_path;
998 mac->enable_sec_rx_path = ngbe_enable_sec_rx_path;
1000 mac->set_rar = ngbe_set_rar;
1001 mac->clear_rar = ngbe_clear_rar;
1002 mac->init_rx_addrs = ngbe_init_rx_addrs;
1003 mac->set_vmdq = ngbe_set_vmdq;
1004 mac->clear_vmdq = ngbe_clear_vmdq;
1007 mac->get_link_capabilities = ngbe_get_link_capabilities_em;
1008 mac->check_link = ngbe_check_mac_link_em;
1009 mac->setup_link = ngbe_setup_mac_link_em;
1011 /* Manageability interface */
1012 mac->init_thermal_sensor_thresh = ngbe_init_thermal_sensor_thresh;
1013 mac->check_overtemp = ngbe_mac_check_overtemp;
1016 rom->init_params = ngbe_init_eeprom_params;
1017 rom->validate_checksum = ngbe_validate_eeprom_checksum_em;
1019 mac->mcft_size = NGBE_EM_MC_TBL_SIZE;
1020 mac->num_rar_entries = NGBE_EM_RAR_ENTRIES;
1021 mac->max_rx_queues = NGBE_EM_MAX_RX_QUEUES;
1022 mac->max_tx_queues = NGBE_EM_MAX_TX_QUEUES;
1024 mac->default_speeds = NGBE_LINK_SPEED_10M_FULL |
1025 NGBE_LINK_SPEED_100M_FULL |
1026 NGBE_LINK_SPEED_1GB_FULL;
1032 * ngbe_init_shared_code - Initialize the shared code
1033 * @hw: pointer to hardware structure
1035 * This will assign function pointers and assign the MAC type and PHY code.
1036 * Does not touch the hardware. This function must be called prior to any
1037 * other function in the shared code. The ngbe_hw structure should be
1038 * memset to 0 prior to calling this function. The following fields in
1039 * hw structure should be filled in prior to calling this function:
1040 * hw_addr, back, device_id, vendor_id, subsystem_device_id
1042 s32 ngbe_init_shared_code(struct ngbe_hw *hw)
1046 DEBUGFUNC("ngbe_init_shared_code");
1051 ngbe_set_mac_type(hw);
1053 ngbe_init_ops_dummy(hw);
1054 switch (hw->mac.type) {
1056 ngbe_init_ops_pf(hw);
1059 status = NGBE_ERR_DEVICE_NOT_SUPPORTED;
1062 hw->mac.max_link_up_time = NGBE_LINK_UP_TIME;
1064 hw->bus.set_lan_id(hw);