1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
8 #include "ngbe_eeprom.h"
13 * ngbe_start_hw - Prepare hardware for Tx/Rx
14 * @hw: pointer to hardware structure
16 * Starts the hardware.
18 s32 ngbe_start_hw(struct ngbe_hw *hw)
20 DEBUGFUNC("ngbe_start_hw");
22 /* Clear the VLAN filter table */
23 hw->mac.clear_vfta(hw);
25 /* Clear statistics registers */
26 hw->mac.clear_hw_cntrs(hw);
28 /* Clear adapter stopped flag */
29 hw->adapter_stopped = false;
35 * ngbe_init_hw - Generic hardware initialization
36 * @hw: pointer to hardware structure
38 * Initialize the hardware by resetting the hardware, filling the bus info
39 * structure and media type, clears all on chip counters, initializes receive
40 * address registers, multicast table, VLAN filter table, calls routine to set
41 * up link and flow control settings, and leaves transmit and receive units
42 * disabled and uninitialized
44 s32 ngbe_init_hw(struct ngbe_hw *hw)
48 DEBUGFUNC("ngbe_init_hw");
50 /* Reset the hardware */
51 status = hw->mac.reset_hw(hw);
54 status = hw->mac.start_hw(hw);
58 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
64 ngbe_reset_misc_em(struct ngbe_hw *hw)
68 wr32(hw, NGBE_ISBADDRL, hw->isb_dma & 0xFFFFFFFF);
69 wr32(hw, NGBE_ISBADDRH, hw->isb_dma >> 32);
71 /* receive packets that size > 2048 */
72 wr32m(hw, NGBE_MACRXCFG,
73 NGBE_MACRXCFG_JUMBO, NGBE_MACRXCFG_JUMBO);
75 wr32m(hw, NGBE_FRMSZ, NGBE_FRMSZ_MAX_MASK,
76 NGBE_FRMSZ_MAX(NGBE_FRAME_SIZE_DFT));
78 /* clear counters on read */
79 wr32m(hw, NGBE_MACCNTCTL,
80 NGBE_MACCNTCTL_RC, NGBE_MACCNTCTL_RC);
82 wr32m(hw, NGBE_RXFCCFG,
83 NGBE_RXFCCFG_FC, NGBE_RXFCCFG_FC);
84 wr32m(hw, NGBE_TXFCCFG,
85 NGBE_TXFCCFG_FC, NGBE_TXFCCFG_FC);
87 wr32m(hw, NGBE_MACRXFLT,
88 NGBE_MACRXFLT_PROMISC, NGBE_MACRXFLT_PROMISC);
90 wr32m(hw, NGBE_RSTSTAT,
91 NGBE_RSTSTAT_TMRINIT_MASK, NGBE_RSTSTAT_TMRINIT(30));
93 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
94 wr32(hw, NGBE_MNGFLEXSEL, 0);
95 for (i = 0; i < 16; i++) {
96 wr32(hw, NGBE_MNGFLEXDWL(i), 0);
97 wr32(hw, NGBE_MNGFLEXDWH(i), 0);
98 wr32(hw, NGBE_MNGFLEXMSK(i), 0);
100 wr32(hw, NGBE_LANFLEXSEL, 0);
101 for (i = 0; i < 16; i++) {
102 wr32(hw, NGBE_LANFLEXDWL(i), 0);
103 wr32(hw, NGBE_LANFLEXDWH(i), 0);
104 wr32(hw, NGBE_LANFLEXMSK(i), 0);
107 /* set pause frame dst mac addr */
108 wr32(hw, NGBE_RXPBPFCDMACL, 0xC2000001);
109 wr32(hw, NGBE_RXPBPFCDMACH, 0x0180);
111 wr32(hw, NGBE_MDIOMODE, 0xF);
113 wr32m(hw, NGBE_GPIE, NGBE_GPIE_MSIX, NGBE_GPIE_MSIX);
115 if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
116 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
117 /* gpio0 is used to power on/off control*/
118 wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));
119 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);
122 hw->mac.init_thermal_sensor_thresh(hw);
124 /* enable mac transmitter */
125 wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_TE, NGBE_MACTXCFG_TE);
128 wr32m(hw, NGBE_MACTXCFG,
129 NGBE_MACTXCFG_SPEED_MASK, NGBE_MACTXCFG_SPEED_1G);
131 for (i = 0; i < 4; i++)
132 wr32m(hw, NGBE_IVAR(i), 0x80808080, 0);
136 * ngbe_reset_hw_em - Perform hardware reset
137 * @hw: pointer to hardware structure
139 * Resets the hardware by resetting the transmit and receive units, masks
140 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
143 s32 ngbe_reset_hw_em(struct ngbe_hw *hw)
147 DEBUGFUNC("ngbe_reset_hw_em");
149 /* Call adapter stop to disable tx/rx and clear interrupts */
150 status = hw->mac.stop_hw(hw);
154 /* Identify PHY and related function pointers */
155 status = ngbe_init_phy(hw);
160 if (!hw->phy.reset_disable)
161 hw->phy.reset_hw(hw);
163 wr32(hw, NGBE_RST, NGBE_RST_LAN(hw->bus.lan_id));
167 ngbe_reset_misc_em(hw);
168 hw->mac.clear_hw_cntrs(hw);
172 /* Store the permanent mac address */
173 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
176 * Store MAC address from RAR0, clear receive address registers, and
177 * clear the multicast table.
179 hw->mac.num_rar_entries = NGBE_EM_RAR_ENTRIES;
180 hw->mac.init_rx_addrs(hw);
186 * ngbe_clear_hw_cntrs - Generic clear hardware counters
187 * @hw: pointer to hardware structure
189 * Clears all hardware statistics counters by reading them from the hardware
190 * Statistics counters are clear on read.
192 s32 ngbe_clear_hw_cntrs(struct ngbe_hw *hw)
196 DEBUGFUNC("ngbe_clear_hw_cntrs");
199 /* don't write clear queue stats */
200 for (i = 0; i < NGBE_MAX_QP; i++) {
201 hw->qp_last[i].rx_qp_packets = 0;
202 hw->qp_last[i].tx_qp_packets = 0;
203 hw->qp_last[i].rx_qp_bytes = 0;
204 hw->qp_last[i].tx_qp_bytes = 0;
205 hw->qp_last[i].rx_qp_mc_packets = 0;
206 hw->qp_last[i].tx_qp_mc_packets = 0;
207 hw->qp_last[i].rx_qp_bc_packets = 0;
208 hw->qp_last[i].tx_qp_bc_packets = 0;
212 rd32(hw, NGBE_PBRXLNKXON);
213 rd32(hw, NGBE_PBRXLNKXOFF);
214 rd32(hw, NGBE_PBTXLNKXON);
215 rd32(hw, NGBE_PBTXLNKXOFF);
218 rd32(hw, NGBE_DMARXPKT);
219 rd32(hw, NGBE_DMATXPKT);
221 rd64(hw, NGBE_DMARXOCTL);
222 rd64(hw, NGBE_DMATXOCTL);
225 rd64(hw, NGBE_MACRXERRCRCL);
226 rd64(hw, NGBE_MACRXMPKTL);
227 rd64(hw, NGBE_MACTXMPKTL);
229 rd64(hw, NGBE_MACRXPKTL);
230 rd64(hw, NGBE_MACTXPKTL);
231 rd64(hw, NGBE_MACRXGBOCTL);
233 rd64(hw, NGBE_MACRXOCTL);
234 rd32(hw, NGBE_MACTXOCTL);
236 rd64(hw, NGBE_MACRX1TO64L);
237 rd64(hw, NGBE_MACRX65TO127L);
238 rd64(hw, NGBE_MACRX128TO255L);
239 rd64(hw, NGBE_MACRX256TO511L);
240 rd64(hw, NGBE_MACRX512TO1023L);
241 rd64(hw, NGBE_MACRX1024TOMAXL);
242 rd64(hw, NGBE_MACTX1TO64L);
243 rd64(hw, NGBE_MACTX65TO127L);
244 rd64(hw, NGBE_MACTX128TO255L);
245 rd64(hw, NGBE_MACTX256TO511L);
246 rd64(hw, NGBE_MACTX512TO1023L);
247 rd64(hw, NGBE_MACTX1024TOMAXL);
249 rd64(hw, NGBE_MACRXERRLENL);
250 rd32(hw, NGBE_MACRXOVERSIZE);
251 rd32(hw, NGBE_MACRXJABBER);
254 rd32(hw, NGBE_LSECTX_UTPKT);
255 rd32(hw, NGBE_LSECTX_ENCPKT);
256 rd32(hw, NGBE_LSECTX_PROTPKT);
257 rd32(hw, NGBE_LSECTX_ENCOCT);
258 rd32(hw, NGBE_LSECTX_PROTOCT);
259 rd32(hw, NGBE_LSECRX_UTPKT);
260 rd32(hw, NGBE_LSECRX_BTPKT);
261 rd32(hw, NGBE_LSECRX_NOSCIPKT);
262 rd32(hw, NGBE_LSECRX_UNSCIPKT);
263 rd32(hw, NGBE_LSECRX_DECOCT);
264 rd32(hw, NGBE_LSECRX_VLDOCT);
265 rd32(hw, NGBE_LSECRX_UNCHKPKT);
266 rd32(hw, NGBE_LSECRX_DLYPKT);
267 rd32(hw, NGBE_LSECRX_LATEPKT);
268 for (i = 0; i < 2; i++) {
269 rd32(hw, NGBE_LSECRX_OKPKT(i));
270 rd32(hw, NGBE_LSECRX_INVPKT(i));
271 rd32(hw, NGBE_LSECRX_BADPKT(i));
273 for (i = 0; i < 4; i++) {
274 rd32(hw, NGBE_LSECRX_INVSAPKT(i));
275 rd32(hw, NGBE_LSECRX_BADSAPKT(i));
282 * ngbe_get_mac_addr - Generic get MAC address
283 * @hw: pointer to hardware structure
284 * @mac_addr: Adapter MAC address
286 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
287 * A reset of the adapter must be performed prior to calling this function
288 * in order for the MAC address to have been loaded from the EEPROM into RAR0
290 s32 ngbe_get_mac_addr(struct ngbe_hw *hw, u8 *mac_addr)
296 DEBUGFUNC("ngbe_get_mac_addr");
298 wr32(hw, NGBE_ETHADDRIDX, 0);
299 rar_high = rd32(hw, NGBE_ETHADDRH);
300 rar_low = rd32(hw, NGBE_ETHADDRL);
302 for (i = 0; i < 2; i++)
303 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
305 for (i = 0; i < 4; i++)
306 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
312 * ngbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
313 * @hw: pointer to the HW structure
315 * Determines the LAN function id by reading memory-mapped registers and swaps
316 * the port value if requested, and set MAC instance for devices.
318 void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw)
320 struct ngbe_bus_info *bus = &hw->bus;
323 DEBUGFUNC("ngbe_set_lan_id_multi_port");
325 reg = rd32(hw, NGBE_PORTSTAT);
326 bus->lan_id = NGBE_PORTSTAT_ID(reg);
327 bus->func = bus->lan_id;
331 * ngbe_stop_hw - Generic stop Tx/Rx units
332 * @hw: pointer to hardware structure
334 * Sets the adapter_stopped flag within ngbe_hw struct. Clears interrupts,
335 * disables transmit and receive units. The adapter_stopped flag is used by
336 * the shared code and drivers to determine if the adapter is in a stopped
337 * state and should not touch the hardware.
339 s32 ngbe_stop_hw(struct ngbe_hw *hw)
344 DEBUGFUNC("ngbe_stop_hw");
347 * Set the adapter_stopped flag so other driver functions stop touching
350 hw->adapter_stopped = true;
352 /* Disable the receive unit */
355 /* Clear interrupt mask to stop interrupts from being generated */
356 wr32(hw, NGBE_IENMISC, 0);
357 wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK);
359 /* Clear any pending interrupts, flush previous writes */
360 wr32(hw, NGBE_ICRMISC, NGBE_ICRMISC_MASK);
361 wr32(hw, NGBE_ICR(0), NGBE_ICR_MASK);
363 /* Disable the transmit unit. Each queue must be disabled. */
364 for (i = 0; i < hw->mac.max_tx_queues; i++)
365 wr32(hw, NGBE_TXCFG(i), NGBE_TXCFG_FLUSH);
367 /* Disable the receive unit by stopping each queue */
368 for (i = 0; i < hw->mac.max_rx_queues; i++) {
369 reg_val = rd32(hw, NGBE_RXCFG(i));
370 reg_val &= ~NGBE_RXCFG_ENA;
371 wr32(hw, NGBE_RXCFG(i), reg_val);
374 /* flush all queues disables */
382 * ngbe_validate_mac_addr - Validate MAC address
383 * @mac_addr: pointer to MAC address.
385 * Tests a MAC address to ensure it is a valid Individual Address.
387 s32 ngbe_validate_mac_addr(u8 *mac_addr)
391 DEBUGFUNC("ngbe_validate_mac_addr");
393 /* Make sure it is not a multicast address */
394 if (NGBE_IS_MULTICAST((struct rte_ether_addr *)mac_addr)) {
395 status = NGBE_ERR_INVALID_MAC_ADDR;
396 /* Not a broadcast address */
397 } else if (NGBE_IS_BROADCAST((struct rte_ether_addr *)mac_addr)) {
398 status = NGBE_ERR_INVALID_MAC_ADDR;
399 /* Reject the zero address */
400 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
401 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
402 status = NGBE_ERR_INVALID_MAC_ADDR;
408 * ngbe_set_rar - Set Rx address register
409 * @hw: pointer to hardware structure
410 * @index: Receive address register to write
411 * @addr: Address to put into receive address register
412 * @vmdq: VMDq "set" or "pool" index
413 * @enable_addr: set flag that address is active
415 * Puts an ethernet address into a receive address register.
417 s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
420 u32 rar_low, rar_high;
421 u32 rar_entries = hw->mac.num_rar_entries;
423 DEBUGFUNC("ngbe_set_rar");
425 /* Make sure we are using a valid rar index range */
426 if (index >= rar_entries) {
427 DEBUGOUT("RAR index %d is out of range.\n", index);
428 return NGBE_ERR_INVALID_ARGUMENT;
431 /* setup VMDq pool selection before this RAR gets enabled */
432 hw->mac.set_vmdq(hw, index, vmdq);
435 * HW expects these in little endian so we reverse the byte
436 * order from network order (big endian) to little endian
438 rar_low = NGBE_ETHADDRL_AD0(addr[5]) |
439 NGBE_ETHADDRL_AD1(addr[4]) |
440 NGBE_ETHADDRL_AD2(addr[3]) |
441 NGBE_ETHADDRL_AD3(addr[2]);
443 * Some parts put the VMDq setting in the extra RAH bits,
444 * so save everything except the lower 16 bits that hold part
445 * of the address and the address valid bit.
447 rar_high = rd32(hw, NGBE_ETHADDRH);
448 rar_high &= ~NGBE_ETHADDRH_AD_MASK;
449 rar_high |= (NGBE_ETHADDRH_AD4(addr[1]) |
450 NGBE_ETHADDRH_AD5(addr[0]));
452 rar_high &= ~NGBE_ETHADDRH_VLD;
453 if (enable_addr != 0)
454 rar_high |= NGBE_ETHADDRH_VLD;
456 wr32(hw, NGBE_ETHADDRIDX, index);
457 wr32(hw, NGBE_ETHADDRL, rar_low);
458 wr32(hw, NGBE_ETHADDRH, rar_high);
464 * ngbe_clear_rar - Remove Rx address register
465 * @hw: pointer to hardware structure
466 * @index: Receive address register to write
468 * Clears an ethernet address from a receive address register.
470 s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index)
473 u32 rar_entries = hw->mac.num_rar_entries;
475 DEBUGFUNC("ngbe_clear_rar");
477 /* Make sure we are using a valid rar index range */
478 if (index >= rar_entries) {
479 DEBUGOUT("RAR index %d is out of range.\n", index);
480 return NGBE_ERR_INVALID_ARGUMENT;
484 * Some parts put the VMDq setting in the extra RAH bits,
485 * so save everything except the lower 16 bits that hold part
486 * of the address and the address valid bit.
488 wr32(hw, NGBE_ETHADDRIDX, index);
489 rar_high = rd32(hw, NGBE_ETHADDRH);
490 rar_high &= ~(NGBE_ETHADDRH_AD_MASK | NGBE_ETHADDRH_VLD);
492 wr32(hw, NGBE_ETHADDRL, 0);
493 wr32(hw, NGBE_ETHADDRH, rar_high);
495 /* clear VMDq pool/queue selection for this RAR */
496 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
502 * ngbe_init_rx_addrs - Initializes receive address filters.
503 * @hw: pointer to hardware structure
505 * Places the MAC address in receive address register 0 and clears the rest
506 * of the receive address registers. Clears the multicast table. Assumes
507 * the receiver is in reset when the routine is called.
509 s32 ngbe_init_rx_addrs(struct ngbe_hw *hw)
513 u32 rar_entries = hw->mac.num_rar_entries;
515 DEBUGFUNC("ngbe_init_rx_addrs");
518 * If the current mac address is valid, assume it is a software override
519 * to the permanent address.
520 * Otherwise, use the permanent address from the eeprom.
522 if (ngbe_validate_mac_addr(hw->mac.addr) ==
523 NGBE_ERR_INVALID_MAC_ADDR) {
524 /* Get the MAC address from the RAR0 for later reference */
525 hw->mac.get_mac_addr(hw, hw->mac.addr);
527 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
528 hw->mac.addr[0], hw->mac.addr[1],
530 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
531 hw->mac.addr[4], hw->mac.addr[5]);
533 /* Setup the receive address. */
534 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
535 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
536 hw->mac.addr[0], hw->mac.addr[1],
538 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
539 hw->mac.addr[4], hw->mac.addr[5]);
541 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
544 /* clear VMDq pool/queue selection for RAR 0 */
545 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
547 /* Zero out the other receive addresses. */
548 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
549 for (i = 1; i < rar_entries; i++) {
550 wr32(hw, NGBE_ETHADDRIDX, i);
551 wr32(hw, NGBE_ETHADDRL, 0);
552 wr32(hw, NGBE_ETHADDRH, 0);
556 hw->addr_ctrl.mta_in_use = 0;
557 psrctl = rd32(hw, NGBE_PSRCTL);
558 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
559 psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
560 wr32(hw, NGBE_PSRCTL, psrctl);
562 DEBUGOUT(" Clearing MTA\n");
563 for (i = 0; i < hw->mac.mcft_size; i++)
564 wr32(hw, NGBE_MCADDRTBL(i), 0);
566 ngbe_init_uta_tables(hw);
572 * ngbe_acquire_swfw_sync - Acquire SWFW semaphore
573 * @hw: pointer to hardware structure
574 * @mask: Mask to specify which semaphore to acquire
576 * Acquires the SWFW semaphore through the MNGSEM register for the specified
577 * function (CSR, PHY0, PHY1, EEPROM, Flash)
579 s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask)
582 u32 swmask = NGBE_MNGSEM_SW(mask);
583 u32 fwmask = NGBE_MNGSEM_FW(mask);
587 DEBUGFUNC("ngbe_acquire_swfw_sync");
589 for (i = 0; i < timeout; i++) {
591 * SW NVM semaphore bit is used for access to all
592 * SW_FW_SYNC bits (not just NVM)
594 if (ngbe_get_eeprom_semaphore(hw))
595 return NGBE_ERR_SWFW_SYNC;
597 mngsem = rd32(hw, NGBE_MNGSEM);
598 if (mngsem & (fwmask | swmask)) {
599 /* Resource is currently in use by FW or SW */
600 ngbe_release_eeprom_semaphore(hw);
604 wr32(hw, NGBE_MNGSEM, mngsem);
605 ngbe_release_eeprom_semaphore(hw);
610 /* If time expired clear the bits holding the lock and retry */
611 if (mngsem & (fwmask | swmask))
612 ngbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
615 return NGBE_ERR_SWFW_SYNC;
619 * ngbe_release_swfw_sync - Release SWFW semaphore
620 * @hw: pointer to hardware structure
621 * @mask: Mask to specify which semaphore to release
623 * Releases the SWFW semaphore through the MNGSEM register for the specified
624 * function (CSR, PHY0, PHY1, EEPROM, Flash)
626 void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask)
631 DEBUGFUNC("ngbe_release_swfw_sync");
633 ngbe_get_eeprom_semaphore(hw);
635 mngsem = rd32(hw, NGBE_MNGSEM);
637 wr32(hw, NGBE_MNGSEM, mngsem);
639 ngbe_release_eeprom_semaphore(hw);
643 * ngbe_disable_sec_rx_path - Stops the receive data path
644 * @hw: pointer to hardware structure
646 * Stops the receive data path and waits for the HW to internally empty
647 * the Rx security block
649 s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw)
651 #define NGBE_MAX_SECRX_POLL 4000
656 DEBUGFUNC("ngbe_disable_sec_rx_path");
659 secrxreg = rd32(hw, NGBE_SECRXCTL);
660 secrxreg |= NGBE_SECRXCTL_XDSA;
661 wr32(hw, NGBE_SECRXCTL, secrxreg);
662 for (i = 0; i < NGBE_MAX_SECRX_POLL; i++) {
663 secrxreg = rd32(hw, NGBE_SECRXSTAT);
664 if (!(secrxreg & NGBE_SECRXSTAT_RDY))
665 /* Use interrupt-safe sleep just in case */
671 /* For informational purposes only */
672 if (i >= NGBE_MAX_SECRX_POLL)
673 DEBUGOUT("Rx unit being enabled before security "
674 "path fully disabled. Continuing with init.\n");
680 * ngbe_enable_sec_rx_path - Enables the receive data path
681 * @hw: pointer to hardware structure
683 * Enables the receive data path.
685 s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw)
689 DEBUGFUNC("ngbe_enable_sec_rx_path");
691 secrxreg = rd32(hw, NGBE_SECRXCTL);
692 secrxreg &= ~NGBE_SECRXCTL_XDSA;
693 wr32(hw, NGBE_SECRXCTL, secrxreg);
700 * ngbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
701 * @hw: pointer to hardware struct
702 * @rar: receive address register index to disassociate
703 * @vmdq: VMDq pool index to remove from the rar
705 s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
708 u32 rar_entries = hw->mac.num_rar_entries;
710 DEBUGFUNC("ngbe_clear_vmdq");
712 /* Make sure we are using a valid rar index range */
713 if (rar >= rar_entries) {
714 DEBUGOUT("RAR index %d is out of range.\n", rar);
715 return NGBE_ERR_INVALID_ARGUMENT;
718 wr32(hw, NGBE_ETHADDRIDX, rar);
719 mpsar = rd32(hw, NGBE_ETHADDRASS);
721 if (NGBE_REMOVED(hw->hw_addr))
727 mpsar &= ~(1 << vmdq);
728 wr32(hw, NGBE_ETHADDRASS, mpsar);
730 /* was that the last pool using this rar? */
731 if (mpsar == 0 && rar != 0)
732 hw->mac.clear_rar(hw, rar);
738 * ngbe_set_vmdq - Associate a VMDq pool index with a rx address
739 * @hw: pointer to hardware struct
740 * @rar: receive address register index to associate with a VMDq index
741 * @vmdq: VMDq pool index
743 s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
746 u32 rar_entries = hw->mac.num_rar_entries;
748 DEBUGFUNC("ngbe_set_vmdq");
750 /* Make sure we are using a valid rar index range */
751 if (rar >= rar_entries) {
752 DEBUGOUT("RAR index %d is out of range.\n", rar);
753 return NGBE_ERR_INVALID_ARGUMENT;
756 wr32(hw, NGBE_ETHADDRIDX, rar);
758 mpsar = rd32(hw, NGBE_ETHADDRASS);
760 wr32(hw, NGBE_ETHADDRASS, mpsar);
766 * ngbe_init_uta_tables - Initialize the Unicast Table Array
767 * @hw: pointer to hardware structure
769 s32 ngbe_init_uta_tables(struct ngbe_hw *hw)
773 DEBUGFUNC("ngbe_init_uta_tables");
774 DEBUGOUT(" Clearing UTA\n");
776 for (i = 0; i < 128; i++)
777 wr32(hw, NGBE_UCADDRTBL(i), 0);
783 * ngbe_clear_vfta - Clear VLAN filter table
784 * @hw: pointer to hardware structure
786 * Clears the VLAN filer table, and the VMDq index associated with the filter
788 s32 ngbe_clear_vfta(struct ngbe_hw *hw)
792 DEBUGFUNC("ngbe_clear_vfta");
794 for (offset = 0; offset < hw->mac.vft_size; offset++)
795 wr32(hw, NGBE_VLANTBL(offset), 0);
797 for (offset = 0; offset < NGBE_NUM_POOL; offset++) {
798 wr32(hw, NGBE_PSRVLANIDX, offset);
799 wr32(hw, NGBE_PSRVLAN, 0);
800 wr32(hw, NGBE_PSRVLANPLM(0), 0);
807 * ngbe_check_mac_link_em - Determine link and speed status
808 * @hw: pointer to hardware structure
809 * @speed: pointer to link speed
810 * @link_up: true when link is up
811 * @link_up_wait_to_complete: bool used to wait for link up or not
813 * Reads the links register to determine if link is up and the current speed
815 s32 ngbe_check_mac_link_em(struct ngbe_hw *hw, u32 *speed,
816 bool *link_up, bool link_up_wait_to_complete)
821 DEBUGFUNC("ngbe_check_mac_link_em");
823 reg = rd32(hw, NGBE_GPIOINTSTAT);
824 wr32(hw, NGBE_GPIOEOI, reg);
826 if (link_up_wait_to_complete) {
827 for (i = 0; i < hw->mac.max_link_up_time; i++) {
828 status = hw->phy.check_link(hw, speed, link_up);
834 status = hw->phy.check_link(hw, speed, link_up);
840 s32 ngbe_get_link_capabilities_em(struct ngbe_hw *hw,
848 hw->mac.autoneg = *autoneg;
850 switch (hw->sub_device_id) {
851 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
852 *speed = NGBE_LINK_SPEED_1GB_FULL |
853 NGBE_LINK_SPEED_100M_FULL |
854 NGBE_LINK_SPEED_10M_FULL;
863 s32 ngbe_setup_mac_link_em(struct ngbe_hw *hw,
865 bool autoneg_wait_to_complete)
871 /* Setup the PHY according to input speed */
872 status = hw->phy.setup_link(hw, speed, autoneg_wait_to_complete);
878 * ngbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
879 * @hw: pointer to hardware structure
881 * Inits the thermal sensor thresholds according to the NVM map
882 * and save off the threshold and location values into mac.thermal_sensor_data
884 s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw)
886 struct ngbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
888 DEBUGFUNC("ngbe_init_thermal_sensor_thresh");
890 memset(data, 0, sizeof(struct ngbe_thermal_sensor_data));
892 if (hw->bus.lan_id != 0)
893 return NGBE_NOT_IMPLEMENTED;
895 wr32(hw, NGBE_TSINTR,
896 NGBE_TSINTR_AEN | NGBE_TSINTR_DEN);
897 wr32(hw, NGBE_TSEN, NGBE_TSEN_ENA);
900 data->sensor[0].alarm_thresh = 115;
901 wr32(hw, NGBE_TSATHRE, 0x344);
902 data->sensor[0].dalarm_thresh = 110;
903 wr32(hw, NGBE_TSDTHRE, 0x330);
908 s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw)
913 DEBUGFUNC("ngbe_mac_check_overtemp");
915 /* Check that the LASI temp alarm status was triggered */
916 ts_state = rd32(hw, NGBE_TSALM);
918 if (ts_state & NGBE_TSALM_HI)
919 status = NGBE_ERR_UNDERTEMP;
920 else if (ts_state & NGBE_TSALM_LO)
921 status = NGBE_ERR_OVERTEMP;
926 void ngbe_disable_rx(struct ngbe_hw *hw)
930 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
931 if (pfdtxgswc & NGBE_PSRCTL_LBENA) {
932 pfdtxgswc &= ~NGBE_PSRCTL_LBENA;
933 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
934 hw->mac.set_lben = true;
936 hw->mac.set_lben = false;
939 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0);
940 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, 0);
943 void ngbe_enable_rx(struct ngbe_hw *hw)
947 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, NGBE_MACRXCFG_ENA);
948 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, NGBE_PBRXCTL_ENA);
950 if (hw->mac.set_lben) {
951 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
952 pfdtxgswc |= NGBE_PSRCTL_LBENA;
953 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
954 hw->mac.set_lben = false;
959 * ngbe_set_mac_type - Sets MAC type
960 * @hw: pointer to the HW structure
962 * This function sets the mac type of the adapter based on the
963 * vendor ID and device ID stored in the hw structure.
965 s32 ngbe_set_mac_type(struct ngbe_hw *hw)
969 DEBUGFUNC("ngbe_set_mac_type");
971 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
972 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
973 return NGBE_ERR_DEVICE_NOT_SUPPORTED;
976 switch (hw->sub_device_id) {
977 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
978 case NGBE_SUB_DEV_ID_EM_MVL_RGMII:
979 hw->phy.media_type = ngbe_media_type_copper;
980 hw->mac.type = ngbe_mac_em;
982 case NGBE_SUB_DEV_ID_EM_MVL_SFP:
983 case NGBE_SUB_DEV_ID_EM_YT8521S_SFP:
984 hw->phy.media_type = ngbe_media_type_fiber;
985 hw->mac.type = ngbe_mac_em;
987 case NGBE_SUB_DEV_ID_EM_VF:
988 hw->phy.media_type = ngbe_media_type_virtual;
989 hw->mac.type = ngbe_mac_em_vf;
992 err = NGBE_ERR_DEVICE_NOT_SUPPORTED;
993 hw->phy.media_type = ngbe_media_type_unknown;
994 hw->mac.type = ngbe_mac_unknown;
995 DEBUGOUT("Unsupported device id: %x", hw->device_id);
999 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
1000 hw->mac.type, hw->phy.media_type, err);
1005 * ngbe_enable_rx_dma - Enable the Rx DMA unit
1006 * @hw: pointer to hardware structure
1007 * @regval: register value to write to RXCTRL
1009 * Enables the Rx DMA unit
1011 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)
1013 DEBUGFUNC("ngbe_enable_rx_dma");
1016 * Workaround silicon errata when enabling the Rx datapath.
1017 * If traffic is incoming before we enable the Rx unit, it could hang
1018 * the Rx DMA unit. Therefore, make sure the security engine is
1019 * completely disabled prior to enabling the Rx unit.
1022 hw->mac.disable_sec_rx_path(hw);
1024 if (regval & NGBE_PBRXCTL_ENA)
1027 ngbe_disable_rx(hw);
1029 hw->mac.enable_sec_rx_path(hw);
1034 void ngbe_map_device_id(struct ngbe_hw *hw)
1036 u16 oem = hw->sub_system_id & NGBE_OEM_MASK;
1037 u16 internal = hw->sub_system_id & NGBE_INTERNAL_MASK;
1040 /* move subsystem_device_id to device_id */
1041 switch (hw->device_id) {
1042 case NGBE_DEV_ID_EM_WX1860AL_W_VF:
1043 case NGBE_DEV_ID_EM_WX1860A2_VF:
1044 case NGBE_DEV_ID_EM_WX1860A2S_VF:
1045 case NGBE_DEV_ID_EM_WX1860A4_VF:
1046 case NGBE_DEV_ID_EM_WX1860A4S_VF:
1047 case NGBE_DEV_ID_EM_WX1860AL2_VF:
1048 case NGBE_DEV_ID_EM_WX1860AL2S_VF:
1049 case NGBE_DEV_ID_EM_WX1860AL4_VF:
1050 case NGBE_DEV_ID_EM_WX1860AL4S_VF:
1051 case NGBE_DEV_ID_EM_WX1860NCSI_VF:
1052 case NGBE_DEV_ID_EM_WX1860A1_VF:
1053 case NGBE_DEV_ID_EM_WX1860A1L_VF:
1054 hw->device_id = NGBE_DEV_ID_EM_VF;
1055 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_VF;
1058 case NGBE_DEV_ID_EM_WX1860AL_W:
1059 case NGBE_DEV_ID_EM_WX1860A2:
1060 case NGBE_DEV_ID_EM_WX1860A2S:
1061 case NGBE_DEV_ID_EM_WX1860A4:
1062 case NGBE_DEV_ID_EM_WX1860A4S:
1063 case NGBE_DEV_ID_EM_WX1860AL2:
1064 case NGBE_DEV_ID_EM_WX1860AL2S:
1065 case NGBE_DEV_ID_EM_WX1860AL4:
1066 case NGBE_DEV_ID_EM_WX1860AL4S:
1067 case NGBE_DEV_ID_EM_WX1860NCSI:
1068 case NGBE_DEV_ID_EM_WX1860A1:
1069 case NGBE_DEV_ID_EM_WX1860A1L:
1070 hw->device_id = NGBE_DEV_ID_EM;
1071 if (oem == NGBE_LY_M88E1512_SFP ||
1072 internal == NGBE_INTERNAL_SFP)
1073 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_SFP;
1074 else if (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45)
1075 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_RGMII;
1076 else if (oem == NGBE_YT8521S_SFP ||
1077 oem == NGBE_LY_YT8521S_SFP)
1078 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_YT8521S_SFP;
1080 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_SGMII;
1088 * ngbe_init_ops_pf - Inits func ptrs and MAC type
1089 * @hw: pointer to hardware structure
1091 * Initialize the function pointers and assign the MAC type.
1092 * Does not touch the hardware.
1094 s32 ngbe_init_ops_pf(struct ngbe_hw *hw)
1096 struct ngbe_bus_info *bus = &hw->bus;
1097 struct ngbe_mac_info *mac = &hw->mac;
1098 struct ngbe_phy_info *phy = &hw->phy;
1099 struct ngbe_rom_info *rom = &hw->rom;
1101 DEBUGFUNC("ngbe_init_ops_pf");
1104 bus->set_lan_id = ngbe_set_lan_id_multi_port;
1107 phy->identify = ngbe_identify_phy;
1108 phy->read_reg = ngbe_read_phy_reg;
1109 phy->write_reg = ngbe_write_phy_reg;
1110 phy->read_reg_unlocked = ngbe_read_phy_reg_mdi;
1111 phy->write_reg_unlocked = ngbe_write_phy_reg_mdi;
1112 phy->reset_hw = ngbe_reset_phy;
1115 mac->init_hw = ngbe_init_hw;
1116 mac->reset_hw = ngbe_reset_hw_em;
1117 mac->start_hw = ngbe_start_hw;
1118 mac->clear_hw_cntrs = ngbe_clear_hw_cntrs;
1119 mac->enable_rx_dma = ngbe_enable_rx_dma;
1120 mac->get_mac_addr = ngbe_get_mac_addr;
1121 mac->stop_hw = ngbe_stop_hw;
1122 mac->acquire_swfw_sync = ngbe_acquire_swfw_sync;
1123 mac->release_swfw_sync = ngbe_release_swfw_sync;
1125 mac->disable_sec_rx_path = ngbe_disable_sec_rx_path;
1126 mac->enable_sec_rx_path = ngbe_enable_sec_rx_path;
1128 mac->set_rar = ngbe_set_rar;
1129 mac->clear_rar = ngbe_clear_rar;
1130 mac->init_rx_addrs = ngbe_init_rx_addrs;
1131 mac->set_vmdq = ngbe_set_vmdq;
1132 mac->clear_vmdq = ngbe_clear_vmdq;
1133 mac->clear_vfta = ngbe_clear_vfta;
1136 mac->get_link_capabilities = ngbe_get_link_capabilities_em;
1137 mac->check_link = ngbe_check_mac_link_em;
1138 mac->setup_link = ngbe_setup_mac_link_em;
1140 /* Manageability interface */
1141 mac->init_thermal_sensor_thresh = ngbe_init_thermal_sensor_thresh;
1142 mac->check_overtemp = ngbe_mac_check_overtemp;
1145 rom->init_params = ngbe_init_eeprom_params;
1146 rom->validate_checksum = ngbe_validate_eeprom_checksum_em;
1148 mac->mcft_size = NGBE_EM_MC_TBL_SIZE;
1149 mac->vft_size = NGBE_EM_VFT_TBL_SIZE;
1150 mac->num_rar_entries = NGBE_EM_RAR_ENTRIES;
1151 mac->max_rx_queues = NGBE_EM_MAX_RX_QUEUES;
1152 mac->max_tx_queues = NGBE_EM_MAX_TX_QUEUES;
1154 mac->default_speeds = NGBE_LINK_SPEED_10M_FULL |
1155 NGBE_LINK_SPEED_100M_FULL |
1156 NGBE_LINK_SPEED_1GB_FULL;
1162 * ngbe_init_shared_code - Initialize the shared code
1163 * @hw: pointer to hardware structure
1165 * This will assign function pointers and assign the MAC type and PHY code.
1166 * Does not touch the hardware. This function must be called prior to any
1167 * other function in the shared code. The ngbe_hw structure should be
1168 * memset to 0 prior to calling this function. The following fields in
1169 * hw structure should be filled in prior to calling this function:
1170 * hw_addr, back, device_id, vendor_id, subsystem_device_id
1172 s32 ngbe_init_shared_code(struct ngbe_hw *hw)
1176 DEBUGFUNC("ngbe_init_shared_code");
1181 ngbe_set_mac_type(hw);
1183 ngbe_init_ops_dummy(hw);
1184 switch (hw->mac.type) {
1186 ngbe_init_ops_pf(hw);
1189 status = NGBE_ERR_DEVICE_NOT_SUPPORTED;
1192 hw->mac.max_link_up_time = NGBE_LINK_UP_TIME;
1194 hw->bus.set_lan_id(hw);