1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
9 #include "ngbe_eeprom.h"
14 * ngbe_start_hw - Prepare hardware for Tx/Rx
15 * @hw: pointer to hardware structure
17 * Starts the hardware.
19 s32 ngbe_start_hw(struct ngbe_hw *hw)
23 DEBUGFUNC("ngbe_start_hw");
25 /* Clear the VLAN filter table */
26 hw->mac.clear_vfta(hw);
28 /* Clear statistics registers */
29 hw->mac.clear_hw_cntrs(hw);
31 /* Setup flow control */
32 err = hw->mac.setup_fc(hw);
33 if (err != 0 && err != NGBE_NOT_IMPLEMENTED) {
34 DEBUGOUT("Flow control setup failed, returning %d\n", err);
38 /* Clear adapter stopped flag */
39 hw->adapter_stopped = false;
45 * ngbe_init_hw - Generic hardware initialization
46 * @hw: pointer to hardware structure
48 * Initialize the hardware by resetting the hardware, filling the bus info
49 * structure and media type, clears all on chip counters, initializes receive
50 * address registers, multicast table, VLAN filter table, calls routine to set
51 * up link and flow control settings, and leaves transmit and receive units
52 * disabled and uninitialized
54 s32 ngbe_init_hw(struct ngbe_hw *hw)
58 DEBUGFUNC("ngbe_init_hw");
60 ngbe_save_eeprom_version(hw);
62 /* Reset the hardware */
63 status = hw->mac.reset_hw(hw);
66 status = hw->mac.start_hw(hw);
70 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
76 ngbe_reset_misc_em(struct ngbe_hw *hw)
80 wr32(hw, NGBE_ISBADDRL, hw->isb_dma & 0xFFFFFFFF);
81 wr32(hw, NGBE_ISBADDRH, hw->isb_dma >> 32);
83 /* receive packets that size > 2048 */
84 wr32m(hw, NGBE_MACRXCFG,
85 NGBE_MACRXCFG_JUMBO, NGBE_MACRXCFG_JUMBO);
87 wr32m(hw, NGBE_FRMSZ, NGBE_FRMSZ_MAX_MASK,
88 NGBE_FRMSZ_MAX(NGBE_FRAME_SIZE_DFT));
90 /* clear counters on read */
91 wr32m(hw, NGBE_MACCNTCTL,
92 NGBE_MACCNTCTL_RC, NGBE_MACCNTCTL_RC);
94 wr32m(hw, NGBE_RXFCCFG,
95 NGBE_RXFCCFG_FC, NGBE_RXFCCFG_FC);
96 wr32m(hw, NGBE_TXFCCFG,
97 NGBE_TXFCCFG_FC, NGBE_TXFCCFG_FC);
99 wr32m(hw, NGBE_MACRXFLT,
100 NGBE_MACRXFLT_PROMISC, NGBE_MACRXFLT_PROMISC);
102 wr32m(hw, NGBE_RSTSTAT,
103 NGBE_RSTSTAT_TMRINIT_MASK, NGBE_RSTSTAT_TMRINIT(30));
105 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
106 wr32(hw, NGBE_MNGFLEXSEL, 0);
107 for (i = 0; i < 16; i++) {
108 wr32(hw, NGBE_MNGFLEXDWL(i), 0);
109 wr32(hw, NGBE_MNGFLEXDWH(i), 0);
110 wr32(hw, NGBE_MNGFLEXMSK(i), 0);
112 wr32(hw, NGBE_LANFLEXSEL, 0);
113 for (i = 0; i < 16; i++) {
114 wr32(hw, NGBE_LANFLEXDWL(i), 0);
115 wr32(hw, NGBE_LANFLEXDWH(i), 0);
116 wr32(hw, NGBE_LANFLEXMSK(i), 0);
119 /* set pause frame dst mac addr */
120 wr32(hw, NGBE_RXPBPFCDMACL, 0xC2000001);
121 wr32(hw, NGBE_RXPBPFCDMACH, 0x0180);
123 wr32(hw, NGBE_MDIOMODE, 0xF);
125 wr32m(hw, NGBE_GPIE, NGBE_GPIE_MSIX, NGBE_GPIE_MSIX);
128 /* gpio0 is used to power on/off control*/
129 wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));
130 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);
133 hw->mac.init_thermal_sensor_thresh(hw);
135 /* enable mac transmitter */
136 wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_TE, NGBE_MACTXCFG_TE);
139 wr32m(hw, NGBE_MACTXCFG,
140 NGBE_MACTXCFG_SPEED_MASK, NGBE_MACTXCFG_SPEED_1G);
142 for (i = 0; i < 4; i++)
143 wr32m(hw, NGBE_IVAR(i), 0x80808080, 0);
147 * ngbe_reset_hw_em - Perform hardware reset
148 * @hw: pointer to hardware structure
150 * Resets the hardware by resetting the transmit and receive units, masks
151 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
154 s32 ngbe_reset_hw_em(struct ngbe_hw *hw)
158 DEBUGFUNC("ngbe_reset_hw_em");
160 /* Call adapter stop to disable tx/rx and clear interrupts */
161 status = hw->mac.stop_hw(hw);
165 /* Identify PHY and related function pointers */
166 status = ngbe_init_phy(hw);
171 if (!hw->phy.reset_disable)
172 hw->phy.reset_hw(hw);
174 wr32(hw, NGBE_RST, NGBE_RST_LAN(hw->bus.lan_id));
178 ngbe_reset_misc_em(hw);
179 hw->mac.clear_hw_cntrs(hw);
183 /* Store the permanent mac address */
184 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
187 * Store MAC address from RAR0, clear receive address registers, and
188 * clear the multicast table.
190 hw->mac.num_rar_entries = NGBE_EM_RAR_ENTRIES;
191 hw->mac.init_rx_addrs(hw);
197 * ngbe_clear_hw_cntrs - Generic clear hardware counters
198 * @hw: pointer to hardware structure
200 * Clears all hardware statistics counters by reading them from the hardware
201 * Statistics counters are clear on read.
203 s32 ngbe_clear_hw_cntrs(struct ngbe_hw *hw)
207 DEBUGFUNC("ngbe_clear_hw_cntrs");
210 /* don't write clear queue stats */
211 for (i = 0; i < NGBE_MAX_QP; i++) {
212 hw->qp_last[i].rx_qp_packets = 0;
213 hw->qp_last[i].tx_qp_packets = 0;
214 hw->qp_last[i].rx_qp_bytes = 0;
215 hw->qp_last[i].tx_qp_bytes = 0;
216 hw->qp_last[i].rx_qp_mc_packets = 0;
217 hw->qp_last[i].tx_qp_mc_packets = 0;
218 hw->qp_last[i].rx_qp_bc_packets = 0;
219 hw->qp_last[i].tx_qp_bc_packets = 0;
223 rd32(hw, NGBE_PBRXLNKXON);
224 rd32(hw, NGBE_PBRXLNKXOFF);
225 rd32(hw, NGBE_PBTXLNKXON);
226 rd32(hw, NGBE_PBTXLNKXOFF);
229 rd32(hw, NGBE_DMARXPKT);
230 rd32(hw, NGBE_DMATXPKT);
232 rd64(hw, NGBE_DMARXOCTL);
233 rd64(hw, NGBE_DMATXOCTL);
236 rd64(hw, NGBE_MACRXERRCRCL);
237 rd64(hw, NGBE_MACRXMPKTL);
238 rd64(hw, NGBE_MACTXMPKTL);
240 rd64(hw, NGBE_MACRXPKTL);
241 rd64(hw, NGBE_MACTXPKTL);
242 rd64(hw, NGBE_MACRXGBOCTL);
244 rd64(hw, NGBE_MACRXOCTL);
245 rd32(hw, NGBE_MACTXOCTL);
247 rd64(hw, NGBE_MACRX1TO64L);
248 rd64(hw, NGBE_MACRX65TO127L);
249 rd64(hw, NGBE_MACRX128TO255L);
250 rd64(hw, NGBE_MACRX256TO511L);
251 rd64(hw, NGBE_MACRX512TO1023L);
252 rd64(hw, NGBE_MACRX1024TOMAXL);
253 rd64(hw, NGBE_MACTX1TO64L);
254 rd64(hw, NGBE_MACTX65TO127L);
255 rd64(hw, NGBE_MACTX128TO255L);
256 rd64(hw, NGBE_MACTX256TO511L);
257 rd64(hw, NGBE_MACTX512TO1023L);
258 rd64(hw, NGBE_MACTX1024TOMAXL);
260 rd64(hw, NGBE_MACRXERRLENL);
261 rd32(hw, NGBE_MACRXOVERSIZE);
262 rd32(hw, NGBE_MACRXJABBER);
265 rd32(hw, NGBE_LSECTX_UTPKT);
266 rd32(hw, NGBE_LSECTX_ENCPKT);
267 rd32(hw, NGBE_LSECTX_PROTPKT);
268 rd32(hw, NGBE_LSECTX_ENCOCT);
269 rd32(hw, NGBE_LSECTX_PROTOCT);
270 rd32(hw, NGBE_LSECRX_UTPKT);
271 rd32(hw, NGBE_LSECRX_BTPKT);
272 rd32(hw, NGBE_LSECRX_NOSCIPKT);
273 rd32(hw, NGBE_LSECRX_UNSCIPKT);
274 rd32(hw, NGBE_LSECRX_DECOCT);
275 rd32(hw, NGBE_LSECRX_VLDOCT);
276 rd32(hw, NGBE_LSECRX_UNCHKPKT);
277 rd32(hw, NGBE_LSECRX_DLYPKT);
278 rd32(hw, NGBE_LSECRX_LATEPKT);
279 for (i = 0; i < 2; i++) {
280 rd32(hw, NGBE_LSECRX_OKPKT(i));
281 rd32(hw, NGBE_LSECRX_INVPKT(i));
282 rd32(hw, NGBE_LSECRX_BADPKT(i));
284 for (i = 0; i < 4; i++) {
285 rd32(hw, NGBE_LSECRX_INVSAPKT(i));
286 rd32(hw, NGBE_LSECRX_BADSAPKT(i));
293 * ngbe_get_mac_addr - Generic get MAC address
294 * @hw: pointer to hardware structure
295 * @mac_addr: Adapter MAC address
297 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
298 * A reset of the adapter must be performed prior to calling this function
299 * in order for the MAC address to have been loaded from the EEPROM into RAR0
301 s32 ngbe_get_mac_addr(struct ngbe_hw *hw, u8 *mac_addr)
307 DEBUGFUNC("ngbe_get_mac_addr");
309 wr32(hw, NGBE_ETHADDRIDX, 0);
310 rar_high = rd32(hw, NGBE_ETHADDRH);
311 rar_low = rd32(hw, NGBE_ETHADDRL);
313 for (i = 0; i < 2; i++)
314 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
316 for (i = 0; i < 4; i++)
317 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
323 * ngbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
324 * @hw: pointer to the HW structure
326 * Determines the LAN function id by reading memory-mapped registers and swaps
327 * the port value if requested, and set MAC instance for devices.
329 void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw)
331 struct ngbe_bus_info *bus = &hw->bus;
334 DEBUGFUNC("ngbe_set_lan_id_multi_port");
336 reg = rd32(hw, NGBE_PORTSTAT);
337 bus->lan_id = NGBE_PORTSTAT_ID(reg);
338 bus->func = bus->lan_id;
342 * ngbe_stop_hw - Generic stop Tx/Rx units
343 * @hw: pointer to hardware structure
345 * Sets the adapter_stopped flag within ngbe_hw struct. Clears interrupts,
346 * disables transmit and receive units. The adapter_stopped flag is used by
347 * the shared code and drivers to determine if the adapter is in a stopped
348 * state and should not touch the hardware.
350 s32 ngbe_stop_hw(struct ngbe_hw *hw)
355 DEBUGFUNC("ngbe_stop_hw");
358 * Set the adapter_stopped flag so other driver functions stop touching
361 hw->adapter_stopped = true;
363 /* Disable the receive unit */
366 /* Clear interrupt mask to stop interrupts from being generated */
367 wr32(hw, NGBE_IENMISC, 0);
368 wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK);
370 /* Clear any pending interrupts, flush previous writes */
371 wr32(hw, NGBE_ICRMISC, NGBE_ICRMISC_MASK);
372 wr32(hw, NGBE_ICR(0), NGBE_ICR_MASK);
374 wr32(hw, NGBE_BMECTL, 0x3);
376 /* Disable the receive unit by stopping each queue */
377 for (i = 0; i < hw->mac.max_rx_queues; i++)
378 wr32(hw, NGBE_RXCFG(i), 0);
380 /* flush all queues disables */
385 * Prevent the PCI-E bus from hanging by disabling PCI-E master
386 * access and verify no pending requests
388 status = ngbe_set_pcie_master(hw, false);
392 /* Disable the transmit unit. Each queue must be disabled. */
393 for (i = 0; i < hw->mac.max_tx_queues; i++)
394 wr32(hw, NGBE_TXCFG(i), 0);
396 /* flush all queues disables */
404 * ngbe_led_on - Turns on the software controllable LEDs.
405 * @hw: pointer to hardware structure
406 * @index: led number to turn on
408 s32 ngbe_led_on(struct ngbe_hw *hw, u32 index)
410 u32 led_reg = rd32(hw, NGBE_LEDCTL);
412 DEBUGFUNC("ngbe_led_on");
415 return NGBE_ERR_PARAM;
417 /* To turn on the LED, set mode to ON. */
418 led_reg |= NGBE_LEDCTL_100M;
419 wr32(hw, NGBE_LEDCTL, led_reg);
426 * ngbe_led_off - Turns off the software controllable LEDs.
427 * @hw: pointer to hardware structure
428 * @index: led number to turn off
430 s32 ngbe_led_off(struct ngbe_hw *hw, u32 index)
432 u32 led_reg = rd32(hw, NGBE_LEDCTL);
434 DEBUGFUNC("ngbe_led_off");
437 return NGBE_ERR_PARAM;
439 /* To turn off the LED, set mode to OFF. */
440 led_reg &= ~NGBE_LEDCTL_100M;
441 wr32(hw, NGBE_LEDCTL, led_reg);
448 * ngbe_validate_mac_addr - Validate MAC address
449 * @mac_addr: pointer to MAC address.
451 * Tests a MAC address to ensure it is a valid Individual Address.
453 s32 ngbe_validate_mac_addr(u8 *mac_addr)
457 DEBUGFUNC("ngbe_validate_mac_addr");
459 /* Make sure it is not a multicast address */
460 if (NGBE_IS_MULTICAST((struct rte_ether_addr *)mac_addr)) {
461 status = NGBE_ERR_INVALID_MAC_ADDR;
462 /* Not a broadcast address */
463 } else if (NGBE_IS_BROADCAST((struct rte_ether_addr *)mac_addr)) {
464 status = NGBE_ERR_INVALID_MAC_ADDR;
465 /* Reject the zero address */
466 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
467 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
468 status = NGBE_ERR_INVALID_MAC_ADDR;
474 * ngbe_set_rar - Set Rx address register
475 * @hw: pointer to hardware structure
476 * @index: Receive address register to write
477 * @addr: Address to put into receive address register
478 * @vmdq: VMDq "set" or "pool" index
479 * @enable_addr: set flag that address is active
481 * Puts an ethernet address into a receive address register.
483 s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
486 u32 rar_low, rar_high;
487 u32 rar_entries = hw->mac.num_rar_entries;
489 DEBUGFUNC("ngbe_set_rar");
491 /* Make sure we are using a valid rar index range */
492 if (index >= rar_entries) {
493 DEBUGOUT("RAR index %d is out of range.\n", index);
494 return NGBE_ERR_INVALID_ARGUMENT;
497 /* setup VMDq pool selection before this RAR gets enabled */
498 hw->mac.set_vmdq(hw, index, vmdq);
501 * HW expects these in little endian so we reverse the byte
502 * order from network order (big endian) to little endian
504 rar_low = NGBE_ETHADDRL_AD0(addr[5]) |
505 NGBE_ETHADDRL_AD1(addr[4]) |
506 NGBE_ETHADDRL_AD2(addr[3]) |
507 NGBE_ETHADDRL_AD3(addr[2]);
509 * Some parts put the VMDq setting in the extra RAH bits,
510 * so save everything except the lower 16 bits that hold part
511 * of the address and the address valid bit.
513 rar_high = rd32(hw, NGBE_ETHADDRH);
514 rar_high &= ~NGBE_ETHADDRH_AD_MASK;
515 rar_high |= (NGBE_ETHADDRH_AD4(addr[1]) |
516 NGBE_ETHADDRH_AD5(addr[0]));
518 rar_high &= ~NGBE_ETHADDRH_VLD;
519 if (enable_addr != 0)
520 rar_high |= NGBE_ETHADDRH_VLD;
522 wr32(hw, NGBE_ETHADDRIDX, index);
523 wr32(hw, NGBE_ETHADDRL, rar_low);
524 wr32(hw, NGBE_ETHADDRH, rar_high);
530 * ngbe_clear_rar - Remove Rx address register
531 * @hw: pointer to hardware structure
532 * @index: Receive address register to write
534 * Clears an ethernet address from a receive address register.
536 s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index)
539 u32 rar_entries = hw->mac.num_rar_entries;
541 DEBUGFUNC("ngbe_clear_rar");
543 /* Make sure we are using a valid rar index range */
544 if (index >= rar_entries) {
545 DEBUGOUT("RAR index %d is out of range.\n", index);
546 return NGBE_ERR_INVALID_ARGUMENT;
550 * Some parts put the VMDq setting in the extra RAH bits,
551 * so save everything except the lower 16 bits that hold part
552 * of the address and the address valid bit.
554 wr32(hw, NGBE_ETHADDRIDX, index);
555 rar_high = rd32(hw, NGBE_ETHADDRH);
556 rar_high &= ~(NGBE_ETHADDRH_AD_MASK | NGBE_ETHADDRH_VLD);
558 wr32(hw, NGBE_ETHADDRL, 0);
559 wr32(hw, NGBE_ETHADDRH, rar_high);
561 /* clear VMDq pool/queue selection for this RAR */
562 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
568 * ngbe_init_rx_addrs - Initializes receive address filters.
569 * @hw: pointer to hardware structure
571 * Places the MAC address in receive address register 0 and clears the rest
572 * of the receive address registers. Clears the multicast table. Assumes
573 * the receiver is in reset when the routine is called.
575 s32 ngbe_init_rx_addrs(struct ngbe_hw *hw)
579 u32 rar_entries = hw->mac.num_rar_entries;
581 DEBUGFUNC("ngbe_init_rx_addrs");
584 * If the current mac address is valid, assume it is a software override
585 * to the permanent address.
586 * Otherwise, use the permanent address from the eeprom.
588 if (ngbe_validate_mac_addr(hw->mac.addr) ==
589 NGBE_ERR_INVALID_MAC_ADDR) {
590 /* Get the MAC address from the RAR0 for later reference */
591 hw->mac.get_mac_addr(hw, hw->mac.addr);
593 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
594 hw->mac.addr[0], hw->mac.addr[1],
596 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
597 hw->mac.addr[4], hw->mac.addr[5]);
599 /* Setup the receive address. */
600 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
601 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
602 hw->mac.addr[0], hw->mac.addr[1],
604 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
605 hw->mac.addr[4], hw->mac.addr[5]);
607 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
610 /* clear VMDq pool/queue selection for RAR 0 */
611 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
613 /* Zero out the other receive addresses. */
614 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
615 for (i = 1; i < rar_entries; i++) {
616 wr32(hw, NGBE_ETHADDRIDX, i);
617 wr32(hw, NGBE_ETHADDRL, 0);
618 wr32(hw, NGBE_ETHADDRH, 0);
622 hw->addr_ctrl.mta_in_use = 0;
623 psrctl = rd32(hw, NGBE_PSRCTL);
624 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
625 psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
626 wr32(hw, NGBE_PSRCTL, psrctl);
628 DEBUGOUT(" Clearing MTA\n");
629 for (i = 0; i < hw->mac.mcft_size; i++)
630 wr32(hw, NGBE_MCADDRTBL(i), 0);
632 ngbe_init_uta_tables(hw);
638 * ngbe_mta_vector - Determines bit-vector in multicast table to set
639 * @hw: pointer to hardware structure
640 * @mc_addr: the multicast address
642 * Extracts the 12 bits, from a multicast address, to determine which
643 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
644 * incoming rx multicast addresses, to determine the bit-vector to check in
645 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
646 * by the MO field of the PSRCTRL. The MO field is set during initialization
649 static s32 ngbe_mta_vector(struct ngbe_hw *hw, u8 *mc_addr)
653 DEBUGFUNC("ngbe_mta_vector");
655 switch (hw->mac.mc_filter_type) {
656 case 0: /* use bits [47:36] of the address */
657 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
659 case 1: /* use bits [46:35] of the address */
660 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
662 case 2: /* use bits [45:34] of the address */
663 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
665 case 3: /* use bits [43:32] of the address */
666 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
668 default: /* Invalid mc_filter_type */
669 DEBUGOUT("MC filter type param set incorrectly\n");
674 /* vector can only be 12-bits or boundary will be exceeded */
680 * ngbe_set_mta - Set bit-vector in multicast table
681 * @hw: pointer to hardware structure
682 * @mc_addr: Multicast address
684 * Sets the bit-vector in the multicast table.
686 void ngbe_set_mta(struct ngbe_hw *hw, u8 *mc_addr)
692 DEBUGFUNC("ngbe_set_mta");
694 hw->addr_ctrl.mta_in_use++;
696 vector = ngbe_mta_vector(hw, mc_addr);
697 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
700 * The MTA is a register array of 128 32-bit registers. It is treated
701 * like an array of 4096 bits. We want to set bit
702 * BitArray[vector_value]. So we figure out what register the bit is
703 * in, read it, OR in the new bit, then write back the new value. The
704 * register is determined by the upper 7 bits of the vector value and
705 * the bit within that register are determined by the lower 5 bits of
708 vector_reg = (vector >> 5) & 0x7F;
709 vector_bit = vector & 0x1F;
710 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
714 * ngbe_update_mc_addr_list - Updates MAC list of multicast addresses
715 * @hw: pointer to hardware structure
716 * @mc_addr_list: the list of new multicast addresses
717 * @mc_addr_count: number of addresses
718 * @next: iterator function to walk the multicast address list
719 * @clear: flag, when set clears the table beforehand
721 * When the clear flag is set, the given list replaces any existing list.
722 * Hashes the given addresses into the multicast table.
724 s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list,
725 u32 mc_addr_count, ngbe_mc_addr_itr next,
731 DEBUGFUNC("ngbe_update_mc_addr_list");
734 * Set the new number of MC addresses that we are being requested to
737 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
738 hw->addr_ctrl.mta_in_use = 0;
740 /* Clear mta_shadow */
742 DEBUGOUT(" Clearing MTA\n");
743 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
746 /* Update mta_shadow */
747 for (i = 0; i < mc_addr_count; i++) {
748 DEBUGOUT(" Adding the multicast addresses:\n");
749 ngbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
753 for (i = 0; i < hw->mac.mcft_size; i++)
754 wr32a(hw, NGBE_MCADDRTBL(0), i,
755 hw->mac.mta_shadow[i]);
757 if (hw->addr_ctrl.mta_in_use > 0) {
758 u32 psrctl = rd32(hw, NGBE_PSRCTL);
759 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
760 psrctl |= NGBE_PSRCTL_MCHFENA |
761 NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
762 wr32(hw, NGBE_PSRCTL, psrctl);
765 DEBUGOUT("ngbe update mc addr list complete\n");
770 * ngbe_setup_fc_em - Set up flow control
771 * @hw: pointer to hardware structure
773 * Called at init time to set up flow control.
775 s32 ngbe_setup_fc_em(struct ngbe_hw *hw)
780 DEBUGFUNC("ngbe_setup_fc");
782 /* Validate the requested mode */
783 if (hw->fc.strict_ieee && hw->fc.requested_mode == ngbe_fc_rx_pause) {
784 DEBUGOUT("ngbe_fc_rx_pause not valid in strict IEEE mode\n");
785 err = NGBE_ERR_INVALID_LINK_SETTINGS;
790 * 1gig parts do not have a word in the EEPROM to determine the
791 * default flow control setting, so we explicitly set it to full.
793 if (hw->fc.requested_mode == ngbe_fc_default)
794 hw->fc.requested_mode = ngbe_fc_full;
797 * The possible values of fc.requested_mode are:
798 * 0: Flow control is completely disabled
799 * 1: Rx flow control is enabled (we can receive pause frames,
800 * but not send pause frames).
801 * 2: Tx flow control is enabled (we can send pause frames but
802 * we do not support receiving pause frames).
803 * 3: Both Rx and Tx flow control (symmetric) are enabled.
806 switch (hw->fc.requested_mode) {
808 /* Flow control completely disabled by software override. */
810 case ngbe_fc_tx_pause:
812 * Tx Flow control is enabled, and Rx Flow control is
813 * disabled by software override.
815 if (hw->phy.type == ngbe_phy_mvl_sfi ||
816 hw->phy.type == ngbe_phy_yt8521s_sfi)
817 reg_cu |= MVL_FANA_ASM_PAUSE;
819 reg_cu |= 0x800; /*need to merge rtl and mvl on page 0*/
821 case ngbe_fc_rx_pause:
823 * Rx Flow control is enabled and Tx Flow control is
824 * disabled by software override. Since there really
825 * isn't a way to advertise that we are capable of RX
826 * Pause ONLY, we will advertise that we support both
827 * symmetric and asymmetric Rx PAUSE, as such we fall
828 * through to the fc_full statement. Later, we will
829 * disable the adapter's ability to send PAUSE frames.
832 /* Flow control (both Rx and Tx) is enabled by SW override. */
833 if (hw->phy.type == ngbe_phy_mvl_sfi ||
834 hw->phy.type == ngbe_phy_yt8521s_sfi)
835 reg_cu |= MVL_FANA_SYM_PAUSE;
837 reg_cu |= 0xC00; /*need to merge rtl and mvl on page 0*/
840 DEBUGOUT("Flow control param set incorrectly\n");
841 err = NGBE_ERR_CONFIG;
845 err = hw->phy.set_pause_adv(hw, reg_cu);
852 * ngbe_fc_enable - Enable flow control
853 * @hw: pointer to hardware structure
855 * Enable flow control according to the current settings.
857 s32 ngbe_fc_enable(struct ngbe_hw *hw)
860 u32 mflcn_reg, fccfg_reg;
864 DEBUGFUNC("ngbe_fc_enable");
866 /* Validate the water mark configuration */
867 if (!hw->fc.pause_time) {
868 err = NGBE_ERR_INVALID_LINK_SETTINGS;
872 /* Low water mark of zero causes XOFF floods */
873 if ((hw->fc.current_mode & ngbe_fc_tx_pause) && hw->fc.high_water) {
874 if (!hw->fc.low_water ||
875 hw->fc.low_water >= hw->fc.high_water) {
876 DEBUGOUT("Invalid water mark configuration\n");
877 err = NGBE_ERR_INVALID_LINK_SETTINGS;
882 /* Negotiate the fc mode to use */
883 hw->mac.fc_autoneg(hw);
885 /* Disable any previous flow control settings */
886 mflcn_reg = rd32(hw, NGBE_RXFCCFG);
887 mflcn_reg &= ~NGBE_RXFCCFG_FC;
889 fccfg_reg = rd32(hw, NGBE_TXFCCFG);
890 fccfg_reg &= ~NGBE_TXFCCFG_FC;
892 * The possible values of fc.current_mode are:
893 * 0: Flow control is completely disabled
894 * 1: Rx flow control is enabled (we can receive pause frames,
895 * but not send pause frames).
896 * 2: Tx flow control is enabled (we can send pause frames but
897 * we do not support receiving pause frames).
898 * 3: Both Rx and Tx flow control (symmetric) are enabled.
901 switch (hw->fc.current_mode) {
904 * Flow control is disabled by software override or autoneg.
905 * The code below will actually disable it in the HW.
908 case ngbe_fc_rx_pause:
910 * Rx Flow control is enabled and Tx Flow control is
911 * disabled by software override. Since there really
912 * isn't a way to advertise that we are capable of RX
913 * Pause ONLY, we will advertise that we support both
914 * symmetric and asymmetric Rx PAUSE. Later, we will
915 * disable the adapter's ability to send PAUSE frames.
917 mflcn_reg |= NGBE_RXFCCFG_FC;
919 case ngbe_fc_tx_pause:
921 * Tx Flow control is enabled, and Rx Flow control is
922 * disabled by software override.
924 fccfg_reg |= NGBE_TXFCCFG_FC;
927 /* Flow control (both Rx and Tx) is enabled by SW override. */
928 mflcn_reg |= NGBE_RXFCCFG_FC;
929 fccfg_reg |= NGBE_TXFCCFG_FC;
932 DEBUGOUT("Flow control param set incorrectly\n");
933 err = NGBE_ERR_CONFIG;
937 /* Set 802.3x based flow control settings. */
938 wr32(hw, NGBE_RXFCCFG, mflcn_reg);
939 wr32(hw, NGBE_TXFCCFG, fccfg_reg);
941 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
942 if ((hw->fc.current_mode & ngbe_fc_tx_pause) &&
944 fcrtl = NGBE_FCWTRLO_TH(hw->fc.low_water) |
946 fcrth = NGBE_FCWTRHI_TH(hw->fc.high_water) |
950 * In order to prevent Tx hangs when the internal Tx
951 * switch is enabled we must set the high water mark
952 * to the Rx packet buffer size - 24KB. This allows
953 * the Tx switch to function even under heavy Rx
957 fcrth = rd32(hw, NGBE_PBRXSIZE) - 24576;
959 wr32(hw, NGBE_FCWTRLO, fcrtl);
960 wr32(hw, NGBE_FCWTRHI, fcrth);
962 /* Configure pause time */
963 pause_time = NGBE_RXFCFSH_TIME(hw->fc.pause_time);
964 wr32(hw, NGBE_FCXOFFTM, pause_time * 0x00010000);
966 /* Configure flow control refresh threshold value */
967 wr32(hw, NGBE_RXFCRFSH, hw->fc.pause_time / 2);
974 * ngbe_negotiate_fc - Negotiate flow control
975 * @hw: pointer to hardware structure
976 * @adv_reg: flow control advertised settings
977 * @lp_reg: link partner's flow control settings
978 * @adv_sym: symmetric pause bit in advertisement
979 * @adv_asm: asymmetric pause bit in advertisement
980 * @lp_sym: symmetric pause bit in link partner advertisement
981 * @lp_asm: asymmetric pause bit in link partner advertisement
983 * Find the intersection between advertised settings and link partner's
984 * advertised settings
986 s32 ngbe_negotiate_fc(struct ngbe_hw *hw, u32 adv_reg, u32 lp_reg,
987 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
989 if ((!(adv_reg)) || (!(lp_reg))) {
990 DEBUGOUT("Local or link partner's advertised flow control "
991 "settings are NULL. Local: %x, link partner: %x\n",
993 return NGBE_ERR_FC_NOT_NEGOTIATED;
996 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
998 * Now we need to check if the user selected Rx ONLY
999 * of pause frames. In this case, we had to advertise
1000 * FULL flow control because we could not advertise RX
1001 * ONLY. Hence, we must now check to see if we need to
1002 * turn OFF the TRANSMISSION of PAUSE frames.
1004 if (hw->fc.requested_mode == ngbe_fc_full) {
1005 hw->fc.current_mode = ngbe_fc_full;
1006 DEBUGOUT("Flow Control = FULL.\n");
1008 hw->fc.current_mode = ngbe_fc_rx_pause;
1009 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
1011 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1012 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1013 hw->fc.current_mode = ngbe_fc_tx_pause;
1014 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1015 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1016 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1017 hw->fc.current_mode = ngbe_fc_rx_pause;
1018 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1020 hw->fc.current_mode = ngbe_fc_none;
1021 DEBUGOUT("Flow Control = NONE.\n");
1027 * ngbe_fc_autoneg_em - Enable flow control IEEE clause 37
1028 * @hw: pointer to hardware structure
1030 * Enable flow control according to IEEE clause 37.
1032 STATIC s32 ngbe_fc_autoneg_em(struct ngbe_hw *hw)
1034 u8 technology_ability_reg = 0;
1035 u8 lp_technology_ability_reg = 0;
1037 hw->phy.get_adv_pause(hw, &technology_ability_reg);
1038 hw->phy.get_lp_adv_pause(hw, &lp_technology_ability_reg);
1040 return ngbe_negotiate_fc(hw, (u32)technology_ability_reg,
1041 (u32)lp_technology_ability_reg,
1042 NGBE_TAF_SYM_PAUSE, NGBE_TAF_ASM_PAUSE,
1043 NGBE_TAF_SYM_PAUSE, NGBE_TAF_ASM_PAUSE);
1047 * ngbe_fc_autoneg - Configure flow control
1048 * @hw: pointer to hardware structure
1050 * Compares our advertised flow control capabilities to those advertised by
1051 * our link partner, and determines the proper flow control mode to use.
1053 void ngbe_fc_autoneg(struct ngbe_hw *hw)
1055 s32 err = NGBE_ERR_FC_NOT_NEGOTIATED;
1059 DEBUGFUNC("ngbe_fc_autoneg");
1062 * AN should have completed when the cable was plugged in.
1063 * Look for reasons to bail out. Bail out if:
1064 * - FC autoneg is disabled, or if
1067 if (hw->fc.disable_fc_autoneg) {
1068 DEBUGOUT("Flow control autoneg is disabled");
1072 hw->mac.check_link(hw, &speed, &link_up, false);
1074 DEBUGOUT("The link is down");
1078 err = ngbe_fc_autoneg_em(hw);
1082 hw->fc.fc_was_autonegged = true;
1084 hw->fc.fc_was_autonegged = false;
1085 hw->fc.current_mode = hw->fc.requested_mode;
1090 * ngbe_set_pcie_master - Disable or Enable PCI-express master access
1091 * @hw: pointer to hardware structure
1093 * Disables PCI-Express master access and verifies there are no pending
1094 * requests. NGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1095 * bit hasn't caused the master requests to be disabled, else 0
1096 * is returned signifying master requests disabled.
1098 s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable)
1104 DEBUGFUNC("ngbe_set_pcie_master");
1106 ngbe_hic_pcie_read(hw, addr, &data, 4);
1112 ngbe_hic_pcie_write(hw, addr, &data, 4);
1117 /* Exit if master requests are blocked */
1118 if (!(rd32(hw, NGBE_BMEPEND)) ||
1119 NGBE_REMOVED(hw->hw_addr))
1122 /* Poll for master request bit to clear */
1123 for (i = 0; i < NGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
1125 if (!(rd32(hw, NGBE_BMEPEND)))
1129 DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
1130 status = NGBE_ERR_MASTER_REQUESTS_PENDING;
1137 * ngbe_acquire_swfw_sync - Acquire SWFW semaphore
1138 * @hw: pointer to hardware structure
1139 * @mask: Mask to specify which semaphore to acquire
1141 * Acquires the SWFW semaphore through the MNGSEM register for the specified
1142 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1144 s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask)
1148 u32 swmask = NGBE_MNGSEM_SW(mask);
1149 u32 fwmask = NGBE_MNGSEM_FW(mask);
1153 DEBUGFUNC("ngbe_acquire_swfw_sync");
1155 for (i = 0; i < timeout; i++) {
1157 * SW NVM semaphore bit is used for access to all
1158 * SW_FW_SYNC bits (not just NVM)
1160 if (ngbe_get_eeprom_semaphore(hw))
1161 return NGBE_ERR_SWFW_SYNC;
1163 mngsem = rd32(hw, NGBE_MNGSEM);
1164 if (mngsem & (fwmask | swmask)) {
1165 /* Resource is currently in use by FW or SW */
1166 ngbe_release_eeprom_semaphore(hw);
1170 wr32(hw, NGBE_MNGSEM, mngsem);
1171 ngbe_release_eeprom_semaphore(hw);
1176 fwsm = rd32(hw, NGBE_MNGFWSYNC);
1177 DEBUGOUT("SWFW semaphore not granted: MNG_SWFW_SYNC = 0x%x, MNG_FW_SM = 0x%x\n",
1181 return NGBE_ERR_SWFW_SYNC;
1185 * ngbe_release_swfw_sync - Release SWFW semaphore
1186 * @hw: pointer to hardware structure
1187 * @mask: Mask to specify which semaphore to release
1189 * Releases the SWFW semaphore through the MNGSEM register for the specified
1190 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1192 void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask)
1197 DEBUGFUNC("ngbe_release_swfw_sync");
1199 ngbe_get_eeprom_semaphore(hw);
1201 mngsem = rd32(hw, NGBE_MNGSEM);
1203 wr32(hw, NGBE_MNGSEM, mngsem);
1205 ngbe_release_eeprom_semaphore(hw);
1209 * ngbe_disable_sec_rx_path - Stops the receive data path
1210 * @hw: pointer to hardware structure
1212 * Stops the receive data path and waits for the HW to internally empty
1213 * the Rx security block
1215 s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw)
1217 #define NGBE_MAX_SECRX_POLL 4000
1222 DEBUGFUNC("ngbe_disable_sec_rx_path");
1225 secrxreg = rd32(hw, NGBE_SECRXCTL);
1226 secrxreg |= NGBE_SECRXCTL_XDSA;
1227 wr32(hw, NGBE_SECRXCTL, secrxreg);
1228 for (i = 0; i < NGBE_MAX_SECRX_POLL; i++) {
1229 secrxreg = rd32(hw, NGBE_SECRXSTAT);
1230 if (!(secrxreg & NGBE_SECRXSTAT_RDY))
1231 /* Use interrupt-safe sleep just in case */
1237 /* For informational purposes only */
1238 if (i >= NGBE_MAX_SECRX_POLL)
1239 DEBUGOUT("Rx unit being enabled before security "
1240 "path fully disabled. Continuing with init.\n");
1246 * ngbe_enable_sec_rx_path - Enables the receive data path
1247 * @hw: pointer to hardware structure
1249 * Enables the receive data path.
1251 s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw)
1255 DEBUGFUNC("ngbe_enable_sec_rx_path");
1257 secrxreg = rd32(hw, NGBE_SECRXCTL);
1258 secrxreg &= ~NGBE_SECRXCTL_XDSA;
1259 wr32(hw, NGBE_SECRXCTL, secrxreg);
1266 * ngbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
1267 * @hw: pointer to hardware struct
1268 * @rar: receive address register index to disassociate
1269 * @vmdq: VMDq pool index to remove from the rar
1271 s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
1274 u32 rar_entries = hw->mac.num_rar_entries;
1276 DEBUGFUNC("ngbe_clear_vmdq");
1278 /* Make sure we are using a valid rar index range */
1279 if (rar >= rar_entries) {
1280 DEBUGOUT("RAR index %d is out of range.\n", rar);
1281 return NGBE_ERR_INVALID_ARGUMENT;
1284 wr32(hw, NGBE_ETHADDRIDX, rar);
1285 mpsar = rd32(hw, NGBE_ETHADDRASS);
1287 if (NGBE_REMOVED(hw->hw_addr))
1293 mpsar &= ~(1 << vmdq);
1294 wr32(hw, NGBE_ETHADDRASS, mpsar);
1296 /* was that the last pool using this rar? */
1297 if (mpsar == 0 && rar != 0)
1298 hw->mac.clear_rar(hw, rar);
1304 * ngbe_set_vmdq - Associate a VMDq pool index with a rx address
1305 * @hw: pointer to hardware struct
1306 * @rar: receive address register index to associate with a VMDq index
1307 * @vmdq: VMDq pool index
1309 s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
1312 u32 rar_entries = hw->mac.num_rar_entries;
1314 DEBUGFUNC("ngbe_set_vmdq");
1316 /* Make sure we are using a valid rar index range */
1317 if (rar >= rar_entries) {
1318 DEBUGOUT("RAR index %d is out of range.\n", rar);
1319 return NGBE_ERR_INVALID_ARGUMENT;
1322 wr32(hw, NGBE_ETHADDRIDX, rar);
1324 mpsar = rd32(hw, NGBE_ETHADDRASS);
1326 wr32(hw, NGBE_ETHADDRASS, mpsar);
1332 * ngbe_init_uta_tables - Initialize the Unicast Table Array
1333 * @hw: pointer to hardware structure
1335 s32 ngbe_init_uta_tables(struct ngbe_hw *hw)
1339 DEBUGFUNC("ngbe_init_uta_tables");
1340 DEBUGOUT(" Clearing UTA\n");
1342 for (i = 0; i < 128; i++)
1343 wr32(hw, NGBE_UCADDRTBL(i), 0);
1349 * ngbe_find_vlvf_slot - find the vlanid or the first empty slot
1350 * @hw: pointer to hardware structure
1351 * @vlan: VLAN id to write to VLAN filter
1352 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1356 * return the VLVF index where this VLAN id should be placed
1359 s32 ngbe_find_vlvf_slot(struct ngbe_hw *hw, u32 vlan, bool vlvf_bypass)
1361 s32 regindex, first_empty_slot;
1364 /* short cut the special case */
1368 /* if vlvf_bypass is set we don't want to use an empty slot, we
1369 * will simply bypass the VLVF if there are no entries present in the
1370 * VLVF that contain our VLAN
1372 first_empty_slot = vlvf_bypass ? NGBE_ERR_NO_SPACE : 0;
1374 /* add VLAN enable bit for comparison */
1375 vlan |= NGBE_PSRVLAN_EA;
1377 /* Search for the vlan id in the VLVF entries. Save off the first empty
1378 * slot found along the way.
1380 * pre-decrement loop covering (NGBE_NUM_POOL - 1) .. 1
1382 for (regindex = NGBE_NUM_POOL; --regindex;) {
1383 wr32(hw, NGBE_PSRVLANIDX, regindex);
1384 bits = rd32(hw, NGBE_PSRVLAN);
1387 if (!first_empty_slot && !bits)
1388 first_empty_slot = regindex;
1391 /* If we are here then we didn't find the VLAN. Return first empty
1392 * slot we found during our search, else error.
1394 if (!first_empty_slot)
1395 DEBUGOUT("No space in VLVF.\n");
1397 return first_empty_slot ? first_empty_slot : NGBE_ERR_NO_SPACE;
1401 * ngbe_set_vfta - Set VLAN filter table
1402 * @hw: pointer to hardware structure
1403 * @vlan: VLAN id to write to VLAN filter
1404 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1405 * @vlan_on: boolean flag to turn on/off VLAN
1406 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1408 * Turn on/off specified VLAN in the VLAN filter table.
1410 s32 ngbe_set_vfta(struct ngbe_hw *hw, u32 vlan, u32 vind,
1411 bool vlan_on, bool vlvf_bypass)
1413 u32 regidx, vfta_delta, vfta;
1416 DEBUGFUNC("ngbe_set_vfta");
1418 if (vlan > 4095 || vind > 63)
1419 return NGBE_ERR_PARAM;
1422 * this is a 2 part operation - first the VFTA, then the
1423 * VLVF and VLVFB if VT Mode is set
1424 * We don't write the VFTA until we know the VLVF part succeeded.
1428 * The VFTA is a bitstring made up of 128 32-bit registers
1429 * that enable the particular VLAN id, much like the MTA:
1430 * bits[11-5]: which register
1431 * bits[4-0]: which bit in the register
1434 vfta_delta = 1 << (vlan % 32);
1435 vfta = rd32(hw, NGBE_VLANTBL(regidx));
1438 * vfta_delta represents the difference between the current value
1439 * of vfta and the value we want in the register. Since the diff
1440 * is an XOR mask we can just update the vfta using an XOR
1442 vfta_delta &= vlan_on ? ~vfta : vfta;
1446 * Call ngbe_set_vlvf to set VLVFB and VLVF
1448 err = ngbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1457 /* Update VFTA now that we are ready for traffic */
1459 wr32(hw, NGBE_VLANTBL(regidx), vfta);
1465 * ngbe_set_vlvf - Set VLAN Pool Filter
1466 * @hw: pointer to hardware structure
1467 * @vlan: VLAN id to write to VLAN filter
1468 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1469 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1470 * @vfta_delta: pointer to the difference between the current value
1471 * of PSRVLANPLM and the desired value
1472 * @vfta: the desired value of the VFTA
1473 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1475 * Turn on/off specified bit in VLVF table.
1477 s32 ngbe_set_vlvf(struct ngbe_hw *hw, u32 vlan, u32 vind,
1478 bool vlan_on, u32 *vfta_delta, u32 vfta,
1485 DEBUGFUNC("ngbe_set_vlvf");
1487 if (vlan > 4095 || vind > 63)
1488 return NGBE_ERR_PARAM;
1490 /* If VT Mode is set
1492 * make sure the vlan is in PSRVLAN
1493 * set the vind bit in the matching PSRVLANPLM
1495 * clear the pool bit and possibly the vind
1497 portctl = rd32(hw, NGBE_PORTCTL);
1498 if (!(portctl & NGBE_PORTCTL_NUMVT_MASK))
1501 vlvf_index = ngbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1505 wr32(hw, NGBE_PSRVLANIDX, vlvf_index);
1506 bits = rd32(hw, NGBE_PSRVLANPLM(vind / 32));
1508 /* set the pool bit */
1509 bits |= 1 << (vind % 32);
1513 /* clear the pool bit */
1514 bits ^= 1 << (vind % 32);
1517 !rd32(hw, NGBE_PSRVLANPLM(vind / 32))) {
1518 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1519 * we run the risk of stray packets leaking into
1520 * the PF via the default pool
1523 wr32(hw, NGBE_PSRVLANPLM(vlan / 32), vfta);
1525 /* disable VLVF and clear remaining bit from pool */
1526 wr32(hw, NGBE_PSRVLAN, 0);
1527 wr32(hw, NGBE_PSRVLANPLM(vind / 32), 0);
1532 /* If there are still bits set in the PSRVLANPLM registers
1533 * for the VLAN ID indicated we need to see if the
1534 * caller is requesting that we clear the PSRVLANPLM entry bit.
1535 * If the caller has requested that we clear the PSRVLANPLM
1536 * entry bit but there are still pools/VFs using this VLAN
1537 * ID entry then ignore the request. We're not worried
1538 * about the case where we're turning the PSRVLANPLM VLAN ID
1539 * entry bit on, only when requested to turn it off as
1540 * there may be multiple pools and/or VFs using the
1541 * VLAN ID entry. In that case we cannot clear the
1542 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1543 * been cleared. This will be indicated by "bits" being
1549 /* record pool change and enable VLAN ID if not already enabled */
1550 wr32(hw, NGBE_PSRVLANPLM(vind / 32), bits);
1551 wr32(hw, NGBE_PSRVLAN, NGBE_PSRVLAN_EA | vlan);
1557 * ngbe_clear_vfta - Clear VLAN filter table
1558 * @hw: pointer to hardware structure
1560 * Clears the VLAN filer table, and the VMDq index associated with the filter
1562 s32 ngbe_clear_vfta(struct ngbe_hw *hw)
1566 DEBUGFUNC("ngbe_clear_vfta");
1568 for (offset = 0; offset < hw->mac.vft_size; offset++)
1569 wr32(hw, NGBE_VLANTBL(offset), 0);
1571 for (offset = 0; offset < NGBE_NUM_POOL; offset++) {
1572 wr32(hw, NGBE_PSRVLANIDX, offset);
1573 wr32(hw, NGBE_PSRVLAN, 0);
1574 wr32(hw, NGBE_PSRVLANPLM(0), 0);
1581 * ngbe_check_mac_link_em - Determine link and speed status
1582 * @hw: pointer to hardware structure
1583 * @speed: pointer to link speed
1584 * @link_up: true when link is up
1585 * @link_up_wait_to_complete: bool used to wait for link up or not
1587 * Reads the links register to determine if link is up and the current speed
1589 s32 ngbe_check_mac_link_em(struct ngbe_hw *hw, u32 *speed,
1590 bool *link_up, bool link_up_wait_to_complete)
1595 DEBUGFUNC("ngbe_check_mac_link_em");
1597 reg = rd32(hw, NGBE_GPIOINTSTAT);
1598 wr32(hw, NGBE_GPIOEOI, reg);
1600 if (link_up_wait_to_complete) {
1601 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1602 status = hw->phy.check_link(hw, speed, link_up);
1608 status = hw->phy.check_link(hw, speed, link_up);
1614 s32 ngbe_get_link_capabilities_em(struct ngbe_hw *hw,
1622 hw->mac.autoneg = *autoneg;
1624 if (hw->phy.type == ngbe_phy_rtl) {
1625 *speed = NGBE_LINK_SPEED_1GB_FULL |
1626 NGBE_LINK_SPEED_100M_FULL |
1627 NGBE_LINK_SPEED_10M_FULL;
1630 if (hw->phy.type == ngbe_phy_yt8521s_sfi) {
1631 ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value);
1632 if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1))
1633 *speed = NGBE_LINK_SPEED_1GB_FULL;
1639 s32 ngbe_setup_mac_link_em(struct ngbe_hw *hw,
1641 bool autoneg_wait_to_complete)
1647 /* Setup the PHY according to input speed */
1648 status = hw->phy.setup_link(hw, speed, autoneg_wait_to_complete);
1654 * ngbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
1655 * @hw: pointer to hardware structure
1656 * @enable: enable or disable switch for MAC anti-spoofing
1657 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
1660 void ngbe_set_mac_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf)
1664 pfvfspoof = rd32(hw, NGBE_POOLTXASMAC);
1666 pfvfspoof |= (1 << vf);
1668 pfvfspoof &= ~(1 << vf);
1669 wr32(hw, NGBE_POOLTXASMAC, pfvfspoof);
1673 * ngbe_set_pba - Initialize Rx packet buffer
1674 * @hw: pointer to hardware structure
1675 * @headroom: reserve n KB of headroom
1677 void ngbe_set_pba(struct ngbe_hw *hw)
1679 u32 rxpktsize = hw->mac.rx_pb_size;
1680 u32 txpktsize, txpbthresh;
1682 /* Reserve 256 KB of headroom */
1686 wr32(hw, NGBE_PBRXSIZE, rxpktsize);
1688 /* Only support an equally distributed Tx packet buffer strategy. */
1689 txpktsize = NGBE_PBTXSIZE_MAX;
1690 txpbthresh = (txpktsize / 1024) - NGBE_TXPKT_SIZE_MAX;
1692 wr32(hw, NGBE_PBTXSIZE, txpktsize);
1693 wr32(hw, NGBE_PBTXDMATH, txpbthresh);
1697 * ngbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
1698 * @hw: pointer to hardware structure
1699 * @enable: enable or disable switch for VLAN anti-spoofing
1700 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
1703 void ngbe_set_vlan_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf)
1707 pfvfspoof = rd32(hw, NGBE_POOLTXASVLAN);
1709 pfvfspoof |= (1 << vf);
1711 pfvfspoof &= ~(1 << vf);
1712 wr32(hw, NGBE_POOLTXASVLAN, pfvfspoof);
1716 * ngbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1717 * @hw: pointer to hardware structure
1719 * Inits the thermal sensor thresholds according to the NVM map
1720 * and save off the threshold and location values into mac.thermal_sensor_data
1722 s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw)
1724 struct ngbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1726 DEBUGFUNC("ngbe_init_thermal_sensor_thresh");
1728 memset(data, 0, sizeof(struct ngbe_thermal_sensor_data));
1730 if (hw->bus.lan_id != 0)
1731 return NGBE_NOT_IMPLEMENTED;
1733 wr32(hw, NGBE_TSINTR,
1734 NGBE_TSINTR_AEN | NGBE_TSINTR_DEN);
1735 wr32(hw, NGBE_TSEN, NGBE_TSEN_ENA);
1738 data->sensor[0].alarm_thresh = 115;
1739 wr32(hw, NGBE_TSATHRE, 0x344);
1740 data->sensor[0].dalarm_thresh = 110;
1741 wr32(hw, NGBE_TSDTHRE, 0x330);
1746 s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw)
1751 DEBUGFUNC("ngbe_mac_check_overtemp");
1753 /* Check that the LASI temp alarm status was triggered */
1754 ts_state = rd32(hw, NGBE_TSALM);
1756 if (ts_state & NGBE_TSALM_HI)
1757 status = NGBE_ERR_UNDERTEMP;
1758 else if (ts_state & NGBE_TSALM_LO)
1759 status = NGBE_ERR_OVERTEMP;
1764 void ngbe_disable_rx(struct ngbe_hw *hw)
1768 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
1769 if (pfdtxgswc & NGBE_PSRCTL_LBENA) {
1770 pfdtxgswc &= ~NGBE_PSRCTL_LBENA;
1771 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
1772 hw->mac.set_lben = true;
1774 hw->mac.set_lben = false;
1777 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0);
1778 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, 0);
1781 void ngbe_enable_rx(struct ngbe_hw *hw)
1785 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, NGBE_MACRXCFG_ENA);
1786 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, NGBE_PBRXCTL_ENA);
1788 if (hw->mac.set_lben) {
1789 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
1790 pfdtxgswc |= NGBE_PSRCTL_LBENA;
1791 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
1792 hw->mac.set_lben = false;
1797 * ngbe_set_mac_type - Sets MAC type
1798 * @hw: pointer to the HW structure
1800 * This function sets the mac type of the adapter based on the
1801 * vendor ID and device ID stored in the hw structure.
1803 s32 ngbe_set_mac_type(struct ngbe_hw *hw)
1807 DEBUGFUNC("ngbe_set_mac_type");
1809 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
1810 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
1811 return NGBE_ERR_DEVICE_NOT_SUPPORTED;
1814 switch (hw->sub_device_id) {
1815 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
1816 case NGBE_SUB_DEV_ID_EM_MVL_RGMII:
1817 hw->phy.media_type = ngbe_media_type_copper;
1818 hw->mac.type = ngbe_mac_em;
1819 hw->mac.link_type = ngbe_link_copper;
1821 case NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP:
1822 hw->phy.media_type = ngbe_media_type_copper;
1823 hw->mac.type = ngbe_mac_em;
1824 hw->mac.link_type = ngbe_link_fiber;
1826 case NGBE_SUB_DEV_ID_EM_MVL_SFP:
1827 case NGBE_SUB_DEV_ID_EM_YT8521S_SFP:
1828 hw->phy.media_type = ngbe_media_type_fiber;
1829 hw->mac.type = ngbe_mac_em;
1830 hw->mac.link_type = ngbe_link_fiber;
1832 case NGBE_SUB_DEV_ID_EM_MVL_MIX:
1833 hw->phy.media_type = ngbe_media_type_unknown;
1834 hw->mac.type = ngbe_mac_em;
1835 hw->mac.link_type = ngbe_link_type_unknown;
1837 case NGBE_SUB_DEV_ID_EM_VF:
1838 hw->phy.media_type = ngbe_media_type_virtual;
1839 hw->mac.type = ngbe_mac_em_vf;
1842 err = NGBE_ERR_DEVICE_NOT_SUPPORTED;
1843 hw->phy.media_type = ngbe_media_type_unknown;
1844 hw->mac.type = ngbe_mac_unknown;
1845 DEBUGOUT("Unsupported device id: %x", hw->device_id);
1849 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
1850 hw->mac.type, hw->phy.media_type, err);
1855 * ngbe_enable_rx_dma - Enable the Rx DMA unit
1856 * @hw: pointer to hardware structure
1857 * @regval: register value to write to RXCTRL
1859 * Enables the Rx DMA unit
1861 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)
1863 DEBUGFUNC("ngbe_enable_rx_dma");
1866 * Workaround silicon errata when enabling the Rx datapath.
1867 * If traffic is incoming before we enable the Rx unit, it could hang
1868 * the Rx DMA unit. Therefore, make sure the security engine is
1869 * completely disabled prior to enabling the Rx unit.
1872 hw->mac.disable_sec_rx_path(hw);
1874 if (regval & NGBE_PBRXCTL_ENA)
1877 ngbe_disable_rx(hw);
1879 hw->mac.enable_sec_rx_path(hw);
1884 void ngbe_map_device_id(struct ngbe_hw *hw)
1886 u16 oem = hw->sub_system_id & NGBE_OEM_MASK;
1890 /* move subsystem_device_id to device_id */
1891 switch (hw->device_id) {
1892 case NGBE_DEV_ID_EM_WX1860AL_W_VF:
1893 case NGBE_DEV_ID_EM_WX1860A2_VF:
1894 case NGBE_DEV_ID_EM_WX1860A2S_VF:
1895 case NGBE_DEV_ID_EM_WX1860A4_VF:
1896 case NGBE_DEV_ID_EM_WX1860A4S_VF:
1897 case NGBE_DEV_ID_EM_WX1860AL2_VF:
1898 case NGBE_DEV_ID_EM_WX1860AL2S_VF:
1899 case NGBE_DEV_ID_EM_WX1860AL4_VF:
1900 case NGBE_DEV_ID_EM_WX1860AL4S_VF:
1901 case NGBE_DEV_ID_EM_WX1860NCSI_VF:
1902 case NGBE_DEV_ID_EM_WX1860A1_VF:
1903 case NGBE_DEV_ID_EM_WX1860A1L_VF:
1904 hw->device_id = NGBE_DEV_ID_EM_VF;
1905 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_VF;
1908 case NGBE_DEV_ID_EM_WX1860AL_W:
1909 case NGBE_DEV_ID_EM_WX1860A2:
1910 case NGBE_DEV_ID_EM_WX1860A2S:
1911 case NGBE_DEV_ID_EM_WX1860A4:
1912 case NGBE_DEV_ID_EM_WX1860A4S:
1913 case NGBE_DEV_ID_EM_WX1860AL2:
1914 case NGBE_DEV_ID_EM_WX1860AL2S:
1915 case NGBE_DEV_ID_EM_WX1860AL4:
1916 case NGBE_DEV_ID_EM_WX1860AL4S:
1917 case NGBE_DEV_ID_EM_WX1860NCSI:
1918 case NGBE_DEV_ID_EM_WX1860A1:
1919 case NGBE_DEV_ID_EM_WX1860A1L:
1920 hw->device_id = NGBE_DEV_ID_EM;
1921 if (oem == NGBE_M88E1512_SFP || oem == NGBE_LY_M88E1512_SFP)
1922 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_SFP;
1923 else if (oem == NGBE_M88E1512_RJ45 ||
1924 (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45))
1925 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_RGMII;
1926 else if (oem == NGBE_M88E1512_MIX)
1927 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_MIX;
1928 else if (oem == NGBE_YT8521S_SFP ||
1929 oem == NGBE_YT8521S_SFP_GPIO ||
1930 oem == NGBE_LY_YT8521S_SFP)
1931 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_YT8521S_SFP;
1932 else if (oem == NGBE_INTERNAL_YT8521S_SFP ||
1933 oem == NGBE_INTERNAL_YT8521S_SFP_GPIO)
1934 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP;
1936 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_SGMII;
1942 if (oem == NGBE_LY_M88E1512_SFP || oem == NGBE_YT8521S_SFP_GPIO ||
1943 oem == NGBE_INTERNAL_YT8521S_SFP_GPIO ||
1944 oem == NGBE_LY_YT8521S_SFP)
1945 hw->gpio_ctl = true;
1949 * ngbe_init_ops_pf - Inits func ptrs and MAC type
1950 * @hw: pointer to hardware structure
1952 * Initialize the function pointers and assign the MAC type.
1953 * Does not touch the hardware.
1955 s32 ngbe_init_ops_pf(struct ngbe_hw *hw)
1957 struct ngbe_bus_info *bus = &hw->bus;
1958 struct ngbe_mac_info *mac = &hw->mac;
1959 struct ngbe_phy_info *phy = &hw->phy;
1960 struct ngbe_rom_info *rom = &hw->rom;
1961 struct ngbe_mbx_info *mbx = &hw->mbx;
1963 DEBUGFUNC("ngbe_init_ops_pf");
1966 bus->set_lan_id = ngbe_set_lan_id_multi_port;
1969 phy->identify = ngbe_identify_phy;
1970 phy->read_reg = ngbe_read_phy_reg;
1971 phy->write_reg = ngbe_write_phy_reg;
1972 phy->read_reg_unlocked = ngbe_read_phy_reg_mdi;
1973 phy->write_reg_unlocked = ngbe_write_phy_reg_mdi;
1974 phy->reset_hw = ngbe_reset_phy;
1977 mac->init_hw = ngbe_init_hw;
1978 mac->reset_hw = ngbe_reset_hw_em;
1979 mac->start_hw = ngbe_start_hw;
1980 mac->clear_hw_cntrs = ngbe_clear_hw_cntrs;
1981 mac->enable_rx_dma = ngbe_enable_rx_dma;
1982 mac->get_mac_addr = ngbe_get_mac_addr;
1983 mac->stop_hw = ngbe_stop_hw;
1984 mac->acquire_swfw_sync = ngbe_acquire_swfw_sync;
1985 mac->release_swfw_sync = ngbe_release_swfw_sync;
1987 mac->disable_sec_rx_path = ngbe_disable_sec_rx_path;
1988 mac->enable_sec_rx_path = ngbe_enable_sec_rx_path;
1991 mac->led_on = ngbe_led_on;
1992 mac->led_off = ngbe_led_off;
1994 /* RAR, VLAN, Multicast */
1995 mac->set_rar = ngbe_set_rar;
1996 mac->clear_rar = ngbe_clear_rar;
1997 mac->init_rx_addrs = ngbe_init_rx_addrs;
1998 mac->update_mc_addr_list = ngbe_update_mc_addr_list;
1999 mac->set_vmdq = ngbe_set_vmdq;
2000 mac->clear_vmdq = ngbe_clear_vmdq;
2001 mac->set_vfta = ngbe_set_vfta;
2002 mac->set_vlvf = ngbe_set_vlvf;
2003 mac->clear_vfta = ngbe_clear_vfta;
2004 mac->set_mac_anti_spoofing = ngbe_set_mac_anti_spoofing;
2005 mac->set_vlan_anti_spoofing = ngbe_set_vlan_anti_spoofing;
2008 mac->fc_enable = ngbe_fc_enable;
2009 mac->fc_autoneg = ngbe_fc_autoneg;
2010 mac->setup_fc = ngbe_setup_fc_em;
2013 mac->get_link_capabilities = ngbe_get_link_capabilities_em;
2014 mac->check_link = ngbe_check_mac_link_em;
2015 mac->setup_link = ngbe_setup_mac_link_em;
2017 mac->setup_pba = ngbe_set_pba;
2019 /* Manageability interface */
2020 mac->init_thermal_sensor_thresh = ngbe_init_thermal_sensor_thresh;
2021 mac->check_overtemp = ngbe_mac_check_overtemp;
2023 mbx->init_params = ngbe_init_mbx_params_pf;
2024 mbx->read = ngbe_read_mbx_pf;
2025 mbx->write = ngbe_write_mbx_pf;
2026 mbx->check_for_msg = ngbe_check_for_msg_pf;
2027 mbx->check_for_ack = ngbe_check_for_ack_pf;
2028 mbx->check_for_rst = ngbe_check_for_rst_pf;
2031 rom->init_params = ngbe_init_eeprom_params;
2032 rom->readw_buffer = ngbe_ee_readw_buffer;
2033 rom->read32 = ngbe_ee_read32;
2034 rom->writew_buffer = ngbe_ee_writew_buffer;
2035 rom->validate_checksum = ngbe_validate_eeprom_checksum_em;
2037 mac->mcft_size = NGBE_EM_MC_TBL_SIZE;
2038 mac->vft_size = NGBE_EM_VFT_TBL_SIZE;
2039 mac->num_rar_entries = NGBE_EM_RAR_ENTRIES;
2040 mac->rx_pb_size = NGBE_EM_RX_PB_SIZE;
2041 mac->max_rx_queues = NGBE_EM_MAX_RX_QUEUES;
2042 mac->max_tx_queues = NGBE_EM_MAX_TX_QUEUES;
2044 mac->default_speeds = NGBE_LINK_SPEED_10M_FULL |
2045 NGBE_LINK_SPEED_100M_FULL |
2046 NGBE_LINK_SPEED_1GB_FULL;
2052 * ngbe_init_shared_code - Initialize the shared code
2053 * @hw: pointer to hardware structure
2055 * This will assign function pointers and assign the MAC type and PHY code.
2056 * Does not touch the hardware. This function must be called prior to any
2057 * other function in the shared code. The ngbe_hw structure should be
2058 * memset to 0 prior to calling this function. The following fields in
2059 * hw structure should be filled in prior to calling this function:
2060 * hw_addr, back, device_id, vendor_id, subsystem_device_id
2062 s32 ngbe_init_shared_code(struct ngbe_hw *hw)
2066 DEBUGFUNC("ngbe_init_shared_code");
2071 ngbe_set_mac_type(hw);
2073 ngbe_init_ops_dummy(hw);
2074 switch (hw->mac.type) {
2076 ngbe_init_ops_pf(hw);
2079 status = NGBE_ERR_DEVICE_NOT_SUPPORTED;
2082 hw->mac.max_link_up_time = NGBE_LINK_UP_TIME;
2084 hw->bus.set_lan_id(hw);