1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
9 #include "ngbe_eeprom.h"
14 * ngbe_start_hw - Prepare hardware for Tx/Rx
15 * @hw: pointer to hardware structure
17 * Starts the hardware.
19 s32 ngbe_start_hw(struct ngbe_hw *hw)
21 DEBUGFUNC("ngbe_start_hw");
23 /* Clear the VLAN filter table */
24 hw->mac.clear_vfta(hw);
26 /* Clear statistics registers */
27 hw->mac.clear_hw_cntrs(hw);
29 /* Clear adapter stopped flag */
30 hw->adapter_stopped = false;
36 * ngbe_init_hw - Generic hardware initialization
37 * @hw: pointer to hardware structure
39 * Initialize the hardware by resetting the hardware, filling the bus info
40 * structure and media type, clears all on chip counters, initializes receive
41 * address registers, multicast table, VLAN filter table, calls routine to set
42 * up link and flow control settings, and leaves transmit and receive units
43 * disabled and uninitialized
45 s32 ngbe_init_hw(struct ngbe_hw *hw)
49 DEBUGFUNC("ngbe_init_hw");
51 ngbe_save_eeprom_version(hw);
53 /* Reset the hardware */
54 status = hw->mac.reset_hw(hw);
57 status = hw->mac.start_hw(hw);
61 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
67 ngbe_reset_misc_em(struct ngbe_hw *hw)
71 wr32(hw, NGBE_ISBADDRL, hw->isb_dma & 0xFFFFFFFF);
72 wr32(hw, NGBE_ISBADDRH, hw->isb_dma >> 32);
74 /* receive packets that size > 2048 */
75 wr32m(hw, NGBE_MACRXCFG,
76 NGBE_MACRXCFG_JUMBO, NGBE_MACRXCFG_JUMBO);
78 wr32m(hw, NGBE_FRMSZ, NGBE_FRMSZ_MAX_MASK,
79 NGBE_FRMSZ_MAX(NGBE_FRAME_SIZE_DFT));
81 /* clear counters on read */
82 wr32m(hw, NGBE_MACCNTCTL,
83 NGBE_MACCNTCTL_RC, NGBE_MACCNTCTL_RC);
85 wr32m(hw, NGBE_RXFCCFG,
86 NGBE_RXFCCFG_FC, NGBE_RXFCCFG_FC);
87 wr32m(hw, NGBE_TXFCCFG,
88 NGBE_TXFCCFG_FC, NGBE_TXFCCFG_FC);
90 wr32m(hw, NGBE_MACRXFLT,
91 NGBE_MACRXFLT_PROMISC, NGBE_MACRXFLT_PROMISC);
93 wr32m(hw, NGBE_RSTSTAT,
94 NGBE_RSTSTAT_TMRINIT_MASK, NGBE_RSTSTAT_TMRINIT(30));
96 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
97 wr32(hw, NGBE_MNGFLEXSEL, 0);
98 for (i = 0; i < 16; i++) {
99 wr32(hw, NGBE_MNGFLEXDWL(i), 0);
100 wr32(hw, NGBE_MNGFLEXDWH(i), 0);
101 wr32(hw, NGBE_MNGFLEXMSK(i), 0);
103 wr32(hw, NGBE_LANFLEXSEL, 0);
104 for (i = 0; i < 16; i++) {
105 wr32(hw, NGBE_LANFLEXDWL(i), 0);
106 wr32(hw, NGBE_LANFLEXDWH(i), 0);
107 wr32(hw, NGBE_LANFLEXMSK(i), 0);
110 /* set pause frame dst mac addr */
111 wr32(hw, NGBE_RXPBPFCDMACL, 0xC2000001);
112 wr32(hw, NGBE_RXPBPFCDMACH, 0x0180);
114 wr32(hw, NGBE_MDIOMODE, 0xF);
116 wr32m(hw, NGBE_GPIE, NGBE_GPIE_MSIX, NGBE_GPIE_MSIX);
118 if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
119 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
120 /* gpio0 is used to power on/off control*/
121 wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));
122 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);
125 hw->mac.init_thermal_sensor_thresh(hw);
127 /* enable mac transmitter */
128 wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_TE, NGBE_MACTXCFG_TE);
131 wr32m(hw, NGBE_MACTXCFG,
132 NGBE_MACTXCFG_SPEED_MASK, NGBE_MACTXCFG_SPEED_1G);
134 for (i = 0; i < 4; i++)
135 wr32m(hw, NGBE_IVAR(i), 0x80808080, 0);
139 * ngbe_reset_hw_em - Perform hardware reset
140 * @hw: pointer to hardware structure
142 * Resets the hardware by resetting the transmit and receive units, masks
143 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
146 s32 ngbe_reset_hw_em(struct ngbe_hw *hw)
150 DEBUGFUNC("ngbe_reset_hw_em");
152 /* Call adapter stop to disable tx/rx and clear interrupts */
153 status = hw->mac.stop_hw(hw);
157 /* Identify PHY and related function pointers */
158 status = ngbe_init_phy(hw);
163 if (!hw->phy.reset_disable)
164 hw->phy.reset_hw(hw);
166 wr32(hw, NGBE_RST, NGBE_RST_LAN(hw->bus.lan_id));
170 ngbe_reset_misc_em(hw);
171 hw->mac.clear_hw_cntrs(hw);
175 /* Store the permanent mac address */
176 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
179 * Store MAC address from RAR0, clear receive address registers, and
180 * clear the multicast table.
182 hw->mac.num_rar_entries = NGBE_EM_RAR_ENTRIES;
183 hw->mac.init_rx_addrs(hw);
189 * ngbe_clear_hw_cntrs - Generic clear hardware counters
190 * @hw: pointer to hardware structure
192 * Clears all hardware statistics counters by reading them from the hardware
193 * Statistics counters are clear on read.
195 s32 ngbe_clear_hw_cntrs(struct ngbe_hw *hw)
199 DEBUGFUNC("ngbe_clear_hw_cntrs");
202 /* don't write clear queue stats */
203 for (i = 0; i < NGBE_MAX_QP; i++) {
204 hw->qp_last[i].rx_qp_packets = 0;
205 hw->qp_last[i].tx_qp_packets = 0;
206 hw->qp_last[i].rx_qp_bytes = 0;
207 hw->qp_last[i].tx_qp_bytes = 0;
208 hw->qp_last[i].rx_qp_mc_packets = 0;
209 hw->qp_last[i].tx_qp_mc_packets = 0;
210 hw->qp_last[i].rx_qp_bc_packets = 0;
211 hw->qp_last[i].tx_qp_bc_packets = 0;
215 rd32(hw, NGBE_PBRXLNKXON);
216 rd32(hw, NGBE_PBRXLNKXOFF);
217 rd32(hw, NGBE_PBTXLNKXON);
218 rd32(hw, NGBE_PBTXLNKXOFF);
221 rd32(hw, NGBE_DMARXPKT);
222 rd32(hw, NGBE_DMATXPKT);
224 rd64(hw, NGBE_DMARXOCTL);
225 rd64(hw, NGBE_DMATXOCTL);
228 rd64(hw, NGBE_MACRXERRCRCL);
229 rd64(hw, NGBE_MACRXMPKTL);
230 rd64(hw, NGBE_MACTXMPKTL);
232 rd64(hw, NGBE_MACRXPKTL);
233 rd64(hw, NGBE_MACTXPKTL);
234 rd64(hw, NGBE_MACRXGBOCTL);
236 rd64(hw, NGBE_MACRXOCTL);
237 rd32(hw, NGBE_MACTXOCTL);
239 rd64(hw, NGBE_MACRX1TO64L);
240 rd64(hw, NGBE_MACRX65TO127L);
241 rd64(hw, NGBE_MACRX128TO255L);
242 rd64(hw, NGBE_MACRX256TO511L);
243 rd64(hw, NGBE_MACRX512TO1023L);
244 rd64(hw, NGBE_MACRX1024TOMAXL);
245 rd64(hw, NGBE_MACTX1TO64L);
246 rd64(hw, NGBE_MACTX65TO127L);
247 rd64(hw, NGBE_MACTX128TO255L);
248 rd64(hw, NGBE_MACTX256TO511L);
249 rd64(hw, NGBE_MACTX512TO1023L);
250 rd64(hw, NGBE_MACTX1024TOMAXL);
252 rd64(hw, NGBE_MACRXERRLENL);
253 rd32(hw, NGBE_MACRXOVERSIZE);
254 rd32(hw, NGBE_MACRXJABBER);
257 rd32(hw, NGBE_LSECTX_UTPKT);
258 rd32(hw, NGBE_LSECTX_ENCPKT);
259 rd32(hw, NGBE_LSECTX_PROTPKT);
260 rd32(hw, NGBE_LSECTX_ENCOCT);
261 rd32(hw, NGBE_LSECTX_PROTOCT);
262 rd32(hw, NGBE_LSECRX_UTPKT);
263 rd32(hw, NGBE_LSECRX_BTPKT);
264 rd32(hw, NGBE_LSECRX_NOSCIPKT);
265 rd32(hw, NGBE_LSECRX_UNSCIPKT);
266 rd32(hw, NGBE_LSECRX_DECOCT);
267 rd32(hw, NGBE_LSECRX_VLDOCT);
268 rd32(hw, NGBE_LSECRX_UNCHKPKT);
269 rd32(hw, NGBE_LSECRX_DLYPKT);
270 rd32(hw, NGBE_LSECRX_LATEPKT);
271 for (i = 0; i < 2; i++) {
272 rd32(hw, NGBE_LSECRX_OKPKT(i));
273 rd32(hw, NGBE_LSECRX_INVPKT(i));
274 rd32(hw, NGBE_LSECRX_BADPKT(i));
276 for (i = 0; i < 4; i++) {
277 rd32(hw, NGBE_LSECRX_INVSAPKT(i));
278 rd32(hw, NGBE_LSECRX_BADSAPKT(i));
285 * ngbe_get_mac_addr - Generic get MAC address
286 * @hw: pointer to hardware structure
287 * @mac_addr: Adapter MAC address
289 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
290 * A reset of the adapter must be performed prior to calling this function
291 * in order for the MAC address to have been loaded from the EEPROM into RAR0
293 s32 ngbe_get_mac_addr(struct ngbe_hw *hw, u8 *mac_addr)
299 DEBUGFUNC("ngbe_get_mac_addr");
301 wr32(hw, NGBE_ETHADDRIDX, 0);
302 rar_high = rd32(hw, NGBE_ETHADDRH);
303 rar_low = rd32(hw, NGBE_ETHADDRL);
305 for (i = 0; i < 2; i++)
306 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
308 for (i = 0; i < 4; i++)
309 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
315 * ngbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
316 * @hw: pointer to the HW structure
318 * Determines the LAN function id by reading memory-mapped registers and swaps
319 * the port value if requested, and set MAC instance for devices.
321 void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw)
323 struct ngbe_bus_info *bus = &hw->bus;
326 DEBUGFUNC("ngbe_set_lan_id_multi_port");
328 reg = rd32(hw, NGBE_PORTSTAT);
329 bus->lan_id = NGBE_PORTSTAT_ID(reg);
330 bus->func = bus->lan_id;
334 * ngbe_stop_hw - Generic stop Tx/Rx units
335 * @hw: pointer to hardware structure
337 * Sets the adapter_stopped flag within ngbe_hw struct. Clears interrupts,
338 * disables transmit and receive units. The adapter_stopped flag is used by
339 * the shared code and drivers to determine if the adapter is in a stopped
340 * state and should not touch the hardware.
342 s32 ngbe_stop_hw(struct ngbe_hw *hw)
347 DEBUGFUNC("ngbe_stop_hw");
350 * Set the adapter_stopped flag so other driver functions stop touching
353 hw->adapter_stopped = true;
355 /* Disable the receive unit */
358 /* Clear interrupt mask to stop interrupts from being generated */
359 wr32(hw, NGBE_IENMISC, 0);
360 wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK);
362 /* Clear any pending interrupts, flush previous writes */
363 wr32(hw, NGBE_ICRMISC, NGBE_ICRMISC_MASK);
364 wr32(hw, NGBE_ICR(0), NGBE_ICR_MASK);
366 /* Disable the transmit unit. Each queue must be disabled. */
367 for (i = 0; i < hw->mac.max_tx_queues; i++)
368 wr32(hw, NGBE_TXCFG(i), NGBE_TXCFG_FLUSH);
370 /* Disable the receive unit by stopping each queue */
371 for (i = 0; i < hw->mac.max_rx_queues; i++) {
372 reg_val = rd32(hw, NGBE_RXCFG(i));
373 reg_val &= ~NGBE_RXCFG_ENA;
374 wr32(hw, NGBE_RXCFG(i), reg_val);
377 /* flush all queues disables */
385 * ngbe_validate_mac_addr - Validate MAC address
386 * @mac_addr: pointer to MAC address.
388 * Tests a MAC address to ensure it is a valid Individual Address.
390 s32 ngbe_validate_mac_addr(u8 *mac_addr)
394 DEBUGFUNC("ngbe_validate_mac_addr");
396 /* Make sure it is not a multicast address */
397 if (NGBE_IS_MULTICAST((struct rte_ether_addr *)mac_addr)) {
398 status = NGBE_ERR_INVALID_MAC_ADDR;
399 /* Not a broadcast address */
400 } else if (NGBE_IS_BROADCAST((struct rte_ether_addr *)mac_addr)) {
401 status = NGBE_ERR_INVALID_MAC_ADDR;
402 /* Reject the zero address */
403 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
404 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
405 status = NGBE_ERR_INVALID_MAC_ADDR;
411 * ngbe_set_rar - Set Rx address register
412 * @hw: pointer to hardware structure
413 * @index: Receive address register to write
414 * @addr: Address to put into receive address register
415 * @vmdq: VMDq "set" or "pool" index
416 * @enable_addr: set flag that address is active
418 * Puts an ethernet address into a receive address register.
420 s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
423 u32 rar_low, rar_high;
424 u32 rar_entries = hw->mac.num_rar_entries;
426 DEBUGFUNC("ngbe_set_rar");
428 /* Make sure we are using a valid rar index range */
429 if (index >= rar_entries) {
430 DEBUGOUT("RAR index %d is out of range.\n", index);
431 return NGBE_ERR_INVALID_ARGUMENT;
434 /* setup VMDq pool selection before this RAR gets enabled */
435 hw->mac.set_vmdq(hw, index, vmdq);
438 * HW expects these in little endian so we reverse the byte
439 * order from network order (big endian) to little endian
441 rar_low = NGBE_ETHADDRL_AD0(addr[5]) |
442 NGBE_ETHADDRL_AD1(addr[4]) |
443 NGBE_ETHADDRL_AD2(addr[3]) |
444 NGBE_ETHADDRL_AD3(addr[2]);
446 * Some parts put the VMDq setting in the extra RAH bits,
447 * so save everything except the lower 16 bits that hold part
448 * of the address and the address valid bit.
450 rar_high = rd32(hw, NGBE_ETHADDRH);
451 rar_high &= ~NGBE_ETHADDRH_AD_MASK;
452 rar_high |= (NGBE_ETHADDRH_AD4(addr[1]) |
453 NGBE_ETHADDRH_AD5(addr[0]));
455 rar_high &= ~NGBE_ETHADDRH_VLD;
456 if (enable_addr != 0)
457 rar_high |= NGBE_ETHADDRH_VLD;
459 wr32(hw, NGBE_ETHADDRIDX, index);
460 wr32(hw, NGBE_ETHADDRL, rar_low);
461 wr32(hw, NGBE_ETHADDRH, rar_high);
467 * ngbe_clear_rar - Remove Rx address register
468 * @hw: pointer to hardware structure
469 * @index: Receive address register to write
471 * Clears an ethernet address from a receive address register.
473 s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index)
476 u32 rar_entries = hw->mac.num_rar_entries;
478 DEBUGFUNC("ngbe_clear_rar");
480 /* Make sure we are using a valid rar index range */
481 if (index >= rar_entries) {
482 DEBUGOUT("RAR index %d is out of range.\n", index);
483 return NGBE_ERR_INVALID_ARGUMENT;
487 * Some parts put the VMDq setting in the extra RAH bits,
488 * so save everything except the lower 16 bits that hold part
489 * of the address and the address valid bit.
491 wr32(hw, NGBE_ETHADDRIDX, index);
492 rar_high = rd32(hw, NGBE_ETHADDRH);
493 rar_high &= ~(NGBE_ETHADDRH_AD_MASK | NGBE_ETHADDRH_VLD);
495 wr32(hw, NGBE_ETHADDRL, 0);
496 wr32(hw, NGBE_ETHADDRH, rar_high);
498 /* clear VMDq pool/queue selection for this RAR */
499 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
505 * ngbe_init_rx_addrs - Initializes receive address filters.
506 * @hw: pointer to hardware structure
508 * Places the MAC address in receive address register 0 and clears the rest
509 * of the receive address registers. Clears the multicast table. Assumes
510 * the receiver is in reset when the routine is called.
512 s32 ngbe_init_rx_addrs(struct ngbe_hw *hw)
516 u32 rar_entries = hw->mac.num_rar_entries;
518 DEBUGFUNC("ngbe_init_rx_addrs");
521 * If the current mac address is valid, assume it is a software override
522 * to the permanent address.
523 * Otherwise, use the permanent address from the eeprom.
525 if (ngbe_validate_mac_addr(hw->mac.addr) ==
526 NGBE_ERR_INVALID_MAC_ADDR) {
527 /* Get the MAC address from the RAR0 for later reference */
528 hw->mac.get_mac_addr(hw, hw->mac.addr);
530 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
531 hw->mac.addr[0], hw->mac.addr[1],
533 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
534 hw->mac.addr[4], hw->mac.addr[5]);
536 /* Setup the receive address. */
537 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
538 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
539 hw->mac.addr[0], hw->mac.addr[1],
541 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
542 hw->mac.addr[4], hw->mac.addr[5]);
544 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
547 /* clear VMDq pool/queue selection for RAR 0 */
548 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
550 /* Zero out the other receive addresses. */
551 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
552 for (i = 1; i < rar_entries; i++) {
553 wr32(hw, NGBE_ETHADDRIDX, i);
554 wr32(hw, NGBE_ETHADDRL, 0);
555 wr32(hw, NGBE_ETHADDRH, 0);
559 hw->addr_ctrl.mta_in_use = 0;
560 psrctl = rd32(hw, NGBE_PSRCTL);
561 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
562 psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
563 wr32(hw, NGBE_PSRCTL, psrctl);
565 DEBUGOUT(" Clearing MTA\n");
566 for (i = 0; i < hw->mac.mcft_size; i++)
567 wr32(hw, NGBE_MCADDRTBL(i), 0);
569 ngbe_init_uta_tables(hw);
575 * ngbe_mta_vector - Determines bit-vector in multicast table to set
576 * @hw: pointer to hardware structure
577 * @mc_addr: the multicast address
579 * Extracts the 12 bits, from a multicast address, to determine which
580 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
581 * incoming rx multicast addresses, to determine the bit-vector to check in
582 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
583 * by the MO field of the PSRCTRL. The MO field is set during initialization
586 static s32 ngbe_mta_vector(struct ngbe_hw *hw, u8 *mc_addr)
590 DEBUGFUNC("ngbe_mta_vector");
592 switch (hw->mac.mc_filter_type) {
593 case 0: /* use bits [47:36] of the address */
594 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
596 case 1: /* use bits [46:35] of the address */
597 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
599 case 2: /* use bits [45:34] of the address */
600 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
602 case 3: /* use bits [43:32] of the address */
603 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
605 default: /* Invalid mc_filter_type */
606 DEBUGOUT("MC filter type param set incorrectly\n");
611 /* vector can only be 12-bits or boundary will be exceeded */
617 * ngbe_set_mta - Set bit-vector in multicast table
618 * @hw: pointer to hardware structure
619 * @mc_addr: Multicast address
621 * Sets the bit-vector in the multicast table.
623 void ngbe_set_mta(struct ngbe_hw *hw, u8 *mc_addr)
629 DEBUGFUNC("ngbe_set_mta");
631 hw->addr_ctrl.mta_in_use++;
633 vector = ngbe_mta_vector(hw, mc_addr);
634 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
637 * The MTA is a register array of 128 32-bit registers. It is treated
638 * like an array of 4096 bits. We want to set bit
639 * BitArray[vector_value]. So we figure out what register the bit is
640 * in, read it, OR in the new bit, then write back the new value. The
641 * register is determined by the upper 7 bits of the vector value and
642 * the bit within that register are determined by the lower 5 bits of
645 vector_reg = (vector >> 5) & 0x7F;
646 vector_bit = vector & 0x1F;
647 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
651 * ngbe_update_mc_addr_list - Updates MAC list of multicast addresses
652 * @hw: pointer to hardware structure
653 * @mc_addr_list: the list of new multicast addresses
654 * @mc_addr_count: number of addresses
655 * @next: iterator function to walk the multicast address list
656 * @clear: flag, when set clears the table beforehand
658 * When the clear flag is set, the given list replaces any existing list.
659 * Hashes the given addresses into the multicast table.
661 s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list,
662 u32 mc_addr_count, ngbe_mc_addr_itr next,
668 DEBUGFUNC("ngbe_update_mc_addr_list");
671 * Set the new number of MC addresses that we are being requested to
674 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
675 hw->addr_ctrl.mta_in_use = 0;
677 /* Clear mta_shadow */
679 DEBUGOUT(" Clearing MTA\n");
680 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
683 /* Update mta_shadow */
684 for (i = 0; i < mc_addr_count; i++) {
685 DEBUGOUT(" Adding the multicast addresses:\n");
686 ngbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
690 for (i = 0; i < hw->mac.mcft_size; i++)
691 wr32a(hw, NGBE_MCADDRTBL(0), i,
692 hw->mac.mta_shadow[i]);
694 if (hw->addr_ctrl.mta_in_use > 0) {
695 u32 psrctl = rd32(hw, NGBE_PSRCTL);
696 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
697 psrctl |= NGBE_PSRCTL_MCHFENA |
698 NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
699 wr32(hw, NGBE_PSRCTL, psrctl);
702 DEBUGOUT("ngbe update mc addr list complete\n");
707 * ngbe_acquire_swfw_sync - Acquire SWFW semaphore
708 * @hw: pointer to hardware structure
709 * @mask: Mask to specify which semaphore to acquire
711 * Acquires the SWFW semaphore through the MNGSEM register for the specified
712 * function (CSR, PHY0, PHY1, EEPROM, Flash)
714 s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask)
717 u32 swmask = NGBE_MNGSEM_SW(mask);
718 u32 fwmask = NGBE_MNGSEM_FW(mask);
722 DEBUGFUNC("ngbe_acquire_swfw_sync");
724 for (i = 0; i < timeout; i++) {
726 * SW NVM semaphore bit is used for access to all
727 * SW_FW_SYNC bits (not just NVM)
729 if (ngbe_get_eeprom_semaphore(hw))
730 return NGBE_ERR_SWFW_SYNC;
732 mngsem = rd32(hw, NGBE_MNGSEM);
733 if (mngsem & (fwmask | swmask)) {
734 /* Resource is currently in use by FW or SW */
735 ngbe_release_eeprom_semaphore(hw);
739 wr32(hw, NGBE_MNGSEM, mngsem);
740 ngbe_release_eeprom_semaphore(hw);
745 /* If time expired clear the bits holding the lock and retry */
746 if (mngsem & (fwmask | swmask))
747 ngbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
750 return NGBE_ERR_SWFW_SYNC;
754 * ngbe_release_swfw_sync - Release SWFW semaphore
755 * @hw: pointer to hardware structure
756 * @mask: Mask to specify which semaphore to release
758 * Releases the SWFW semaphore through the MNGSEM register for the specified
759 * function (CSR, PHY0, PHY1, EEPROM, Flash)
761 void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask)
766 DEBUGFUNC("ngbe_release_swfw_sync");
768 ngbe_get_eeprom_semaphore(hw);
770 mngsem = rd32(hw, NGBE_MNGSEM);
772 wr32(hw, NGBE_MNGSEM, mngsem);
774 ngbe_release_eeprom_semaphore(hw);
778 * ngbe_disable_sec_rx_path - Stops the receive data path
779 * @hw: pointer to hardware structure
781 * Stops the receive data path and waits for the HW to internally empty
782 * the Rx security block
784 s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw)
786 #define NGBE_MAX_SECRX_POLL 4000
791 DEBUGFUNC("ngbe_disable_sec_rx_path");
794 secrxreg = rd32(hw, NGBE_SECRXCTL);
795 secrxreg |= NGBE_SECRXCTL_XDSA;
796 wr32(hw, NGBE_SECRXCTL, secrxreg);
797 for (i = 0; i < NGBE_MAX_SECRX_POLL; i++) {
798 secrxreg = rd32(hw, NGBE_SECRXSTAT);
799 if (!(secrxreg & NGBE_SECRXSTAT_RDY))
800 /* Use interrupt-safe sleep just in case */
806 /* For informational purposes only */
807 if (i >= NGBE_MAX_SECRX_POLL)
808 DEBUGOUT("Rx unit being enabled before security "
809 "path fully disabled. Continuing with init.\n");
815 * ngbe_enable_sec_rx_path - Enables the receive data path
816 * @hw: pointer to hardware structure
818 * Enables the receive data path.
820 s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw)
824 DEBUGFUNC("ngbe_enable_sec_rx_path");
826 secrxreg = rd32(hw, NGBE_SECRXCTL);
827 secrxreg &= ~NGBE_SECRXCTL_XDSA;
828 wr32(hw, NGBE_SECRXCTL, secrxreg);
835 * ngbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
836 * @hw: pointer to hardware struct
837 * @rar: receive address register index to disassociate
838 * @vmdq: VMDq pool index to remove from the rar
840 s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
843 u32 rar_entries = hw->mac.num_rar_entries;
845 DEBUGFUNC("ngbe_clear_vmdq");
847 /* Make sure we are using a valid rar index range */
848 if (rar >= rar_entries) {
849 DEBUGOUT("RAR index %d is out of range.\n", rar);
850 return NGBE_ERR_INVALID_ARGUMENT;
853 wr32(hw, NGBE_ETHADDRIDX, rar);
854 mpsar = rd32(hw, NGBE_ETHADDRASS);
856 if (NGBE_REMOVED(hw->hw_addr))
862 mpsar &= ~(1 << vmdq);
863 wr32(hw, NGBE_ETHADDRASS, mpsar);
865 /* was that the last pool using this rar? */
866 if (mpsar == 0 && rar != 0)
867 hw->mac.clear_rar(hw, rar);
873 * ngbe_set_vmdq - Associate a VMDq pool index with a rx address
874 * @hw: pointer to hardware struct
875 * @rar: receive address register index to associate with a VMDq index
876 * @vmdq: VMDq pool index
878 s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
881 u32 rar_entries = hw->mac.num_rar_entries;
883 DEBUGFUNC("ngbe_set_vmdq");
885 /* Make sure we are using a valid rar index range */
886 if (rar >= rar_entries) {
887 DEBUGOUT("RAR index %d is out of range.\n", rar);
888 return NGBE_ERR_INVALID_ARGUMENT;
891 wr32(hw, NGBE_ETHADDRIDX, rar);
893 mpsar = rd32(hw, NGBE_ETHADDRASS);
895 wr32(hw, NGBE_ETHADDRASS, mpsar);
901 * ngbe_init_uta_tables - Initialize the Unicast Table Array
902 * @hw: pointer to hardware structure
904 s32 ngbe_init_uta_tables(struct ngbe_hw *hw)
908 DEBUGFUNC("ngbe_init_uta_tables");
909 DEBUGOUT(" Clearing UTA\n");
911 for (i = 0; i < 128; i++)
912 wr32(hw, NGBE_UCADDRTBL(i), 0);
918 * ngbe_clear_vfta - Clear VLAN filter table
919 * @hw: pointer to hardware structure
921 * Clears the VLAN filer table, and the VMDq index associated with the filter
923 s32 ngbe_clear_vfta(struct ngbe_hw *hw)
927 DEBUGFUNC("ngbe_clear_vfta");
929 for (offset = 0; offset < hw->mac.vft_size; offset++)
930 wr32(hw, NGBE_VLANTBL(offset), 0);
932 for (offset = 0; offset < NGBE_NUM_POOL; offset++) {
933 wr32(hw, NGBE_PSRVLANIDX, offset);
934 wr32(hw, NGBE_PSRVLAN, 0);
935 wr32(hw, NGBE_PSRVLANPLM(0), 0);
942 * ngbe_check_mac_link_em - Determine link and speed status
943 * @hw: pointer to hardware structure
944 * @speed: pointer to link speed
945 * @link_up: true when link is up
946 * @link_up_wait_to_complete: bool used to wait for link up or not
948 * Reads the links register to determine if link is up and the current speed
950 s32 ngbe_check_mac_link_em(struct ngbe_hw *hw, u32 *speed,
951 bool *link_up, bool link_up_wait_to_complete)
956 DEBUGFUNC("ngbe_check_mac_link_em");
958 reg = rd32(hw, NGBE_GPIOINTSTAT);
959 wr32(hw, NGBE_GPIOEOI, reg);
961 if (link_up_wait_to_complete) {
962 for (i = 0; i < hw->mac.max_link_up_time; i++) {
963 status = hw->phy.check_link(hw, speed, link_up);
969 status = hw->phy.check_link(hw, speed, link_up);
975 s32 ngbe_get_link_capabilities_em(struct ngbe_hw *hw,
983 hw->mac.autoneg = *autoneg;
985 switch (hw->sub_device_id) {
986 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
987 *speed = NGBE_LINK_SPEED_1GB_FULL |
988 NGBE_LINK_SPEED_100M_FULL |
989 NGBE_LINK_SPEED_10M_FULL;
998 s32 ngbe_setup_mac_link_em(struct ngbe_hw *hw,
1000 bool autoneg_wait_to_complete)
1006 /* Setup the PHY according to input speed */
1007 status = hw->phy.setup_link(hw, speed, autoneg_wait_to_complete);
1013 * ngbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
1014 * @hw: pointer to hardware structure
1015 * @enable: enable or disable switch for MAC anti-spoofing
1016 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
1019 void ngbe_set_mac_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf)
1023 pfvfspoof = rd32(hw, NGBE_POOLTXASMAC);
1025 pfvfspoof |= (1 << vf);
1027 pfvfspoof &= ~(1 << vf);
1028 wr32(hw, NGBE_POOLTXASMAC, pfvfspoof);
1032 * ngbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
1033 * @hw: pointer to hardware structure
1034 * @enable: enable or disable switch for VLAN anti-spoofing
1035 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
1038 void ngbe_set_vlan_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf)
1042 pfvfspoof = rd32(hw, NGBE_POOLTXASVLAN);
1044 pfvfspoof |= (1 << vf);
1046 pfvfspoof &= ~(1 << vf);
1047 wr32(hw, NGBE_POOLTXASVLAN, pfvfspoof);
1051 * ngbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1052 * @hw: pointer to hardware structure
1054 * Inits the thermal sensor thresholds according to the NVM map
1055 * and save off the threshold and location values into mac.thermal_sensor_data
1057 s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw)
1059 struct ngbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1061 DEBUGFUNC("ngbe_init_thermal_sensor_thresh");
1063 memset(data, 0, sizeof(struct ngbe_thermal_sensor_data));
1065 if (hw->bus.lan_id != 0)
1066 return NGBE_NOT_IMPLEMENTED;
1068 wr32(hw, NGBE_TSINTR,
1069 NGBE_TSINTR_AEN | NGBE_TSINTR_DEN);
1070 wr32(hw, NGBE_TSEN, NGBE_TSEN_ENA);
1073 data->sensor[0].alarm_thresh = 115;
1074 wr32(hw, NGBE_TSATHRE, 0x344);
1075 data->sensor[0].dalarm_thresh = 110;
1076 wr32(hw, NGBE_TSDTHRE, 0x330);
1081 s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw)
1086 DEBUGFUNC("ngbe_mac_check_overtemp");
1088 /* Check that the LASI temp alarm status was triggered */
1089 ts_state = rd32(hw, NGBE_TSALM);
1091 if (ts_state & NGBE_TSALM_HI)
1092 status = NGBE_ERR_UNDERTEMP;
1093 else if (ts_state & NGBE_TSALM_LO)
1094 status = NGBE_ERR_OVERTEMP;
1099 void ngbe_disable_rx(struct ngbe_hw *hw)
1103 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
1104 if (pfdtxgswc & NGBE_PSRCTL_LBENA) {
1105 pfdtxgswc &= ~NGBE_PSRCTL_LBENA;
1106 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
1107 hw->mac.set_lben = true;
1109 hw->mac.set_lben = false;
1112 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0);
1113 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, 0);
1116 void ngbe_enable_rx(struct ngbe_hw *hw)
1120 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, NGBE_MACRXCFG_ENA);
1121 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, NGBE_PBRXCTL_ENA);
1123 if (hw->mac.set_lben) {
1124 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
1125 pfdtxgswc |= NGBE_PSRCTL_LBENA;
1126 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
1127 hw->mac.set_lben = false;
1132 * ngbe_set_mac_type - Sets MAC type
1133 * @hw: pointer to the HW structure
1135 * This function sets the mac type of the adapter based on the
1136 * vendor ID and device ID stored in the hw structure.
1138 s32 ngbe_set_mac_type(struct ngbe_hw *hw)
1142 DEBUGFUNC("ngbe_set_mac_type");
1144 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
1145 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
1146 return NGBE_ERR_DEVICE_NOT_SUPPORTED;
1149 switch (hw->sub_device_id) {
1150 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
1151 case NGBE_SUB_DEV_ID_EM_MVL_RGMII:
1152 hw->phy.media_type = ngbe_media_type_copper;
1153 hw->mac.type = ngbe_mac_em;
1155 case NGBE_SUB_DEV_ID_EM_MVL_SFP:
1156 case NGBE_SUB_DEV_ID_EM_YT8521S_SFP:
1157 hw->phy.media_type = ngbe_media_type_fiber;
1158 hw->mac.type = ngbe_mac_em;
1160 case NGBE_SUB_DEV_ID_EM_VF:
1161 hw->phy.media_type = ngbe_media_type_virtual;
1162 hw->mac.type = ngbe_mac_em_vf;
1165 err = NGBE_ERR_DEVICE_NOT_SUPPORTED;
1166 hw->phy.media_type = ngbe_media_type_unknown;
1167 hw->mac.type = ngbe_mac_unknown;
1168 DEBUGOUT("Unsupported device id: %x", hw->device_id);
1172 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
1173 hw->mac.type, hw->phy.media_type, err);
1178 * ngbe_enable_rx_dma - Enable the Rx DMA unit
1179 * @hw: pointer to hardware structure
1180 * @regval: register value to write to RXCTRL
1182 * Enables the Rx DMA unit
1184 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)
1186 DEBUGFUNC("ngbe_enable_rx_dma");
1189 * Workaround silicon errata when enabling the Rx datapath.
1190 * If traffic is incoming before we enable the Rx unit, it could hang
1191 * the Rx DMA unit. Therefore, make sure the security engine is
1192 * completely disabled prior to enabling the Rx unit.
1195 hw->mac.disable_sec_rx_path(hw);
1197 if (regval & NGBE_PBRXCTL_ENA)
1200 ngbe_disable_rx(hw);
1202 hw->mac.enable_sec_rx_path(hw);
1207 void ngbe_map_device_id(struct ngbe_hw *hw)
1209 u16 oem = hw->sub_system_id & NGBE_OEM_MASK;
1210 u16 internal = hw->sub_system_id & NGBE_INTERNAL_MASK;
1213 /* move subsystem_device_id to device_id */
1214 switch (hw->device_id) {
1215 case NGBE_DEV_ID_EM_WX1860AL_W_VF:
1216 case NGBE_DEV_ID_EM_WX1860A2_VF:
1217 case NGBE_DEV_ID_EM_WX1860A2S_VF:
1218 case NGBE_DEV_ID_EM_WX1860A4_VF:
1219 case NGBE_DEV_ID_EM_WX1860A4S_VF:
1220 case NGBE_DEV_ID_EM_WX1860AL2_VF:
1221 case NGBE_DEV_ID_EM_WX1860AL2S_VF:
1222 case NGBE_DEV_ID_EM_WX1860AL4_VF:
1223 case NGBE_DEV_ID_EM_WX1860AL4S_VF:
1224 case NGBE_DEV_ID_EM_WX1860NCSI_VF:
1225 case NGBE_DEV_ID_EM_WX1860A1_VF:
1226 case NGBE_DEV_ID_EM_WX1860A1L_VF:
1227 hw->device_id = NGBE_DEV_ID_EM_VF;
1228 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_VF;
1231 case NGBE_DEV_ID_EM_WX1860AL_W:
1232 case NGBE_DEV_ID_EM_WX1860A2:
1233 case NGBE_DEV_ID_EM_WX1860A2S:
1234 case NGBE_DEV_ID_EM_WX1860A4:
1235 case NGBE_DEV_ID_EM_WX1860A4S:
1236 case NGBE_DEV_ID_EM_WX1860AL2:
1237 case NGBE_DEV_ID_EM_WX1860AL2S:
1238 case NGBE_DEV_ID_EM_WX1860AL4:
1239 case NGBE_DEV_ID_EM_WX1860AL4S:
1240 case NGBE_DEV_ID_EM_WX1860NCSI:
1241 case NGBE_DEV_ID_EM_WX1860A1:
1242 case NGBE_DEV_ID_EM_WX1860A1L:
1243 hw->device_id = NGBE_DEV_ID_EM;
1244 if (oem == NGBE_LY_M88E1512_SFP ||
1245 internal == NGBE_INTERNAL_SFP)
1246 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_SFP;
1247 else if (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45)
1248 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_RGMII;
1249 else if (oem == NGBE_YT8521S_SFP ||
1250 oem == NGBE_LY_YT8521S_SFP)
1251 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_YT8521S_SFP;
1253 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_SGMII;
1261 * ngbe_init_ops_pf - Inits func ptrs and MAC type
1262 * @hw: pointer to hardware structure
1264 * Initialize the function pointers and assign the MAC type.
1265 * Does not touch the hardware.
1267 s32 ngbe_init_ops_pf(struct ngbe_hw *hw)
1269 struct ngbe_bus_info *bus = &hw->bus;
1270 struct ngbe_mac_info *mac = &hw->mac;
1271 struct ngbe_phy_info *phy = &hw->phy;
1272 struct ngbe_rom_info *rom = &hw->rom;
1273 struct ngbe_mbx_info *mbx = &hw->mbx;
1275 DEBUGFUNC("ngbe_init_ops_pf");
1278 bus->set_lan_id = ngbe_set_lan_id_multi_port;
1281 phy->identify = ngbe_identify_phy;
1282 phy->read_reg = ngbe_read_phy_reg;
1283 phy->write_reg = ngbe_write_phy_reg;
1284 phy->read_reg_unlocked = ngbe_read_phy_reg_mdi;
1285 phy->write_reg_unlocked = ngbe_write_phy_reg_mdi;
1286 phy->reset_hw = ngbe_reset_phy;
1289 mac->init_hw = ngbe_init_hw;
1290 mac->reset_hw = ngbe_reset_hw_em;
1291 mac->start_hw = ngbe_start_hw;
1292 mac->clear_hw_cntrs = ngbe_clear_hw_cntrs;
1293 mac->enable_rx_dma = ngbe_enable_rx_dma;
1294 mac->get_mac_addr = ngbe_get_mac_addr;
1295 mac->stop_hw = ngbe_stop_hw;
1296 mac->acquire_swfw_sync = ngbe_acquire_swfw_sync;
1297 mac->release_swfw_sync = ngbe_release_swfw_sync;
1299 mac->disable_sec_rx_path = ngbe_disable_sec_rx_path;
1300 mac->enable_sec_rx_path = ngbe_enable_sec_rx_path;
1301 /* RAR, VLAN, Multicast */
1302 mac->set_rar = ngbe_set_rar;
1303 mac->clear_rar = ngbe_clear_rar;
1304 mac->init_rx_addrs = ngbe_init_rx_addrs;
1305 mac->update_mc_addr_list = ngbe_update_mc_addr_list;
1306 mac->set_vmdq = ngbe_set_vmdq;
1307 mac->clear_vmdq = ngbe_clear_vmdq;
1308 mac->clear_vfta = ngbe_clear_vfta;
1309 mac->set_mac_anti_spoofing = ngbe_set_mac_anti_spoofing;
1310 mac->set_vlan_anti_spoofing = ngbe_set_vlan_anti_spoofing;
1313 mac->get_link_capabilities = ngbe_get_link_capabilities_em;
1314 mac->check_link = ngbe_check_mac_link_em;
1315 mac->setup_link = ngbe_setup_mac_link_em;
1317 /* Manageability interface */
1318 mac->init_thermal_sensor_thresh = ngbe_init_thermal_sensor_thresh;
1319 mac->check_overtemp = ngbe_mac_check_overtemp;
1321 mbx->init_params = ngbe_init_mbx_params_pf;
1324 rom->init_params = ngbe_init_eeprom_params;
1325 rom->read32 = ngbe_ee_read32;
1326 rom->validate_checksum = ngbe_validate_eeprom_checksum_em;
1328 mac->mcft_size = NGBE_EM_MC_TBL_SIZE;
1329 mac->vft_size = NGBE_EM_VFT_TBL_SIZE;
1330 mac->num_rar_entries = NGBE_EM_RAR_ENTRIES;
1331 mac->max_rx_queues = NGBE_EM_MAX_RX_QUEUES;
1332 mac->max_tx_queues = NGBE_EM_MAX_TX_QUEUES;
1334 mac->default_speeds = NGBE_LINK_SPEED_10M_FULL |
1335 NGBE_LINK_SPEED_100M_FULL |
1336 NGBE_LINK_SPEED_1GB_FULL;
1342 * ngbe_init_shared_code - Initialize the shared code
1343 * @hw: pointer to hardware structure
1345 * This will assign function pointers and assign the MAC type and PHY code.
1346 * Does not touch the hardware. This function must be called prior to any
1347 * other function in the shared code. The ngbe_hw structure should be
1348 * memset to 0 prior to calling this function. The following fields in
1349 * hw structure should be filled in prior to calling this function:
1350 * hw_addr, back, device_id, vendor_id, subsystem_device_id
1352 s32 ngbe_init_shared_code(struct ngbe_hw *hw)
1356 DEBUGFUNC("ngbe_init_shared_code");
1361 ngbe_set_mac_type(hw);
1363 ngbe_init_ops_dummy(hw);
1364 switch (hw->mac.type) {
1366 ngbe_init_ops_pf(hw);
1369 status = NGBE_ERR_DEVICE_NOT_SUPPORTED;
1372 hw->mac.max_link_up_time = NGBE_LINK_UP_TIME;
1374 hw->bus.set_lan_id(hw);