1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
9 #include "ngbe_eeprom.h"
14 * ngbe_start_hw - Prepare hardware for Tx/Rx
15 * @hw: pointer to hardware structure
17 * Starts the hardware.
19 s32 ngbe_start_hw(struct ngbe_hw *hw)
23 DEBUGFUNC("ngbe_start_hw");
25 /* Clear the VLAN filter table */
26 hw->mac.clear_vfta(hw);
28 /* Clear statistics registers */
29 hw->mac.clear_hw_cntrs(hw);
31 /* Setup flow control */
32 err = hw->mac.setup_fc(hw);
33 if (err != 0 && err != NGBE_NOT_IMPLEMENTED) {
34 DEBUGOUT("Flow control setup failed, returning %d\n", err);
38 /* Clear adapter stopped flag */
39 hw->adapter_stopped = false;
45 * ngbe_init_hw - Generic hardware initialization
46 * @hw: pointer to hardware structure
48 * Initialize the hardware by resetting the hardware, filling the bus info
49 * structure and media type, clears all on chip counters, initializes receive
50 * address registers, multicast table, VLAN filter table, calls routine to set
51 * up link and flow control settings, and leaves transmit and receive units
52 * disabled and uninitialized
54 s32 ngbe_init_hw(struct ngbe_hw *hw)
58 DEBUGFUNC("ngbe_init_hw");
60 ngbe_save_eeprom_version(hw);
62 /* Reset the hardware */
63 status = hw->mac.reset_hw(hw);
66 status = hw->mac.start_hw(hw);
70 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
76 ngbe_reset_misc_em(struct ngbe_hw *hw)
80 wr32(hw, NGBE_ISBADDRL, hw->isb_dma & 0xFFFFFFFF);
81 wr32(hw, NGBE_ISBADDRH, hw->isb_dma >> 32);
83 /* receive packets that size > 2048 */
84 wr32m(hw, NGBE_MACRXCFG,
85 NGBE_MACRXCFG_JUMBO, NGBE_MACRXCFG_JUMBO);
87 wr32m(hw, NGBE_FRMSZ, NGBE_FRMSZ_MAX_MASK,
88 NGBE_FRMSZ_MAX(NGBE_FRAME_SIZE_DFT));
90 /* clear counters on read */
91 wr32m(hw, NGBE_MACCNTCTL,
92 NGBE_MACCNTCTL_RC, NGBE_MACCNTCTL_RC);
94 wr32m(hw, NGBE_RXFCCFG,
95 NGBE_RXFCCFG_FC, NGBE_RXFCCFG_FC);
96 wr32m(hw, NGBE_TXFCCFG,
97 NGBE_TXFCCFG_FC, NGBE_TXFCCFG_FC);
99 wr32m(hw, NGBE_MACRXFLT,
100 NGBE_MACRXFLT_PROMISC, NGBE_MACRXFLT_PROMISC);
102 wr32m(hw, NGBE_RSTSTAT,
103 NGBE_RSTSTAT_TMRINIT_MASK, NGBE_RSTSTAT_TMRINIT(30));
105 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
106 wr32(hw, NGBE_MNGFLEXSEL, 0);
107 for (i = 0; i < 16; i++) {
108 wr32(hw, NGBE_MNGFLEXDWL(i), 0);
109 wr32(hw, NGBE_MNGFLEXDWH(i), 0);
110 wr32(hw, NGBE_MNGFLEXMSK(i), 0);
112 wr32(hw, NGBE_LANFLEXSEL, 0);
113 for (i = 0; i < 16; i++) {
114 wr32(hw, NGBE_LANFLEXDWL(i), 0);
115 wr32(hw, NGBE_LANFLEXDWH(i), 0);
116 wr32(hw, NGBE_LANFLEXMSK(i), 0);
119 /* set pause frame dst mac addr */
120 wr32(hw, NGBE_RXPBPFCDMACL, 0xC2000001);
121 wr32(hw, NGBE_RXPBPFCDMACH, 0x0180);
123 wr32(hw, NGBE_MDIOMODE, 0xF);
125 wr32m(hw, NGBE_GPIE, NGBE_GPIE_MSIX, NGBE_GPIE_MSIX);
127 if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
128 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
129 /* gpio0 is used to power on/off control*/
130 wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));
131 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);
134 hw->mac.init_thermal_sensor_thresh(hw);
136 /* enable mac transmitter */
137 wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_TE, NGBE_MACTXCFG_TE);
140 wr32m(hw, NGBE_MACTXCFG,
141 NGBE_MACTXCFG_SPEED_MASK, NGBE_MACTXCFG_SPEED_1G);
143 for (i = 0; i < 4; i++)
144 wr32m(hw, NGBE_IVAR(i), 0x80808080, 0);
148 * ngbe_reset_hw_em - Perform hardware reset
149 * @hw: pointer to hardware structure
151 * Resets the hardware by resetting the transmit and receive units, masks
152 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
155 s32 ngbe_reset_hw_em(struct ngbe_hw *hw)
159 DEBUGFUNC("ngbe_reset_hw_em");
161 /* Call adapter stop to disable tx/rx and clear interrupts */
162 status = hw->mac.stop_hw(hw);
166 /* Identify PHY and related function pointers */
167 status = ngbe_init_phy(hw);
172 if (!hw->phy.reset_disable)
173 hw->phy.reset_hw(hw);
175 wr32(hw, NGBE_RST, NGBE_RST_LAN(hw->bus.lan_id));
179 ngbe_reset_misc_em(hw);
180 hw->mac.clear_hw_cntrs(hw);
184 /* Store the permanent mac address */
185 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
188 * Store MAC address from RAR0, clear receive address registers, and
189 * clear the multicast table.
191 hw->mac.num_rar_entries = NGBE_EM_RAR_ENTRIES;
192 hw->mac.init_rx_addrs(hw);
198 * ngbe_clear_hw_cntrs - Generic clear hardware counters
199 * @hw: pointer to hardware structure
201 * Clears all hardware statistics counters by reading them from the hardware
202 * Statistics counters are clear on read.
204 s32 ngbe_clear_hw_cntrs(struct ngbe_hw *hw)
208 DEBUGFUNC("ngbe_clear_hw_cntrs");
211 /* don't write clear queue stats */
212 for (i = 0; i < NGBE_MAX_QP; i++) {
213 hw->qp_last[i].rx_qp_packets = 0;
214 hw->qp_last[i].tx_qp_packets = 0;
215 hw->qp_last[i].rx_qp_bytes = 0;
216 hw->qp_last[i].tx_qp_bytes = 0;
217 hw->qp_last[i].rx_qp_mc_packets = 0;
218 hw->qp_last[i].tx_qp_mc_packets = 0;
219 hw->qp_last[i].rx_qp_bc_packets = 0;
220 hw->qp_last[i].tx_qp_bc_packets = 0;
224 rd32(hw, NGBE_PBRXLNKXON);
225 rd32(hw, NGBE_PBRXLNKXOFF);
226 rd32(hw, NGBE_PBTXLNKXON);
227 rd32(hw, NGBE_PBTXLNKXOFF);
230 rd32(hw, NGBE_DMARXPKT);
231 rd32(hw, NGBE_DMATXPKT);
233 rd64(hw, NGBE_DMARXOCTL);
234 rd64(hw, NGBE_DMATXOCTL);
237 rd64(hw, NGBE_MACRXERRCRCL);
238 rd64(hw, NGBE_MACRXMPKTL);
239 rd64(hw, NGBE_MACTXMPKTL);
241 rd64(hw, NGBE_MACRXPKTL);
242 rd64(hw, NGBE_MACTXPKTL);
243 rd64(hw, NGBE_MACRXGBOCTL);
245 rd64(hw, NGBE_MACRXOCTL);
246 rd32(hw, NGBE_MACTXOCTL);
248 rd64(hw, NGBE_MACRX1TO64L);
249 rd64(hw, NGBE_MACRX65TO127L);
250 rd64(hw, NGBE_MACRX128TO255L);
251 rd64(hw, NGBE_MACRX256TO511L);
252 rd64(hw, NGBE_MACRX512TO1023L);
253 rd64(hw, NGBE_MACRX1024TOMAXL);
254 rd64(hw, NGBE_MACTX1TO64L);
255 rd64(hw, NGBE_MACTX65TO127L);
256 rd64(hw, NGBE_MACTX128TO255L);
257 rd64(hw, NGBE_MACTX256TO511L);
258 rd64(hw, NGBE_MACTX512TO1023L);
259 rd64(hw, NGBE_MACTX1024TOMAXL);
261 rd64(hw, NGBE_MACRXERRLENL);
262 rd32(hw, NGBE_MACRXOVERSIZE);
263 rd32(hw, NGBE_MACRXJABBER);
266 rd32(hw, NGBE_LSECTX_UTPKT);
267 rd32(hw, NGBE_LSECTX_ENCPKT);
268 rd32(hw, NGBE_LSECTX_PROTPKT);
269 rd32(hw, NGBE_LSECTX_ENCOCT);
270 rd32(hw, NGBE_LSECTX_PROTOCT);
271 rd32(hw, NGBE_LSECRX_UTPKT);
272 rd32(hw, NGBE_LSECRX_BTPKT);
273 rd32(hw, NGBE_LSECRX_NOSCIPKT);
274 rd32(hw, NGBE_LSECRX_UNSCIPKT);
275 rd32(hw, NGBE_LSECRX_DECOCT);
276 rd32(hw, NGBE_LSECRX_VLDOCT);
277 rd32(hw, NGBE_LSECRX_UNCHKPKT);
278 rd32(hw, NGBE_LSECRX_DLYPKT);
279 rd32(hw, NGBE_LSECRX_LATEPKT);
280 for (i = 0; i < 2; i++) {
281 rd32(hw, NGBE_LSECRX_OKPKT(i));
282 rd32(hw, NGBE_LSECRX_INVPKT(i));
283 rd32(hw, NGBE_LSECRX_BADPKT(i));
285 for (i = 0; i < 4; i++) {
286 rd32(hw, NGBE_LSECRX_INVSAPKT(i));
287 rd32(hw, NGBE_LSECRX_BADSAPKT(i));
294 * ngbe_get_mac_addr - Generic get MAC address
295 * @hw: pointer to hardware structure
296 * @mac_addr: Adapter MAC address
298 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
299 * A reset of the adapter must be performed prior to calling this function
300 * in order for the MAC address to have been loaded from the EEPROM into RAR0
302 s32 ngbe_get_mac_addr(struct ngbe_hw *hw, u8 *mac_addr)
308 DEBUGFUNC("ngbe_get_mac_addr");
310 wr32(hw, NGBE_ETHADDRIDX, 0);
311 rar_high = rd32(hw, NGBE_ETHADDRH);
312 rar_low = rd32(hw, NGBE_ETHADDRL);
314 for (i = 0; i < 2; i++)
315 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
317 for (i = 0; i < 4; i++)
318 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
324 * ngbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
325 * @hw: pointer to the HW structure
327 * Determines the LAN function id by reading memory-mapped registers and swaps
328 * the port value if requested, and set MAC instance for devices.
330 void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw)
332 struct ngbe_bus_info *bus = &hw->bus;
335 DEBUGFUNC("ngbe_set_lan_id_multi_port");
337 reg = rd32(hw, NGBE_PORTSTAT);
338 bus->lan_id = NGBE_PORTSTAT_ID(reg);
339 bus->func = bus->lan_id;
343 * ngbe_stop_hw - Generic stop Tx/Rx units
344 * @hw: pointer to hardware structure
346 * Sets the adapter_stopped flag within ngbe_hw struct. Clears interrupts,
347 * disables transmit and receive units. The adapter_stopped flag is used by
348 * the shared code and drivers to determine if the adapter is in a stopped
349 * state and should not touch the hardware.
351 s32 ngbe_stop_hw(struct ngbe_hw *hw)
356 DEBUGFUNC("ngbe_stop_hw");
359 * Set the adapter_stopped flag so other driver functions stop touching
362 hw->adapter_stopped = true;
364 /* Disable the receive unit */
367 /* Clear interrupt mask to stop interrupts from being generated */
368 wr32(hw, NGBE_IENMISC, 0);
369 wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK);
371 /* Clear any pending interrupts, flush previous writes */
372 wr32(hw, NGBE_ICRMISC, NGBE_ICRMISC_MASK);
373 wr32(hw, NGBE_ICR(0), NGBE_ICR_MASK);
375 wr32(hw, NGBE_BMECTL, 0x3);
377 /* Disable the receive unit by stopping each queue */
378 for (i = 0; i < hw->mac.max_rx_queues; i++)
379 wr32(hw, NGBE_RXCFG(i), 0);
381 /* flush all queues disables */
386 * Prevent the PCI-E bus from hanging by disabling PCI-E master
387 * access and verify no pending requests
389 status = ngbe_set_pcie_master(hw, false);
393 /* Disable the transmit unit. Each queue must be disabled. */
394 for (i = 0; i < hw->mac.max_tx_queues; i++)
395 wr32(hw, NGBE_TXCFG(i), 0);
397 /* flush all queues disables */
405 * ngbe_led_on - Turns on the software controllable LEDs.
406 * @hw: pointer to hardware structure
407 * @index: led number to turn on
409 s32 ngbe_led_on(struct ngbe_hw *hw, u32 index)
411 u32 led_reg = rd32(hw, NGBE_LEDCTL);
413 DEBUGFUNC("ngbe_led_on");
416 return NGBE_ERR_PARAM;
418 /* To turn on the LED, set mode to ON. */
419 led_reg |= NGBE_LEDCTL_100M;
420 wr32(hw, NGBE_LEDCTL, led_reg);
427 * ngbe_led_off - Turns off the software controllable LEDs.
428 * @hw: pointer to hardware structure
429 * @index: led number to turn off
431 s32 ngbe_led_off(struct ngbe_hw *hw, u32 index)
433 u32 led_reg = rd32(hw, NGBE_LEDCTL);
435 DEBUGFUNC("ngbe_led_off");
438 return NGBE_ERR_PARAM;
440 /* To turn off the LED, set mode to OFF. */
441 led_reg &= ~NGBE_LEDCTL_100M;
442 wr32(hw, NGBE_LEDCTL, led_reg);
449 * ngbe_validate_mac_addr - Validate MAC address
450 * @mac_addr: pointer to MAC address.
452 * Tests a MAC address to ensure it is a valid Individual Address.
454 s32 ngbe_validate_mac_addr(u8 *mac_addr)
458 DEBUGFUNC("ngbe_validate_mac_addr");
460 /* Make sure it is not a multicast address */
461 if (NGBE_IS_MULTICAST((struct rte_ether_addr *)mac_addr)) {
462 status = NGBE_ERR_INVALID_MAC_ADDR;
463 /* Not a broadcast address */
464 } else if (NGBE_IS_BROADCAST((struct rte_ether_addr *)mac_addr)) {
465 status = NGBE_ERR_INVALID_MAC_ADDR;
466 /* Reject the zero address */
467 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
468 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
469 status = NGBE_ERR_INVALID_MAC_ADDR;
475 * ngbe_set_rar - Set Rx address register
476 * @hw: pointer to hardware structure
477 * @index: Receive address register to write
478 * @addr: Address to put into receive address register
479 * @vmdq: VMDq "set" or "pool" index
480 * @enable_addr: set flag that address is active
482 * Puts an ethernet address into a receive address register.
484 s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
487 u32 rar_low, rar_high;
488 u32 rar_entries = hw->mac.num_rar_entries;
490 DEBUGFUNC("ngbe_set_rar");
492 /* Make sure we are using a valid rar index range */
493 if (index >= rar_entries) {
494 DEBUGOUT("RAR index %d is out of range.\n", index);
495 return NGBE_ERR_INVALID_ARGUMENT;
498 /* setup VMDq pool selection before this RAR gets enabled */
499 hw->mac.set_vmdq(hw, index, vmdq);
502 * HW expects these in little endian so we reverse the byte
503 * order from network order (big endian) to little endian
505 rar_low = NGBE_ETHADDRL_AD0(addr[5]) |
506 NGBE_ETHADDRL_AD1(addr[4]) |
507 NGBE_ETHADDRL_AD2(addr[3]) |
508 NGBE_ETHADDRL_AD3(addr[2]);
510 * Some parts put the VMDq setting in the extra RAH bits,
511 * so save everything except the lower 16 bits that hold part
512 * of the address and the address valid bit.
514 rar_high = rd32(hw, NGBE_ETHADDRH);
515 rar_high &= ~NGBE_ETHADDRH_AD_MASK;
516 rar_high |= (NGBE_ETHADDRH_AD4(addr[1]) |
517 NGBE_ETHADDRH_AD5(addr[0]));
519 rar_high &= ~NGBE_ETHADDRH_VLD;
520 if (enable_addr != 0)
521 rar_high |= NGBE_ETHADDRH_VLD;
523 wr32(hw, NGBE_ETHADDRIDX, index);
524 wr32(hw, NGBE_ETHADDRL, rar_low);
525 wr32(hw, NGBE_ETHADDRH, rar_high);
531 * ngbe_clear_rar - Remove Rx address register
532 * @hw: pointer to hardware structure
533 * @index: Receive address register to write
535 * Clears an ethernet address from a receive address register.
537 s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index)
540 u32 rar_entries = hw->mac.num_rar_entries;
542 DEBUGFUNC("ngbe_clear_rar");
544 /* Make sure we are using a valid rar index range */
545 if (index >= rar_entries) {
546 DEBUGOUT("RAR index %d is out of range.\n", index);
547 return NGBE_ERR_INVALID_ARGUMENT;
551 * Some parts put the VMDq setting in the extra RAH bits,
552 * so save everything except the lower 16 bits that hold part
553 * of the address and the address valid bit.
555 wr32(hw, NGBE_ETHADDRIDX, index);
556 rar_high = rd32(hw, NGBE_ETHADDRH);
557 rar_high &= ~(NGBE_ETHADDRH_AD_MASK | NGBE_ETHADDRH_VLD);
559 wr32(hw, NGBE_ETHADDRL, 0);
560 wr32(hw, NGBE_ETHADDRH, rar_high);
562 /* clear VMDq pool/queue selection for this RAR */
563 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
569 * ngbe_init_rx_addrs - Initializes receive address filters.
570 * @hw: pointer to hardware structure
572 * Places the MAC address in receive address register 0 and clears the rest
573 * of the receive address registers. Clears the multicast table. Assumes
574 * the receiver is in reset when the routine is called.
576 s32 ngbe_init_rx_addrs(struct ngbe_hw *hw)
580 u32 rar_entries = hw->mac.num_rar_entries;
582 DEBUGFUNC("ngbe_init_rx_addrs");
585 * If the current mac address is valid, assume it is a software override
586 * to the permanent address.
587 * Otherwise, use the permanent address from the eeprom.
589 if (ngbe_validate_mac_addr(hw->mac.addr) ==
590 NGBE_ERR_INVALID_MAC_ADDR) {
591 /* Get the MAC address from the RAR0 for later reference */
592 hw->mac.get_mac_addr(hw, hw->mac.addr);
594 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
595 hw->mac.addr[0], hw->mac.addr[1],
597 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
598 hw->mac.addr[4], hw->mac.addr[5]);
600 /* Setup the receive address. */
601 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
602 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
603 hw->mac.addr[0], hw->mac.addr[1],
605 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
606 hw->mac.addr[4], hw->mac.addr[5]);
608 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
611 /* clear VMDq pool/queue selection for RAR 0 */
612 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
614 /* Zero out the other receive addresses. */
615 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
616 for (i = 1; i < rar_entries; i++) {
617 wr32(hw, NGBE_ETHADDRIDX, i);
618 wr32(hw, NGBE_ETHADDRL, 0);
619 wr32(hw, NGBE_ETHADDRH, 0);
623 hw->addr_ctrl.mta_in_use = 0;
624 psrctl = rd32(hw, NGBE_PSRCTL);
625 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
626 psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
627 wr32(hw, NGBE_PSRCTL, psrctl);
629 DEBUGOUT(" Clearing MTA\n");
630 for (i = 0; i < hw->mac.mcft_size; i++)
631 wr32(hw, NGBE_MCADDRTBL(i), 0);
633 ngbe_init_uta_tables(hw);
639 * ngbe_mta_vector - Determines bit-vector in multicast table to set
640 * @hw: pointer to hardware structure
641 * @mc_addr: the multicast address
643 * Extracts the 12 bits, from a multicast address, to determine which
644 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
645 * incoming rx multicast addresses, to determine the bit-vector to check in
646 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
647 * by the MO field of the PSRCTRL. The MO field is set during initialization
650 static s32 ngbe_mta_vector(struct ngbe_hw *hw, u8 *mc_addr)
654 DEBUGFUNC("ngbe_mta_vector");
656 switch (hw->mac.mc_filter_type) {
657 case 0: /* use bits [47:36] of the address */
658 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
660 case 1: /* use bits [46:35] of the address */
661 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
663 case 2: /* use bits [45:34] of the address */
664 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
666 case 3: /* use bits [43:32] of the address */
667 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
669 default: /* Invalid mc_filter_type */
670 DEBUGOUT("MC filter type param set incorrectly\n");
675 /* vector can only be 12-bits or boundary will be exceeded */
681 * ngbe_set_mta - Set bit-vector in multicast table
682 * @hw: pointer to hardware structure
683 * @mc_addr: Multicast address
685 * Sets the bit-vector in the multicast table.
687 void ngbe_set_mta(struct ngbe_hw *hw, u8 *mc_addr)
693 DEBUGFUNC("ngbe_set_mta");
695 hw->addr_ctrl.mta_in_use++;
697 vector = ngbe_mta_vector(hw, mc_addr);
698 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
701 * The MTA is a register array of 128 32-bit registers. It is treated
702 * like an array of 4096 bits. We want to set bit
703 * BitArray[vector_value]. So we figure out what register the bit is
704 * in, read it, OR in the new bit, then write back the new value. The
705 * register is determined by the upper 7 bits of the vector value and
706 * the bit within that register are determined by the lower 5 bits of
709 vector_reg = (vector >> 5) & 0x7F;
710 vector_bit = vector & 0x1F;
711 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
715 * ngbe_update_mc_addr_list - Updates MAC list of multicast addresses
716 * @hw: pointer to hardware structure
717 * @mc_addr_list: the list of new multicast addresses
718 * @mc_addr_count: number of addresses
719 * @next: iterator function to walk the multicast address list
720 * @clear: flag, when set clears the table beforehand
722 * When the clear flag is set, the given list replaces any existing list.
723 * Hashes the given addresses into the multicast table.
725 s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list,
726 u32 mc_addr_count, ngbe_mc_addr_itr next,
732 DEBUGFUNC("ngbe_update_mc_addr_list");
735 * Set the new number of MC addresses that we are being requested to
738 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
739 hw->addr_ctrl.mta_in_use = 0;
741 /* Clear mta_shadow */
743 DEBUGOUT(" Clearing MTA\n");
744 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
747 /* Update mta_shadow */
748 for (i = 0; i < mc_addr_count; i++) {
749 DEBUGOUT(" Adding the multicast addresses:\n");
750 ngbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
754 for (i = 0; i < hw->mac.mcft_size; i++)
755 wr32a(hw, NGBE_MCADDRTBL(0), i,
756 hw->mac.mta_shadow[i]);
758 if (hw->addr_ctrl.mta_in_use > 0) {
759 u32 psrctl = rd32(hw, NGBE_PSRCTL);
760 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
761 psrctl |= NGBE_PSRCTL_MCHFENA |
762 NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
763 wr32(hw, NGBE_PSRCTL, psrctl);
766 DEBUGOUT("ngbe update mc addr list complete\n");
771 * ngbe_setup_fc_em - Set up flow control
772 * @hw: pointer to hardware structure
774 * Called at init time to set up flow control.
776 s32 ngbe_setup_fc_em(struct ngbe_hw *hw)
781 DEBUGFUNC("ngbe_setup_fc");
783 /* Validate the requested mode */
784 if (hw->fc.strict_ieee && hw->fc.requested_mode == ngbe_fc_rx_pause) {
785 DEBUGOUT("ngbe_fc_rx_pause not valid in strict IEEE mode\n");
786 err = NGBE_ERR_INVALID_LINK_SETTINGS;
791 * 1gig parts do not have a word in the EEPROM to determine the
792 * default flow control setting, so we explicitly set it to full.
794 if (hw->fc.requested_mode == ngbe_fc_default)
795 hw->fc.requested_mode = ngbe_fc_full;
798 * The possible values of fc.requested_mode are:
799 * 0: Flow control is completely disabled
800 * 1: Rx flow control is enabled (we can receive pause frames,
801 * but not send pause frames).
802 * 2: Tx flow control is enabled (we can send pause frames but
803 * we do not support receiving pause frames).
804 * 3: Both Rx and Tx flow control (symmetric) are enabled.
807 switch (hw->fc.requested_mode) {
809 /* Flow control completely disabled by software override. */
811 case ngbe_fc_tx_pause:
813 * Tx Flow control is enabled, and Rx Flow control is
814 * disabled by software override.
816 if (hw->phy.type == ngbe_phy_mvl_sfi ||
817 hw->phy.type == ngbe_phy_yt8521s_sfi)
818 reg_cu |= MVL_FANA_ASM_PAUSE;
820 reg_cu |= 0x800; /*need to merge rtl and mvl on page 0*/
822 case ngbe_fc_rx_pause:
824 * Rx Flow control is enabled and Tx Flow control is
825 * disabled by software override. Since there really
826 * isn't a way to advertise that we are capable of RX
827 * Pause ONLY, we will advertise that we support both
828 * symmetric and asymmetric Rx PAUSE, as such we fall
829 * through to the fc_full statement. Later, we will
830 * disable the adapter's ability to send PAUSE frames.
833 /* Flow control (both Rx and Tx) is enabled by SW override. */
834 if (hw->phy.type == ngbe_phy_mvl_sfi ||
835 hw->phy.type == ngbe_phy_yt8521s_sfi)
836 reg_cu |= MVL_FANA_SYM_PAUSE;
838 reg_cu |= 0xC00; /*need to merge rtl and mvl on page 0*/
841 DEBUGOUT("Flow control param set incorrectly\n");
842 err = NGBE_ERR_CONFIG;
846 err = hw->phy.set_pause_adv(hw, reg_cu);
853 * ngbe_fc_enable - Enable flow control
854 * @hw: pointer to hardware structure
856 * Enable flow control according to the current settings.
858 s32 ngbe_fc_enable(struct ngbe_hw *hw)
861 u32 mflcn_reg, fccfg_reg;
865 DEBUGFUNC("ngbe_fc_enable");
867 /* Validate the water mark configuration */
868 if (!hw->fc.pause_time) {
869 err = NGBE_ERR_INVALID_LINK_SETTINGS;
873 /* Low water mark of zero causes XOFF floods */
874 if ((hw->fc.current_mode & ngbe_fc_tx_pause) && hw->fc.high_water) {
875 if (!hw->fc.low_water ||
876 hw->fc.low_water >= hw->fc.high_water) {
877 DEBUGOUT("Invalid water mark configuration\n");
878 err = NGBE_ERR_INVALID_LINK_SETTINGS;
883 /* Negotiate the fc mode to use */
884 hw->mac.fc_autoneg(hw);
886 /* Disable any previous flow control settings */
887 mflcn_reg = rd32(hw, NGBE_RXFCCFG);
888 mflcn_reg &= ~NGBE_RXFCCFG_FC;
890 fccfg_reg = rd32(hw, NGBE_TXFCCFG);
891 fccfg_reg &= ~NGBE_TXFCCFG_FC;
893 * The possible values of fc.current_mode are:
894 * 0: Flow control is completely disabled
895 * 1: Rx flow control is enabled (we can receive pause frames,
896 * but not send pause frames).
897 * 2: Tx flow control is enabled (we can send pause frames but
898 * we do not support receiving pause frames).
899 * 3: Both Rx and Tx flow control (symmetric) are enabled.
902 switch (hw->fc.current_mode) {
905 * Flow control is disabled by software override or autoneg.
906 * The code below will actually disable it in the HW.
909 case ngbe_fc_rx_pause:
911 * Rx Flow control is enabled and Tx Flow control is
912 * disabled by software override. Since there really
913 * isn't a way to advertise that we are capable of RX
914 * Pause ONLY, we will advertise that we support both
915 * symmetric and asymmetric Rx PAUSE. Later, we will
916 * disable the adapter's ability to send PAUSE frames.
918 mflcn_reg |= NGBE_RXFCCFG_FC;
920 case ngbe_fc_tx_pause:
922 * Tx Flow control is enabled, and Rx Flow control is
923 * disabled by software override.
925 fccfg_reg |= NGBE_TXFCCFG_FC;
928 /* Flow control (both Rx and Tx) is enabled by SW override. */
929 mflcn_reg |= NGBE_RXFCCFG_FC;
930 fccfg_reg |= NGBE_TXFCCFG_FC;
933 DEBUGOUT("Flow control param set incorrectly\n");
934 err = NGBE_ERR_CONFIG;
938 /* Set 802.3x based flow control settings. */
939 wr32(hw, NGBE_RXFCCFG, mflcn_reg);
940 wr32(hw, NGBE_TXFCCFG, fccfg_reg);
942 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
943 if ((hw->fc.current_mode & ngbe_fc_tx_pause) &&
945 fcrtl = NGBE_FCWTRLO_TH(hw->fc.low_water) |
947 fcrth = NGBE_FCWTRHI_TH(hw->fc.high_water) |
951 * In order to prevent Tx hangs when the internal Tx
952 * switch is enabled we must set the high water mark
953 * to the Rx packet buffer size - 24KB. This allows
954 * the Tx switch to function even under heavy Rx
958 fcrth = rd32(hw, NGBE_PBRXSIZE) - 24576;
960 wr32(hw, NGBE_FCWTRLO, fcrtl);
961 wr32(hw, NGBE_FCWTRHI, fcrth);
963 /* Configure pause time */
964 pause_time = NGBE_RXFCFSH_TIME(hw->fc.pause_time);
965 wr32(hw, NGBE_FCXOFFTM, pause_time * 0x00010000);
967 /* Configure flow control refresh threshold value */
968 wr32(hw, NGBE_RXFCRFSH, hw->fc.pause_time / 2);
975 * ngbe_negotiate_fc - Negotiate flow control
976 * @hw: pointer to hardware structure
977 * @adv_reg: flow control advertised settings
978 * @lp_reg: link partner's flow control settings
979 * @adv_sym: symmetric pause bit in advertisement
980 * @adv_asm: asymmetric pause bit in advertisement
981 * @lp_sym: symmetric pause bit in link partner advertisement
982 * @lp_asm: asymmetric pause bit in link partner advertisement
984 * Find the intersection between advertised settings and link partner's
985 * advertised settings
987 s32 ngbe_negotiate_fc(struct ngbe_hw *hw, u32 adv_reg, u32 lp_reg,
988 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
990 if ((!(adv_reg)) || (!(lp_reg))) {
991 DEBUGOUT("Local or link partner's advertised flow control "
992 "settings are NULL. Local: %x, link partner: %x\n",
994 return NGBE_ERR_FC_NOT_NEGOTIATED;
997 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
999 * Now we need to check if the user selected Rx ONLY
1000 * of pause frames. In this case, we had to advertise
1001 * FULL flow control because we could not advertise RX
1002 * ONLY. Hence, we must now check to see if we need to
1003 * turn OFF the TRANSMISSION of PAUSE frames.
1005 if (hw->fc.requested_mode == ngbe_fc_full) {
1006 hw->fc.current_mode = ngbe_fc_full;
1007 DEBUGOUT("Flow Control = FULL.\n");
1009 hw->fc.current_mode = ngbe_fc_rx_pause;
1010 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
1012 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1013 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1014 hw->fc.current_mode = ngbe_fc_tx_pause;
1015 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1016 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1017 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1018 hw->fc.current_mode = ngbe_fc_rx_pause;
1019 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1021 hw->fc.current_mode = ngbe_fc_none;
1022 DEBUGOUT("Flow Control = NONE.\n");
1028 * ngbe_fc_autoneg_em - Enable flow control IEEE clause 37
1029 * @hw: pointer to hardware structure
1031 * Enable flow control according to IEEE clause 37.
1033 STATIC s32 ngbe_fc_autoneg_em(struct ngbe_hw *hw)
1035 u8 technology_ability_reg = 0;
1036 u8 lp_technology_ability_reg = 0;
1038 hw->phy.get_adv_pause(hw, &technology_ability_reg);
1039 hw->phy.get_lp_adv_pause(hw, &lp_technology_ability_reg);
1041 return ngbe_negotiate_fc(hw, (u32)technology_ability_reg,
1042 (u32)lp_technology_ability_reg,
1043 NGBE_TAF_SYM_PAUSE, NGBE_TAF_ASM_PAUSE,
1044 NGBE_TAF_SYM_PAUSE, NGBE_TAF_ASM_PAUSE);
1048 * ngbe_fc_autoneg - Configure flow control
1049 * @hw: pointer to hardware structure
1051 * Compares our advertised flow control capabilities to those advertised by
1052 * our link partner, and determines the proper flow control mode to use.
1054 void ngbe_fc_autoneg(struct ngbe_hw *hw)
1056 s32 err = NGBE_ERR_FC_NOT_NEGOTIATED;
1060 DEBUGFUNC("ngbe_fc_autoneg");
1063 * AN should have completed when the cable was plugged in.
1064 * Look for reasons to bail out. Bail out if:
1065 * - FC autoneg is disabled, or if
1068 if (hw->fc.disable_fc_autoneg) {
1069 DEBUGOUT("Flow control autoneg is disabled");
1073 hw->mac.check_link(hw, &speed, &link_up, false);
1075 DEBUGOUT("The link is down");
1079 err = ngbe_fc_autoneg_em(hw);
1083 hw->fc.fc_was_autonegged = true;
1085 hw->fc.fc_was_autonegged = false;
1086 hw->fc.current_mode = hw->fc.requested_mode;
1091 * ngbe_set_pcie_master - Disable or Enable PCI-express master access
1092 * @hw: pointer to hardware structure
1094 * Disables PCI-Express master access and verifies there are no pending
1095 * requests. NGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1096 * bit hasn't caused the master requests to be disabled, else 0
1097 * is returned signifying master requests disabled.
1099 s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable)
1105 DEBUGFUNC("ngbe_set_pcie_master");
1107 ngbe_hic_pcie_read(hw, addr, &data, 4);
1113 ngbe_hic_pcie_write(hw, addr, &data, 4);
1118 /* Exit if master requests are blocked */
1119 if (!(rd32(hw, NGBE_BMEPEND)) ||
1120 NGBE_REMOVED(hw->hw_addr))
1123 /* Poll for master request bit to clear */
1124 for (i = 0; i < NGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
1126 if (!(rd32(hw, NGBE_BMEPEND)))
1130 DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
1131 status = NGBE_ERR_MASTER_REQUESTS_PENDING;
1138 * ngbe_acquire_swfw_sync - Acquire SWFW semaphore
1139 * @hw: pointer to hardware structure
1140 * @mask: Mask to specify which semaphore to acquire
1142 * Acquires the SWFW semaphore through the MNGSEM register for the specified
1143 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1145 s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask)
1148 u32 swmask = NGBE_MNGSEM_SW(mask);
1149 u32 fwmask = NGBE_MNGSEM_FW(mask);
1153 DEBUGFUNC("ngbe_acquire_swfw_sync");
1155 for (i = 0; i < timeout; i++) {
1157 * SW NVM semaphore bit is used for access to all
1158 * SW_FW_SYNC bits (not just NVM)
1160 if (ngbe_get_eeprom_semaphore(hw))
1161 return NGBE_ERR_SWFW_SYNC;
1163 mngsem = rd32(hw, NGBE_MNGSEM);
1164 if (mngsem & (fwmask | swmask)) {
1165 /* Resource is currently in use by FW or SW */
1166 ngbe_release_eeprom_semaphore(hw);
1170 wr32(hw, NGBE_MNGSEM, mngsem);
1171 ngbe_release_eeprom_semaphore(hw);
1176 /* If time expired clear the bits holding the lock and retry */
1177 if (mngsem & (fwmask | swmask))
1178 ngbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
1181 return NGBE_ERR_SWFW_SYNC;
1185 * ngbe_release_swfw_sync - Release SWFW semaphore
1186 * @hw: pointer to hardware structure
1187 * @mask: Mask to specify which semaphore to release
1189 * Releases the SWFW semaphore through the MNGSEM register for the specified
1190 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1192 void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask)
1197 DEBUGFUNC("ngbe_release_swfw_sync");
1199 ngbe_get_eeprom_semaphore(hw);
1201 mngsem = rd32(hw, NGBE_MNGSEM);
1203 wr32(hw, NGBE_MNGSEM, mngsem);
1205 ngbe_release_eeprom_semaphore(hw);
1209 * ngbe_disable_sec_rx_path - Stops the receive data path
1210 * @hw: pointer to hardware structure
1212 * Stops the receive data path and waits for the HW to internally empty
1213 * the Rx security block
1215 s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw)
1217 #define NGBE_MAX_SECRX_POLL 4000
1222 DEBUGFUNC("ngbe_disable_sec_rx_path");
1225 secrxreg = rd32(hw, NGBE_SECRXCTL);
1226 secrxreg |= NGBE_SECRXCTL_XDSA;
1227 wr32(hw, NGBE_SECRXCTL, secrxreg);
1228 for (i = 0; i < NGBE_MAX_SECRX_POLL; i++) {
1229 secrxreg = rd32(hw, NGBE_SECRXSTAT);
1230 if (!(secrxreg & NGBE_SECRXSTAT_RDY))
1231 /* Use interrupt-safe sleep just in case */
1237 /* For informational purposes only */
1238 if (i >= NGBE_MAX_SECRX_POLL)
1239 DEBUGOUT("Rx unit being enabled before security "
1240 "path fully disabled. Continuing with init.\n");
1246 * ngbe_enable_sec_rx_path - Enables the receive data path
1247 * @hw: pointer to hardware structure
1249 * Enables the receive data path.
1251 s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw)
1255 DEBUGFUNC("ngbe_enable_sec_rx_path");
1257 secrxreg = rd32(hw, NGBE_SECRXCTL);
1258 secrxreg &= ~NGBE_SECRXCTL_XDSA;
1259 wr32(hw, NGBE_SECRXCTL, secrxreg);
1266 * ngbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
1267 * @hw: pointer to hardware struct
1268 * @rar: receive address register index to disassociate
1269 * @vmdq: VMDq pool index to remove from the rar
1271 s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
1274 u32 rar_entries = hw->mac.num_rar_entries;
1276 DEBUGFUNC("ngbe_clear_vmdq");
1278 /* Make sure we are using a valid rar index range */
1279 if (rar >= rar_entries) {
1280 DEBUGOUT("RAR index %d is out of range.\n", rar);
1281 return NGBE_ERR_INVALID_ARGUMENT;
1284 wr32(hw, NGBE_ETHADDRIDX, rar);
1285 mpsar = rd32(hw, NGBE_ETHADDRASS);
1287 if (NGBE_REMOVED(hw->hw_addr))
1293 mpsar &= ~(1 << vmdq);
1294 wr32(hw, NGBE_ETHADDRASS, mpsar);
1296 /* was that the last pool using this rar? */
1297 if (mpsar == 0 && rar != 0)
1298 hw->mac.clear_rar(hw, rar);
1304 * ngbe_set_vmdq - Associate a VMDq pool index with a rx address
1305 * @hw: pointer to hardware struct
1306 * @rar: receive address register index to associate with a VMDq index
1307 * @vmdq: VMDq pool index
1309 s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
1312 u32 rar_entries = hw->mac.num_rar_entries;
1314 DEBUGFUNC("ngbe_set_vmdq");
1316 /* Make sure we are using a valid rar index range */
1317 if (rar >= rar_entries) {
1318 DEBUGOUT("RAR index %d is out of range.\n", rar);
1319 return NGBE_ERR_INVALID_ARGUMENT;
1322 wr32(hw, NGBE_ETHADDRIDX, rar);
1324 mpsar = rd32(hw, NGBE_ETHADDRASS);
1326 wr32(hw, NGBE_ETHADDRASS, mpsar);
1332 * ngbe_init_uta_tables - Initialize the Unicast Table Array
1333 * @hw: pointer to hardware structure
1335 s32 ngbe_init_uta_tables(struct ngbe_hw *hw)
1339 DEBUGFUNC("ngbe_init_uta_tables");
1340 DEBUGOUT(" Clearing UTA\n");
1342 for (i = 0; i < 128; i++)
1343 wr32(hw, NGBE_UCADDRTBL(i), 0);
1349 * ngbe_find_vlvf_slot - find the vlanid or the first empty slot
1350 * @hw: pointer to hardware structure
1351 * @vlan: VLAN id to write to VLAN filter
1352 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1356 * return the VLVF index where this VLAN id should be placed
1359 s32 ngbe_find_vlvf_slot(struct ngbe_hw *hw, u32 vlan, bool vlvf_bypass)
1361 s32 regindex, first_empty_slot;
1364 /* short cut the special case */
1368 /* if vlvf_bypass is set we don't want to use an empty slot, we
1369 * will simply bypass the VLVF if there are no entries present in the
1370 * VLVF that contain our VLAN
1372 first_empty_slot = vlvf_bypass ? NGBE_ERR_NO_SPACE : 0;
1374 /* add VLAN enable bit for comparison */
1375 vlan |= NGBE_PSRVLAN_EA;
1377 /* Search for the vlan id in the VLVF entries. Save off the first empty
1378 * slot found along the way.
1380 * pre-decrement loop covering (NGBE_NUM_POOL - 1) .. 1
1382 for (regindex = NGBE_NUM_POOL; --regindex;) {
1383 wr32(hw, NGBE_PSRVLANIDX, regindex);
1384 bits = rd32(hw, NGBE_PSRVLAN);
1387 if (!first_empty_slot && !bits)
1388 first_empty_slot = regindex;
1391 /* If we are here then we didn't find the VLAN. Return first empty
1392 * slot we found during our search, else error.
1394 if (!first_empty_slot)
1395 DEBUGOUT("No space in VLVF.\n");
1397 return first_empty_slot ? first_empty_slot : NGBE_ERR_NO_SPACE;
1401 * ngbe_set_vfta - Set VLAN filter table
1402 * @hw: pointer to hardware structure
1403 * @vlan: VLAN id to write to VLAN filter
1404 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1405 * @vlan_on: boolean flag to turn on/off VLAN
1406 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1408 * Turn on/off specified VLAN in the VLAN filter table.
1410 s32 ngbe_set_vfta(struct ngbe_hw *hw, u32 vlan, u32 vind,
1411 bool vlan_on, bool vlvf_bypass)
1413 u32 regidx, vfta_delta, vfta;
1416 DEBUGFUNC("ngbe_set_vfta");
1418 if (vlan > 4095 || vind > 63)
1419 return NGBE_ERR_PARAM;
1422 * this is a 2 part operation - first the VFTA, then the
1423 * VLVF and VLVFB if VT Mode is set
1424 * We don't write the VFTA until we know the VLVF part succeeded.
1428 * The VFTA is a bitstring made up of 128 32-bit registers
1429 * that enable the particular VLAN id, much like the MTA:
1430 * bits[11-5]: which register
1431 * bits[4-0]: which bit in the register
1434 vfta_delta = 1 << (vlan % 32);
1435 vfta = rd32(hw, NGBE_VLANTBL(regidx));
1438 * vfta_delta represents the difference between the current value
1439 * of vfta and the value we want in the register. Since the diff
1440 * is an XOR mask we can just update the vfta using an XOR
1442 vfta_delta &= vlan_on ? ~vfta : vfta;
1446 * Call ngbe_set_vlvf to set VLVFB and VLVF
1448 err = ngbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1457 /* Update VFTA now that we are ready for traffic */
1459 wr32(hw, NGBE_VLANTBL(regidx), vfta);
1465 * ngbe_set_vlvf - Set VLAN Pool Filter
1466 * @hw: pointer to hardware structure
1467 * @vlan: VLAN id to write to VLAN filter
1468 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1469 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1470 * @vfta_delta: pointer to the difference between the current value
1471 * of PSRVLANPLM and the desired value
1472 * @vfta: the desired value of the VFTA
1473 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1475 * Turn on/off specified bit in VLVF table.
1477 s32 ngbe_set_vlvf(struct ngbe_hw *hw, u32 vlan, u32 vind,
1478 bool vlan_on, u32 *vfta_delta, u32 vfta,
1485 DEBUGFUNC("ngbe_set_vlvf");
1487 if (vlan > 4095 || vind > 63)
1488 return NGBE_ERR_PARAM;
1490 /* If VT Mode is set
1492 * make sure the vlan is in PSRVLAN
1493 * set the vind bit in the matching PSRVLANPLM
1495 * clear the pool bit and possibly the vind
1497 portctl = rd32(hw, NGBE_PORTCTL);
1498 if (!(portctl & NGBE_PORTCTL_NUMVT_MASK))
1501 vlvf_index = ngbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1505 wr32(hw, NGBE_PSRVLANIDX, vlvf_index);
1506 bits = rd32(hw, NGBE_PSRVLANPLM(vind / 32));
1508 /* set the pool bit */
1509 bits |= 1 << (vind % 32);
1513 /* clear the pool bit */
1514 bits ^= 1 << (vind % 32);
1517 !rd32(hw, NGBE_PSRVLANPLM(vind / 32))) {
1518 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1519 * we run the risk of stray packets leaking into
1520 * the PF via the default pool
1523 wr32(hw, NGBE_PSRVLANPLM(vlan / 32), vfta);
1525 /* disable VLVF and clear remaining bit from pool */
1526 wr32(hw, NGBE_PSRVLAN, 0);
1527 wr32(hw, NGBE_PSRVLANPLM(vind / 32), 0);
1532 /* If there are still bits set in the PSRVLANPLM registers
1533 * for the VLAN ID indicated we need to see if the
1534 * caller is requesting that we clear the PSRVLANPLM entry bit.
1535 * If the caller has requested that we clear the PSRVLANPLM
1536 * entry bit but there are still pools/VFs using this VLAN
1537 * ID entry then ignore the request. We're not worried
1538 * about the case where we're turning the PSRVLANPLM VLAN ID
1539 * entry bit on, only when requested to turn it off as
1540 * there may be multiple pools and/or VFs using the
1541 * VLAN ID entry. In that case we cannot clear the
1542 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1543 * been cleared. This will be indicated by "bits" being
1549 /* record pool change and enable VLAN ID if not already enabled */
1550 wr32(hw, NGBE_PSRVLANPLM(vind / 32), bits);
1551 wr32(hw, NGBE_PSRVLAN, NGBE_PSRVLAN_EA | vlan);
1557 * ngbe_clear_vfta - Clear VLAN filter table
1558 * @hw: pointer to hardware structure
1560 * Clears the VLAN filer table, and the VMDq index associated with the filter
1562 s32 ngbe_clear_vfta(struct ngbe_hw *hw)
1566 DEBUGFUNC("ngbe_clear_vfta");
1568 for (offset = 0; offset < hw->mac.vft_size; offset++)
1569 wr32(hw, NGBE_VLANTBL(offset), 0);
1571 for (offset = 0; offset < NGBE_NUM_POOL; offset++) {
1572 wr32(hw, NGBE_PSRVLANIDX, offset);
1573 wr32(hw, NGBE_PSRVLAN, 0);
1574 wr32(hw, NGBE_PSRVLANPLM(0), 0);
1581 * ngbe_check_mac_link_em - Determine link and speed status
1582 * @hw: pointer to hardware structure
1583 * @speed: pointer to link speed
1584 * @link_up: true when link is up
1585 * @link_up_wait_to_complete: bool used to wait for link up or not
1587 * Reads the links register to determine if link is up and the current speed
1589 s32 ngbe_check_mac_link_em(struct ngbe_hw *hw, u32 *speed,
1590 bool *link_up, bool link_up_wait_to_complete)
1595 DEBUGFUNC("ngbe_check_mac_link_em");
1597 reg = rd32(hw, NGBE_GPIOINTSTAT);
1598 wr32(hw, NGBE_GPIOEOI, reg);
1600 if (link_up_wait_to_complete) {
1601 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1602 status = hw->phy.check_link(hw, speed, link_up);
1608 status = hw->phy.check_link(hw, speed, link_up);
1614 s32 ngbe_get_link_capabilities_em(struct ngbe_hw *hw,
1622 hw->mac.autoneg = *autoneg;
1624 switch (hw->sub_device_id) {
1625 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
1626 *speed = NGBE_LINK_SPEED_1GB_FULL |
1627 NGBE_LINK_SPEED_100M_FULL |
1628 NGBE_LINK_SPEED_10M_FULL;
1637 s32 ngbe_setup_mac_link_em(struct ngbe_hw *hw,
1639 bool autoneg_wait_to_complete)
1645 /* Setup the PHY according to input speed */
1646 status = hw->phy.setup_link(hw, speed, autoneg_wait_to_complete);
1652 * ngbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
1653 * @hw: pointer to hardware structure
1654 * @enable: enable or disable switch for MAC anti-spoofing
1655 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
1658 void ngbe_set_mac_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf)
1662 pfvfspoof = rd32(hw, NGBE_POOLTXASMAC);
1664 pfvfspoof |= (1 << vf);
1666 pfvfspoof &= ~(1 << vf);
1667 wr32(hw, NGBE_POOLTXASMAC, pfvfspoof);
1671 * ngbe_set_pba - Initialize Rx packet buffer
1672 * @hw: pointer to hardware structure
1673 * @headroom: reserve n KB of headroom
1675 void ngbe_set_pba(struct ngbe_hw *hw)
1677 u32 rxpktsize = hw->mac.rx_pb_size;
1678 u32 txpktsize, txpbthresh;
1680 /* Reserve 256 KB of headroom */
1684 wr32(hw, NGBE_PBRXSIZE, rxpktsize);
1686 /* Only support an equally distributed Tx packet buffer strategy. */
1687 txpktsize = NGBE_PBTXSIZE_MAX;
1688 txpbthresh = (txpktsize / 1024) - NGBE_TXPKT_SIZE_MAX;
1690 wr32(hw, NGBE_PBTXSIZE, txpktsize);
1691 wr32(hw, NGBE_PBTXDMATH, txpbthresh);
1695 * ngbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
1696 * @hw: pointer to hardware structure
1697 * @enable: enable or disable switch for VLAN anti-spoofing
1698 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
1701 void ngbe_set_vlan_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf)
1705 pfvfspoof = rd32(hw, NGBE_POOLTXASVLAN);
1707 pfvfspoof |= (1 << vf);
1709 pfvfspoof &= ~(1 << vf);
1710 wr32(hw, NGBE_POOLTXASVLAN, pfvfspoof);
1714 * ngbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1715 * @hw: pointer to hardware structure
1717 * Inits the thermal sensor thresholds according to the NVM map
1718 * and save off the threshold and location values into mac.thermal_sensor_data
1720 s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw)
1722 struct ngbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1724 DEBUGFUNC("ngbe_init_thermal_sensor_thresh");
1726 memset(data, 0, sizeof(struct ngbe_thermal_sensor_data));
1728 if (hw->bus.lan_id != 0)
1729 return NGBE_NOT_IMPLEMENTED;
1731 wr32(hw, NGBE_TSINTR,
1732 NGBE_TSINTR_AEN | NGBE_TSINTR_DEN);
1733 wr32(hw, NGBE_TSEN, NGBE_TSEN_ENA);
1736 data->sensor[0].alarm_thresh = 115;
1737 wr32(hw, NGBE_TSATHRE, 0x344);
1738 data->sensor[0].dalarm_thresh = 110;
1739 wr32(hw, NGBE_TSDTHRE, 0x330);
1744 s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw)
1749 DEBUGFUNC("ngbe_mac_check_overtemp");
1751 /* Check that the LASI temp alarm status was triggered */
1752 ts_state = rd32(hw, NGBE_TSALM);
1754 if (ts_state & NGBE_TSALM_HI)
1755 status = NGBE_ERR_UNDERTEMP;
1756 else if (ts_state & NGBE_TSALM_LO)
1757 status = NGBE_ERR_OVERTEMP;
1762 void ngbe_disable_rx(struct ngbe_hw *hw)
1766 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
1767 if (pfdtxgswc & NGBE_PSRCTL_LBENA) {
1768 pfdtxgswc &= ~NGBE_PSRCTL_LBENA;
1769 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
1770 hw->mac.set_lben = true;
1772 hw->mac.set_lben = false;
1775 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0);
1776 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, 0);
1779 void ngbe_enable_rx(struct ngbe_hw *hw)
1783 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, NGBE_MACRXCFG_ENA);
1784 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, NGBE_PBRXCTL_ENA);
1786 if (hw->mac.set_lben) {
1787 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
1788 pfdtxgswc |= NGBE_PSRCTL_LBENA;
1789 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
1790 hw->mac.set_lben = false;
1795 * ngbe_set_mac_type - Sets MAC type
1796 * @hw: pointer to the HW structure
1798 * This function sets the mac type of the adapter based on the
1799 * vendor ID and device ID stored in the hw structure.
1801 s32 ngbe_set_mac_type(struct ngbe_hw *hw)
1805 DEBUGFUNC("ngbe_set_mac_type");
1807 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
1808 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
1809 return NGBE_ERR_DEVICE_NOT_SUPPORTED;
1812 switch (hw->sub_device_id) {
1813 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
1814 case NGBE_SUB_DEV_ID_EM_MVL_RGMII:
1815 hw->phy.media_type = ngbe_media_type_copper;
1816 hw->mac.type = ngbe_mac_em;
1818 case NGBE_SUB_DEV_ID_EM_MVL_SFP:
1819 case NGBE_SUB_DEV_ID_EM_YT8521S_SFP:
1820 hw->phy.media_type = ngbe_media_type_fiber;
1821 hw->mac.type = ngbe_mac_em;
1823 case NGBE_SUB_DEV_ID_EM_VF:
1824 hw->phy.media_type = ngbe_media_type_virtual;
1825 hw->mac.type = ngbe_mac_em_vf;
1828 err = NGBE_ERR_DEVICE_NOT_SUPPORTED;
1829 hw->phy.media_type = ngbe_media_type_unknown;
1830 hw->mac.type = ngbe_mac_unknown;
1831 DEBUGOUT("Unsupported device id: %x", hw->device_id);
1835 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
1836 hw->mac.type, hw->phy.media_type, err);
1841 * ngbe_enable_rx_dma - Enable the Rx DMA unit
1842 * @hw: pointer to hardware structure
1843 * @regval: register value to write to RXCTRL
1845 * Enables the Rx DMA unit
1847 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)
1849 DEBUGFUNC("ngbe_enable_rx_dma");
1852 * Workaround silicon errata when enabling the Rx datapath.
1853 * If traffic is incoming before we enable the Rx unit, it could hang
1854 * the Rx DMA unit. Therefore, make sure the security engine is
1855 * completely disabled prior to enabling the Rx unit.
1858 hw->mac.disable_sec_rx_path(hw);
1860 if (regval & NGBE_PBRXCTL_ENA)
1863 ngbe_disable_rx(hw);
1865 hw->mac.enable_sec_rx_path(hw);
1870 void ngbe_map_device_id(struct ngbe_hw *hw)
1872 u16 oem = hw->sub_system_id & NGBE_OEM_MASK;
1873 u16 internal = hw->sub_system_id & NGBE_INTERNAL_MASK;
1876 /* move subsystem_device_id to device_id */
1877 switch (hw->device_id) {
1878 case NGBE_DEV_ID_EM_WX1860AL_W_VF:
1879 case NGBE_DEV_ID_EM_WX1860A2_VF:
1880 case NGBE_DEV_ID_EM_WX1860A2S_VF:
1881 case NGBE_DEV_ID_EM_WX1860A4_VF:
1882 case NGBE_DEV_ID_EM_WX1860A4S_VF:
1883 case NGBE_DEV_ID_EM_WX1860AL2_VF:
1884 case NGBE_DEV_ID_EM_WX1860AL2S_VF:
1885 case NGBE_DEV_ID_EM_WX1860AL4_VF:
1886 case NGBE_DEV_ID_EM_WX1860AL4S_VF:
1887 case NGBE_DEV_ID_EM_WX1860NCSI_VF:
1888 case NGBE_DEV_ID_EM_WX1860A1_VF:
1889 case NGBE_DEV_ID_EM_WX1860A1L_VF:
1890 hw->device_id = NGBE_DEV_ID_EM_VF;
1891 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_VF;
1894 case NGBE_DEV_ID_EM_WX1860AL_W:
1895 case NGBE_DEV_ID_EM_WX1860A2:
1896 case NGBE_DEV_ID_EM_WX1860A2S:
1897 case NGBE_DEV_ID_EM_WX1860A4:
1898 case NGBE_DEV_ID_EM_WX1860A4S:
1899 case NGBE_DEV_ID_EM_WX1860AL2:
1900 case NGBE_DEV_ID_EM_WX1860AL2S:
1901 case NGBE_DEV_ID_EM_WX1860AL4:
1902 case NGBE_DEV_ID_EM_WX1860AL4S:
1903 case NGBE_DEV_ID_EM_WX1860NCSI:
1904 case NGBE_DEV_ID_EM_WX1860A1:
1905 case NGBE_DEV_ID_EM_WX1860A1L:
1906 hw->device_id = NGBE_DEV_ID_EM;
1907 if (oem == NGBE_LY_M88E1512_SFP ||
1908 internal == NGBE_INTERNAL_SFP)
1909 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_SFP;
1910 else if (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45)
1911 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_RGMII;
1912 else if (oem == NGBE_YT8521S_SFP ||
1913 oem == NGBE_LY_YT8521S_SFP)
1914 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_YT8521S_SFP;
1916 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_SGMII;
1924 * ngbe_init_ops_pf - Inits func ptrs and MAC type
1925 * @hw: pointer to hardware structure
1927 * Initialize the function pointers and assign the MAC type.
1928 * Does not touch the hardware.
1930 s32 ngbe_init_ops_pf(struct ngbe_hw *hw)
1932 struct ngbe_bus_info *bus = &hw->bus;
1933 struct ngbe_mac_info *mac = &hw->mac;
1934 struct ngbe_phy_info *phy = &hw->phy;
1935 struct ngbe_rom_info *rom = &hw->rom;
1936 struct ngbe_mbx_info *mbx = &hw->mbx;
1938 DEBUGFUNC("ngbe_init_ops_pf");
1941 bus->set_lan_id = ngbe_set_lan_id_multi_port;
1944 phy->identify = ngbe_identify_phy;
1945 phy->read_reg = ngbe_read_phy_reg;
1946 phy->write_reg = ngbe_write_phy_reg;
1947 phy->read_reg_unlocked = ngbe_read_phy_reg_mdi;
1948 phy->write_reg_unlocked = ngbe_write_phy_reg_mdi;
1949 phy->reset_hw = ngbe_reset_phy;
1952 mac->init_hw = ngbe_init_hw;
1953 mac->reset_hw = ngbe_reset_hw_em;
1954 mac->start_hw = ngbe_start_hw;
1955 mac->clear_hw_cntrs = ngbe_clear_hw_cntrs;
1956 mac->enable_rx_dma = ngbe_enable_rx_dma;
1957 mac->get_mac_addr = ngbe_get_mac_addr;
1958 mac->stop_hw = ngbe_stop_hw;
1959 mac->acquire_swfw_sync = ngbe_acquire_swfw_sync;
1960 mac->release_swfw_sync = ngbe_release_swfw_sync;
1962 mac->disable_sec_rx_path = ngbe_disable_sec_rx_path;
1963 mac->enable_sec_rx_path = ngbe_enable_sec_rx_path;
1966 mac->led_on = ngbe_led_on;
1967 mac->led_off = ngbe_led_off;
1969 /* RAR, VLAN, Multicast */
1970 mac->set_rar = ngbe_set_rar;
1971 mac->clear_rar = ngbe_clear_rar;
1972 mac->init_rx_addrs = ngbe_init_rx_addrs;
1973 mac->update_mc_addr_list = ngbe_update_mc_addr_list;
1974 mac->set_vmdq = ngbe_set_vmdq;
1975 mac->clear_vmdq = ngbe_clear_vmdq;
1976 mac->set_vfta = ngbe_set_vfta;
1977 mac->set_vlvf = ngbe_set_vlvf;
1978 mac->clear_vfta = ngbe_clear_vfta;
1979 mac->set_mac_anti_spoofing = ngbe_set_mac_anti_spoofing;
1980 mac->set_vlan_anti_spoofing = ngbe_set_vlan_anti_spoofing;
1983 mac->fc_enable = ngbe_fc_enable;
1984 mac->fc_autoneg = ngbe_fc_autoneg;
1985 mac->setup_fc = ngbe_setup_fc_em;
1988 mac->get_link_capabilities = ngbe_get_link_capabilities_em;
1989 mac->check_link = ngbe_check_mac_link_em;
1990 mac->setup_link = ngbe_setup_mac_link_em;
1992 mac->setup_pba = ngbe_set_pba;
1994 /* Manageability interface */
1995 mac->init_thermal_sensor_thresh = ngbe_init_thermal_sensor_thresh;
1996 mac->check_overtemp = ngbe_mac_check_overtemp;
1998 mbx->init_params = ngbe_init_mbx_params_pf;
1999 mbx->read = ngbe_read_mbx_pf;
2000 mbx->write = ngbe_write_mbx_pf;
2001 mbx->check_for_msg = ngbe_check_for_msg_pf;
2002 mbx->check_for_ack = ngbe_check_for_ack_pf;
2003 mbx->check_for_rst = ngbe_check_for_rst_pf;
2006 rom->init_params = ngbe_init_eeprom_params;
2007 rom->readw_buffer = ngbe_ee_readw_buffer;
2008 rom->read32 = ngbe_ee_read32;
2009 rom->writew_buffer = ngbe_ee_writew_buffer;
2010 rom->validate_checksum = ngbe_validate_eeprom_checksum_em;
2012 mac->mcft_size = NGBE_EM_MC_TBL_SIZE;
2013 mac->vft_size = NGBE_EM_VFT_TBL_SIZE;
2014 mac->num_rar_entries = NGBE_EM_RAR_ENTRIES;
2015 mac->rx_pb_size = NGBE_EM_RX_PB_SIZE;
2016 mac->max_rx_queues = NGBE_EM_MAX_RX_QUEUES;
2017 mac->max_tx_queues = NGBE_EM_MAX_TX_QUEUES;
2019 mac->default_speeds = NGBE_LINK_SPEED_10M_FULL |
2020 NGBE_LINK_SPEED_100M_FULL |
2021 NGBE_LINK_SPEED_1GB_FULL;
2027 * ngbe_init_shared_code - Initialize the shared code
2028 * @hw: pointer to hardware structure
2030 * This will assign function pointers and assign the MAC type and PHY code.
2031 * Does not touch the hardware. This function must be called prior to any
2032 * other function in the shared code. The ngbe_hw structure should be
2033 * memset to 0 prior to calling this function. The following fields in
2034 * hw structure should be filled in prior to calling this function:
2035 * hw_addr, back, device_id, vendor_id, subsystem_device_id
2037 s32 ngbe_init_shared_code(struct ngbe_hw *hw)
2041 DEBUGFUNC("ngbe_init_shared_code");
2046 ngbe_set_mac_type(hw);
2048 ngbe_init_ops_dummy(hw);
2049 switch (hw->mac.type) {
2051 ngbe_init_ops_pf(hw);
2054 status = NGBE_ERR_DEVICE_NOT_SUPPORTED;
2057 hw->mac.max_link_up_time = NGBE_LINK_UP_TIME;
2059 hw->bus.set_lan_id(hw);