1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
8 #include "ngbe_eeprom.h"
13 * ngbe_start_hw - Prepare hardware for Tx/Rx
14 * @hw: pointer to hardware structure
16 * Starts the hardware.
18 s32 ngbe_start_hw(struct ngbe_hw *hw)
20 DEBUGFUNC("ngbe_start_hw");
22 /* Clear the VLAN filter table */
23 hw->mac.clear_vfta(hw);
25 /* Clear statistics registers */
26 hw->mac.clear_hw_cntrs(hw);
28 /* Clear adapter stopped flag */
29 hw->adapter_stopped = false;
35 * ngbe_init_hw - Generic hardware initialization
36 * @hw: pointer to hardware structure
38 * Initialize the hardware by resetting the hardware, filling the bus info
39 * structure and media type, clears all on chip counters, initializes receive
40 * address registers, multicast table, VLAN filter table, calls routine to set
41 * up link and flow control settings, and leaves transmit and receive units
42 * disabled and uninitialized
44 s32 ngbe_init_hw(struct ngbe_hw *hw)
48 DEBUGFUNC("ngbe_init_hw");
50 ngbe_save_eeprom_version(hw);
52 /* Reset the hardware */
53 status = hw->mac.reset_hw(hw);
56 status = hw->mac.start_hw(hw);
60 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
66 ngbe_reset_misc_em(struct ngbe_hw *hw)
70 wr32(hw, NGBE_ISBADDRL, hw->isb_dma & 0xFFFFFFFF);
71 wr32(hw, NGBE_ISBADDRH, hw->isb_dma >> 32);
73 /* receive packets that size > 2048 */
74 wr32m(hw, NGBE_MACRXCFG,
75 NGBE_MACRXCFG_JUMBO, NGBE_MACRXCFG_JUMBO);
77 wr32m(hw, NGBE_FRMSZ, NGBE_FRMSZ_MAX_MASK,
78 NGBE_FRMSZ_MAX(NGBE_FRAME_SIZE_DFT));
80 /* clear counters on read */
81 wr32m(hw, NGBE_MACCNTCTL,
82 NGBE_MACCNTCTL_RC, NGBE_MACCNTCTL_RC);
84 wr32m(hw, NGBE_RXFCCFG,
85 NGBE_RXFCCFG_FC, NGBE_RXFCCFG_FC);
86 wr32m(hw, NGBE_TXFCCFG,
87 NGBE_TXFCCFG_FC, NGBE_TXFCCFG_FC);
89 wr32m(hw, NGBE_MACRXFLT,
90 NGBE_MACRXFLT_PROMISC, NGBE_MACRXFLT_PROMISC);
92 wr32m(hw, NGBE_RSTSTAT,
93 NGBE_RSTSTAT_TMRINIT_MASK, NGBE_RSTSTAT_TMRINIT(30));
95 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
96 wr32(hw, NGBE_MNGFLEXSEL, 0);
97 for (i = 0; i < 16; i++) {
98 wr32(hw, NGBE_MNGFLEXDWL(i), 0);
99 wr32(hw, NGBE_MNGFLEXDWH(i), 0);
100 wr32(hw, NGBE_MNGFLEXMSK(i), 0);
102 wr32(hw, NGBE_LANFLEXSEL, 0);
103 for (i = 0; i < 16; i++) {
104 wr32(hw, NGBE_LANFLEXDWL(i), 0);
105 wr32(hw, NGBE_LANFLEXDWH(i), 0);
106 wr32(hw, NGBE_LANFLEXMSK(i), 0);
109 /* set pause frame dst mac addr */
110 wr32(hw, NGBE_RXPBPFCDMACL, 0xC2000001);
111 wr32(hw, NGBE_RXPBPFCDMACH, 0x0180);
113 wr32(hw, NGBE_MDIOMODE, 0xF);
115 wr32m(hw, NGBE_GPIE, NGBE_GPIE_MSIX, NGBE_GPIE_MSIX);
117 if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
118 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
119 /* gpio0 is used to power on/off control*/
120 wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));
121 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);
124 hw->mac.init_thermal_sensor_thresh(hw);
126 /* enable mac transmitter */
127 wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_TE, NGBE_MACTXCFG_TE);
130 wr32m(hw, NGBE_MACTXCFG,
131 NGBE_MACTXCFG_SPEED_MASK, NGBE_MACTXCFG_SPEED_1G);
133 for (i = 0; i < 4; i++)
134 wr32m(hw, NGBE_IVAR(i), 0x80808080, 0);
138 * ngbe_reset_hw_em - Perform hardware reset
139 * @hw: pointer to hardware structure
141 * Resets the hardware by resetting the transmit and receive units, masks
142 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
145 s32 ngbe_reset_hw_em(struct ngbe_hw *hw)
149 DEBUGFUNC("ngbe_reset_hw_em");
151 /* Call adapter stop to disable tx/rx and clear interrupts */
152 status = hw->mac.stop_hw(hw);
156 /* Identify PHY and related function pointers */
157 status = ngbe_init_phy(hw);
162 if (!hw->phy.reset_disable)
163 hw->phy.reset_hw(hw);
165 wr32(hw, NGBE_RST, NGBE_RST_LAN(hw->bus.lan_id));
169 ngbe_reset_misc_em(hw);
170 hw->mac.clear_hw_cntrs(hw);
174 /* Store the permanent mac address */
175 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
178 * Store MAC address from RAR0, clear receive address registers, and
179 * clear the multicast table.
181 hw->mac.num_rar_entries = NGBE_EM_RAR_ENTRIES;
182 hw->mac.init_rx_addrs(hw);
188 * ngbe_clear_hw_cntrs - Generic clear hardware counters
189 * @hw: pointer to hardware structure
191 * Clears all hardware statistics counters by reading them from the hardware
192 * Statistics counters are clear on read.
194 s32 ngbe_clear_hw_cntrs(struct ngbe_hw *hw)
198 DEBUGFUNC("ngbe_clear_hw_cntrs");
201 /* don't write clear queue stats */
202 for (i = 0; i < NGBE_MAX_QP; i++) {
203 hw->qp_last[i].rx_qp_packets = 0;
204 hw->qp_last[i].tx_qp_packets = 0;
205 hw->qp_last[i].rx_qp_bytes = 0;
206 hw->qp_last[i].tx_qp_bytes = 0;
207 hw->qp_last[i].rx_qp_mc_packets = 0;
208 hw->qp_last[i].tx_qp_mc_packets = 0;
209 hw->qp_last[i].rx_qp_bc_packets = 0;
210 hw->qp_last[i].tx_qp_bc_packets = 0;
214 rd32(hw, NGBE_PBRXLNKXON);
215 rd32(hw, NGBE_PBRXLNKXOFF);
216 rd32(hw, NGBE_PBTXLNKXON);
217 rd32(hw, NGBE_PBTXLNKXOFF);
220 rd32(hw, NGBE_DMARXPKT);
221 rd32(hw, NGBE_DMATXPKT);
223 rd64(hw, NGBE_DMARXOCTL);
224 rd64(hw, NGBE_DMATXOCTL);
227 rd64(hw, NGBE_MACRXERRCRCL);
228 rd64(hw, NGBE_MACRXMPKTL);
229 rd64(hw, NGBE_MACTXMPKTL);
231 rd64(hw, NGBE_MACRXPKTL);
232 rd64(hw, NGBE_MACTXPKTL);
233 rd64(hw, NGBE_MACRXGBOCTL);
235 rd64(hw, NGBE_MACRXOCTL);
236 rd32(hw, NGBE_MACTXOCTL);
238 rd64(hw, NGBE_MACRX1TO64L);
239 rd64(hw, NGBE_MACRX65TO127L);
240 rd64(hw, NGBE_MACRX128TO255L);
241 rd64(hw, NGBE_MACRX256TO511L);
242 rd64(hw, NGBE_MACRX512TO1023L);
243 rd64(hw, NGBE_MACRX1024TOMAXL);
244 rd64(hw, NGBE_MACTX1TO64L);
245 rd64(hw, NGBE_MACTX65TO127L);
246 rd64(hw, NGBE_MACTX128TO255L);
247 rd64(hw, NGBE_MACTX256TO511L);
248 rd64(hw, NGBE_MACTX512TO1023L);
249 rd64(hw, NGBE_MACTX1024TOMAXL);
251 rd64(hw, NGBE_MACRXERRLENL);
252 rd32(hw, NGBE_MACRXOVERSIZE);
253 rd32(hw, NGBE_MACRXJABBER);
256 rd32(hw, NGBE_LSECTX_UTPKT);
257 rd32(hw, NGBE_LSECTX_ENCPKT);
258 rd32(hw, NGBE_LSECTX_PROTPKT);
259 rd32(hw, NGBE_LSECTX_ENCOCT);
260 rd32(hw, NGBE_LSECTX_PROTOCT);
261 rd32(hw, NGBE_LSECRX_UTPKT);
262 rd32(hw, NGBE_LSECRX_BTPKT);
263 rd32(hw, NGBE_LSECRX_NOSCIPKT);
264 rd32(hw, NGBE_LSECRX_UNSCIPKT);
265 rd32(hw, NGBE_LSECRX_DECOCT);
266 rd32(hw, NGBE_LSECRX_VLDOCT);
267 rd32(hw, NGBE_LSECRX_UNCHKPKT);
268 rd32(hw, NGBE_LSECRX_DLYPKT);
269 rd32(hw, NGBE_LSECRX_LATEPKT);
270 for (i = 0; i < 2; i++) {
271 rd32(hw, NGBE_LSECRX_OKPKT(i));
272 rd32(hw, NGBE_LSECRX_INVPKT(i));
273 rd32(hw, NGBE_LSECRX_BADPKT(i));
275 for (i = 0; i < 4; i++) {
276 rd32(hw, NGBE_LSECRX_INVSAPKT(i));
277 rd32(hw, NGBE_LSECRX_BADSAPKT(i));
284 * ngbe_get_mac_addr - Generic get MAC address
285 * @hw: pointer to hardware structure
286 * @mac_addr: Adapter MAC address
288 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
289 * A reset of the adapter must be performed prior to calling this function
290 * in order for the MAC address to have been loaded from the EEPROM into RAR0
292 s32 ngbe_get_mac_addr(struct ngbe_hw *hw, u8 *mac_addr)
298 DEBUGFUNC("ngbe_get_mac_addr");
300 wr32(hw, NGBE_ETHADDRIDX, 0);
301 rar_high = rd32(hw, NGBE_ETHADDRH);
302 rar_low = rd32(hw, NGBE_ETHADDRL);
304 for (i = 0; i < 2; i++)
305 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
307 for (i = 0; i < 4; i++)
308 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
314 * ngbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
315 * @hw: pointer to the HW structure
317 * Determines the LAN function id by reading memory-mapped registers and swaps
318 * the port value if requested, and set MAC instance for devices.
320 void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw)
322 struct ngbe_bus_info *bus = &hw->bus;
325 DEBUGFUNC("ngbe_set_lan_id_multi_port");
327 reg = rd32(hw, NGBE_PORTSTAT);
328 bus->lan_id = NGBE_PORTSTAT_ID(reg);
329 bus->func = bus->lan_id;
333 * ngbe_stop_hw - Generic stop Tx/Rx units
334 * @hw: pointer to hardware structure
336 * Sets the adapter_stopped flag within ngbe_hw struct. Clears interrupts,
337 * disables transmit and receive units. The adapter_stopped flag is used by
338 * the shared code and drivers to determine if the adapter is in a stopped
339 * state and should not touch the hardware.
341 s32 ngbe_stop_hw(struct ngbe_hw *hw)
346 DEBUGFUNC("ngbe_stop_hw");
349 * Set the adapter_stopped flag so other driver functions stop touching
352 hw->adapter_stopped = true;
354 /* Disable the receive unit */
357 /* Clear interrupt mask to stop interrupts from being generated */
358 wr32(hw, NGBE_IENMISC, 0);
359 wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK);
361 /* Clear any pending interrupts, flush previous writes */
362 wr32(hw, NGBE_ICRMISC, NGBE_ICRMISC_MASK);
363 wr32(hw, NGBE_ICR(0), NGBE_ICR_MASK);
365 /* Disable the transmit unit. Each queue must be disabled. */
366 for (i = 0; i < hw->mac.max_tx_queues; i++)
367 wr32(hw, NGBE_TXCFG(i), NGBE_TXCFG_FLUSH);
369 /* Disable the receive unit by stopping each queue */
370 for (i = 0; i < hw->mac.max_rx_queues; i++) {
371 reg_val = rd32(hw, NGBE_RXCFG(i));
372 reg_val &= ~NGBE_RXCFG_ENA;
373 wr32(hw, NGBE_RXCFG(i), reg_val);
376 /* flush all queues disables */
384 * ngbe_validate_mac_addr - Validate MAC address
385 * @mac_addr: pointer to MAC address.
387 * Tests a MAC address to ensure it is a valid Individual Address.
389 s32 ngbe_validate_mac_addr(u8 *mac_addr)
393 DEBUGFUNC("ngbe_validate_mac_addr");
395 /* Make sure it is not a multicast address */
396 if (NGBE_IS_MULTICAST((struct rte_ether_addr *)mac_addr)) {
397 status = NGBE_ERR_INVALID_MAC_ADDR;
398 /* Not a broadcast address */
399 } else if (NGBE_IS_BROADCAST((struct rte_ether_addr *)mac_addr)) {
400 status = NGBE_ERR_INVALID_MAC_ADDR;
401 /* Reject the zero address */
402 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
403 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
404 status = NGBE_ERR_INVALID_MAC_ADDR;
410 * ngbe_set_rar - Set Rx address register
411 * @hw: pointer to hardware structure
412 * @index: Receive address register to write
413 * @addr: Address to put into receive address register
414 * @vmdq: VMDq "set" or "pool" index
415 * @enable_addr: set flag that address is active
417 * Puts an ethernet address into a receive address register.
419 s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
422 u32 rar_low, rar_high;
423 u32 rar_entries = hw->mac.num_rar_entries;
425 DEBUGFUNC("ngbe_set_rar");
427 /* Make sure we are using a valid rar index range */
428 if (index >= rar_entries) {
429 DEBUGOUT("RAR index %d is out of range.\n", index);
430 return NGBE_ERR_INVALID_ARGUMENT;
433 /* setup VMDq pool selection before this RAR gets enabled */
434 hw->mac.set_vmdq(hw, index, vmdq);
437 * HW expects these in little endian so we reverse the byte
438 * order from network order (big endian) to little endian
440 rar_low = NGBE_ETHADDRL_AD0(addr[5]) |
441 NGBE_ETHADDRL_AD1(addr[4]) |
442 NGBE_ETHADDRL_AD2(addr[3]) |
443 NGBE_ETHADDRL_AD3(addr[2]);
445 * Some parts put the VMDq setting in the extra RAH bits,
446 * so save everything except the lower 16 bits that hold part
447 * of the address and the address valid bit.
449 rar_high = rd32(hw, NGBE_ETHADDRH);
450 rar_high &= ~NGBE_ETHADDRH_AD_MASK;
451 rar_high |= (NGBE_ETHADDRH_AD4(addr[1]) |
452 NGBE_ETHADDRH_AD5(addr[0]));
454 rar_high &= ~NGBE_ETHADDRH_VLD;
455 if (enable_addr != 0)
456 rar_high |= NGBE_ETHADDRH_VLD;
458 wr32(hw, NGBE_ETHADDRIDX, index);
459 wr32(hw, NGBE_ETHADDRL, rar_low);
460 wr32(hw, NGBE_ETHADDRH, rar_high);
466 * ngbe_clear_rar - Remove Rx address register
467 * @hw: pointer to hardware structure
468 * @index: Receive address register to write
470 * Clears an ethernet address from a receive address register.
472 s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index)
475 u32 rar_entries = hw->mac.num_rar_entries;
477 DEBUGFUNC("ngbe_clear_rar");
479 /* Make sure we are using a valid rar index range */
480 if (index >= rar_entries) {
481 DEBUGOUT("RAR index %d is out of range.\n", index);
482 return NGBE_ERR_INVALID_ARGUMENT;
486 * Some parts put the VMDq setting in the extra RAH bits,
487 * so save everything except the lower 16 bits that hold part
488 * of the address and the address valid bit.
490 wr32(hw, NGBE_ETHADDRIDX, index);
491 rar_high = rd32(hw, NGBE_ETHADDRH);
492 rar_high &= ~(NGBE_ETHADDRH_AD_MASK | NGBE_ETHADDRH_VLD);
494 wr32(hw, NGBE_ETHADDRL, 0);
495 wr32(hw, NGBE_ETHADDRH, rar_high);
497 /* clear VMDq pool/queue selection for this RAR */
498 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
504 * ngbe_init_rx_addrs - Initializes receive address filters.
505 * @hw: pointer to hardware structure
507 * Places the MAC address in receive address register 0 and clears the rest
508 * of the receive address registers. Clears the multicast table. Assumes
509 * the receiver is in reset when the routine is called.
511 s32 ngbe_init_rx_addrs(struct ngbe_hw *hw)
515 u32 rar_entries = hw->mac.num_rar_entries;
517 DEBUGFUNC("ngbe_init_rx_addrs");
520 * If the current mac address is valid, assume it is a software override
521 * to the permanent address.
522 * Otherwise, use the permanent address from the eeprom.
524 if (ngbe_validate_mac_addr(hw->mac.addr) ==
525 NGBE_ERR_INVALID_MAC_ADDR) {
526 /* Get the MAC address from the RAR0 for later reference */
527 hw->mac.get_mac_addr(hw, hw->mac.addr);
529 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
530 hw->mac.addr[0], hw->mac.addr[1],
532 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
533 hw->mac.addr[4], hw->mac.addr[5]);
535 /* Setup the receive address. */
536 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
537 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
538 hw->mac.addr[0], hw->mac.addr[1],
540 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
541 hw->mac.addr[4], hw->mac.addr[5]);
543 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
546 /* clear VMDq pool/queue selection for RAR 0 */
547 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
549 /* Zero out the other receive addresses. */
550 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
551 for (i = 1; i < rar_entries; i++) {
552 wr32(hw, NGBE_ETHADDRIDX, i);
553 wr32(hw, NGBE_ETHADDRL, 0);
554 wr32(hw, NGBE_ETHADDRH, 0);
558 hw->addr_ctrl.mta_in_use = 0;
559 psrctl = rd32(hw, NGBE_PSRCTL);
560 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
561 psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
562 wr32(hw, NGBE_PSRCTL, psrctl);
564 DEBUGOUT(" Clearing MTA\n");
565 for (i = 0; i < hw->mac.mcft_size; i++)
566 wr32(hw, NGBE_MCADDRTBL(i), 0);
568 ngbe_init_uta_tables(hw);
574 * ngbe_mta_vector - Determines bit-vector in multicast table to set
575 * @hw: pointer to hardware structure
576 * @mc_addr: the multicast address
578 * Extracts the 12 bits, from a multicast address, to determine which
579 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
580 * incoming rx multicast addresses, to determine the bit-vector to check in
581 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
582 * by the MO field of the PSRCTRL. The MO field is set during initialization
585 static s32 ngbe_mta_vector(struct ngbe_hw *hw, u8 *mc_addr)
589 DEBUGFUNC("ngbe_mta_vector");
591 switch (hw->mac.mc_filter_type) {
592 case 0: /* use bits [47:36] of the address */
593 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
595 case 1: /* use bits [46:35] of the address */
596 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
598 case 2: /* use bits [45:34] of the address */
599 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
601 case 3: /* use bits [43:32] of the address */
602 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
604 default: /* Invalid mc_filter_type */
605 DEBUGOUT("MC filter type param set incorrectly\n");
610 /* vector can only be 12-bits or boundary will be exceeded */
616 * ngbe_set_mta - Set bit-vector in multicast table
617 * @hw: pointer to hardware structure
618 * @mc_addr: Multicast address
620 * Sets the bit-vector in the multicast table.
622 void ngbe_set_mta(struct ngbe_hw *hw, u8 *mc_addr)
628 DEBUGFUNC("ngbe_set_mta");
630 hw->addr_ctrl.mta_in_use++;
632 vector = ngbe_mta_vector(hw, mc_addr);
633 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
636 * The MTA is a register array of 128 32-bit registers. It is treated
637 * like an array of 4096 bits. We want to set bit
638 * BitArray[vector_value]. So we figure out what register the bit is
639 * in, read it, OR in the new bit, then write back the new value. The
640 * register is determined by the upper 7 bits of the vector value and
641 * the bit within that register are determined by the lower 5 bits of
644 vector_reg = (vector >> 5) & 0x7F;
645 vector_bit = vector & 0x1F;
646 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
650 * ngbe_update_mc_addr_list - Updates MAC list of multicast addresses
651 * @hw: pointer to hardware structure
652 * @mc_addr_list: the list of new multicast addresses
653 * @mc_addr_count: number of addresses
654 * @next: iterator function to walk the multicast address list
655 * @clear: flag, when set clears the table beforehand
657 * When the clear flag is set, the given list replaces any existing list.
658 * Hashes the given addresses into the multicast table.
660 s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list,
661 u32 mc_addr_count, ngbe_mc_addr_itr next,
667 DEBUGFUNC("ngbe_update_mc_addr_list");
670 * Set the new number of MC addresses that we are being requested to
673 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
674 hw->addr_ctrl.mta_in_use = 0;
676 /* Clear mta_shadow */
678 DEBUGOUT(" Clearing MTA\n");
679 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
682 /* Update mta_shadow */
683 for (i = 0; i < mc_addr_count; i++) {
684 DEBUGOUT(" Adding the multicast addresses:\n");
685 ngbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
689 for (i = 0; i < hw->mac.mcft_size; i++)
690 wr32a(hw, NGBE_MCADDRTBL(0), i,
691 hw->mac.mta_shadow[i]);
693 if (hw->addr_ctrl.mta_in_use > 0) {
694 u32 psrctl = rd32(hw, NGBE_PSRCTL);
695 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
696 psrctl |= NGBE_PSRCTL_MCHFENA |
697 NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
698 wr32(hw, NGBE_PSRCTL, psrctl);
701 DEBUGOUT("ngbe update mc addr list complete\n");
706 * ngbe_acquire_swfw_sync - Acquire SWFW semaphore
707 * @hw: pointer to hardware structure
708 * @mask: Mask to specify which semaphore to acquire
710 * Acquires the SWFW semaphore through the MNGSEM register for the specified
711 * function (CSR, PHY0, PHY1, EEPROM, Flash)
713 s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask)
716 u32 swmask = NGBE_MNGSEM_SW(mask);
717 u32 fwmask = NGBE_MNGSEM_FW(mask);
721 DEBUGFUNC("ngbe_acquire_swfw_sync");
723 for (i = 0; i < timeout; i++) {
725 * SW NVM semaphore bit is used for access to all
726 * SW_FW_SYNC bits (not just NVM)
728 if (ngbe_get_eeprom_semaphore(hw))
729 return NGBE_ERR_SWFW_SYNC;
731 mngsem = rd32(hw, NGBE_MNGSEM);
732 if (mngsem & (fwmask | swmask)) {
733 /* Resource is currently in use by FW or SW */
734 ngbe_release_eeprom_semaphore(hw);
738 wr32(hw, NGBE_MNGSEM, mngsem);
739 ngbe_release_eeprom_semaphore(hw);
744 /* If time expired clear the bits holding the lock and retry */
745 if (mngsem & (fwmask | swmask))
746 ngbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
749 return NGBE_ERR_SWFW_SYNC;
753 * ngbe_release_swfw_sync - Release SWFW semaphore
754 * @hw: pointer to hardware structure
755 * @mask: Mask to specify which semaphore to release
757 * Releases the SWFW semaphore through the MNGSEM register for the specified
758 * function (CSR, PHY0, PHY1, EEPROM, Flash)
760 void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask)
765 DEBUGFUNC("ngbe_release_swfw_sync");
767 ngbe_get_eeprom_semaphore(hw);
769 mngsem = rd32(hw, NGBE_MNGSEM);
771 wr32(hw, NGBE_MNGSEM, mngsem);
773 ngbe_release_eeprom_semaphore(hw);
777 * ngbe_disable_sec_rx_path - Stops the receive data path
778 * @hw: pointer to hardware structure
780 * Stops the receive data path and waits for the HW to internally empty
781 * the Rx security block
783 s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw)
785 #define NGBE_MAX_SECRX_POLL 4000
790 DEBUGFUNC("ngbe_disable_sec_rx_path");
793 secrxreg = rd32(hw, NGBE_SECRXCTL);
794 secrxreg |= NGBE_SECRXCTL_XDSA;
795 wr32(hw, NGBE_SECRXCTL, secrxreg);
796 for (i = 0; i < NGBE_MAX_SECRX_POLL; i++) {
797 secrxreg = rd32(hw, NGBE_SECRXSTAT);
798 if (!(secrxreg & NGBE_SECRXSTAT_RDY))
799 /* Use interrupt-safe sleep just in case */
805 /* For informational purposes only */
806 if (i >= NGBE_MAX_SECRX_POLL)
807 DEBUGOUT("Rx unit being enabled before security "
808 "path fully disabled. Continuing with init.\n");
814 * ngbe_enable_sec_rx_path - Enables the receive data path
815 * @hw: pointer to hardware structure
817 * Enables the receive data path.
819 s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw)
823 DEBUGFUNC("ngbe_enable_sec_rx_path");
825 secrxreg = rd32(hw, NGBE_SECRXCTL);
826 secrxreg &= ~NGBE_SECRXCTL_XDSA;
827 wr32(hw, NGBE_SECRXCTL, secrxreg);
834 * ngbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
835 * @hw: pointer to hardware struct
836 * @rar: receive address register index to disassociate
837 * @vmdq: VMDq pool index to remove from the rar
839 s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
842 u32 rar_entries = hw->mac.num_rar_entries;
844 DEBUGFUNC("ngbe_clear_vmdq");
846 /* Make sure we are using a valid rar index range */
847 if (rar >= rar_entries) {
848 DEBUGOUT("RAR index %d is out of range.\n", rar);
849 return NGBE_ERR_INVALID_ARGUMENT;
852 wr32(hw, NGBE_ETHADDRIDX, rar);
853 mpsar = rd32(hw, NGBE_ETHADDRASS);
855 if (NGBE_REMOVED(hw->hw_addr))
861 mpsar &= ~(1 << vmdq);
862 wr32(hw, NGBE_ETHADDRASS, mpsar);
864 /* was that the last pool using this rar? */
865 if (mpsar == 0 && rar != 0)
866 hw->mac.clear_rar(hw, rar);
872 * ngbe_set_vmdq - Associate a VMDq pool index with a rx address
873 * @hw: pointer to hardware struct
874 * @rar: receive address register index to associate with a VMDq index
875 * @vmdq: VMDq pool index
877 s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
880 u32 rar_entries = hw->mac.num_rar_entries;
882 DEBUGFUNC("ngbe_set_vmdq");
884 /* Make sure we are using a valid rar index range */
885 if (rar >= rar_entries) {
886 DEBUGOUT("RAR index %d is out of range.\n", rar);
887 return NGBE_ERR_INVALID_ARGUMENT;
890 wr32(hw, NGBE_ETHADDRIDX, rar);
892 mpsar = rd32(hw, NGBE_ETHADDRASS);
894 wr32(hw, NGBE_ETHADDRASS, mpsar);
900 * ngbe_init_uta_tables - Initialize the Unicast Table Array
901 * @hw: pointer to hardware structure
903 s32 ngbe_init_uta_tables(struct ngbe_hw *hw)
907 DEBUGFUNC("ngbe_init_uta_tables");
908 DEBUGOUT(" Clearing UTA\n");
910 for (i = 0; i < 128; i++)
911 wr32(hw, NGBE_UCADDRTBL(i), 0);
917 * ngbe_clear_vfta - Clear VLAN filter table
918 * @hw: pointer to hardware structure
920 * Clears the VLAN filer table, and the VMDq index associated with the filter
922 s32 ngbe_clear_vfta(struct ngbe_hw *hw)
926 DEBUGFUNC("ngbe_clear_vfta");
928 for (offset = 0; offset < hw->mac.vft_size; offset++)
929 wr32(hw, NGBE_VLANTBL(offset), 0);
931 for (offset = 0; offset < NGBE_NUM_POOL; offset++) {
932 wr32(hw, NGBE_PSRVLANIDX, offset);
933 wr32(hw, NGBE_PSRVLAN, 0);
934 wr32(hw, NGBE_PSRVLANPLM(0), 0);
941 * ngbe_check_mac_link_em - Determine link and speed status
942 * @hw: pointer to hardware structure
943 * @speed: pointer to link speed
944 * @link_up: true when link is up
945 * @link_up_wait_to_complete: bool used to wait for link up or not
947 * Reads the links register to determine if link is up and the current speed
949 s32 ngbe_check_mac_link_em(struct ngbe_hw *hw, u32 *speed,
950 bool *link_up, bool link_up_wait_to_complete)
955 DEBUGFUNC("ngbe_check_mac_link_em");
957 reg = rd32(hw, NGBE_GPIOINTSTAT);
958 wr32(hw, NGBE_GPIOEOI, reg);
960 if (link_up_wait_to_complete) {
961 for (i = 0; i < hw->mac.max_link_up_time; i++) {
962 status = hw->phy.check_link(hw, speed, link_up);
968 status = hw->phy.check_link(hw, speed, link_up);
974 s32 ngbe_get_link_capabilities_em(struct ngbe_hw *hw,
982 hw->mac.autoneg = *autoneg;
984 switch (hw->sub_device_id) {
985 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
986 *speed = NGBE_LINK_SPEED_1GB_FULL |
987 NGBE_LINK_SPEED_100M_FULL |
988 NGBE_LINK_SPEED_10M_FULL;
997 s32 ngbe_setup_mac_link_em(struct ngbe_hw *hw,
999 bool autoneg_wait_to_complete)
1005 /* Setup the PHY according to input speed */
1006 status = hw->phy.setup_link(hw, speed, autoneg_wait_to_complete);
1012 * ngbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1013 * @hw: pointer to hardware structure
1015 * Inits the thermal sensor thresholds according to the NVM map
1016 * and save off the threshold and location values into mac.thermal_sensor_data
1018 s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw)
1020 struct ngbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1022 DEBUGFUNC("ngbe_init_thermal_sensor_thresh");
1024 memset(data, 0, sizeof(struct ngbe_thermal_sensor_data));
1026 if (hw->bus.lan_id != 0)
1027 return NGBE_NOT_IMPLEMENTED;
1029 wr32(hw, NGBE_TSINTR,
1030 NGBE_TSINTR_AEN | NGBE_TSINTR_DEN);
1031 wr32(hw, NGBE_TSEN, NGBE_TSEN_ENA);
1034 data->sensor[0].alarm_thresh = 115;
1035 wr32(hw, NGBE_TSATHRE, 0x344);
1036 data->sensor[0].dalarm_thresh = 110;
1037 wr32(hw, NGBE_TSDTHRE, 0x330);
1042 s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw)
1047 DEBUGFUNC("ngbe_mac_check_overtemp");
1049 /* Check that the LASI temp alarm status was triggered */
1050 ts_state = rd32(hw, NGBE_TSALM);
1052 if (ts_state & NGBE_TSALM_HI)
1053 status = NGBE_ERR_UNDERTEMP;
1054 else if (ts_state & NGBE_TSALM_LO)
1055 status = NGBE_ERR_OVERTEMP;
1060 void ngbe_disable_rx(struct ngbe_hw *hw)
1064 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
1065 if (pfdtxgswc & NGBE_PSRCTL_LBENA) {
1066 pfdtxgswc &= ~NGBE_PSRCTL_LBENA;
1067 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
1068 hw->mac.set_lben = true;
1070 hw->mac.set_lben = false;
1073 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0);
1074 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, 0);
1077 void ngbe_enable_rx(struct ngbe_hw *hw)
1081 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, NGBE_MACRXCFG_ENA);
1082 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, NGBE_PBRXCTL_ENA);
1084 if (hw->mac.set_lben) {
1085 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
1086 pfdtxgswc |= NGBE_PSRCTL_LBENA;
1087 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
1088 hw->mac.set_lben = false;
1093 * ngbe_set_mac_type - Sets MAC type
1094 * @hw: pointer to the HW structure
1096 * This function sets the mac type of the adapter based on the
1097 * vendor ID and device ID stored in the hw structure.
1099 s32 ngbe_set_mac_type(struct ngbe_hw *hw)
1103 DEBUGFUNC("ngbe_set_mac_type");
1105 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
1106 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
1107 return NGBE_ERR_DEVICE_NOT_SUPPORTED;
1110 switch (hw->sub_device_id) {
1111 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
1112 case NGBE_SUB_DEV_ID_EM_MVL_RGMII:
1113 hw->phy.media_type = ngbe_media_type_copper;
1114 hw->mac.type = ngbe_mac_em;
1116 case NGBE_SUB_DEV_ID_EM_MVL_SFP:
1117 case NGBE_SUB_DEV_ID_EM_YT8521S_SFP:
1118 hw->phy.media_type = ngbe_media_type_fiber;
1119 hw->mac.type = ngbe_mac_em;
1121 case NGBE_SUB_DEV_ID_EM_VF:
1122 hw->phy.media_type = ngbe_media_type_virtual;
1123 hw->mac.type = ngbe_mac_em_vf;
1126 err = NGBE_ERR_DEVICE_NOT_SUPPORTED;
1127 hw->phy.media_type = ngbe_media_type_unknown;
1128 hw->mac.type = ngbe_mac_unknown;
1129 DEBUGOUT("Unsupported device id: %x", hw->device_id);
1133 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
1134 hw->mac.type, hw->phy.media_type, err);
1139 * ngbe_enable_rx_dma - Enable the Rx DMA unit
1140 * @hw: pointer to hardware structure
1141 * @regval: register value to write to RXCTRL
1143 * Enables the Rx DMA unit
1145 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)
1147 DEBUGFUNC("ngbe_enable_rx_dma");
1150 * Workaround silicon errata when enabling the Rx datapath.
1151 * If traffic is incoming before we enable the Rx unit, it could hang
1152 * the Rx DMA unit. Therefore, make sure the security engine is
1153 * completely disabled prior to enabling the Rx unit.
1156 hw->mac.disable_sec_rx_path(hw);
1158 if (regval & NGBE_PBRXCTL_ENA)
1161 ngbe_disable_rx(hw);
1163 hw->mac.enable_sec_rx_path(hw);
1168 void ngbe_map_device_id(struct ngbe_hw *hw)
1170 u16 oem = hw->sub_system_id & NGBE_OEM_MASK;
1171 u16 internal = hw->sub_system_id & NGBE_INTERNAL_MASK;
1174 /* move subsystem_device_id to device_id */
1175 switch (hw->device_id) {
1176 case NGBE_DEV_ID_EM_WX1860AL_W_VF:
1177 case NGBE_DEV_ID_EM_WX1860A2_VF:
1178 case NGBE_DEV_ID_EM_WX1860A2S_VF:
1179 case NGBE_DEV_ID_EM_WX1860A4_VF:
1180 case NGBE_DEV_ID_EM_WX1860A4S_VF:
1181 case NGBE_DEV_ID_EM_WX1860AL2_VF:
1182 case NGBE_DEV_ID_EM_WX1860AL2S_VF:
1183 case NGBE_DEV_ID_EM_WX1860AL4_VF:
1184 case NGBE_DEV_ID_EM_WX1860AL4S_VF:
1185 case NGBE_DEV_ID_EM_WX1860NCSI_VF:
1186 case NGBE_DEV_ID_EM_WX1860A1_VF:
1187 case NGBE_DEV_ID_EM_WX1860A1L_VF:
1188 hw->device_id = NGBE_DEV_ID_EM_VF;
1189 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_VF;
1192 case NGBE_DEV_ID_EM_WX1860AL_W:
1193 case NGBE_DEV_ID_EM_WX1860A2:
1194 case NGBE_DEV_ID_EM_WX1860A2S:
1195 case NGBE_DEV_ID_EM_WX1860A4:
1196 case NGBE_DEV_ID_EM_WX1860A4S:
1197 case NGBE_DEV_ID_EM_WX1860AL2:
1198 case NGBE_DEV_ID_EM_WX1860AL2S:
1199 case NGBE_DEV_ID_EM_WX1860AL4:
1200 case NGBE_DEV_ID_EM_WX1860AL4S:
1201 case NGBE_DEV_ID_EM_WX1860NCSI:
1202 case NGBE_DEV_ID_EM_WX1860A1:
1203 case NGBE_DEV_ID_EM_WX1860A1L:
1204 hw->device_id = NGBE_DEV_ID_EM;
1205 if (oem == NGBE_LY_M88E1512_SFP ||
1206 internal == NGBE_INTERNAL_SFP)
1207 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_SFP;
1208 else if (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45)
1209 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_RGMII;
1210 else if (oem == NGBE_YT8521S_SFP ||
1211 oem == NGBE_LY_YT8521S_SFP)
1212 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_YT8521S_SFP;
1214 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_SGMII;
1222 * ngbe_init_ops_pf - Inits func ptrs and MAC type
1223 * @hw: pointer to hardware structure
1225 * Initialize the function pointers and assign the MAC type.
1226 * Does not touch the hardware.
1228 s32 ngbe_init_ops_pf(struct ngbe_hw *hw)
1230 struct ngbe_bus_info *bus = &hw->bus;
1231 struct ngbe_mac_info *mac = &hw->mac;
1232 struct ngbe_phy_info *phy = &hw->phy;
1233 struct ngbe_rom_info *rom = &hw->rom;
1235 DEBUGFUNC("ngbe_init_ops_pf");
1238 bus->set_lan_id = ngbe_set_lan_id_multi_port;
1241 phy->identify = ngbe_identify_phy;
1242 phy->read_reg = ngbe_read_phy_reg;
1243 phy->write_reg = ngbe_write_phy_reg;
1244 phy->read_reg_unlocked = ngbe_read_phy_reg_mdi;
1245 phy->write_reg_unlocked = ngbe_write_phy_reg_mdi;
1246 phy->reset_hw = ngbe_reset_phy;
1249 mac->init_hw = ngbe_init_hw;
1250 mac->reset_hw = ngbe_reset_hw_em;
1251 mac->start_hw = ngbe_start_hw;
1252 mac->clear_hw_cntrs = ngbe_clear_hw_cntrs;
1253 mac->enable_rx_dma = ngbe_enable_rx_dma;
1254 mac->get_mac_addr = ngbe_get_mac_addr;
1255 mac->stop_hw = ngbe_stop_hw;
1256 mac->acquire_swfw_sync = ngbe_acquire_swfw_sync;
1257 mac->release_swfw_sync = ngbe_release_swfw_sync;
1259 mac->disable_sec_rx_path = ngbe_disable_sec_rx_path;
1260 mac->enable_sec_rx_path = ngbe_enable_sec_rx_path;
1261 /* RAR, VLAN, Multicast */
1262 mac->set_rar = ngbe_set_rar;
1263 mac->clear_rar = ngbe_clear_rar;
1264 mac->init_rx_addrs = ngbe_init_rx_addrs;
1265 mac->update_mc_addr_list = ngbe_update_mc_addr_list;
1266 mac->set_vmdq = ngbe_set_vmdq;
1267 mac->clear_vmdq = ngbe_clear_vmdq;
1268 mac->clear_vfta = ngbe_clear_vfta;
1271 mac->get_link_capabilities = ngbe_get_link_capabilities_em;
1272 mac->check_link = ngbe_check_mac_link_em;
1273 mac->setup_link = ngbe_setup_mac_link_em;
1275 /* Manageability interface */
1276 mac->init_thermal_sensor_thresh = ngbe_init_thermal_sensor_thresh;
1277 mac->check_overtemp = ngbe_mac_check_overtemp;
1280 rom->init_params = ngbe_init_eeprom_params;
1281 rom->read32 = ngbe_ee_read32;
1282 rom->validate_checksum = ngbe_validate_eeprom_checksum_em;
1284 mac->mcft_size = NGBE_EM_MC_TBL_SIZE;
1285 mac->vft_size = NGBE_EM_VFT_TBL_SIZE;
1286 mac->num_rar_entries = NGBE_EM_RAR_ENTRIES;
1287 mac->max_rx_queues = NGBE_EM_MAX_RX_QUEUES;
1288 mac->max_tx_queues = NGBE_EM_MAX_TX_QUEUES;
1290 mac->default_speeds = NGBE_LINK_SPEED_10M_FULL |
1291 NGBE_LINK_SPEED_100M_FULL |
1292 NGBE_LINK_SPEED_1GB_FULL;
1298 * ngbe_init_shared_code - Initialize the shared code
1299 * @hw: pointer to hardware structure
1301 * This will assign function pointers and assign the MAC type and PHY code.
1302 * Does not touch the hardware. This function must be called prior to any
1303 * other function in the shared code. The ngbe_hw structure should be
1304 * memset to 0 prior to calling this function. The following fields in
1305 * hw structure should be filled in prior to calling this function:
1306 * hw_addr, back, device_id, vendor_id, subsystem_device_id
1308 s32 ngbe_init_shared_code(struct ngbe_hw *hw)
1312 DEBUGFUNC("ngbe_init_shared_code");
1317 ngbe_set_mac_type(hw);
1319 ngbe_init_ops_dummy(hw);
1320 switch (hw->mac.type) {
1322 ngbe_init_ops_pf(hw);
1325 status = NGBE_ERR_DEVICE_NOT_SUPPORTED;
1328 hw->mac.max_link_up_time = NGBE_LINK_UP_TIME;
1330 hw->bus.set_lan_id(hw);