1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
11 #define NGBE_PMMBX_QSIZE 64 /* Num of dwords in range */
12 #define NGBE_PMMBX_BSIZE (NGBE_PMMBX_QSIZE * 4)
13 #define NGBE_PMMBX_DATA_SIZE (NGBE_PMMBX_BSIZE - FW_NVM_DATA_OFFSET * 4)
14 #define NGBE_HI_COMMAND_TIMEOUT 5000 /* Process HI command limit */
17 #define FW_CEM_MAX_RETRIES 3
18 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
19 #define FW_READ_SHADOW_RAM_CMD 0x31
20 #define FW_READ_SHADOW_RAM_LEN 0x6
21 #define FW_WRITE_SHADOW_RAM_CMD 0x33
22 #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */
23 #define FW_PCIE_READ_CMD 0xEC
24 #define FW_PCIE_WRITE_CMD 0xED
25 #define FW_PCIE_BUSMASTER_OFFSET 2
26 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
27 #define FW_NVM_DATA_OFFSET 3
28 #define FW_EEPROM_CHECK_STATUS 0xE9
29 #define FW_PHY_LED_CONF 0xF1
31 #define FW_CHECKSUM_CAP_ST_PASS 0x80658383
32 #define FW_CHECKSUM_CAP_ST_FAIL 0x70657376
34 /* Host Interface Command Structures */
45 struct ngbe_hic_hdr2_req {
52 struct ngbe_hic_hdr2_rsp {
55 u8 ret_status; /* 7-5: high bits of buf_len, 4-0: status */
60 struct ngbe_hic_hdr2_req req;
61 struct ngbe_hic_hdr2_rsp rsp;
64 /* These need to be dword aligned */
65 struct ngbe_hic_read_shadow_ram {
66 union ngbe_hic_hdr2 hdr;
74 struct ngbe_hic_write_shadow_ram {
75 union ngbe_hic_hdr2 hdr;
83 struct ngbe_hic_read_pcie {
84 struct ngbe_hic_hdr hdr;
91 struct ngbe_hic_write_pcie {
92 struct ngbe_hic_hdr hdr;
99 s32 ngbe_hic_sr_read(struct ngbe_hw *hw, u32 addr, u8 *buf, int len);
100 s32 ngbe_hic_sr_write(struct ngbe_hw *hw, u32 addr, u8 *buf, int len);
101 s32 ngbe_hic_pcie_read(struct ngbe_hw *hw, u16 addr, u32 *buf, int len);
102 s32 ngbe_hic_pcie_write(struct ngbe_hw *hw, u16 addr, u32 *buf, int len);
104 s32 ngbe_hic_check_cap(struct ngbe_hw *hw);
105 s32 ngbe_phy_led_oem_chk(struct ngbe_hw *hw, u32 *data);
107 #endif /* _NGBE_MNG_H_ */