1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
11 #define NGBE_PMMBX_QSIZE 64 /* Num of dwords in range */
12 #define NGBE_PMMBX_BSIZE (NGBE_PMMBX_QSIZE * 4)
13 #define NGBE_HI_COMMAND_TIMEOUT 5000 /* Process HI command limit */
16 #define FW_CEM_MAX_RETRIES 3
17 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
18 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
19 #define FW_EEPROM_CHECK_STATUS 0xE9
21 #define FW_CHECKSUM_CAP_ST_PASS 0x80658383
22 #define FW_CHECKSUM_CAP_ST_FAIL 0x70657376
24 /* Host Interface Command Structures */
35 struct ngbe_hic_hdr2_req {
42 struct ngbe_hic_hdr2_rsp {
45 u8 ret_status; /* 7-5: high bits of buf_len, 4-0: status */
50 struct ngbe_hic_hdr2_req req;
51 struct ngbe_hic_hdr2_rsp rsp;
54 /* These need to be dword aligned */
55 struct ngbe_hic_read_shadow_ram {
56 union ngbe_hic_hdr2 hdr;
64 s32 ngbe_hic_check_cap(struct ngbe_hw *hw);
65 #endif /* _NGBE_MNG_H_ */