1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
9 s32 ngbe_mdi_map_register(mdi_reg_t *reg, mdi_reg_22_t *reg22)
12 switch (reg->device_type) {
13 case NGBE_MD_DEV_PMA_PMD:
15 case NGBE_MD_PHY_ID_HIGH:
16 case NGBE_MD_PHY_ID_LOW:
18 reg22->addr = reg->addr;
19 reg22->device_type = 0;
31 reg22->page = reg->device_type;
32 reg22->device_type = reg->device_type;
33 reg22->addr = reg->addr;
40 * ngbe_probe_phy - Identify a single address for a PHY
41 * @hw: pointer to hardware structure
42 * @phy_addr: PHY address to probe
44 * Returns true if PHY found
46 static bool ngbe_probe_phy(struct ngbe_hw *hw, u16 phy_addr)
48 if (!ngbe_validate_phy_addr(hw, phy_addr)) {
49 DEBUGOUT("Unable to validate PHY address 0x%04X\n",
54 if (ngbe_get_phy_id(hw))
57 hw->phy.type = ngbe_get_phy_type_from_id(hw);
58 if (hw->phy.type == ngbe_phy_unknown)
65 * ngbe_identify_phy - Get physical layer module
66 * @hw: pointer to hardware structure
68 * Determines the physical layer module found on the current adapter.
70 s32 ngbe_identify_phy(struct ngbe_hw *hw)
72 s32 err = NGBE_ERR_PHY_ADDR_INVALID;
75 DEBUGFUNC("ngbe_identify_phy");
77 if (hw->phy.type != ngbe_phy_unknown)
81 wr32(hw, NGBE_MDIOMODE, NGBE_MDIOMODE_MASK);
83 for (phy_addr = 0; phy_addr < NGBE_MAX_PHY_ADDR; phy_addr++) {
84 if (ngbe_probe_phy(hw, phy_addr)) {
94 * ngbe_check_reset_blocked - check status of MNG FW veto bit
95 * @hw: pointer to the hardware structure
97 * This function checks the STAT.MNGVETO bit to see if there are
98 * any constraints on link from manageability. For MAC's that don't
99 * have this bit just return faluse since the link can not be blocked
102 s32 ngbe_check_reset_blocked(struct ngbe_hw *hw)
106 DEBUGFUNC("ngbe_check_reset_blocked");
108 mmngc = rd32(hw, NGBE_STAT);
109 if (mmngc & NGBE_STAT_MNGVETO) {
110 DEBUGOUT("MNG_VETO bit detected.\n");
118 * ngbe_validate_phy_addr - Determines phy address is valid
119 * @hw: pointer to hardware structure
120 * @phy_addr: PHY address
123 bool ngbe_validate_phy_addr(struct ngbe_hw *hw, u32 phy_addr)
128 DEBUGFUNC("ngbe_validate_phy_addr");
130 if (hw->sub_device_id == NGBE_SUB_DEV_ID_EM_YT8521S_SFP)
133 hw->phy.addr = phy_addr;
134 hw->phy.read_reg(hw, NGBE_MD_PHY_ID_HIGH,
135 NGBE_MD_DEV_PMA_PMD, &phy_id);
137 if (phy_id != 0xFFFF && phy_id != 0x0)
140 DEBUGOUT("PHY ID HIGH is 0x%04X\n", phy_id);
146 * ngbe_get_phy_id - Get the phy ID
147 * @hw: pointer to hardware structure
150 s32 ngbe_get_phy_id(struct ngbe_hw *hw)
156 DEBUGFUNC("ngbe_get_phy_id");
158 err = hw->phy.read_reg(hw, NGBE_MD_PHY_ID_HIGH,
161 hw->phy.id = (u32)(phy_id_high << 16);
163 err = hw->phy.read_reg(hw, NGBE_MD_PHY_ID_LOW,
166 hw->phy.id |= (u32)(phy_id_low & NGBE_PHY_REVISION_MASK);
167 hw->phy.revision = (u32)(phy_id_low & ~NGBE_PHY_REVISION_MASK);
169 DEBUGOUT("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
170 phy_id_high, phy_id_low);
176 * ngbe_get_phy_type_from_id - Get the phy type
177 * @phy_id: PHY ID information
180 enum ngbe_phy_type ngbe_get_phy_type_from_id(struct ngbe_hw *hw)
182 enum ngbe_phy_type phy_type;
184 DEBUGFUNC("ngbe_get_phy_type_from_id");
186 switch (hw->phy.id) {
188 phy_type = ngbe_phy_rtl;
191 if (hw->phy.media_type == ngbe_media_type_fiber)
192 phy_type = ngbe_phy_mvl_sfi;
194 phy_type = ngbe_phy_mvl;
197 if (hw->phy.media_type == ngbe_media_type_fiber)
198 phy_type = ngbe_phy_yt8521s_sfi;
200 phy_type = ngbe_phy_yt8521s;
203 phy_type = ngbe_phy_unknown;
211 * ngbe_reset_phy - Performs a PHY reset
212 * @hw: pointer to hardware structure
214 s32 ngbe_reset_phy(struct ngbe_hw *hw)
218 DEBUGFUNC("ngbe_reset_phy");
220 if (hw->phy.type == ngbe_phy_unknown)
221 err = ngbe_identify_phy(hw);
223 if (err != 0 || hw->phy.type == ngbe_phy_none)
226 /* Don't reset PHY if it's shut down due to overtemp. */
227 if (hw->mac.check_overtemp(hw) == NGBE_ERR_OVERTEMP)
230 /* Blocked by MNG FW so bail */
231 if (ngbe_check_reset_blocked(hw))
234 switch (hw->phy.type) {
236 err = ngbe_reset_phy_rtl(hw);
239 case ngbe_phy_mvl_sfi:
240 err = ngbe_reset_phy_mvl(hw);
242 case ngbe_phy_yt8521s:
243 case ngbe_phy_yt8521s_sfi:
244 err = ngbe_reset_phy_yt(hw);
254 * ngbe_read_phy_mdi - Reads a value from a specified PHY register without
256 * @hw: pointer to hardware structure
257 * @reg_addr: 32 bit address of PHY register to read
258 * @device_type: 5 bit device type
259 * @phy_data: Pointer to read data from PHY register
261 s32 ngbe_read_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,
266 /* Setup and write the address cycle command */
267 command = NGBE_MDIOSCA_REG(reg_addr) |
268 NGBE_MDIOSCA_DEV(device_type) |
269 NGBE_MDIOSCA_PORT(hw->phy.addr);
270 wr32(hw, NGBE_MDIOSCA, command);
272 command = NGBE_MDIOSCD_CMD_READ |
274 NGBE_MDIOSCD_CLOCK(6);
275 wr32(hw, NGBE_MDIOSCD, command);
278 * Check every 10 usec to see if the address cycle completed.
279 * The MDI Command bit will clear when the operation is
282 if (!po32m(hw, NGBE_MDIOSCD, NGBE_MDIOSCD_BUSY,
283 0, NULL, 100, 100)) {
284 DEBUGOUT("PHY address command did not complete\n");
288 data = rd32(hw, NGBE_MDIOSCD);
289 *phy_data = (u16)NGBE_MDIOSCD_DAT_R(data);
295 * ngbe_read_phy_reg - Reads a value from a specified PHY register
296 * using the SWFW lock - this function is needed in most cases
297 * @hw: pointer to hardware structure
298 * @reg_addr: 32 bit address of PHY register to read
299 * @device_type: 5 bit device type
300 * @phy_data: Pointer to read data from PHY register
302 s32 ngbe_read_phy_reg(struct ngbe_hw *hw, u32 reg_addr,
303 u32 device_type, u16 *phy_data)
306 u32 gssr = hw->phy.phy_semaphore_mask;
308 DEBUGFUNC("ngbe_read_phy_reg");
310 if (hw->mac.acquire_swfw_sync(hw, gssr))
311 return NGBE_ERR_SWFW_SYNC;
313 err = hw->phy.read_reg_unlocked(hw, reg_addr, device_type,
316 hw->mac.release_swfw_sync(hw, gssr);
322 * ngbe_write_phy_reg_mdi - Writes a value to specified PHY register
324 * @hw: pointer to hardware structure
325 * @reg_addr: 32 bit PHY register to write
326 * @device_type: 5 bit device type
327 * @phy_data: Data to write to the PHY register
329 s32 ngbe_write_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr,
330 u32 device_type, u16 phy_data)
335 command = NGBE_MDIOSCA_REG(reg_addr) |
336 NGBE_MDIOSCA_DEV(device_type) |
337 NGBE_MDIOSCA_PORT(hw->phy.addr);
338 wr32(hw, NGBE_MDIOSCA, command);
340 command = NGBE_MDIOSCD_CMD_WRITE |
341 NGBE_MDIOSCD_DAT(phy_data) |
343 NGBE_MDIOSCD_CLOCK(6);
344 wr32(hw, NGBE_MDIOSCD, command);
346 /* wait for completion */
347 if (!po32m(hw, NGBE_MDIOSCD, NGBE_MDIOSCD_BUSY,
348 0, NULL, 100, 100)) {
349 TLOG_DEBUG("PHY write cmd didn't complete\n");
357 * ngbe_write_phy_reg - Writes a value to specified PHY register
358 * using SWFW lock- this function is needed in most cases
359 * @hw: pointer to hardware structure
360 * @reg_addr: 32 bit PHY register to write
361 * @device_type: 5 bit device type
362 * @phy_data: Data to write to the PHY register
364 s32 ngbe_write_phy_reg(struct ngbe_hw *hw, u32 reg_addr,
365 u32 device_type, u16 phy_data)
368 u32 gssr = hw->phy.phy_semaphore_mask;
370 DEBUGFUNC("ngbe_write_phy_reg");
372 if (hw->mac.acquire_swfw_sync(hw, gssr))
373 err = NGBE_ERR_SWFW_SYNC;
375 err = hw->phy.write_reg_unlocked(hw, reg_addr, device_type,
378 hw->mac.release_swfw_sync(hw, gssr);
384 * ngbe_init_phy - PHY specific init
385 * @hw: pointer to hardware structure
387 * Initialize any function pointers that were not able to be
388 * set during init_shared_code because the PHY type was
392 s32 ngbe_init_phy(struct ngbe_hw *hw)
394 struct ngbe_phy_info *phy = &hw->phy;
397 DEBUGFUNC("ngbe_init_phy");
401 switch (hw->sub_device_id) {
402 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
403 hw->phy.read_reg_unlocked = ngbe_read_phy_reg_rtl;
404 hw->phy.write_reg_unlocked = ngbe_write_phy_reg_rtl;
406 case NGBE_SUB_DEV_ID_EM_MVL_RGMII:
407 case NGBE_SUB_DEV_ID_EM_MVL_SFP:
408 hw->phy.read_reg_unlocked = ngbe_read_phy_reg_mvl;
409 hw->phy.write_reg_unlocked = ngbe_write_phy_reg_mvl;
411 case NGBE_SUB_DEV_ID_EM_YT8521S_SFP:
412 hw->phy.read_reg_unlocked = ngbe_read_phy_reg_yt;
413 hw->phy.write_reg_unlocked = ngbe_write_phy_reg_yt;
419 hw->phy.phy_semaphore_mask = NGBE_MNGSEM_SWPHY;
421 /* Identify the PHY */
422 err = phy->identify(hw);
423 if (err == NGBE_ERR_PHY_ADDR_INVALID)
424 goto init_phy_ops_out;
426 /* Set necessary function pointers based on PHY type */
427 switch (hw->phy.type) {
429 hw->phy.init_hw = ngbe_init_phy_rtl;
430 hw->phy.check_link = ngbe_check_phy_link_rtl;
431 hw->phy.setup_link = ngbe_setup_phy_link_rtl;
432 hw->phy.get_adv_pause = ngbe_get_phy_advertised_pause_rtl;
433 hw->phy.get_lp_adv_pause = ngbe_get_phy_lp_advertised_pause_rtl;
434 hw->phy.set_pause_adv = ngbe_set_phy_pause_adv_rtl;
437 case ngbe_phy_mvl_sfi:
438 hw->phy.init_hw = ngbe_init_phy_mvl;
439 hw->phy.check_link = ngbe_check_phy_link_mvl;
440 hw->phy.setup_link = ngbe_setup_phy_link_mvl;
441 hw->phy.get_adv_pause = ngbe_get_phy_advertised_pause_mvl;
442 hw->phy.get_lp_adv_pause = ngbe_get_phy_lp_advertised_pause_mvl;
443 hw->phy.set_pause_adv = ngbe_set_phy_pause_adv_mvl;
445 case ngbe_phy_yt8521s:
446 case ngbe_phy_yt8521s_sfi:
447 hw->phy.init_hw = ngbe_init_phy_yt;
448 hw->phy.check_link = ngbe_check_phy_link_yt;
449 hw->phy.setup_link = ngbe_setup_phy_link_yt;
450 hw->phy.get_adv_pause = ngbe_get_phy_advertised_pause_yt;
451 hw->phy.get_lp_adv_pause = ngbe_get_phy_lp_advertised_pause_yt;
452 hw->phy.set_pause_adv = ngbe_set_phy_pause_adv_yt;