1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
5 #include "ngbe_phy_mvl.h"
7 #define MVL_PHY_RST_WAIT_PERIOD 5
9 s32 ngbe_read_phy_reg_mvl(struct ngbe_hw *hw,
10 u32 reg_addr, u32 device_type, u16 *phy_data)
15 reg.device_type = device_type;
18 if (hw->phy.media_type == ngbe_media_type_fiber)
19 ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 1);
21 ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 0);
23 ngbe_mdi_map_register(®, ®22);
25 ngbe_read_phy_reg_mdi(hw, reg22.addr, reg22.device_type, phy_data);
30 s32 ngbe_write_phy_reg_mvl(struct ngbe_hw *hw,
31 u32 reg_addr, u32 device_type, u16 phy_data)
36 reg.device_type = device_type;
39 if (hw->phy.media_type == ngbe_media_type_fiber)
40 ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 1);
42 ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 0);
44 ngbe_mdi_map_register(®, ®22);
46 ngbe_write_phy_reg_mdi(hw, reg22.addr, reg22.device_type, phy_data);
51 s32 ngbe_check_phy_mode_mvl(struct ngbe_hw *hw)
55 /* select page 18 reg 20 */
56 ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 18);
57 ngbe_read_phy_reg_mdi(hw, MVL_GEN_CTL, 0, &value);
58 if (MVL_GEN_CTL_MODE(value) == MVL_GEN_CTL_MODE_COPPER) {
59 /* mode select to RGMII-to-copper */
60 hw->phy.type = ngbe_phy_mvl;
61 hw->phy.media_type = ngbe_media_type_copper;
62 hw->mac.link_type = ngbe_link_copper;
63 } else if (MVL_GEN_CTL_MODE(value) == MVL_GEN_CTL_MODE_FIBER) {
64 /* mode select to RGMII-to-sfi */
65 hw->phy.type = ngbe_phy_mvl_sfi;
66 hw->phy.media_type = ngbe_media_type_fiber;
67 hw->mac.link_type = ngbe_link_fiber;
69 DEBUGOUT("marvell 88E1512 mode %x is not supported.", value);
70 return NGBE_ERR_DEVICE_NOT_SUPPORTED;
76 s32 ngbe_init_phy_mvl(struct ngbe_hw *hw)
82 /* enable interrupts, only link status change and an done is allowed */
83 ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 2);
84 ngbe_read_phy_reg_mdi(hw, MVL_RGM_CTL2, 0, &value);
85 value &= ~MVL_RGM_CTL2_TTC;
86 value |= MVL_RGM_CTL2_RTC;
87 ngbe_write_phy_reg_mdi(hw, MVL_RGM_CTL2, 0, value);
89 hw->phy.write_reg(hw, MVL_CTRL, 0, MVL_CTRL_RESET);
90 for (i = 0; i < 15; i++) {
91 ngbe_read_phy_reg_mdi(hw, MVL_CTRL, 0, &value);
92 if (value & MVL_CTRL_RESET)
99 DEBUGOUT("phy reset exceeds maximum waiting period.");
100 return NGBE_ERR_TIMEOUT;
103 ret_val = hw->phy.reset_hw(hw);
107 /* set LED2 to interrupt output and INTn active low */
108 ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 3);
109 ngbe_read_phy_reg_mdi(hw, MVL_LEDTCR, 0, &value);
110 value |= MVL_LEDTCR_INTR_EN;
111 value &= ~(MVL_LEDTCR_INTR_POL);
112 ngbe_write_phy_reg_mdi(hw, MVL_LEDTCR, 0, value);
114 if (hw->phy.type == ngbe_phy_mvl_sfi) {
115 hw->phy.read_reg(hw, MVL_CTRL1, 0, &value);
116 value &= ~MVL_CTRL1_INTR_POL;
117 ngbe_write_phy_reg_mdi(hw, MVL_CTRL1, 0, value);
120 /* enable link status change and AN complete interrupts */
121 value = MVL_INTR_EN_ANC | MVL_INTR_EN_LSC;
122 hw->phy.write_reg(hw, MVL_INTR_EN, 0, value);
124 hw->phy.set_phy_power(hw, false);
129 s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
130 bool autoneg_wait_to_complete)
136 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
138 if (hw->led_conf == 0xFFFF) {
140 ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 3);
141 ngbe_read_phy_reg_mdi(hw, MVL_LEDFCR, 0, &value);
142 value &= ~(MVL_LEDFCR_CTL0 | MVL_LEDFCR_CTL1);
143 value |= MVL_LEDFCR_CTL0_CONF | MVL_LEDFCR_CTL1_CONF;
144 ngbe_write_phy_reg_mdi(hw, MVL_LEDFCR, 0, value);
145 ngbe_read_phy_reg_mdi(hw, MVL_LEDPCR, 0, &value);
146 value &= ~(MVL_LEDPCR_CTL0 | MVL_LEDPCR_CTL1);
147 value |= MVL_LEDPCR_CTL0_CONF | MVL_LEDPCR_CTL1_CONF;
148 ngbe_write_phy_reg_mdi(hw, MVL_LEDPCR, 0, value);
151 hw->phy.autoneg_advertised = 0;
153 if (hw->phy.type == ngbe_phy_mvl) {
154 if (!hw->mac.autoneg) {
156 case NGBE_LINK_SPEED_1GB_FULL:
157 value = MVL_CTRL_SPEED_SELECT1;
159 case NGBE_LINK_SPEED_100M_FULL:
160 value = MVL_CTRL_SPEED_SELECT0;
162 case NGBE_LINK_SPEED_10M_FULL:
166 value = MVL_CTRL_SPEED_SELECT0 |
167 MVL_CTRL_SPEED_SELECT1;
168 DEBUGOUT("unknown speed = 0x%x.", speed);
172 value |= MVL_CTRL_DUPLEX | MVL_CTRL_RESET;
173 ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
177 if (speed & NGBE_LINK_SPEED_1GB_FULL) {
178 value_r9 |= MVL_PHY_1000BASET_FULL;
179 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
182 if (speed & NGBE_LINK_SPEED_100M_FULL) {
183 value_r4 |= MVL_PHY_100BASET_FULL;
184 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_100M_FULL;
187 if (speed & NGBE_LINK_SPEED_10M_FULL) {
188 value_r4 |= MVL_PHY_10BASET_FULL;
189 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_10M_FULL;
192 hw->phy.read_reg(hw, MVL_ANA, 0, &value);
193 value &= ~(MVL_PHY_100BASET_FULL |
194 MVL_PHY_100BASET_HALF |
195 MVL_PHY_10BASET_FULL |
196 MVL_PHY_10BASET_HALF);
198 hw->phy.write_reg(hw, MVL_ANA, 0, value_r4);
200 hw->phy.read_reg(hw, MVL_PHY_1000BASET, 0, &value);
201 value &= ~(MVL_PHY_1000BASET_FULL |
202 MVL_PHY_1000BASET_HALF);
204 hw->phy.write_reg(hw, MVL_PHY_1000BASET, 0, value_r9);
206 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
208 hw->phy.read_reg(hw, MVL_ANA, 0, &value);
209 value &= ~(MVL_PHY_1000BASEX_HALF | MVL_PHY_1000BASEX_FULL);
210 value |= MVL_PHY_1000BASEX_FULL;
211 hw->phy.write_reg(hw, MVL_ANA, 0, value);
214 value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE | MVL_CTRL_RESET;
215 ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
218 hw->phy.set_phy_power(hw, true);
220 hw->phy.read_reg(hw, MVL_INTR, 0, &value);
225 s32 ngbe_reset_phy_mvl(struct ngbe_hw *hw)
231 if (hw->phy.type != ngbe_phy_mvl && hw->phy.type != ngbe_phy_mvl_sfi)
232 return NGBE_ERR_PHY_TYPE;
234 /* select page 18 reg 20 */
235 status = ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 18);
237 /* mode select to RGMII-to-copper or RGMII-to-sfi*/
238 if (hw->phy.type == ngbe_phy_mvl)
239 ctrl = MVL_GEN_CTL_MODE_COPPER;
241 ctrl = MVL_GEN_CTL_MODE_FIBER;
242 status = ngbe_write_phy_reg_mdi(hw, MVL_GEN_CTL, 0, ctrl);
244 ctrl |= MVL_GEN_CTL_RESET;
245 status = ngbe_write_phy_reg_mdi(hw, MVL_GEN_CTL, 0, ctrl);
247 for (i = 0; i < MVL_PHY_RST_WAIT_PERIOD; i++) {
248 status = ngbe_read_phy_reg_mdi(hw, MVL_GEN_CTL, 0, &ctrl);
249 if (!(ctrl & MVL_GEN_CTL_RESET))
254 if (i == MVL_PHY_RST_WAIT_PERIOD) {
255 DEBUGOUT("PHY reset polling failed to complete.");
256 return NGBE_ERR_RESET_FAILED;
262 s32 ngbe_get_phy_advertised_pause_mvl(struct ngbe_hw *hw, u8 *pause_bit)
267 if (hw->phy.type == ngbe_phy_mvl) {
268 status = hw->phy.read_reg(hw, MVL_ANA, 0, &value);
269 value &= MVL_CANA_ASM_PAUSE | MVL_CANA_PAUSE;
270 *pause_bit = (u8)(value >> 10);
272 status = hw->phy.read_reg(hw, MVL_ANA, 0, &value);
273 value &= MVL_FANA_PAUSE_MASK;
274 *pause_bit = (u8)(value >> 7);
280 s32 ngbe_get_phy_lp_advertised_pause_mvl(struct ngbe_hw *hw, u8 *pause_bit)
285 if (hw->phy.type == ngbe_phy_mvl) {
286 status = hw->phy.read_reg(hw, MVL_LPAR, 0, &value);
287 value &= MVL_CLPAR_ASM_PAUSE | MVL_CLPAR_PAUSE;
288 *pause_bit = (u8)(value >> 10);
290 status = hw->phy.read_reg(hw, MVL_LPAR, 0, &value);
291 value &= MVL_FLPAR_PAUSE_MASK;
292 *pause_bit = (u8)(value >> 7);
298 s32 ngbe_set_phy_pause_adv_mvl(struct ngbe_hw *hw, u16 pause_bit)
303 if (hw->phy.type == ngbe_phy_mvl) {
304 status = hw->phy.read_reg(hw, MVL_ANA, 0, &value);
305 value &= ~(MVL_CANA_ASM_PAUSE | MVL_CANA_PAUSE);
307 status = hw->phy.read_reg(hw, MVL_ANA, 0, &value);
308 value &= ~MVL_FANA_PAUSE_MASK;
312 status = hw->phy.write_reg(hw, MVL_ANA, 0, value);
317 s32 ngbe_check_phy_link_mvl(struct ngbe_hw *hw,
318 u32 *speed, bool *link_up)
326 /* Initialize speed and link to default case */
328 *speed = NGBE_LINK_SPEED_UNKNOWN;
330 hw->phy.read_reg(hw, MVL_INTR, 0, &insr);
333 * Check current speed and link status of the PHY register.
334 * This is a vendor specific register and may have to
335 * be changed for other copper PHYs.
337 status = hw->phy.read_reg(hw, MVL_PHYSR, 0, &phy_data);
338 phy_link = phy_data & MVL_PHYSR_LINK;
339 phy_speed = phy_data & MVL_PHYSR_SPEED_MASK;
341 if (phy_link == MVL_PHYSR_LINK) {
344 if (phy_speed == MVL_PHYSR_SPEED_1000M)
345 *speed = NGBE_LINK_SPEED_1GB_FULL;
346 else if (phy_speed == MVL_PHYSR_SPEED_100M)
347 *speed = NGBE_LINK_SPEED_100M_FULL;
348 else if (phy_speed == MVL_PHYSR_SPEED_10M)
349 *speed = NGBE_LINK_SPEED_10M_FULL;
355 s32 ngbe_set_phy_power_mvl(struct ngbe_hw *hw, bool on)
359 hw->phy.read_reg(hw, MVL_CTRL, 0, &value);
361 value &= ~MVL_CTRL_PWDN;
363 value |= MVL_CTRL_PWDN;
364 hw->phy.write_reg(hw, MVL_CTRL, 0, value);