1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
5 #include "ngbe_phy_rtl.h"
7 s32 ngbe_read_phy_reg_rtl(struct ngbe_hw *hw,
8 u32 reg_addr, u32 device_type, u16 *phy_data)
13 reg.device_type = device_type;
15 ngbe_mdi_map_register(®, ®22);
17 wr32(hw, NGBE_PHY_CONFIG(RTL_PAGE_SELECT), reg22.page);
18 *phy_data = 0xFFFF & rd32(hw, NGBE_PHY_CONFIG(reg22.addr));
23 s32 ngbe_write_phy_reg_rtl(struct ngbe_hw *hw,
24 u32 reg_addr, u32 device_type, u16 phy_data)
29 reg.device_type = device_type;
31 ngbe_mdi_map_register(®, ®22);
33 wr32(hw, NGBE_PHY_CONFIG(RTL_PAGE_SELECT), reg22.page);
34 wr32(hw, NGBE_PHY_CONFIG(reg22.addr), phy_data);
39 s32 ngbe_init_phy_rtl(struct ngbe_hw *hw)
44 /* enable interrupts, only link status change and an done is allowed */
45 value = RTL_INER_LSC | RTL_INER_ANC;
46 hw->phy.write_reg(hw, RTL_INER, 0xa42, value);
48 hw->phy.read_reg(hw, RTL_INSR, 0xa43, &value);
50 for (i = 0; i < 15; i++) {
51 if (!rd32m(hw, NGBE_STAT,
52 NGBE_STAT_GPHY_IN_RST(hw->bus.lan_id)))
58 DEBUGOUT("GPhy reset exceeds maximum times.\n");
59 return NGBE_ERR_PHY_TIMEOUT;
62 hw->phy.write_reg(hw, RTL_SCR, 0xa46, RTL_SCR_EFUSE);
63 hw->phy.read_reg(hw, RTL_SCR, 0xa46, &value);
64 if (!(value & RTL_SCR_EFUSE)) {
65 DEBUGOUT("Write EFUSE failed.\n");
66 return NGBE_ERR_PHY_TIMEOUT;
69 for (i = 0; i < 1000; i++) {
70 hw->phy.read_reg(hw, RTL_INSR, 0xa43, &value);
71 if (value & RTL_INSR_ACCESS)
76 DEBUGOUT("PHY wait mdio 1 access timeout.\n");
79 hw->phy.write_reg(hw, RTL_SCR, 0xa46, RTL_SCR_EXTINI);
80 hw->phy.read_reg(hw, RTL_SCR, 0xa46, &value);
81 if (!(value & RTL_SCR_EXTINI)) {
82 DEBUGOUT("Write EXIINI failed.\n");
83 return NGBE_ERR_PHY_TIMEOUT;
86 for (i = 0; i < 1000; i++) {
87 hw->phy.read_reg(hw, RTL_INSR, 0xa43, &value);
88 if (value & RTL_INSR_ACCESS)
93 DEBUGOUT("PHY wait mdio 2 access timeout.\n");
95 for (i = 0; i < 1000; i++) {
96 hw->phy.read_reg(hw, RTL_GSR, 0xa42, &value);
97 if ((value & RTL_GSR_ST) == RTL_GSR_ST_LANON)
102 return NGBE_ERR_PHY_TIMEOUT;
108 * ngbe_setup_phy_link_rtl - Set and restart auto-neg
109 * @hw: pointer to hardware structure
111 * Restart auto-negotiation and PHY and waits for completion.
113 s32 ngbe_setup_phy_link_rtl(struct ngbe_hw *hw,
114 u32 speed, bool autoneg_wait_to_complete)
116 u16 autoneg_reg = NGBE_MII_AUTONEG_REG;
119 DEBUGFUNC("ngbe_setup_phy_link_rtl");
121 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
123 hw->phy.read_reg(hw, RTL_INSR, 0xa43, &autoneg_reg);
125 if (!hw->mac.autoneg) {
126 hw->phy.reset_hw(hw);
129 case NGBE_LINK_SPEED_1GB_FULL:
130 value = RTL_BMCR_SPEED_SELECT1;
132 case NGBE_LINK_SPEED_100M_FULL:
133 value = RTL_BMCR_SPEED_SELECT0;
135 case NGBE_LINK_SPEED_10M_FULL:
139 value = RTL_BMCR_SPEED_SELECT1 | RTL_BMCR_SPEED_SELECT0;
140 DEBUGOUT("unknown speed = 0x%x.\n", speed);
144 value |= RTL_BMCR_DUPLEX;
145 hw->phy.write_reg(hw, RTL_BMCR, RTL_DEV_ZERO, value);
151 * Clear autoneg_advertised and set new values based on input link
155 hw->phy.autoneg_advertised = 0;
157 if (speed & NGBE_LINK_SPEED_1GB_FULL)
158 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
160 if (speed & NGBE_LINK_SPEED_100M_FULL)
161 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_100M_FULL;
163 if (speed & NGBE_LINK_SPEED_10M_FULL)
164 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_10M_FULL;
167 /* disable 10/100M Half Duplex */
168 hw->phy.read_reg(hw, RTL_ANAR, RTL_DEV_ZERO, &autoneg_reg);
169 autoneg_reg &= 0xFF5F;
170 hw->phy.write_reg(hw, RTL_ANAR, RTL_DEV_ZERO, autoneg_reg);
172 /* set advertise enable according to input speed */
173 if (!(speed & NGBE_LINK_SPEED_1GB_FULL)) {
174 hw->phy.read_reg(hw, RTL_GBCR,
175 RTL_DEV_ZERO, &autoneg_reg);
176 autoneg_reg &= ~RTL_GBCR_1000F;
177 hw->phy.write_reg(hw, RTL_GBCR,
178 RTL_DEV_ZERO, autoneg_reg);
180 hw->phy.read_reg(hw, RTL_GBCR,
181 RTL_DEV_ZERO, &autoneg_reg);
182 autoneg_reg |= RTL_GBCR_1000F;
183 hw->phy.write_reg(hw, RTL_GBCR,
184 RTL_DEV_ZERO, autoneg_reg);
187 if (!(speed & NGBE_LINK_SPEED_100M_FULL)) {
188 hw->phy.read_reg(hw, RTL_ANAR,
189 RTL_DEV_ZERO, &autoneg_reg);
190 autoneg_reg &= ~RTL_ANAR_100F;
191 autoneg_reg &= ~RTL_ANAR_100H;
192 hw->phy.write_reg(hw, RTL_ANAR,
193 RTL_DEV_ZERO, autoneg_reg);
195 hw->phy.read_reg(hw, RTL_ANAR,
196 RTL_DEV_ZERO, &autoneg_reg);
197 autoneg_reg |= RTL_ANAR_100F;
198 hw->phy.write_reg(hw, RTL_ANAR,
199 RTL_DEV_ZERO, autoneg_reg);
202 if (!(speed & NGBE_LINK_SPEED_10M_FULL)) {
203 hw->phy.read_reg(hw, RTL_ANAR,
204 RTL_DEV_ZERO, &autoneg_reg);
205 autoneg_reg &= ~RTL_ANAR_10F;
206 autoneg_reg &= ~RTL_ANAR_10H;
207 hw->phy.write_reg(hw, RTL_ANAR,
208 RTL_DEV_ZERO, autoneg_reg);
210 hw->phy.read_reg(hw, RTL_ANAR,
211 RTL_DEV_ZERO, &autoneg_reg);
212 autoneg_reg |= RTL_ANAR_10F;
213 hw->phy.write_reg(hw, RTL_ANAR,
214 RTL_DEV_ZERO, autoneg_reg);
217 /* restart AN and wait AN done interrupt */
218 autoneg_reg = RTL_BMCR_RESTART_AN | RTL_BMCR_ANE;
219 hw->phy.write_reg(hw, RTL_BMCR, RTL_DEV_ZERO, autoneg_reg);
222 autoneg_reg = 0x205B;
223 hw->phy.write_reg(hw, RTL_LCR, 0xd04, autoneg_reg);
224 hw->phy.write_reg(hw, RTL_EEELCR, 0xd04, 0);
226 hw->phy.read_reg(hw, RTL_LPCR, 0xd04, &autoneg_reg);
227 autoneg_reg = autoneg_reg & 0xFFFC;
228 /* act led blinking mode set to 60ms */
230 hw->phy.write_reg(hw, RTL_LPCR, 0xd04, autoneg_reg);
235 s32 ngbe_reset_phy_rtl(struct ngbe_hw *hw)
240 DEBUGFUNC("ngbe_reset_phy_rtl");
242 value |= RTL_BMCR_RESET;
243 status = hw->phy.write_reg(hw, RTL_BMCR, RTL_DEV_ZERO, value);
250 s32 ngbe_get_phy_advertised_pause_rtl(struct ngbe_hw *hw, u8 *pause_bit)
255 status = hw->phy.read_reg(hw, RTL_ANAR, RTL_DEV_ZERO, &value);
256 value &= RTL_ANAR_APAUSE | RTL_ANAR_PAUSE;
257 *pause_bit = (u8)(value >> 10);
261 s32 ngbe_get_phy_lp_advertised_pause_rtl(struct ngbe_hw *hw, u8 *pause_bit)
266 status = hw->phy.read_reg(hw, RTL_INSR, 0xa43, &value);
268 status = hw->phy.read_reg(hw, RTL_BMSR, RTL_DEV_ZERO, &value);
269 value = value & RTL_BMSR_ANC;
271 /* if AN complete then check lp adv pause */
272 status = hw->phy.read_reg(hw, RTL_ANLPAR, RTL_DEV_ZERO, &value);
273 value &= RTL_ANLPAR_LP;
274 *pause_bit = (u8)(value >> 10);
278 s32 ngbe_set_phy_pause_adv_rtl(struct ngbe_hw *hw, u16 pause_bit)
283 status = hw->phy.read_reg(hw, RTL_ANAR, RTL_DEV_ZERO, &value);
284 value &= ~(RTL_ANAR_APAUSE | RTL_ANAR_PAUSE);
287 status = hw->phy.write_reg(hw, RTL_ANAR, RTL_DEV_ZERO, value);
292 s32 ngbe_check_phy_link_rtl(struct ngbe_hw *hw, u32 *speed, bool *link_up)
300 DEBUGFUNC("ngbe_check_phy_link_rtl");
302 hw->phy.read_reg(hw, RTL_INSR, 0xa43, &insr);
304 /* Initialize speed and link to default case */
306 *speed = NGBE_LINK_SPEED_UNKNOWN;
309 * Check current speed and link status of the PHY register.
310 * This is a vendor specific register and may have to
311 * be changed for other copper PHYs.
313 status = hw->phy.read_reg(hw, RTL_PHYSR, 0xa43, &phy_data);
314 phy_link = phy_data & RTL_PHYSR_RTLS;
315 phy_speed = phy_data & (RTL_PHYSR_SPEED_MASK | RTL_PHYSR_DP);
316 if (phy_link == RTL_PHYSR_RTLS) {
319 if (phy_speed == (RTL_PHYSR_SPEED_1000M | RTL_PHYSR_DP))
320 *speed = NGBE_LINK_SPEED_1GB_FULL;
321 else if (phy_speed == (RTL_PHYSR_SPEED_100M | RTL_PHYSR_DP))
322 *speed = NGBE_LINK_SPEED_100M_FULL;
323 else if (phy_speed == (RTL_PHYSR_SPEED_10M | RTL_PHYSR_DP))
324 *speed = NGBE_LINK_SPEED_10M_FULL;