drivers/net/ngbe/base/ngbe_phy_yt.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
   3  */
   4
   5 #include "ngbe_phy_yt.h"
   6
   7 #define YT_PHY_RST_WAIT_PERIOD          5
   8
   9 s32 ngbe_read_phy_reg_yt(struct ngbe_hw *hw,
  10                 u32 reg_addr, u32 device_type, u16 *phy_data)
  11 {
  12         mdi_reg_t reg;
  13         mdi_reg_22_t reg22;
  14
  15         reg.device_type = device_type;
  16         reg.addr = reg_addr;
  17
  18         ngbe_mdi_map_register(&reg, &reg22);
  19
  20         /* Read MII reg according to media type */
  21         if (hw->phy.media_type == ngbe_media_type_fiber) {
  22                 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,
  23                                         reg22.device_type, YT_SMI_PHY_SDS);
  24                 ngbe_read_phy_reg_mdi(hw, reg22.addr,
  25                                         reg22.device_type, phy_data);
  26                 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,
  27                                         reg22.device_type, 0);
  28         } else {
  29                 ngbe_read_phy_reg_mdi(hw, reg22.addr,
  30                                         reg22.device_type, phy_data);
  31         }
  32
  33         return 0;
  34 }
  35
  36 s32 ngbe_write_phy_reg_yt(struct ngbe_hw *hw,
  37                 u32 reg_addr, u32 device_type, u16 phy_data)
  38 {
  39         mdi_reg_t reg;
  40         mdi_reg_22_t reg22;
  41
  42         reg.device_type = device_type;
  43         reg.addr = reg_addr;
  44
  45         ngbe_mdi_map_register(&reg, &reg22);
  46
  47         /* Write MII reg according to media type */
  48         if (hw->phy.media_type == ngbe_media_type_fiber) {
  49                 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,
  50                                         reg22.device_type, YT_SMI_PHY_SDS);
  51                 ngbe_write_phy_reg_mdi(hw, reg22.addr,
  52                                         reg22.device_type, phy_data);
  53                 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,
  54                                         reg22.device_type, 0);
  55         } else {
  56                 ngbe_write_phy_reg_mdi(hw, reg22.addr,
  57                                         reg22.device_type, phy_data);
  58         }
  59
  60         return 0;
  61 }
  62
  63 s32 ngbe_read_phy_reg_ext_yt(struct ngbe_hw *hw,
  64                 u32 reg_addr, u32 device_type, u16 *phy_data)
  65 {
  66         ngbe_write_phy_reg_mdi(hw, 0x1E, device_type, reg_addr);
  67         ngbe_read_phy_reg_mdi(hw, 0x1F, device_type, phy_data);
  68
  69         return 0;
  70 }
  71
  72 s32 ngbe_write_phy_reg_ext_yt(struct ngbe_hw *hw,
  73                 u32 reg_addr, u32 device_type, u16 phy_data)
  74 {
  75         ngbe_write_phy_reg_mdi(hw, 0x1E, device_type, reg_addr);
  76         ngbe_write_phy_reg_mdi(hw, 0x1F, device_type, phy_data);
  77
  78         return 0;
  79 }
  80
  81 s32 ngbe_read_phy_reg_sds_ext_yt(struct ngbe_hw *hw,
  82                 u32 reg_addr, u32 device_type, u16 *phy_data)
  83 {
  84         ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, device_type, YT_SMI_PHY_SDS);
  85         ngbe_read_phy_reg_ext_yt(hw, reg_addr, device_type, phy_data);
  86         ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, device_type, 0);
  87
  88         return 0;
  89 }
  90
  91 s32 ngbe_write_phy_reg_sds_ext_yt(struct ngbe_hw *hw,
  92                 u32 reg_addr, u32 device_type, u16 phy_data)
  93 {
  94         ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, device_type, YT_SMI_PHY_SDS);
  95         ngbe_write_phy_reg_ext_yt(hw, reg_addr, device_type, phy_data);
  96         ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, device_type, 0);
  97
  98         return 0;
  99 }
 100
 101 s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 102                                 bool autoneg_wait_to_complete)
 103 {
 104         u16 value_r4 = 0;
 105         u16 value_r9 = 0;
 106         u16 value;
 107
 108         DEBUGFUNC("ngbe_setup_phy_link_yt");
 109         UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
 110
 111         hw->phy.autoneg_advertised = 0;
 112
 113         if (hw->phy.type == ngbe_phy_yt8521s) {
 114                 /*disable 100/10base-T Self-negotiation ability*/
 115                 hw->phy.read_reg(hw, YT_ANA, 0, &value);
 116                 value &= ~(YT_ANA_100BASET_FULL | YT_ANA_10BASET_FULL);
 117                 hw->phy.write_reg(hw, YT_ANA, 0, value);
 118
 119                 /*disable 1000base-T Self-negotiation ability*/
 120                 hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
 121                 value &= ~YT_MS_1000BASET_FULL;
 122                 hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
 123
 124                 if (speed & NGBE_LINK_SPEED_1GB_FULL) {
 125                         hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
 126                         value_r9 |= YT_MS_1000BASET_FULL;
 127                 }
 128                 if (speed & NGBE_LINK_SPEED_100M_FULL) {
 129                         hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_100M_FULL;
 130                         value_r4 |= YT_ANA_100BASET_FULL;
 131                 }
 132                 if (speed & NGBE_LINK_SPEED_10M_FULL) {
 133                         hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_10M_FULL;
 134                         value_r4 |= YT_ANA_10BASET_FULL;
 135                 }
 136
 137                 /* enable 1000base-T Self-negotiation ability */
 138                 hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
 139                 value |= value_r9;
 140                 hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
 141
 142                 /* enable 100/10base-T Self-negotiation ability */
 143                 hw->phy.read_reg(hw, YT_ANA, 0, &value);
 144                 value |= value_r4;
 145                 hw->phy.write_reg(hw, YT_ANA, 0, value);
 146
 147                 /* software reset to make the above configuration take effect*/
 148                 hw->phy.read_reg(hw, YT_BCR, 0, &value);
 149                 value |= YT_BCR_RESET;
 150                 hw->phy.write_reg(hw, YT_BCR, 0, value);
 151         } else {
 152                 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
 153
 154                 /* RGMII_Config1 : Config rx and tx training delay */
 155                 value = YT_RGMII_CONF1_RXDELAY |
 156                         YT_RGMII_CONF1_TXDELAY_FE |
 157                         YT_RGMII_CONF1_TXDELAY;
 158                 ngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, value);
 159                 value = YT_CHIP_MODE_SEL(1) |
 160                         YT_CHIP_SW_LDO_EN |
 161                         YT_CHIP_SW_RST;
 162                 ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);
 163
 164                 /* software reset */
 165                 ngbe_write_phy_reg_sds_ext_yt(hw, 0x0, 0, 0x9140);
 166
 167                 /* power on phy */
 168                 hw->phy.read_reg(hw, YT_BCR, 0, &value);
 169                 value &= ~YT_BCR_PWDN;
 170                 hw->phy.write_reg(hw, YT_BCR, 0, value);
 171         }
 172
 173         ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);
 174         ngbe_read_phy_reg_mdi(hw, YT_INTR_STATUS, 0, &value);
 175
 176         return 0;
 177 }
 178
 179 s32 ngbe_reset_phy_yt(struct ngbe_hw *hw)
 180 {
 181         u32 i;
 182         u16 ctrl = 0;
 183         s32 status = 0;
 184
 185         DEBUGFUNC("ngbe_reset_phy_yt");
 186
 187         if (hw->phy.type != ngbe_phy_yt8521s &&
 188                 hw->phy.type != ngbe_phy_yt8521s_sfi)
 189                 return NGBE_ERR_PHY_TYPE;
 190
 191         status = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl);
 192         /* sds software reset */
 193         ctrl |= YT_BCR_RESET;
 194         status = hw->phy.write_reg(hw, YT_BCR, 0, ctrl);
 195
 196         for (i = 0; i < YT_PHY_RST_WAIT_PERIOD; i++) {
 197                 status = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl);
 198                 if (!(ctrl & YT_BCR_RESET))
 199                         break;
 200                 msleep(1);
 201         }
 202
 203         if (i == YT_PHY_RST_WAIT_PERIOD) {
 204                 DEBUGOUT("PHY reset polling failed to complete.\n");
 205                 return NGBE_ERR_RESET_FAILED;
 206         }
 207
 208         return status;
 209 }
 210
 211 s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw,
 212                 u32 *speed, bool *link_up)
 213 {
 214         s32 status = 0;
 215         u16 phy_link = 0;
 216         u16 phy_speed = 0;
 217         u16 phy_data = 0;
 218         u16 insr = 0;
 219
 220         DEBUGFUNC("ngbe_check_phy_link_yt");
 221
 222         /* Initialize speed and link to default case */
 223         *link_up = false;
 224         *speed = NGBE_LINK_SPEED_UNKNOWN;
 225
 226         ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);
 227         ngbe_read_phy_reg_mdi(hw, YT_INTR_STATUS, 0, &insr);
 228
 229         status = hw->phy.read_reg(hw, YT_SPST, 0, &phy_data);
 230         phy_link = phy_data & YT_SPST_LINK;
 231         phy_speed = phy_data & YT_SPST_SPEED_MASK;
 232
 233         if (phy_link) {
 234                 *link_up = true;
 235
 236                 if (phy_speed == YT_SPST_SPEED_1000M)
 237                         *speed = NGBE_LINK_SPEED_1GB_FULL;
 238                 else if (phy_speed == YT_SPST_SPEED_100M)
 239                         *speed = NGBE_LINK_SPEED_100M_FULL;
 240                 else if (phy_speed == YT_SPST_SPEED_10M)
 241                         *speed = NGBE_LINK_SPEED_10M_FULL;
 242         }
 243
 244         return status;
 245 }
 246