drivers/net/ngbe/base/ngbe_phy_yt.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
   3  */
   4
   5 #include "ngbe_phy_yt.h"
   6
   7 #define YT_PHY_RST_WAIT_PERIOD          5
   8
   9 s32 ngbe_read_phy_reg_yt(struct ngbe_hw *hw,
  10                 u32 reg_addr, u32 device_type, u16 *phy_data)
  11 {
  12         mdi_reg_t reg;
  13         mdi_reg_22_t reg22;
  14
  15         reg.device_type = device_type;
  16         reg.addr = reg_addr;
  17
  18         ngbe_mdi_map_register(&reg, &reg22);
  19
  20         /* Read MII reg according to media type */
  21         if (hw->phy.media_type == ngbe_media_type_fiber) {
  22                 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,
  23                                         reg22.device_type, YT_SMI_PHY_SDS);
  24                 ngbe_read_phy_reg_mdi(hw, reg22.addr,
  25                                         reg22.device_type, phy_data);
  26                 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,
  27                                         reg22.device_type, 0);
  28         } else {
  29                 ngbe_read_phy_reg_mdi(hw, reg22.addr,
  30                                         reg22.device_type, phy_data);
  31         }
  32
  33         return 0;
  34 }
  35
  36 s32 ngbe_write_phy_reg_yt(struct ngbe_hw *hw,
  37                 u32 reg_addr, u32 device_type, u16 phy_data)
  38 {
  39         mdi_reg_t reg;
  40         mdi_reg_22_t reg22;
  41
  42         reg.device_type = device_type;
  43         reg.addr = reg_addr;
  44
  45         ngbe_mdi_map_register(&reg, &reg22);
  46
  47         /* Write MII reg according to media type */
  48         if (hw->phy.media_type == ngbe_media_type_fiber) {
  49                 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,
  50                                         reg22.device_type, YT_SMI_PHY_SDS);
  51                 ngbe_write_phy_reg_mdi(hw, reg22.addr,
  52                                         reg22.device_type, phy_data);
  53                 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,
  54                                         reg22.device_type, 0);
  55         } else {
  56                 ngbe_write_phy_reg_mdi(hw, reg22.addr,
  57                                         reg22.device_type, phy_data);
  58         }
  59
  60         return 0;
  61 }
  62
  63 s32 ngbe_read_phy_reg_ext_yt(struct ngbe_hw *hw,
  64                 u32 reg_addr, u32 device_type, u16 *phy_data)
  65 {
  66         ngbe_write_phy_reg_mdi(hw, 0x1E, device_type, reg_addr);
  67         ngbe_read_phy_reg_mdi(hw, 0x1F, device_type, phy_data);
  68
  69         return 0;
  70 }
  71
  72 s32 ngbe_write_phy_reg_ext_yt(struct ngbe_hw *hw,
  73                 u32 reg_addr, u32 device_type, u16 phy_data)
  74 {
  75         ngbe_write_phy_reg_mdi(hw, 0x1E, device_type, reg_addr);
  76         ngbe_write_phy_reg_mdi(hw, 0x1F, device_type, phy_data);
  77
  78         return 0;
  79 }
  80
  81 s32 ngbe_reset_phy_yt(struct ngbe_hw *hw)
  82 {
  83         u32 i;
  84         u16 ctrl = 0;
  85         s32 status = 0;
  86
  87         DEBUGFUNC("ngbe_reset_phy_yt");
  88
  89         if (hw->phy.type != ngbe_phy_yt8521s &&
  90                 hw->phy.type != ngbe_phy_yt8521s_sfi)
  91                 return NGBE_ERR_PHY_TYPE;
  92
  93         status = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl);
  94         /* sds software reset */
  95         ctrl |= YT_BCR_RESET;
  96         status = hw->phy.write_reg(hw, YT_BCR, 0, ctrl);
  97
  98         for (i = 0; i < YT_PHY_RST_WAIT_PERIOD; i++) {
  99                 status = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl);
 100                 if (!(ctrl & YT_BCR_RESET))
 101                         break;
 102                 msleep(1);
 103         }
 104
 105         if (i == YT_PHY_RST_WAIT_PERIOD) {
 106                 DEBUGOUT("PHY reset polling failed to complete.\n");
 107                 return NGBE_ERR_RESET_FAILED;
 108         }
 109
 110         return status;
 111 }
 112