1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
5 #include "ngbe_phy_yt.h"
7 #define YT_PHY_RST_WAIT_PERIOD 5
9 s32 ngbe_read_phy_reg_yt(struct ngbe_hw *hw,
10 u32 reg_addr, u32 device_type, u16 *phy_data)
15 reg.device_type = device_type;
18 ngbe_mdi_map_register(®, ®22);
20 /* Read MII reg according to media type */
21 if (hw->phy.media_type == ngbe_media_type_fiber) {
22 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,
23 reg22.device_type, YT_SMI_PHY_SDS);
24 ngbe_read_phy_reg_mdi(hw, reg22.addr,
25 reg22.device_type, phy_data);
26 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,
27 reg22.device_type, 0);
29 ngbe_read_phy_reg_mdi(hw, reg22.addr,
30 reg22.device_type, phy_data);
36 s32 ngbe_write_phy_reg_yt(struct ngbe_hw *hw,
37 u32 reg_addr, u32 device_type, u16 phy_data)
42 reg.device_type = device_type;
45 ngbe_mdi_map_register(®, ®22);
47 /* Write MII reg according to media type */
48 if (hw->phy.media_type == ngbe_media_type_fiber) {
49 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,
50 reg22.device_type, YT_SMI_PHY_SDS);
51 ngbe_write_phy_reg_mdi(hw, reg22.addr,
52 reg22.device_type, phy_data);
53 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,
54 reg22.device_type, 0);
56 ngbe_write_phy_reg_mdi(hw, reg22.addr,
57 reg22.device_type, phy_data);
63 s32 ngbe_read_phy_reg_ext_yt(struct ngbe_hw *hw,
64 u32 reg_addr, u32 device_type, u16 *phy_data)
66 ngbe_write_phy_reg_mdi(hw, 0x1E, device_type, reg_addr);
67 ngbe_read_phy_reg_mdi(hw, 0x1F, device_type, phy_data);
72 s32 ngbe_write_phy_reg_ext_yt(struct ngbe_hw *hw,
73 u32 reg_addr, u32 device_type, u16 phy_data)
75 ngbe_write_phy_reg_mdi(hw, 0x1E, device_type, reg_addr);
76 ngbe_write_phy_reg_mdi(hw, 0x1F, device_type, phy_data);
81 s32 ngbe_read_phy_reg_sds_ext_yt(struct ngbe_hw *hw,
82 u32 reg_addr, u32 device_type, u16 *phy_data)
84 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, device_type, YT_SMI_PHY_SDS);
85 ngbe_read_phy_reg_ext_yt(hw, reg_addr, device_type, phy_data);
86 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, device_type, 0);
91 s32 ngbe_write_phy_reg_sds_ext_yt(struct ngbe_hw *hw,
92 u32 reg_addr, u32 device_type, u16 phy_data)
94 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, device_type, YT_SMI_PHY_SDS);
95 ngbe_write_phy_reg_ext_yt(hw, reg_addr, device_type, phy_data);
96 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, device_type, 0);
101 s32 ngbe_init_phy_yt(struct ngbe_hw *hw)
105 /* close sds area register */
106 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);
107 /* enable interrupts */
108 ngbe_write_phy_reg_mdi(hw, YT_INTR, 0,
109 YT_INTR_ENA_MASK | YT_SDS_INTR_ENA_MASK);
111 /* power down in fiber mode */
112 hw->phy.read_reg(hw, YT_BCR, 0, &value);
113 value |= YT_BCR_PWDN;
114 hw->phy.write_reg(hw, YT_BCR, 0, value);
116 /* power down in UTP mode */
117 ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
118 value |= YT_BCR_PWDN;
119 ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
124 s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
125 bool autoneg_wait_to_complete)
131 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
133 hw->phy.autoneg_advertised = 0;
135 /* check chip_mode first */
136 ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value);
137 if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(0)) {
139 if (!hw->mac.autoneg) {
141 case NGBE_LINK_SPEED_1GB_FULL:
142 value = YT_BCR_SPEED_SELECT1;
144 case NGBE_LINK_SPEED_100M_FULL:
145 value = YT_BCR_SPEED_SELECT0;
147 case NGBE_LINK_SPEED_10M_FULL:
151 value = YT_BCR_SPEED_SELECT0 |
152 YT_BCR_SPEED_SELECT1;
153 DEBUGOUT("unknown speed = 0x%x.",
158 value |= YT_BCR_DUPLEX | YT_BCR_RESET;
159 hw->phy.write_reg(hw, YT_BCR, 0, value);
164 /*disable 100/10base-T Self-negotiation ability*/
165 hw->phy.read_reg(hw, YT_ANA, 0, &value);
166 value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF |
167 YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF);
168 hw->phy.write_reg(hw, YT_ANA, 0, value);
170 /*disable 1000base-T Self-negotiation ability*/
171 hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
172 value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF);
173 hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
175 if (speed & NGBE_LINK_SPEED_1GB_FULL) {
176 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
177 value_r9 |= YT_MS_1000BASET_FULL;
179 if (speed & NGBE_LINK_SPEED_100M_FULL) {
180 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_100M_FULL;
181 value_r4 |= YT_ANA_100BASET_FULL;
183 if (speed & NGBE_LINK_SPEED_10M_FULL) {
184 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_10M_FULL;
185 value_r4 |= YT_ANA_10BASET_FULL;
188 /* enable 1000base-T Self-negotiation ability */
189 hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
191 hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
193 /* enable 100/10base-T Self-negotiation ability */
194 hw->phy.read_reg(hw, YT_ANA, 0, &value);
196 hw->phy.write_reg(hw, YT_ANA, 0, value);
198 /* software reset to make the above configuration take effect*/
199 hw->phy.read_reg(hw, YT_BCR, 0, &value);
200 value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN;
201 hw->phy.write_reg(hw, YT_BCR, 0, value);
203 /* power on in UTP mode */
204 ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
205 value &= ~YT_BCR_PWDN;
206 ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
207 } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) {
209 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
211 /* RGMII_Config1 : Config rx and tx training delay */
212 value = YT_RGMII_CONF1_RXDELAY |
213 YT_RGMII_CONF1_TXDELAY_FE |
214 YT_RGMII_CONF1_TXDELAY;
215 ngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, value);
216 value = YT_CHIP_MODE_SEL(1) |
219 ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);
222 ngbe_write_phy_reg_sds_ext_yt(hw, 0x0, 0, 0x9140);
225 hw->phy.read_reg(hw, YT_BCR, 0, &value);
226 value &= ~YT_BCR_PWDN;
227 hw->phy.write_reg(hw, YT_BCR, 0, value);
228 } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) {
229 /* power on in UTP mode */
230 ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
231 value &= ~YT_BCR_PWDN;
232 ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
233 /* power down in fiber mode */
234 hw->phy.read_reg(hw, YT_BCR, 0, &value);
235 value &= ~YT_BCR_PWDN;
236 hw->phy.write_reg(hw, YT_BCR, 0, value);
238 hw->phy.read_reg(hw, YT_SPST, 0, &value);
239 if (value & YT_SPST_LINK) {
241 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
244 /*disable 100/10base-T Self-negotiation ability*/
245 hw->phy.read_reg(hw, YT_ANA, 0, &value);
246 value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF |
247 YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF);
248 hw->phy.write_reg(hw, YT_ANA, 0, value);
250 /*disable 1000base-T Self-negotiation ability*/
251 hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
252 value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF);
253 hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
255 if (speed & NGBE_LINK_SPEED_1GB_FULL) {
256 hw->phy.autoneg_advertised |=
257 NGBE_LINK_SPEED_1GB_FULL;
258 value_r9 |= YT_MS_1000BASET_FULL;
260 if (speed & NGBE_LINK_SPEED_100M_FULL) {
261 hw->phy.autoneg_advertised |=
262 NGBE_LINK_SPEED_100M_FULL;
263 value_r4 |= YT_ANA_100BASET_FULL;
265 if (speed & NGBE_LINK_SPEED_10M_FULL) {
266 hw->phy.autoneg_advertised |=
267 NGBE_LINK_SPEED_10M_FULL;
268 value_r4 |= YT_ANA_10BASET_FULL;
271 /* enable 1000base-T Self-negotiation ability */
272 hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
274 hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
276 /* enable 100/10base-T Self-negotiation ability */
277 hw->phy.read_reg(hw, YT_ANA, 0, &value);
279 hw->phy.write_reg(hw, YT_ANA, 0, value);
281 /* software reset to make the above configuration
284 hw->phy.read_reg(hw, YT_BCR, 0, &value);
285 value |= YT_BCR_RESET;
286 hw->phy.write_reg(hw, YT_BCR, 0, value);
288 } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(4)) {
289 hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
291 ngbe_read_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, &value);
292 value |= YT_RGMII_CONF1_MODE;
293 ngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, value);
295 ngbe_read_phy_reg_ext_yt(hw, YT_RGMII_CONF2, 0, &value);
296 value &= ~(YT_RGMII_CONF2_SPEED_MASK | YT_RGMII_CONF2_DUPLEX |
297 YT_RGMII_CONF2_LINKUP);
298 value |= YT_RGMII_CONF2_SPEED(2) | YT_RGMII_CONF2_DUPLEX |
299 YT_RGMII_CONF2_LINKUP;
300 ngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF2, 0, value);
302 ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value);
303 value &= ~YT_SMI_PHY_SW_RST;
304 ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);
307 hw->phy.read_reg(hw, YT_BCR, 0, &value);
308 value &= ~YT_BCR_PWDN;
309 hw->phy.write_reg(hw, YT_BCR, 0, value);
312 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);
313 ngbe_read_phy_reg_mdi(hw, YT_INTR_STATUS, 0, &value);
318 s32 ngbe_reset_phy_yt(struct ngbe_hw *hw)
324 if (hw->phy.type != ngbe_phy_yt8521s &&
325 hw->phy.type != ngbe_phy_yt8521s_sfi)
326 return NGBE_ERR_PHY_TYPE;
328 /* check chip_mode first */
329 ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &ctrl);
330 if (ctrl & YT_CHIP_MODE_MASK) {
332 status = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl);
333 /* sds software reset */
334 ctrl |= YT_BCR_RESET;
335 status = hw->phy.write_reg(hw, YT_BCR, 0, ctrl);
337 for (i = 0; i < YT_PHY_RST_WAIT_PERIOD; i++) {
338 status = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl);
339 if (!(ctrl & YT_BCR_RESET))
345 status = ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &ctrl);
346 /* sds software reset */
347 ctrl |= YT_BCR_RESET;
348 status = ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, ctrl);
350 for (i = 0; i < YT_PHY_RST_WAIT_PERIOD; i++) {
351 status = ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &ctrl);
352 if (!(ctrl & YT_BCR_RESET))
358 if (i == YT_PHY_RST_WAIT_PERIOD) {
359 DEBUGOUT("PHY reset polling failed to complete.");
360 return NGBE_ERR_RESET_FAILED;
366 s32 ngbe_get_phy_advertised_pause_yt(struct ngbe_hw *hw, u8 *pause_bit)
371 status = hw->phy.read_reg(hw, YT_ANA, 0, &value);
372 value &= YT_FANA_PAUSE_MASK;
373 *pause_bit = (u8)(value >> 7);
378 s32 ngbe_get_phy_lp_advertised_pause_yt(struct ngbe_hw *hw, u8 *pause_bit)
383 status = hw->phy.read_reg(hw, YT_LPAR, 0, &value);
384 value &= YT_FLPAR_PAUSE_MASK;
385 *pause_bit = (u8)(value >> 7);
390 s32 ngbe_set_phy_pause_adv_yt(struct ngbe_hw *hw, u16 pause_bit)
395 status = hw->phy.read_reg(hw, YT_ANA, 0, &value);
396 value &= ~YT_FANA_PAUSE_MASK;
398 status = hw->phy.write_reg(hw, YT_ANA, 0, value);
403 s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw,
404 u32 *speed, bool *link_up)
412 /* Initialize speed and link to default case */
414 *speed = NGBE_LINK_SPEED_UNKNOWN;
416 ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);
417 ngbe_read_phy_reg_mdi(hw, YT_INTR_STATUS, 0, &insr);
419 status = hw->phy.read_reg(hw, YT_SPST, 0, &phy_data);
420 phy_link = phy_data & YT_SPST_LINK;
421 phy_speed = phy_data & YT_SPST_SPEED_MASK;
426 if (phy_speed == YT_SPST_SPEED_1000M)
427 *speed = NGBE_LINK_SPEED_1GB_FULL;
428 else if (phy_speed == YT_SPST_SPEED_100M)
429 *speed = NGBE_LINK_SPEED_100M_FULL;
430 else if (phy_speed == YT_SPST_SPEED_10M)
431 *speed = NGBE_LINK_SPEED_10M_FULL;