1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
7 #include <rte_common.h>
8 #include <ethdev_pci.h>
10 #include <rte_alarm.h>
12 #include "ngbe_logs.h"
14 #include "ngbe_ethdev.h"
15 #include "ngbe_rxtx.h"
17 static int ngbe_dev_close(struct rte_eth_dev *dev);
18 static int ngbe_dev_link_update(struct rte_eth_dev *dev,
19 int wait_to_complete);
21 static void ngbe_dev_link_status_print(struct rte_eth_dev *dev);
22 static int ngbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
23 static int ngbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
24 static int ngbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev);
25 static int ngbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
26 static void ngbe_dev_interrupt_handler(void *param);
27 static void ngbe_dev_interrupt_delayed_handler(void *param);
28 static void ngbe_configure_msix(struct rte_eth_dev *dev);
31 * The set of PCI devices this driver supports
33 static const struct rte_pci_id pci_id_ngbe_map[] = {
34 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A2) },
35 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A2S) },
36 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A4) },
37 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A4S) },
38 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL2) },
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL2S) },
40 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL4) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL4S) },
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860NCSI) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A1) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A1L) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL_W) },
46 { .vendor_id = 0, /* sentinel */ },
49 static const struct rte_eth_desc_lim rx_desc_lim = {
50 .nb_max = NGBE_RING_DESC_MAX,
51 .nb_min = NGBE_RING_DESC_MIN,
52 .nb_align = NGBE_RXD_ALIGN,
55 static const struct rte_eth_desc_lim tx_desc_lim = {
56 .nb_max = NGBE_RING_DESC_MAX,
57 .nb_min = NGBE_RING_DESC_MIN,
58 .nb_align = NGBE_TXD_ALIGN,
59 .nb_seg_max = NGBE_TX_MAX_SEG,
60 .nb_mtu_seg_max = NGBE_TX_MAX_SEG,
63 static const struct eth_dev_ops ngbe_eth_dev_ops;
66 ngbe_pf_reset_hw(struct ngbe_hw *hw)
71 status = hw->mac.reset_hw(hw);
73 ctrl_ext = rd32(hw, NGBE_PORTCTL);
74 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
75 ctrl_ext |= NGBE_PORTCTL_RSTDONE;
76 wr32(hw, NGBE_PORTCTL, ctrl_ext);
79 if (status == NGBE_ERR_SFP_NOT_PRESENT)
85 ngbe_enable_intr(struct rte_eth_dev *dev)
87 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
88 struct ngbe_hw *hw = ngbe_dev_hw(dev);
90 wr32(hw, NGBE_IENMISC, intr->mask_misc);
91 wr32(hw, NGBE_IMC(0), intr->mask & BIT_MASK32);
96 ngbe_disable_intr(struct ngbe_hw *hw)
98 PMD_INIT_FUNC_TRACE();
100 wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK);
105 * Ensure that all locks are released before first NVM or PHY access
108 ngbe_swfw_lock_reset(struct ngbe_hw *hw)
113 * These ones are more tricky since they are common to all ports; but
114 * swfw_sync retries last long enough (1s) to be almost sure that if
115 * lock can not be taken it is due to an improper lock of the
118 mask = NGBE_MNGSEM_SWPHY |
121 if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
122 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
124 hw->mac.release_swfw_sync(hw, mask);
128 eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
130 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
131 struct ngbe_hw *hw = ngbe_dev_hw(eth_dev);
132 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
133 const struct rte_memzone *mz;
137 PMD_INIT_FUNC_TRACE();
139 eth_dev->dev_ops = &ngbe_eth_dev_ops;
141 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
144 rte_eth_copy_pci_info(eth_dev, pci_dev);
146 /* Vendor and Device ID need to be set before init of shared code */
147 hw->device_id = pci_dev->id.device_id;
148 hw->vendor_id = pci_dev->id.vendor_id;
149 hw->sub_system_id = pci_dev->id.subsystem_device_id;
150 ngbe_map_device_id(hw);
151 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
153 /* Reserve memory for interrupt status block */
154 mz = rte_eth_dma_zone_reserve(eth_dev, "ngbe_driver", -1,
155 NGBE_ISB_SIZE, NGBE_ALIGN, SOCKET_ID_ANY);
159 hw->isb_dma = TMZ_PADDR(mz);
160 hw->isb_mem = TMZ_VADDR(mz);
162 /* Initialize the shared code (base driver) */
163 err = ngbe_init_shared_code(hw);
165 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
169 /* Unlock any pending hardware semaphore */
170 ngbe_swfw_lock_reset(hw);
172 err = hw->rom.init_params(hw);
174 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
178 /* Make sure we have a good EEPROM before we read from it */
179 err = hw->rom.validate_checksum(hw, NULL);
181 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
185 err = hw->mac.init_hw(hw);
187 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
191 /* disable interrupt */
192 ngbe_disable_intr(hw);
194 /* Allocate memory for storing MAC addresses */
195 eth_dev->data->mac_addrs = rte_zmalloc("ngbe", RTE_ETHER_ADDR_LEN *
196 hw->mac.num_rar_entries, 0);
197 if (eth_dev->data->mac_addrs == NULL) {
199 "Failed to allocate %u bytes needed to store MAC addresses",
200 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
204 /* Copy the permanent MAC address */
205 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
206 ð_dev->data->mac_addrs[0]);
208 /* Allocate memory for storing hash filter MAC addresses */
209 eth_dev->data->hash_mac_addrs = rte_zmalloc("ngbe",
210 RTE_ETHER_ADDR_LEN * NGBE_VMDQ_NUM_UC_MAC, 0);
211 if (eth_dev->data->hash_mac_addrs == NULL) {
213 "Failed to allocate %d bytes needed to store MAC addresses",
214 RTE_ETHER_ADDR_LEN * NGBE_VMDQ_NUM_UC_MAC);
215 rte_free(eth_dev->data->mac_addrs);
216 eth_dev->data->mac_addrs = NULL;
220 ctrl_ext = rd32(hw, NGBE_PORTCTL);
221 /* let hardware know driver is loaded */
222 ctrl_ext |= NGBE_PORTCTL_DRVLOAD;
223 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
224 ctrl_ext |= NGBE_PORTCTL_RSTDONE;
225 wr32(hw, NGBE_PORTCTL, ctrl_ext);
228 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
229 (int)hw->mac.type, (int)hw->phy.type);
231 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
232 eth_dev->data->port_id, pci_dev->id.vendor_id,
233 pci_dev->id.device_id);
235 rte_intr_callback_register(intr_handle,
236 ngbe_dev_interrupt_handler, eth_dev);
238 /* enable uio/vfio intr/eventfd mapping */
239 rte_intr_enable(intr_handle);
241 /* enable support intr */
242 ngbe_enable_intr(eth_dev);
248 eth_ngbe_dev_uninit(struct rte_eth_dev *eth_dev)
250 PMD_INIT_FUNC_TRACE();
252 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
255 ngbe_dev_close(eth_dev);
261 eth_ngbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
262 struct rte_pci_device *pci_dev)
264 return rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
265 sizeof(struct ngbe_adapter),
266 eth_dev_pci_specific_init, pci_dev,
267 eth_ngbe_dev_init, NULL);
270 static int eth_ngbe_pci_remove(struct rte_pci_device *pci_dev)
272 struct rte_eth_dev *ethdev;
274 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
278 return rte_eth_dev_destroy(ethdev, eth_ngbe_dev_uninit);
281 static struct rte_pci_driver rte_ngbe_pmd = {
282 .id_table = pci_id_ngbe_map,
283 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
284 RTE_PCI_DRV_INTR_LSC,
285 .probe = eth_ngbe_pci_probe,
286 .remove = eth_ngbe_pci_remove,
290 ngbe_dev_configure(struct rte_eth_dev *dev)
292 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
293 struct ngbe_adapter *adapter = ngbe_dev_adapter(dev);
295 PMD_INIT_FUNC_TRACE();
297 /* set flag to update link status after init */
298 intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE;
301 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
302 * allocation Rx preconditions we will reset it.
304 adapter->rx_bulk_alloc_allowed = true;
310 ngbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
312 struct ngbe_hw *hw = ngbe_dev_hw(dev);
313 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
315 wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));
316 wr32(hw, NGBE_GPIOINTEN, NGBE_GPIOINTEN_INT(3));
317 wr32(hw, NGBE_GPIOINTTYPE, NGBE_GPIOINTTYPE_LEVEL(0));
318 if (hw->phy.type == ngbe_phy_yt8521s_sfi)
319 wr32(hw, NGBE_GPIOINTPOL, NGBE_GPIOINTPOL_ACT(0));
321 wr32(hw, NGBE_GPIOINTPOL, NGBE_GPIOINTPOL_ACT(3));
323 intr->mask_misc |= NGBE_ICRMISC_GPIO;
327 * Configure device link speed and setup link.
328 * It returns 0 on success.
331 ngbe_dev_start(struct rte_eth_dev *dev)
333 struct ngbe_hw *hw = ngbe_dev_hw(dev);
334 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
335 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
336 uint32_t intr_vector = 0;
338 bool link_up = false, negotiate = false;
340 uint32_t allowed_speeds = 0;
342 uint32_t *link_speeds;
344 PMD_INIT_FUNC_TRACE();
346 /* disable uio/vfio intr/eventfd mapping */
347 rte_intr_disable(intr_handle);
350 hw->adapter_stopped = 0;
353 /* reinitialize adapter, this calls reset and start */
354 hw->nb_rx_queues = dev->data->nb_rx_queues;
355 hw->nb_tx_queues = dev->data->nb_tx_queues;
356 status = ngbe_pf_reset_hw(hw);
359 hw->mac.start_hw(hw);
360 hw->mac.get_link_status = true;
362 ngbe_dev_phy_intr_setup(dev);
364 /* check and configure queue intr-vector mapping */
365 if ((rte_intr_cap_multiple(intr_handle) ||
366 !RTE_ETH_DEV_SRIOV(dev).active) &&
367 dev->data->dev_conf.intr_conf.rxq != 0) {
368 intr_vector = dev->data->nb_rx_queues;
369 if (rte_intr_efd_enable(intr_handle, intr_vector))
373 if (rte_intr_dp_is_en(intr_handle) && intr_handle->intr_vec == NULL) {
374 intr_handle->intr_vec =
375 rte_zmalloc("intr_vec",
376 dev->data->nb_rx_queues * sizeof(int), 0);
377 if (intr_handle->intr_vec == NULL) {
379 "Failed to allocate %d rx_queues intr_vec",
380 dev->data->nb_rx_queues);
385 /* confiugre MSI-X for sleep until Rx interrupt */
386 ngbe_configure_msix(dev);
388 /* initialize transmission unit */
389 ngbe_dev_tx_init(dev);
391 /* This can fail when allocating mbufs for descriptor rings */
392 err = ngbe_dev_rx_init(dev);
394 PMD_INIT_LOG(ERR, "Unable to initialize Rx hardware");
398 err = ngbe_dev_rxtx_start(dev);
400 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
404 err = hw->mac.check_link(hw, &speed, &link_up, 0);
407 dev->data->dev_link.link_status = link_up;
409 link_speeds = &dev->data->dev_conf.link_speeds;
410 if (*link_speeds == ETH_LINK_SPEED_AUTONEG)
413 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
418 if (hw->mac.default_speeds & NGBE_LINK_SPEED_1GB_FULL)
419 allowed_speeds |= ETH_LINK_SPEED_1G;
420 if (hw->mac.default_speeds & NGBE_LINK_SPEED_100M_FULL)
421 allowed_speeds |= ETH_LINK_SPEED_100M;
422 if (hw->mac.default_speeds & NGBE_LINK_SPEED_10M_FULL)
423 allowed_speeds |= ETH_LINK_SPEED_10M;
425 if (*link_speeds & ~allowed_speeds) {
426 PMD_INIT_LOG(ERR, "Invalid link setting");
431 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
432 speed = hw->mac.default_speeds;
434 if (*link_speeds & ETH_LINK_SPEED_1G)
435 speed |= NGBE_LINK_SPEED_1GB_FULL;
436 if (*link_speeds & ETH_LINK_SPEED_100M)
437 speed |= NGBE_LINK_SPEED_100M_FULL;
438 if (*link_speeds & ETH_LINK_SPEED_10M)
439 speed |= NGBE_LINK_SPEED_10M_FULL;
443 err = hw->mac.setup_link(hw, speed, link_up);
447 if (rte_intr_allow_others(intr_handle)) {
448 ngbe_dev_misc_interrupt_setup(dev);
449 /* check if lsc interrupt is enabled */
450 if (dev->data->dev_conf.intr_conf.lsc != 0)
451 ngbe_dev_lsc_interrupt_setup(dev, TRUE);
453 ngbe_dev_lsc_interrupt_setup(dev, FALSE);
454 ngbe_dev_macsec_interrupt_setup(dev);
455 ngbe_set_ivar_map(hw, -1, 1, NGBE_MISC_VEC_ID);
457 rte_intr_callback_unregister(intr_handle,
458 ngbe_dev_interrupt_handler, dev);
459 if (dev->data->dev_conf.intr_conf.lsc != 0)
461 "LSC won't enable because of no intr multiplex");
464 /* check if rxq interrupt is enabled */
465 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
466 rte_intr_dp_is_en(intr_handle))
467 ngbe_dev_rxq_interrupt_setup(dev);
469 /* enable UIO/VFIO intr/eventfd mapping */
470 rte_intr_enable(intr_handle);
472 /* resume enabled intr since HW reset */
473 ngbe_enable_intr(dev);
475 if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
476 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
477 /* gpio0 is used to power on/off control*/
478 wr32(hw, NGBE_GPIODATA, 0);
482 * Update link status right before return, because it may
483 * start link configuration process in a separate thread.
485 ngbe_dev_link_update(dev, 0);
490 PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
491 ngbe_dev_clear_queues(dev);
496 * Stop device: disable rx and tx functions to allow for reconfiguring.
499 ngbe_dev_stop(struct rte_eth_dev *dev)
501 struct rte_eth_link link;
502 struct ngbe_hw *hw = ngbe_dev_hw(dev);
503 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
504 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
506 if (hw->adapter_stopped)
509 PMD_INIT_FUNC_TRACE();
511 if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
512 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
513 /* gpio0 is used to power on/off control*/
514 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);
517 /* disable interrupts */
518 ngbe_disable_intr(hw);
521 ngbe_pf_reset_hw(hw);
522 hw->adapter_stopped = 0;
527 ngbe_dev_clear_queues(dev);
529 /* Clear recorded link status */
530 memset(&link, 0, sizeof(link));
531 rte_eth_linkstatus_set(dev, &link);
533 if (!rte_intr_allow_others(intr_handle))
534 /* resume to the default handler */
535 rte_intr_callback_register(intr_handle,
536 ngbe_dev_interrupt_handler,
539 /* Clean datapath event and queue/vec mapping */
540 rte_intr_efd_disable(intr_handle);
541 if (intr_handle->intr_vec != NULL) {
542 rte_free(intr_handle->intr_vec);
543 intr_handle->intr_vec = NULL;
546 hw->adapter_stopped = true;
547 dev->data->dev_started = 0;
553 * Reset and stop device.
556 ngbe_dev_close(struct rte_eth_dev *dev)
558 PMD_INIT_FUNC_TRACE();
566 ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
568 struct ngbe_hw *hw = ngbe_dev_hw(dev);
570 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
571 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
573 dev_info->default_rxconf = (struct rte_eth_rxconf) {
575 .pthresh = NGBE_DEFAULT_RX_PTHRESH,
576 .hthresh = NGBE_DEFAULT_RX_HTHRESH,
577 .wthresh = NGBE_DEFAULT_RX_WTHRESH,
579 .rx_free_thresh = NGBE_DEFAULT_RX_FREE_THRESH,
584 dev_info->default_txconf = (struct rte_eth_txconf) {
586 .pthresh = NGBE_DEFAULT_TX_PTHRESH,
587 .hthresh = NGBE_DEFAULT_TX_HTHRESH,
588 .wthresh = NGBE_DEFAULT_TX_WTHRESH,
590 .tx_free_thresh = NGBE_DEFAULT_TX_FREE_THRESH,
594 dev_info->rx_desc_lim = rx_desc_lim;
595 dev_info->tx_desc_lim = tx_desc_lim;
597 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_100M |
600 /* Driver-preferred Rx/Tx parameters */
601 dev_info->default_txportconf.burst_size = 32;
602 dev_info->default_rxportconf.nb_queues = 1;
603 dev_info->default_txportconf.nb_queues = 1;
604 dev_info->default_rxportconf.ring_size = 256;
605 dev_info->default_txportconf.ring_size = 256;
610 /* return 0 means link status changed, -1 means not changed */
612 ngbe_dev_link_update_share(struct rte_eth_dev *dev,
613 int wait_to_complete)
615 struct ngbe_hw *hw = ngbe_dev_hw(dev);
616 struct rte_eth_link link;
617 u32 link_speed = NGBE_LINK_SPEED_UNKNOWN;
619 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
624 memset(&link, 0, sizeof(link));
625 link.link_status = ETH_LINK_DOWN;
626 link.link_speed = ETH_SPEED_NUM_NONE;
627 link.link_duplex = ETH_LINK_HALF_DUPLEX;
628 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
629 ~ETH_LINK_SPEED_AUTONEG);
631 hw->mac.get_link_status = true;
633 if (intr->flags & NGBE_FLAG_NEED_LINK_CONFIG)
634 return rte_eth_linkstatus_set(dev, &link);
636 /* check if it needs to wait to complete, if lsc interrupt is enabled */
637 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
640 err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
642 link.link_speed = ETH_SPEED_NUM_NONE;
643 link.link_duplex = ETH_LINK_FULL_DUPLEX;
644 return rte_eth_linkstatus_set(dev, &link);
648 return rte_eth_linkstatus_set(dev, &link);
650 intr->flags &= ~NGBE_FLAG_NEED_LINK_CONFIG;
651 link.link_status = ETH_LINK_UP;
652 link.link_duplex = ETH_LINK_FULL_DUPLEX;
654 switch (link_speed) {
656 case NGBE_LINK_SPEED_UNKNOWN:
657 link.link_speed = ETH_SPEED_NUM_NONE;
660 case NGBE_LINK_SPEED_10M_FULL:
661 link.link_speed = ETH_SPEED_NUM_10M;
665 case NGBE_LINK_SPEED_100M_FULL:
666 link.link_speed = ETH_SPEED_NUM_100M;
670 case NGBE_LINK_SPEED_1GB_FULL:
671 link.link_speed = ETH_SPEED_NUM_1G;
677 wr32m(hw, NGBE_LAN_SPEED, NGBE_LAN_SPEED_MASK, lan_speed);
678 if (link_speed & (NGBE_LINK_SPEED_1GB_FULL |
679 NGBE_LINK_SPEED_100M_FULL |
680 NGBE_LINK_SPEED_10M_FULL)) {
681 wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_SPEED_MASK,
682 NGBE_MACTXCFG_SPEED_1G | NGBE_MACTXCFG_TE);
686 return rte_eth_linkstatus_set(dev, &link);
690 ngbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
692 return ngbe_dev_link_update_share(dev, wait_to_complete);
696 * It clears the interrupt causes and enables the interrupt.
697 * It will be called once only during NIC initialized.
700 * Pointer to struct rte_eth_dev.
705 * - On success, zero.
706 * - On failure, a negative value.
709 ngbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
711 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
713 ngbe_dev_link_status_print(dev);
715 intr->mask_misc |= NGBE_ICRMISC_PHY;
716 intr->mask_misc |= NGBE_ICRMISC_GPIO;
718 intr->mask_misc &= ~NGBE_ICRMISC_PHY;
719 intr->mask_misc &= ~NGBE_ICRMISC_GPIO;
726 * It clears the interrupt causes and enables the interrupt.
727 * It will be called once only during NIC initialized.
730 * Pointer to struct rte_eth_dev.
733 * - On success, zero.
734 * - On failure, a negative value.
737 ngbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev)
739 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
742 mask = NGBE_ICR_MASK;
743 mask &= (1ULL << NGBE_MISC_VEC_ID);
745 intr->mask_misc |= NGBE_ICRMISC_GPIO;
751 * It clears the interrupt causes and enables the interrupt.
752 * It will be called once only during NIC initialized.
755 * Pointer to struct rte_eth_dev.
758 * - On success, zero.
759 * - On failure, a negative value.
762 ngbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
764 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
767 mask = NGBE_ICR_MASK;
768 mask &= ~((1ULL << NGBE_RX_VEC_START) - 1);
775 * It clears the interrupt causes and enables the interrupt.
776 * It will be called once only during NIC initialized.
779 * Pointer to struct rte_eth_dev.
782 * - On success, zero.
783 * - On failure, a negative value.
786 ngbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
788 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
790 intr->mask_misc |= NGBE_ICRMISC_LNKSEC;
796 * It reads ICR and sets flag for the link_update.
799 * Pointer to struct rte_eth_dev.
802 * - On success, zero.
803 * - On failure, a negative value.
806 ngbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
809 struct ngbe_hw *hw = ngbe_dev_hw(dev);
810 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
812 /* clear all cause mask */
813 ngbe_disable_intr(hw);
815 /* read-on-clear nic registers here */
816 eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_MISC];
817 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
821 /* set flag for async link update */
822 if (eicr & NGBE_ICRMISC_PHY)
823 intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE;
825 if (eicr & NGBE_ICRMISC_VFMBX)
826 intr->flags |= NGBE_FLAG_MAILBOX;
828 if (eicr & NGBE_ICRMISC_LNKSEC)
829 intr->flags |= NGBE_FLAG_MACSEC;
831 if (eicr & NGBE_ICRMISC_GPIO)
832 intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE;
838 * It gets and then prints the link status.
841 * Pointer to struct rte_eth_dev.
844 * - On success, zero.
845 * - On failure, a negative value.
848 ngbe_dev_link_status_print(struct rte_eth_dev *dev)
850 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
851 struct rte_eth_link link;
853 rte_eth_linkstatus_get(dev, &link);
855 if (link.link_status == ETH_LINK_UP) {
856 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
857 (int)(dev->data->port_id),
858 (unsigned int)link.link_speed,
859 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
860 "full-duplex" : "half-duplex");
862 PMD_INIT_LOG(INFO, " Port %d: Link Down",
863 (int)(dev->data->port_id));
865 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
866 pci_dev->addr.domain,
869 pci_dev->addr.function);
873 * It executes link_update after knowing an interrupt occurred.
876 * Pointer to struct rte_eth_dev.
879 * - On success, zero.
880 * - On failure, a negative value.
883 ngbe_dev_interrupt_action(struct rte_eth_dev *dev)
885 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
888 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
890 if (intr->flags & NGBE_FLAG_NEED_LINK_UPDATE) {
891 struct rte_eth_link link;
893 /*get the link status before link update, for predicting later*/
894 rte_eth_linkstatus_get(dev, &link);
896 ngbe_dev_link_update(dev, 0);
899 if (link.link_status != ETH_LINK_UP)
900 /* handle it 1 sec later, wait it being stable */
901 timeout = NGBE_LINK_UP_CHECK_TIMEOUT;
904 /* handle it 4 sec later, wait it being stable */
905 timeout = NGBE_LINK_DOWN_CHECK_TIMEOUT;
907 ngbe_dev_link_status_print(dev);
908 if (rte_eal_alarm_set(timeout * 1000,
909 ngbe_dev_interrupt_delayed_handler,
911 PMD_DRV_LOG(ERR, "Error setting alarm");
913 /* remember original mask */
914 intr->mask_misc_orig = intr->mask_misc;
915 /* only disable lsc interrupt */
916 intr->mask_misc &= ~NGBE_ICRMISC_PHY;
918 intr->mask_orig = intr->mask;
919 /* only disable all misc interrupts */
920 intr->mask &= ~(1ULL << NGBE_MISC_VEC_ID);
924 PMD_DRV_LOG(DEBUG, "enable intr immediately");
925 ngbe_enable_intr(dev);
931 * Interrupt handler which shall be registered for alarm callback for delayed
932 * handling specific interrupt to wait for the stable nic state. As the
933 * NIC interrupt state is not stable for ngbe after link is just down,
934 * it needs to wait 4 seconds to get the stable status.
937 * The address of parameter (struct rte_eth_dev *) registered before.
940 ngbe_dev_interrupt_delayed_handler(void *param)
942 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
943 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
944 struct ngbe_hw *hw = ngbe_dev_hw(dev);
947 ngbe_disable_intr(hw);
949 eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_MISC];
951 if (intr->flags & NGBE_FLAG_NEED_LINK_UPDATE) {
952 ngbe_dev_link_update(dev, 0);
953 intr->flags &= ~NGBE_FLAG_NEED_LINK_UPDATE;
954 ngbe_dev_link_status_print(dev);
955 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
959 if (intr->flags & NGBE_FLAG_MACSEC) {
960 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
962 intr->flags &= ~NGBE_FLAG_MACSEC;
965 /* restore original mask */
966 intr->mask_misc = intr->mask_misc_orig;
967 intr->mask_misc_orig = 0;
968 intr->mask = intr->mask_orig;
971 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
972 ngbe_enable_intr(dev);
976 * Interrupt handler triggered by NIC for handling
977 * specific interrupt.
980 * The address of parameter (struct rte_eth_dev *) registered before.
983 ngbe_dev_interrupt_handler(void *param)
985 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
987 ngbe_dev_interrupt_get_status(dev);
988 ngbe_dev_interrupt_action(dev);
992 * Set the IVAR registers, mapping interrupt causes to vectors
994 * pointer to ngbe_hw struct
996 * 0 for Rx, 1 for Tx, -1 for other causes
998 * queue to map the corresponding interrupt to
1000 * the vector to map to the corresponding queue
1003 ngbe_set_ivar_map(struct ngbe_hw *hw, int8_t direction,
1004 uint8_t queue, uint8_t msix_vector)
1008 if (direction == -1) {
1010 msix_vector |= NGBE_IVARMISC_VLD;
1012 tmp = rd32(hw, NGBE_IVARMISC);
1013 tmp &= ~(0xFF << idx);
1014 tmp |= (msix_vector << idx);
1015 wr32(hw, NGBE_IVARMISC, tmp);
1017 /* rx or tx causes */
1018 /* Workround for ICR lost */
1019 idx = ((16 * (queue & 1)) + (8 * direction));
1020 tmp = rd32(hw, NGBE_IVAR(queue >> 1));
1021 tmp &= ~(0xFF << idx);
1022 tmp |= (msix_vector << idx);
1023 wr32(hw, NGBE_IVAR(queue >> 1), tmp);
1028 * Sets up the hardware to properly generate MSI-X interrupts
1030 * board private structure
1033 ngbe_configure_msix(struct rte_eth_dev *dev)
1035 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1036 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1037 struct ngbe_hw *hw = ngbe_dev_hw(dev);
1038 uint32_t queue_id, base = NGBE_MISC_VEC_ID;
1039 uint32_t vec = NGBE_MISC_VEC_ID;
1043 * Won't configure MSI-X register if no mapping is done
1044 * between intr vector and event fd
1045 * but if MSI-X has been enabled already, need to configure
1046 * auto clean, auto mask and throttling.
1048 gpie = rd32(hw, NGBE_GPIE);
1049 if (!rte_intr_dp_is_en(intr_handle) &&
1050 !(gpie & NGBE_GPIE_MSIX))
1053 if (rte_intr_allow_others(intr_handle)) {
1054 base = NGBE_RX_VEC_START;
1058 /* setup GPIE for MSI-X mode */
1059 gpie = rd32(hw, NGBE_GPIE);
1060 gpie |= NGBE_GPIE_MSIX;
1061 wr32(hw, NGBE_GPIE, gpie);
1063 /* Populate the IVAR table and set the ITR values to the
1064 * corresponding register.
1066 if (rte_intr_dp_is_en(intr_handle)) {
1067 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
1069 /* by default, 1:1 mapping */
1070 ngbe_set_ivar_map(hw, 0, queue_id, vec);
1071 intr_handle->intr_vec[queue_id] = vec;
1072 if (vec < base + intr_handle->nb_efd - 1)
1076 ngbe_set_ivar_map(hw, -1, 1, NGBE_MISC_VEC_ID);
1078 wr32(hw, NGBE_ITR(NGBE_MISC_VEC_ID),
1079 NGBE_ITR_IVAL_1G(NGBE_QUEUE_ITR_INTERVAL_DEFAULT)
1083 static const struct eth_dev_ops ngbe_eth_dev_ops = {
1084 .dev_configure = ngbe_dev_configure,
1085 .dev_infos_get = ngbe_dev_info_get,
1086 .dev_start = ngbe_dev_start,
1087 .dev_stop = ngbe_dev_stop,
1088 .link_update = ngbe_dev_link_update,
1089 .tx_queue_start = ngbe_dev_tx_queue_start,
1090 .tx_queue_stop = ngbe_dev_tx_queue_stop,
1091 .rx_queue_setup = ngbe_dev_rx_queue_setup,
1092 .rx_queue_release = ngbe_dev_rx_queue_release,
1093 .tx_queue_setup = ngbe_dev_tx_queue_setup,
1094 .tx_queue_release = ngbe_dev_tx_queue_release,
1097 RTE_PMD_REGISTER_PCI(net_ngbe, rte_ngbe_pmd);
1098 RTE_PMD_REGISTER_PCI_TABLE(net_ngbe, pci_id_ngbe_map);
1099 RTE_PMD_REGISTER_KMOD_DEP(net_ngbe, "* igb_uio | uio_pci_generic | vfio-pci");
1101 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_init, init, NOTICE);
1102 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_driver, driver, NOTICE);
1104 #ifdef RTE_ETHDEV_DEBUG_RX
1105 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_rx, rx, DEBUG);
1107 #ifdef RTE_ETHDEV_DEBUG_TX
1108 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_tx, tx, DEBUG);