drivers/net/ngbe/ngbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
   3  * Copyright(c) 2010-2017 Intel Corporation
   4  */
   5
   6 #include <errno.h>
   7 #include <rte_common.h>
   8 #include <ethdev_pci.h>
   9
  10 #include <rte_alarm.h>
  11
  12 #include "ngbe_logs.h"
  13 #include "ngbe.h"
  14 #include "ngbe_ethdev.h"
  15 #include "ngbe_rxtx.h"
  16
  17 static int ngbe_dev_close(struct rte_eth_dev *dev);
  18 static int ngbe_dev_link_update(struct rte_eth_dev *dev,
  19                                 int wait_to_complete);
  20
  21 static void ngbe_dev_link_status_print(struct rte_eth_dev *dev);
  22 static int ngbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
  23 static int ngbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
  24 static int ngbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev);
  25 static int ngbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
  26 static void ngbe_dev_interrupt_handler(void *param);
  27 static void ngbe_dev_interrupt_delayed_handler(void *param);
  28 static void ngbe_configure_msix(struct rte_eth_dev *dev);
  29
  30 /*
  31  * The set of PCI devices this driver supports
  32  */
  33 static const struct rte_pci_id pci_id_ngbe_map[] = {
  34         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A2) },
  35         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A2S) },
  36         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A4) },
  37         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A4S) },
  38         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL2) },
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL2S) },
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL4) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL4S) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860NCSI) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A1L) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL_W) },
  46         { .vendor_id = 0, /* sentinel */ },
  47 };
  48
  49 static const struct rte_eth_desc_lim rx_desc_lim = {
  50         .nb_max = NGBE_RING_DESC_MAX,
  51         .nb_min = NGBE_RING_DESC_MIN,
  52         .nb_align = NGBE_RXD_ALIGN,
  53 };
  54
  55 static const struct rte_eth_desc_lim tx_desc_lim = {
  56         .nb_max = NGBE_RING_DESC_MAX,
  57         .nb_min = NGBE_RING_DESC_MIN,
  58         .nb_align = NGBE_TXD_ALIGN,
  59         .nb_seg_max = NGBE_TX_MAX_SEG,
  60         .nb_mtu_seg_max = NGBE_TX_MAX_SEG,
  61 };
  62
  63 static const struct eth_dev_ops ngbe_eth_dev_ops;
  64
  65 static inline int32_t
  66 ngbe_pf_reset_hw(struct ngbe_hw *hw)
  67 {
  68         uint32_t ctrl_ext;
  69         int32_t status;
  70
  71         status = hw->mac.reset_hw(hw);
  72
  73         ctrl_ext = rd32(hw, NGBE_PORTCTL);
  74         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
  75         ctrl_ext |= NGBE_PORTCTL_RSTDONE;
  76         wr32(hw, NGBE_PORTCTL, ctrl_ext);
  77         ngbe_flush(hw);
  78
  79         if (status == NGBE_ERR_SFP_NOT_PRESENT)
  80                 status = 0;
  81         return status;
  82 }
  83
  84 static inline void
  85 ngbe_enable_intr(struct rte_eth_dev *dev)
  86 {
  87         struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
  88         struct ngbe_hw *hw = ngbe_dev_hw(dev);
  89
  90         wr32(hw, NGBE_IENMISC, intr->mask_misc);
  91         wr32(hw, NGBE_IMC(0), intr->mask & BIT_MASK32);
  92         ngbe_flush(hw);
  93 }
  94
  95 static void
  96 ngbe_disable_intr(struct ngbe_hw *hw)
  97 {
  98         PMD_INIT_FUNC_TRACE();
  99
 100         wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK);
 101         ngbe_flush(hw);
 102 }
 103
 104 /*
 105  * Ensure that all locks are released before first NVM or PHY access
 106  */
 107 static void
 108 ngbe_swfw_lock_reset(struct ngbe_hw *hw)
 109 {
 110         uint16_t mask;
 111
 112         /*
 113          * These ones are more tricky since they are common to all ports; but
 114          * swfw_sync retries last long enough (1s) to be almost sure that if
 115          * lock can not be taken it is due to an improper lock of the
 116          * semaphore.
 117          */
 118         mask = NGBE_MNGSEM_SWPHY |
 119                NGBE_MNGSEM_SWMBX |
 120                NGBE_MNGSEM_SWFLASH;
 121         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 122                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 123
 124         hw->mac.release_swfw_sync(hw, mask);
 125 }
 126
 127 static int
 128 eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 129 {
 130         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 131         struct ngbe_hw *hw = ngbe_dev_hw(eth_dev);
 132         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 133         const struct rte_memzone *mz;
 134         uint32_t ctrl_ext;
 135         int err;
 136
 137         PMD_INIT_FUNC_TRACE();
 138
 139         eth_dev->dev_ops = &ngbe_eth_dev_ops;
 140         eth_dev->rx_pkt_burst = &ngbe_recv_pkts;
 141         eth_dev->tx_pkt_burst = &ngbe_xmit_pkts;
 142         eth_dev->tx_pkt_prepare = &ngbe_prep_pkts;
 143
 144         /*
 145          * For secondary processes, we don't initialise any further as primary
 146          * has already done this work. Only check we don't need a different
 147          * Rx and Tx function.
 148          */
 149         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 150                 struct ngbe_tx_queue *txq;
 151                 /* Tx queue function in primary, set by last queue initialized
 152                  * Tx queue may not initialized by primary process
 153                  */
 154                 if (eth_dev->data->tx_queues) {
 155                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 156                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 157                         ngbe_set_tx_function(eth_dev, txq);
 158                 } else {
 159                         /* Use default Tx function if we get here */
 160                         PMD_INIT_LOG(NOTICE,
 161                                 "No Tx queues configured yet. Using default Tx function.");
 162                 }
 163
 164                 ngbe_set_rx_function(eth_dev);
 165
 166                 return 0;
 167         }
 168
 169         rte_eth_copy_pci_info(eth_dev, pci_dev);
 170
 171         /* Vendor and Device ID need to be set before init of shared code */
 172         hw->device_id = pci_dev->id.device_id;
 173         hw->vendor_id = pci_dev->id.vendor_id;
 174         hw->sub_system_id = pci_dev->id.subsystem_device_id;
 175         ngbe_map_device_id(hw);
 176         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 177
 178         /* Reserve memory for interrupt status block */
 179         mz = rte_eth_dma_zone_reserve(eth_dev, "ngbe_driver", -1,
 180                 NGBE_ISB_SIZE, NGBE_ALIGN, SOCKET_ID_ANY);
 181         if (mz == NULL)
 182                 return -ENOMEM;
 183
 184         hw->isb_dma = TMZ_PADDR(mz);
 185         hw->isb_mem = TMZ_VADDR(mz);
 186
 187         /* Initialize the shared code (base driver) */
 188         err = ngbe_init_shared_code(hw);
 189         if (err != 0) {
 190                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 191                 return -EIO;
 192         }
 193
 194         /* Unlock any pending hardware semaphore */
 195         ngbe_swfw_lock_reset(hw);
 196
 197         err = hw->rom.init_params(hw);
 198         if (err != 0) {
 199                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 200                 return -EIO;
 201         }
 202
 203         /* Make sure we have a good EEPROM before we read from it */
 204         err = hw->rom.validate_checksum(hw, NULL);
 205         if (err != 0) {
 206                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 207                 return -EIO;
 208         }
 209
 210         err = hw->mac.init_hw(hw);
 211         if (err != 0) {
 212                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 213                 return -EIO;
 214         }
 215
 216         /* disable interrupt */
 217         ngbe_disable_intr(hw);
 218
 219         /* Allocate memory for storing MAC addresses */
 220         eth_dev->data->mac_addrs = rte_zmalloc("ngbe", RTE_ETHER_ADDR_LEN *
 221                                                hw->mac.num_rar_entries, 0);
 222         if (eth_dev->data->mac_addrs == NULL) {
 223                 PMD_INIT_LOG(ERR,
 224                              "Failed to allocate %u bytes needed to store MAC addresses",
 225                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 226                 return -ENOMEM;
 227         }
 228
 229         /* Copy the permanent MAC address */
 230         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 231                         &eth_dev->data->mac_addrs[0]);
 232
 233         /* Allocate memory for storing hash filter MAC addresses */
 234         eth_dev->data->hash_mac_addrs = rte_zmalloc("ngbe",
 235                         RTE_ETHER_ADDR_LEN * NGBE_VMDQ_NUM_UC_MAC, 0);
 236         if (eth_dev->data->hash_mac_addrs == NULL) {
 237                 PMD_INIT_LOG(ERR,
 238                              "Failed to allocate %d bytes needed to store MAC addresses",
 239                              RTE_ETHER_ADDR_LEN * NGBE_VMDQ_NUM_UC_MAC);
 240                 rte_free(eth_dev->data->mac_addrs);
 241                 eth_dev->data->mac_addrs = NULL;
 242                 return -ENOMEM;
 243         }
 244
 245         ctrl_ext = rd32(hw, NGBE_PORTCTL);
 246         /* let hardware know driver is loaded */
 247         ctrl_ext |= NGBE_PORTCTL_DRVLOAD;
 248         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 249         ctrl_ext |= NGBE_PORTCTL_RSTDONE;
 250         wr32(hw, NGBE_PORTCTL, ctrl_ext);
 251         ngbe_flush(hw);
 252
 253         PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 254                         (int)hw->mac.type, (int)hw->phy.type);
 255
 256         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 257                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 258                      pci_dev->id.device_id);
 259
 260         rte_intr_callback_register(intr_handle,
 261                                    ngbe_dev_interrupt_handler, eth_dev);
 262
 263         /* enable uio/vfio intr/eventfd mapping */
 264         rte_intr_enable(intr_handle);
 265
 266         /* enable support intr */
 267         ngbe_enable_intr(eth_dev);
 268
 269         return 0;
 270 }
 271
 272 static int
 273 eth_ngbe_dev_uninit(struct rte_eth_dev *eth_dev)
 274 {
 275         PMD_INIT_FUNC_TRACE();
 276
 277         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 278                 return 0;
 279
 280         ngbe_dev_close(eth_dev);
 281
 282         return 0;
 283 }
 284
 285 static int
 286 eth_ngbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 287                 struct rte_pci_device *pci_dev)
 288 {
 289         return rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 290                         sizeof(struct ngbe_adapter),
 291                         eth_dev_pci_specific_init, pci_dev,
 292                         eth_ngbe_dev_init, NULL);
 293 }
 294
 295 static int eth_ngbe_pci_remove(struct rte_pci_device *pci_dev)
 296 {
 297         struct rte_eth_dev *ethdev;
 298
 299         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 300         if (ethdev == NULL)
 301                 return 0;
 302
 303         return rte_eth_dev_destroy(ethdev, eth_ngbe_dev_uninit);
 304 }
 305
 306 static struct rte_pci_driver rte_ngbe_pmd = {
 307         .id_table = pci_id_ngbe_map,
 308         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 309                      RTE_PCI_DRV_INTR_LSC,
 310         .probe = eth_ngbe_pci_probe,
 311         .remove = eth_ngbe_pci_remove,
 312 };
 313
 314 static int
 315 ngbe_dev_configure(struct rte_eth_dev *dev)
 316 {
 317         struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
 318         struct ngbe_adapter *adapter = ngbe_dev_adapter(dev);
 319
 320         PMD_INIT_FUNC_TRACE();
 321
 322         /* set flag to update link status after init */
 323         intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE;
 324
 325         /*
 326          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
 327          * allocation Rx preconditions we will reset it.
 328          */
 329         adapter->rx_bulk_alloc_allowed = true;
 330
 331         return 0;
 332 }
 333
 334 static void
 335 ngbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
 336 {
 337         struct ngbe_hw *hw = ngbe_dev_hw(dev);
 338         struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
 339
 340         wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));
 341         wr32(hw, NGBE_GPIOINTEN, NGBE_GPIOINTEN_INT(3));
 342         wr32(hw, NGBE_GPIOINTTYPE, NGBE_GPIOINTTYPE_LEVEL(0));
 343         if (hw->phy.type == ngbe_phy_yt8521s_sfi)
 344                 wr32(hw, NGBE_GPIOINTPOL, NGBE_GPIOINTPOL_ACT(0));
 345         else
 346                 wr32(hw, NGBE_GPIOINTPOL, NGBE_GPIOINTPOL_ACT(3));
 347
 348         intr->mask_misc |= NGBE_ICRMISC_GPIO;
 349 }
 350
 351 /*
 352  * Configure device link speed and setup link.
 353  * It returns 0 on success.
 354  */
 355 static int
 356 ngbe_dev_start(struct rte_eth_dev *dev)
 357 {
 358         struct ngbe_hw *hw = ngbe_dev_hw(dev);
 359         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 360         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 361         uint32_t intr_vector = 0;
 362         int err;
 363         bool link_up = false, negotiate = false;
 364         uint32_t speed = 0;
 365         uint32_t allowed_speeds = 0;
 366         int status;
 367         uint32_t *link_speeds;
 368
 369         PMD_INIT_FUNC_TRACE();
 370
 371         /* disable uio/vfio intr/eventfd mapping */
 372         rte_intr_disable(intr_handle);
 373
 374         /* stop adapter */
 375         hw->adapter_stopped = 0;
 376         ngbe_stop_hw(hw);
 377
 378         /* reinitialize adapter, this calls reset and start */
 379         hw->nb_rx_queues = dev->data->nb_rx_queues;
 380         hw->nb_tx_queues = dev->data->nb_tx_queues;
 381         status = ngbe_pf_reset_hw(hw);
 382         if (status != 0)
 383                 return -1;
 384         hw->mac.start_hw(hw);
 385         hw->mac.get_link_status = true;
 386
 387         ngbe_dev_phy_intr_setup(dev);
 388
 389         /* check and configure queue intr-vector mapping */
 390         if ((rte_intr_cap_multiple(intr_handle) ||
 391              !RTE_ETH_DEV_SRIOV(dev).active) &&
 392             dev->data->dev_conf.intr_conf.rxq != 0) {
 393                 intr_vector = dev->data->nb_rx_queues;
 394                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 395                         return -1;
 396         }
 397
 398         if (rte_intr_dp_is_en(intr_handle)) {
 399                 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
 400                                                    dev->data->nb_rx_queues)) {
 401                         PMD_INIT_LOG(ERR,
 402                                      "Failed to allocate %d rx_queues intr_vec",
 403                                      dev->data->nb_rx_queues);
 404                         return -ENOMEM;
 405                 }
 406         }
 407
 408         /* confiugre MSI-X for sleep until Rx interrupt */
 409         ngbe_configure_msix(dev);
 410
 411         /* initialize transmission unit */
 412         ngbe_dev_tx_init(dev);
 413
 414         /* This can fail when allocating mbufs for descriptor rings */
 415         err = ngbe_dev_rx_init(dev);
 416         if (err != 0) {
 417                 PMD_INIT_LOG(ERR, "Unable to initialize Rx hardware");
 418                 goto error;
 419         }
 420
 421         err = ngbe_dev_rxtx_start(dev);
 422         if (err < 0) {
 423                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
 424                 goto error;
 425         }
 426
 427         err = hw->mac.check_link(hw, &speed, &link_up, 0);
 428         if (err != 0)
 429                 goto error;
 430         dev->data->dev_link.link_status = link_up;
 431
 432         link_speeds = &dev->data->dev_conf.link_speeds;
 433         if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG)
 434                 negotiate = true;
 435
 436         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
 437         if (err != 0)
 438                 goto error;
 439
 440         allowed_speeds = 0;
 441         if (hw->mac.default_speeds & NGBE_LINK_SPEED_1GB_FULL)
 442                 allowed_speeds |= RTE_ETH_LINK_SPEED_1G;
 443         if (hw->mac.default_speeds & NGBE_LINK_SPEED_100M_FULL)
 444                 allowed_speeds |= RTE_ETH_LINK_SPEED_100M;
 445         if (hw->mac.default_speeds & NGBE_LINK_SPEED_10M_FULL)
 446                 allowed_speeds |= RTE_ETH_LINK_SPEED_10M;
 447
 448         if (*link_speeds & ~allowed_speeds) {
 449                 PMD_INIT_LOG(ERR, "Invalid link setting");
 450                 goto error;
 451         }
 452
 453         speed = 0x0;
 454         if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
 455                 speed = hw->mac.default_speeds;
 456         } else {
 457                 if (*link_speeds & RTE_ETH_LINK_SPEED_1G)
 458                         speed |= NGBE_LINK_SPEED_1GB_FULL;
 459                 if (*link_speeds & RTE_ETH_LINK_SPEED_100M)
 460                         speed |= NGBE_LINK_SPEED_100M_FULL;
 461                 if (*link_speeds & RTE_ETH_LINK_SPEED_10M)
 462                         speed |= NGBE_LINK_SPEED_10M_FULL;
 463         }
 464
 465         hw->phy.init_hw(hw);
 466         err = hw->mac.setup_link(hw, speed, link_up);
 467         if (err != 0)
 468                 goto error;
 469
 470         if (rte_intr_allow_others(intr_handle)) {
 471                 ngbe_dev_misc_interrupt_setup(dev);
 472                 /* check if lsc interrupt is enabled */
 473                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 474                         ngbe_dev_lsc_interrupt_setup(dev, TRUE);
 475                 else
 476                         ngbe_dev_lsc_interrupt_setup(dev, FALSE);
 477                 ngbe_dev_macsec_interrupt_setup(dev);
 478                 ngbe_set_ivar_map(hw, -1, 1, NGBE_MISC_VEC_ID);
 479         } else {
 480                 rte_intr_callback_unregister(intr_handle,
 481                                              ngbe_dev_interrupt_handler, dev);
 482                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 483                         PMD_INIT_LOG(INFO,
 484                                      "LSC won't enable because of no intr multiplex");
 485         }
 486
 487         /* check if rxq interrupt is enabled */
 488         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
 489             rte_intr_dp_is_en(intr_handle))
 490                 ngbe_dev_rxq_interrupt_setup(dev);
 491
 492         /* enable UIO/VFIO intr/eventfd mapping */
 493         rte_intr_enable(intr_handle);
 494
 495         /* resume enabled intr since HW reset */
 496         ngbe_enable_intr(dev);
 497
 498         if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
 499                 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
 500                 /* gpio0 is used to power on/off control*/
 501                 wr32(hw, NGBE_GPIODATA, 0);
 502         }
 503
 504         /*
 505          * Update link status right before return, because it may
 506          * start link configuration process in a separate thread.
 507          */
 508         ngbe_dev_link_update(dev, 0);
 509
 510         return 0;
 511
 512 error:
 513         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
 514         ngbe_dev_clear_queues(dev);
 515         return -EIO;
 516 }
 517
 518 /*
 519  * Stop device: disable rx and tx functions to allow for reconfiguring.
 520  */
 521 static int
 522 ngbe_dev_stop(struct rte_eth_dev *dev)
 523 {
 524         struct rte_eth_link link;
 525         struct ngbe_hw *hw = ngbe_dev_hw(dev);
 526         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 527         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 528
 529         if (hw->adapter_stopped)
 530                 return 0;
 531
 532         PMD_INIT_FUNC_TRACE();
 533
 534         if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
 535                 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
 536                 /* gpio0 is used to power on/off control*/
 537                 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);
 538         }
 539
 540         /* disable interrupts */
 541         ngbe_disable_intr(hw);
 542
 543         /* reset the NIC */
 544         ngbe_pf_reset_hw(hw);
 545         hw->adapter_stopped = 0;
 546
 547         /* stop adapter */
 548         ngbe_stop_hw(hw);
 549
 550         ngbe_dev_clear_queues(dev);
 551
 552         /* Clear stored conf */
 553         dev->data->scattered_rx = 0;
 554
 555         /* Clear recorded link status */
 556         memset(&link, 0, sizeof(link));
 557         rte_eth_linkstatus_set(dev, &link);
 558
 559         if (!rte_intr_allow_others(intr_handle))
 560                 /* resume to the default handler */
 561                 rte_intr_callback_register(intr_handle,
 562                                            ngbe_dev_interrupt_handler,
 563                                            (void *)dev);
 564
 565         /* Clean datapath event and queue/vec mapping */
 566         rte_intr_efd_disable(intr_handle);
 567         rte_intr_vec_list_free(intr_handle);
 568
 569         hw->adapter_stopped = true;
 570         dev->data->dev_started = 0;
 571
 572         return 0;
 573 }
 574
 575 /*
 576  * Reset and stop device.
 577  */
 578 static int
 579 ngbe_dev_close(struct rte_eth_dev *dev)
 580 {
 581         struct ngbe_hw *hw = ngbe_dev_hw(dev);
 582         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 583         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 584         int retries = 0;
 585         int ret;
 586
 587         PMD_INIT_FUNC_TRACE();
 588
 589         ngbe_pf_reset_hw(hw);
 590
 591         ngbe_dev_stop(dev);
 592
 593         ngbe_dev_free_queues(dev);
 594
 595         /* reprogram the RAR[0] in case user changed it. */
 596         ngbe_set_rar(hw, 0, hw->mac.addr, 0, true);
 597
 598         /* Unlock any pending hardware semaphore */
 599         ngbe_swfw_lock_reset(hw);
 600
 601         /* disable uio intr before callback unregister */
 602         rte_intr_disable(intr_handle);
 603
 604         do {
 605                 ret = rte_intr_callback_unregister(intr_handle,
 606                                 ngbe_dev_interrupt_handler, dev);
 607                 if (ret >= 0 || ret == -ENOENT) {
 608                         break;
 609                 } else if (ret != -EAGAIN) {
 610                         PMD_INIT_LOG(ERR,
 611                                 "intr callback unregister failed: %d",
 612                                 ret);
 613                 }
 614                 rte_delay_ms(100);
 615         } while (retries++ < (10 + NGBE_LINK_UP_TIME));
 616
 617         rte_free(dev->data->mac_addrs);
 618         dev->data->mac_addrs = NULL;
 619
 620         rte_free(dev->data->hash_mac_addrs);
 621         dev->data->hash_mac_addrs = NULL;
 622
 623         return ret;
 624 }
 625
 626 /*
 627  * Reset PF device.
 628  */
 629 static int
 630 ngbe_dev_reset(struct rte_eth_dev *dev)
 631 {
 632         int ret;
 633
 634         ret = eth_ngbe_dev_uninit(dev);
 635         if (ret != 0)
 636                 return ret;
 637
 638         ret = eth_ngbe_dev_init(dev, NULL);
 639
 640         return ret;
 641 }
 642
 643 static int
 644 ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 645 {
 646         struct ngbe_hw *hw = ngbe_dev_hw(dev);
 647
 648         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
 649         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
 650         dev_info->min_rx_bufsize = 1024;
 651         dev_info->max_rx_pktlen = 15872;
 652         dev_info->rx_offload_capa = (ngbe_get_rx_port_offloads(dev) |
 653                                      dev_info->rx_queue_offload_capa);
 654         dev_info->tx_queue_offload_capa = 0;
 655         dev_info->tx_offload_capa = ngbe_get_tx_port_offloads(dev);
 656
 657         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 658                 .rx_thresh = {
 659                         .pthresh = NGBE_DEFAULT_RX_PTHRESH,
 660                         .hthresh = NGBE_DEFAULT_RX_HTHRESH,
 661                         .wthresh = NGBE_DEFAULT_RX_WTHRESH,
 662                 },
 663                 .rx_free_thresh = NGBE_DEFAULT_RX_FREE_THRESH,
 664                 .rx_drop_en = 0,
 665                 .offloads = 0,
 666         };
 667
 668         dev_info->default_txconf = (struct rte_eth_txconf) {
 669                 .tx_thresh = {
 670                         .pthresh = NGBE_DEFAULT_TX_PTHRESH,
 671                         .hthresh = NGBE_DEFAULT_TX_HTHRESH,
 672                         .wthresh = NGBE_DEFAULT_TX_WTHRESH,
 673                 },
 674                 .tx_free_thresh = NGBE_DEFAULT_TX_FREE_THRESH,
 675                 .offloads = 0,
 676         };
 677
 678         dev_info->rx_desc_lim = rx_desc_lim;
 679         dev_info->tx_desc_lim = tx_desc_lim;
 680
 681         dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_100M |
 682                                 RTE_ETH_LINK_SPEED_10M;
 683
 684         /* Driver-preferred Rx/Tx parameters */
 685         dev_info->default_rxportconf.burst_size = 32;
 686         dev_info->default_txportconf.burst_size = 32;
 687         dev_info->default_rxportconf.nb_queues = 1;
 688         dev_info->default_txportconf.nb_queues = 1;
 689         dev_info->default_rxportconf.ring_size = 256;
 690         dev_info->default_txportconf.ring_size = 256;
 691
 692         return 0;
 693 }
 694
 695 const uint32_t *
 696 ngbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 697 {
 698         if (dev->rx_pkt_burst == ngbe_recv_pkts ||
 699             dev->rx_pkt_burst == ngbe_recv_pkts_sc_single_alloc ||
 700             dev->rx_pkt_burst == ngbe_recv_pkts_sc_bulk_alloc ||
 701             dev->rx_pkt_burst == ngbe_recv_pkts_bulk_alloc)
 702                 return ngbe_get_supported_ptypes();
 703
 704         return NULL;
 705 }
 706
 707 /* return 0 means link status changed, -1 means not changed */
 708 int
 709 ngbe_dev_link_update_share(struct rte_eth_dev *dev,
 710                             int wait_to_complete)
 711 {
 712         struct ngbe_hw *hw = ngbe_dev_hw(dev);
 713         struct rte_eth_link link;
 714         u32 link_speed = NGBE_LINK_SPEED_UNKNOWN;
 715         u32 lan_speed = 0;
 716         struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
 717         bool link_up;
 718         int err;
 719         int wait = 1;
 720
 721         memset(&link, 0, sizeof(link));
 722         link.link_status = RTE_ETH_LINK_DOWN;
 723         link.link_speed = RTE_ETH_SPEED_NUM_NONE;
 724         link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
 725         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
 726                         ~RTE_ETH_LINK_SPEED_AUTONEG);
 727
 728         hw->mac.get_link_status = true;
 729
 730         if (intr->flags & NGBE_FLAG_NEED_LINK_CONFIG)
 731                 return rte_eth_linkstatus_set(dev, &link);
 732
 733         /* check if it needs to wait to complete, if lsc interrupt is enabled */
 734         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
 735                 wait = 0;
 736
 737         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
 738         if (err != 0) {
 739                 link.link_speed = RTE_ETH_SPEED_NUM_NONE;
 740                 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
 741                 return rte_eth_linkstatus_set(dev, &link);
 742         }
 743
 744         if (!link_up)
 745                 return rte_eth_linkstatus_set(dev, &link);
 746
 747         intr->flags &= ~NGBE_FLAG_NEED_LINK_CONFIG;
 748         link.link_status = RTE_ETH_LINK_UP;
 749         link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
 750
 751         switch (link_speed) {
 752         default:
 753         case NGBE_LINK_SPEED_UNKNOWN:
 754                 link.link_speed = RTE_ETH_SPEED_NUM_NONE;
 755                 break;
 756
 757         case NGBE_LINK_SPEED_10M_FULL:
 758                 link.link_speed = RTE_ETH_SPEED_NUM_10M;
 759                 lan_speed = 0;
 760                 break;
 761
 762         case NGBE_LINK_SPEED_100M_FULL:
 763                 link.link_speed = RTE_ETH_SPEED_NUM_100M;
 764                 lan_speed = 1;
 765                 break;
 766
 767         case NGBE_LINK_SPEED_1GB_FULL:
 768                 link.link_speed = RTE_ETH_SPEED_NUM_1G;
 769                 lan_speed = 2;
 770                 break;
 771         }
 772
 773         if (hw->is_pf) {
 774                 wr32m(hw, NGBE_LAN_SPEED, NGBE_LAN_SPEED_MASK, lan_speed);
 775                 if (link_speed & (NGBE_LINK_SPEED_1GB_FULL |
 776                                 NGBE_LINK_SPEED_100M_FULL |
 777                                 NGBE_LINK_SPEED_10M_FULL)) {
 778                         wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_SPEED_MASK,
 779                                 NGBE_MACTXCFG_SPEED_1G | NGBE_MACTXCFG_TE);
 780                 }
 781         }
 782
 783         return rte_eth_linkstatus_set(dev, &link);
 784 }
 785
 786 static int
 787 ngbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 788 {
 789         return ngbe_dev_link_update_share(dev, wait_to_complete);
 790 }
 791
 792 /**
 793  * It clears the interrupt causes and enables the interrupt.
 794  * It will be called once only during NIC initialized.
 795  *
 796  * @param dev
 797  *  Pointer to struct rte_eth_dev.
 798  * @param on
 799  *  Enable or Disable.
 800  *
 801  * @return
 802  *  - On success, zero.
 803  *  - On failure, a negative value.
 804  */
 805 static int
 806 ngbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
 807 {
 808         struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
 809
 810         ngbe_dev_link_status_print(dev);
 811         if (on != 0) {
 812                 intr->mask_misc |= NGBE_ICRMISC_PHY;
 813                 intr->mask_misc |= NGBE_ICRMISC_GPIO;
 814         } else {
 815                 intr->mask_misc &= ~NGBE_ICRMISC_PHY;
 816                 intr->mask_misc &= ~NGBE_ICRMISC_GPIO;
 817         }
 818
 819         return 0;
 820 }
 821
 822 /**
 823  * It clears the interrupt causes and enables the interrupt.
 824  * It will be called once only during NIC initialized.
 825  *
 826  * @param dev
 827  *  Pointer to struct rte_eth_dev.
 828  *
 829  * @return
 830  *  - On success, zero.
 831  *  - On failure, a negative value.
 832  */
 833 static int
 834 ngbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev)
 835 {
 836         struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
 837         u64 mask;
 838
 839         mask = NGBE_ICR_MASK;
 840         mask &= (1ULL << NGBE_MISC_VEC_ID);
 841         intr->mask |= mask;
 842         intr->mask_misc |= NGBE_ICRMISC_GPIO;
 843
 844         return 0;
 845 }
 846
 847 /**
 848  * It clears the interrupt causes and enables the interrupt.
 849  * It will be called once only during NIC initialized.
 850  *
 851  * @param dev
 852  *  Pointer to struct rte_eth_dev.
 853  *
 854  * @return
 855  *  - On success, zero.
 856  *  - On failure, a negative value.
 857  */
 858 static int
 859 ngbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
 860 {
 861         struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
 862         u64 mask;
 863
 864         mask = NGBE_ICR_MASK;
 865         mask &= ~((1ULL << NGBE_RX_VEC_START) - 1);
 866         intr->mask |= mask;
 867
 868         return 0;
 869 }
 870
 871 /**
 872  * It clears the interrupt causes and enables the interrupt.
 873  * It will be called once only during NIC initialized.
 874  *
 875  * @param dev
 876  *  Pointer to struct rte_eth_dev.
 877  *
 878  * @return
 879  *  - On success, zero.
 880  *  - On failure, a negative value.
 881  */
 882 static int
 883 ngbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
 884 {
 885         struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
 886
 887         intr->mask_misc |= NGBE_ICRMISC_LNKSEC;
 888
 889         return 0;
 890 }
 891
 892 /*
 893  * It reads ICR and sets flag for the link_update.
 894  *
 895  * @param dev
 896  *  Pointer to struct rte_eth_dev.
 897  *
 898  * @return
 899  *  - On success, zero.
 900  *  - On failure, a negative value.
 901  */
 902 static int
 903 ngbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
 904 {
 905         uint32_t eicr;
 906         struct ngbe_hw *hw = ngbe_dev_hw(dev);
 907         struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
 908
 909         /* clear all cause mask */
 910         ngbe_disable_intr(hw);
 911
 912         /* read-on-clear nic registers here */
 913         eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_MISC];
 914         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
 915
 916         intr->flags = 0;
 917
 918         /* set flag for async link update */
 919         if (eicr & NGBE_ICRMISC_PHY)
 920                 intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE;
 921
 922         if (eicr & NGBE_ICRMISC_VFMBX)
 923                 intr->flags |= NGBE_FLAG_MAILBOX;
 924
 925         if (eicr & NGBE_ICRMISC_LNKSEC)
 926                 intr->flags |= NGBE_FLAG_MACSEC;
 927
 928         if (eicr & NGBE_ICRMISC_GPIO)
 929                 intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE;
 930
 931         return 0;
 932 }
 933
 934 /**
 935  * It gets and then prints the link status.
 936  *
 937  * @param dev
 938  *  Pointer to struct rte_eth_dev.
 939  *
 940  * @return
 941  *  - On success, zero.
 942  *  - On failure, a negative value.
 943  */
 944 static void
 945 ngbe_dev_link_status_print(struct rte_eth_dev *dev)
 946 {
 947         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 948         struct rte_eth_link link;
 949
 950         rte_eth_linkstatus_get(dev, &link);
 951
 952         if (link.link_status == RTE_ETH_LINK_UP) {
 953                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
 954                                         (int)(dev->data->port_id),
 955                                         (unsigned int)link.link_speed,
 956                         link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ?
 957                                         "full-duplex" : "half-duplex");
 958         } else {
 959                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
 960                                 (int)(dev->data->port_id));
 961         }
 962         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
 963                                 pci_dev->addr.domain,
 964                                 pci_dev->addr.bus,
 965                                 pci_dev->addr.devid,
 966                                 pci_dev->addr.function);
 967 }
 968
 969 /*
 970  * It executes link_update after knowing an interrupt occurred.
 971  *
 972  * @param dev
 973  *  Pointer to struct rte_eth_dev.
 974  *
 975  * @return
 976  *  - On success, zero.
 977  *  - On failure, a negative value.
 978  */
 979 static int
 980 ngbe_dev_interrupt_action(struct rte_eth_dev *dev)
 981 {
 982         struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
 983         int64_t timeout;
 984
 985         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
 986
 987         if (intr->flags & NGBE_FLAG_NEED_LINK_UPDATE) {
 988                 struct rte_eth_link link;
 989
 990                 /*get the link status before link update, for predicting later*/
 991                 rte_eth_linkstatus_get(dev, &link);
 992
 993                 ngbe_dev_link_update(dev, 0);
 994
 995                 /* likely to up */
 996                 if (link.link_status != RTE_ETH_LINK_UP)
 997                         /* handle it 1 sec later, wait it being stable */
 998                         timeout = NGBE_LINK_UP_CHECK_TIMEOUT;
 999                 /* likely to down */
1000                 else
1001                         /* handle it 4 sec later, wait it being stable */
1002                         timeout = NGBE_LINK_DOWN_CHECK_TIMEOUT;
1003
1004                 ngbe_dev_link_status_print(dev);
1005                 if (rte_eal_alarm_set(timeout * 1000,
1006                                       ngbe_dev_interrupt_delayed_handler,
1007                                       (void *)dev) < 0) {
1008                         PMD_DRV_LOG(ERR, "Error setting alarm");
1009                 } else {
1010                         /* remember original mask */
1011                         intr->mask_misc_orig = intr->mask_misc;
1012                         /* only disable lsc interrupt */
1013                         intr->mask_misc &= ~NGBE_ICRMISC_PHY;
1014
1015                         intr->mask_orig = intr->mask;
1016                         /* only disable all misc interrupts */
1017                         intr->mask &= ~(1ULL << NGBE_MISC_VEC_ID);
1018                 }
1019         }
1020
1021         PMD_DRV_LOG(DEBUG, "enable intr immediately");
1022         ngbe_enable_intr(dev);
1023
1024         return 0;
1025 }
1026
1027 /**
1028  * Interrupt handler which shall be registered for alarm callback for delayed
1029  * handling specific interrupt to wait for the stable nic state. As the
1030  * NIC interrupt state is not stable for ngbe after link is just down,
1031  * it needs to wait 4 seconds to get the stable status.
1032  *
1033  * @param param
1034  *  The address of parameter (struct rte_eth_dev *) registered before.
1035  */
1036 static void
1037 ngbe_dev_interrupt_delayed_handler(void *param)
1038 {
1039         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1040         struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
1041         struct ngbe_hw *hw = ngbe_dev_hw(dev);
1042         uint32_t eicr;
1043
1044         ngbe_disable_intr(hw);
1045
1046         eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_MISC];
1047
1048         if (intr->flags & NGBE_FLAG_NEED_LINK_UPDATE) {
1049                 ngbe_dev_link_update(dev, 0);
1050                 intr->flags &= ~NGBE_FLAG_NEED_LINK_UPDATE;
1051                 ngbe_dev_link_status_print(dev);
1052                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
1053                                               NULL);
1054         }
1055
1056         if (intr->flags & NGBE_FLAG_MACSEC) {
1057                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
1058                                               NULL);
1059                 intr->flags &= ~NGBE_FLAG_MACSEC;
1060         }
1061
1062         /* restore original mask */
1063         intr->mask_misc = intr->mask_misc_orig;
1064         intr->mask_misc_orig = 0;
1065         intr->mask = intr->mask_orig;
1066         intr->mask_orig = 0;
1067
1068         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
1069         ngbe_enable_intr(dev);
1070 }
1071
1072 /**
1073  * Interrupt handler triggered by NIC  for handling
1074  * specific interrupt.
1075  *
1076  * @param param
1077  *  The address of parameter (struct rte_eth_dev *) registered before.
1078  */
1079 static void
1080 ngbe_dev_interrupt_handler(void *param)
1081 {
1082         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1083
1084         ngbe_dev_interrupt_get_status(dev);
1085         ngbe_dev_interrupt_action(dev);
1086 }
1087
1088 /**
1089  * Set the IVAR registers, mapping interrupt causes to vectors
1090  * @param hw
1091  *  pointer to ngbe_hw struct
1092  * @direction
1093  *  0 for Rx, 1 for Tx, -1 for other causes
1094  * @queue
1095  *  queue to map the corresponding interrupt to
1096  * @msix_vector
1097  *  the vector to map to the corresponding queue
1098  */
1099 void
1100 ngbe_set_ivar_map(struct ngbe_hw *hw, int8_t direction,
1101                    uint8_t queue, uint8_t msix_vector)
1102 {
1103         uint32_t tmp, idx;
1104
1105         if (direction == -1) {
1106                 /* other causes */
1107                 msix_vector |= NGBE_IVARMISC_VLD;
1108                 idx = 0;
1109                 tmp = rd32(hw, NGBE_IVARMISC);
1110                 tmp &= ~(0xFF << idx);
1111                 tmp |= (msix_vector << idx);
1112                 wr32(hw, NGBE_IVARMISC, tmp);
1113         } else {
1114                 /* rx or tx causes */
1115                 /* Workround for ICR lost */
1116                 idx = ((16 * (queue & 1)) + (8 * direction));
1117                 tmp = rd32(hw, NGBE_IVAR(queue >> 1));
1118                 tmp &= ~(0xFF << idx);
1119                 tmp |= (msix_vector << idx);
1120                 wr32(hw, NGBE_IVAR(queue >> 1), tmp);
1121         }
1122 }
1123
1124 /**
1125  * Sets up the hardware to properly generate MSI-X interrupts
1126  * @hw
1127  *  board private structure
1128  */
1129 static void
1130 ngbe_configure_msix(struct rte_eth_dev *dev)
1131 {
1132         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1133         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1134         struct ngbe_hw *hw = ngbe_dev_hw(dev);
1135         uint32_t queue_id, base = NGBE_MISC_VEC_ID;
1136         uint32_t vec = NGBE_MISC_VEC_ID;
1137         uint32_t gpie;
1138
1139         /*
1140          * Won't configure MSI-X register if no mapping is done
1141          * between intr vector and event fd
1142          * but if MSI-X has been enabled already, need to configure
1143          * auto clean, auto mask and throttling.
1144          */
1145         gpie = rd32(hw, NGBE_GPIE);
1146         if (!rte_intr_dp_is_en(intr_handle) &&
1147             !(gpie & NGBE_GPIE_MSIX))
1148                 return;
1149
1150         if (rte_intr_allow_others(intr_handle)) {
1151                 base = NGBE_RX_VEC_START;
1152                 vec = base;
1153         }
1154
1155         /* setup GPIE for MSI-X mode */
1156         gpie = rd32(hw, NGBE_GPIE);
1157         gpie |= NGBE_GPIE_MSIX;
1158         wr32(hw, NGBE_GPIE, gpie);
1159
1160         /* Populate the IVAR table and set the ITR values to the
1161          * corresponding register.
1162          */
1163         if (rte_intr_dp_is_en(intr_handle)) {
1164                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
1165                         queue_id++) {
1166                         /* by default, 1:1 mapping */
1167                         ngbe_set_ivar_map(hw, 0, queue_id, vec);
1168                         rte_intr_vec_list_index_set(intr_handle,
1169                                                            queue_id, vec);
1170                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
1171                             - 1)
1172                                 vec++;
1173                 }
1174
1175                 ngbe_set_ivar_map(hw, -1, 1, NGBE_MISC_VEC_ID);
1176         }
1177         wr32(hw, NGBE_ITR(NGBE_MISC_VEC_ID),
1178                         NGBE_ITR_IVAL_1G(NGBE_QUEUE_ITR_INTERVAL_DEFAULT)
1179                         | NGBE_ITR_WRDSA);
1180 }
1181
1182 static const struct eth_dev_ops ngbe_eth_dev_ops = {
1183         .dev_configure              = ngbe_dev_configure,
1184         .dev_infos_get              = ngbe_dev_info_get,
1185         .dev_start                  = ngbe_dev_start,
1186         .dev_stop                   = ngbe_dev_stop,
1187         .dev_close                  = ngbe_dev_close,
1188         .dev_reset                  = ngbe_dev_reset,
1189         .link_update                = ngbe_dev_link_update,
1190         .dev_supported_ptypes_get   = ngbe_dev_supported_ptypes_get,
1191         .rx_queue_start             = ngbe_dev_rx_queue_start,
1192         .rx_queue_stop              = ngbe_dev_rx_queue_stop,
1193         .tx_queue_start             = ngbe_dev_tx_queue_start,
1194         .tx_queue_stop              = ngbe_dev_tx_queue_stop,
1195         .rx_queue_setup             = ngbe_dev_rx_queue_setup,
1196         .rx_queue_release           = ngbe_dev_rx_queue_release,
1197         .tx_queue_setup             = ngbe_dev_tx_queue_setup,
1198         .tx_queue_release           = ngbe_dev_tx_queue_release,
1199         .rx_burst_mode_get          = ngbe_rx_burst_mode_get,
1200         .tx_burst_mode_get          = ngbe_tx_burst_mode_get,
1201 };
1202
1203 RTE_PMD_REGISTER_PCI(net_ngbe, rte_ngbe_pmd);
1204 RTE_PMD_REGISTER_PCI_TABLE(net_ngbe, pci_id_ngbe_map);
1205 RTE_PMD_REGISTER_KMOD_DEP(net_ngbe, "* igb_uio | uio_pci_generic | vfio-pci");
1206
1207 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_init, init, NOTICE);
1208 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_driver, driver, NOTICE);
1209
1210 #ifdef RTE_ETHDEV_DEBUG_RX
1211         RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_rx, rx, DEBUG);
1212 #endif
1213 #ifdef RTE_ETHDEV_DEBUG_TX
1214         RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_tx, tx, DEBUG);
1215 #endif