1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
7 #include <rte_common.h>
8 #include <ethdev_pci.h>
10 #include <rte_alarm.h>
12 #include "ngbe_logs.h"
14 #include "ngbe_ethdev.h"
15 #include "ngbe_rxtx.h"
17 static int ngbe_dev_close(struct rte_eth_dev *dev);
18 static int ngbe_dev_link_update(struct rte_eth_dev *dev,
19 int wait_to_complete);
21 static void ngbe_dev_link_status_print(struct rte_eth_dev *dev);
22 static int ngbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
23 static int ngbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
24 static int ngbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev);
25 static int ngbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
26 static void ngbe_dev_interrupt_handler(void *param);
27 static void ngbe_dev_interrupt_delayed_handler(void *param);
28 static void ngbe_configure_msix(struct rte_eth_dev *dev);
31 * The set of PCI devices this driver supports
33 static const struct rte_pci_id pci_id_ngbe_map[] = {
34 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A2) },
35 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A2S) },
36 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A4) },
37 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A4S) },
38 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL2) },
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL2S) },
40 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL4) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL4S) },
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860NCSI) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A1) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A1L) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL_W) },
46 { .vendor_id = 0, /* sentinel */ },
49 static const struct rte_eth_desc_lim rx_desc_lim = {
50 .nb_max = NGBE_RING_DESC_MAX,
51 .nb_min = NGBE_RING_DESC_MIN,
52 .nb_align = NGBE_RXD_ALIGN,
55 static const struct rte_eth_desc_lim tx_desc_lim = {
56 .nb_max = NGBE_RING_DESC_MAX,
57 .nb_min = NGBE_RING_DESC_MIN,
58 .nb_align = NGBE_TXD_ALIGN,
59 .nb_seg_max = NGBE_TX_MAX_SEG,
60 .nb_mtu_seg_max = NGBE_TX_MAX_SEG,
63 static const struct eth_dev_ops ngbe_eth_dev_ops;
66 ngbe_pf_reset_hw(struct ngbe_hw *hw)
71 status = hw->mac.reset_hw(hw);
73 ctrl_ext = rd32(hw, NGBE_PORTCTL);
74 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
75 ctrl_ext |= NGBE_PORTCTL_RSTDONE;
76 wr32(hw, NGBE_PORTCTL, ctrl_ext);
79 if (status == NGBE_ERR_SFP_NOT_PRESENT)
85 ngbe_enable_intr(struct rte_eth_dev *dev)
87 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
88 struct ngbe_hw *hw = ngbe_dev_hw(dev);
90 wr32(hw, NGBE_IENMISC, intr->mask_misc);
91 wr32(hw, NGBE_IMC(0), intr->mask & BIT_MASK32);
96 ngbe_disable_intr(struct ngbe_hw *hw)
98 PMD_INIT_FUNC_TRACE();
100 wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK);
105 * Ensure that all locks are released before first NVM or PHY access
108 ngbe_swfw_lock_reset(struct ngbe_hw *hw)
113 * These ones are more tricky since they are common to all ports; but
114 * swfw_sync retries last long enough (1s) to be almost sure that if
115 * lock can not be taken it is due to an improper lock of the
118 mask = NGBE_MNGSEM_SWPHY |
121 if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
122 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
124 hw->mac.release_swfw_sync(hw, mask);
128 eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
130 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
131 struct ngbe_hw *hw = ngbe_dev_hw(eth_dev);
132 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
133 const struct rte_memzone *mz;
137 PMD_INIT_FUNC_TRACE();
139 eth_dev->dev_ops = &ngbe_eth_dev_ops;
140 eth_dev->rx_pkt_burst = &ngbe_recv_pkts;
141 eth_dev->tx_pkt_burst = &ngbe_xmit_pkts_simple;
143 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
146 rte_eth_copy_pci_info(eth_dev, pci_dev);
148 /* Vendor and Device ID need to be set before init of shared code */
149 hw->device_id = pci_dev->id.device_id;
150 hw->vendor_id = pci_dev->id.vendor_id;
151 hw->sub_system_id = pci_dev->id.subsystem_device_id;
152 ngbe_map_device_id(hw);
153 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
155 /* Reserve memory for interrupt status block */
156 mz = rte_eth_dma_zone_reserve(eth_dev, "ngbe_driver", -1,
157 NGBE_ISB_SIZE, NGBE_ALIGN, SOCKET_ID_ANY);
161 hw->isb_dma = TMZ_PADDR(mz);
162 hw->isb_mem = TMZ_VADDR(mz);
164 /* Initialize the shared code (base driver) */
165 err = ngbe_init_shared_code(hw);
167 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
171 /* Unlock any pending hardware semaphore */
172 ngbe_swfw_lock_reset(hw);
174 err = hw->rom.init_params(hw);
176 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
180 /* Make sure we have a good EEPROM before we read from it */
181 err = hw->rom.validate_checksum(hw, NULL);
183 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
187 err = hw->mac.init_hw(hw);
189 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
193 /* disable interrupt */
194 ngbe_disable_intr(hw);
196 /* Allocate memory for storing MAC addresses */
197 eth_dev->data->mac_addrs = rte_zmalloc("ngbe", RTE_ETHER_ADDR_LEN *
198 hw->mac.num_rar_entries, 0);
199 if (eth_dev->data->mac_addrs == NULL) {
201 "Failed to allocate %u bytes needed to store MAC addresses",
202 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
206 /* Copy the permanent MAC address */
207 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
208 ð_dev->data->mac_addrs[0]);
210 /* Allocate memory for storing hash filter MAC addresses */
211 eth_dev->data->hash_mac_addrs = rte_zmalloc("ngbe",
212 RTE_ETHER_ADDR_LEN * NGBE_VMDQ_NUM_UC_MAC, 0);
213 if (eth_dev->data->hash_mac_addrs == NULL) {
215 "Failed to allocate %d bytes needed to store MAC addresses",
216 RTE_ETHER_ADDR_LEN * NGBE_VMDQ_NUM_UC_MAC);
217 rte_free(eth_dev->data->mac_addrs);
218 eth_dev->data->mac_addrs = NULL;
222 ctrl_ext = rd32(hw, NGBE_PORTCTL);
223 /* let hardware know driver is loaded */
224 ctrl_ext |= NGBE_PORTCTL_DRVLOAD;
225 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
226 ctrl_ext |= NGBE_PORTCTL_RSTDONE;
227 wr32(hw, NGBE_PORTCTL, ctrl_ext);
230 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
231 (int)hw->mac.type, (int)hw->phy.type);
233 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
234 eth_dev->data->port_id, pci_dev->id.vendor_id,
235 pci_dev->id.device_id);
237 rte_intr_callback_register(intr_handle,
238 ngbe_dev_interrupt_handler, eth_dev);
240 /* enable uio/vfio intr/eventfd mapping */
241 rte_intr_enable(intr_handle);
243 /* enable support intr */
244 ngbe_enable_intr(eth_dev);
250 eth_ngbe_dev_uninit(struct rte_eth_dev *eth_dev)
252 PMD_INIT_FUNC_TRACE();
254 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
257 ngbe_dev_close(eth_dev);
263 eth_ngbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
264 struct rte_pci_device *pci_dev)
266 return rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
267 sizeof(struct ngbe_adapter),
268 eth_dev_pci_specific_init, pci_dev,
269 eth_ngbe_dev_init, NULL);
272 static int eth_ngbe_pci_remove(struct rte_pci_device *pci_dev)
274 struct rte_eth_dev *ethdev;
276 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
280 return rte_eth_dev_destroy(ethdev, eth_ngbe_dev_uninit);
283 static struct rte_pci_driver rte_ngbe_pmd = {
284 .id_table = pci_id_ngbe_map,
285 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
286 RTE_PCI_DRV_INTR_LSC,
287 .probe = eth_ngbe_pci_probe,
288 .remove = eth_ngbe_pci_remove,
292 ngbe_dev_configure(struct rte_eth_dev *dev)
294 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
295 struct ngbe_adapter *adapter = ngbe_dev_adapter(dev);
297 PMD_INIT_FUNC_TRACE();
299 /* set flag to update link status after init */
300 intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE;
303 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
304 * allocation Rx preconditions we will reset it.
306 adapter->rx_bulk_alloc_allowed = true;
312 ngbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
314 struct ngbe_hw *hw = ngbe_dev_hw(dev);
315 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
317 wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));
318 wr32(hw, NGBE_GPIOINTEN, NGBE_GPIOINTEN_INT(3));
319 wr32(hw, NGBE_GPIOINTTYPE, NGBE_GPIOINTTYPE_LEVEL(0));
320 if (hw->phy.type == ngbe_phy_yt8521s_sfi)
321 wr32(hw, NGBE_GPIOINTPOL, NGBE_GPIOINTPOL_ACT(0));
323 wr32(hw, NGBE_GPIOINTPOL, NGBE_GPIOINTPOL_ACT(3));
325 intr->mask_misc |= NGBE_ICRMISC_GPIO;
329 * Configure device link speed and setup link.
330 * It returns 0 on success.
333 ngbe_dev_start(struct rte_eth_dev *dev)
335 struct ngbe_hw *hw = ngbe_dev_hw(dev);
336 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
337 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
338 uint32_t intr_vector = 0;
340 bool link_up = false, negotiate = false;
342 uint32_t allowed_speeds = 0;
344 uint32_t *link_speeds;
346 PMD_INIT_FUNC_TRACE();
348 /* disable uio/vfio intr/eventfd mapping */
349 rte_intr_disable(intr_handle);
352 hw->adapter_stopped = 0;
355 /* reinitialize adapter, this calls reset and start */
356 hw->nb_rx_queues = dev->data->nb_rx_queues;
357 hw->nb_tx_queues = dev->data->nb_tx_queues;
358 status = ngbe_pf_reset_hw(hw);
361 hw->mac.start_hw(hw);
362 hw->mac.get_link_status = true;
364 ngbe_dev_phy_intr_setup(dev);
366 /* check and configure queue intr-vector mapping */
367 if ((rte_intr_cap_multiple(intr_handle) ||
368 !RTE_ETH_DEV_SRIOV(dev).active) &&
369 dev->data->dev_conf.intr_conf.rxq != 0) {
370 intr_vector = dev->data->nb_rx_queues;
371 if (rte_intr_efd_enable(intr_handle, intr_vector))
375 if (rte_intr_dp_is_en(intr_handle)) {
376 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
377 dev->data->nb_rx_queues)) {
379 "Failed to allocate %d rx_queues intr_vec",
380 dev->data->nb_rx_queues);
385 /* confiugre MSI-X for sleep until Rx interrupt */
386 ngbe_configure_msix(dev);
388 /* initialize transmission unit */
389 ngbe_dev_tx_init(dev);
391 /* This can fail when allocating mbufs for descriptor rings */
392 err = ngbe_dev_rx_init(dev);
394 PMD_INIT_LOG(ERR, "Unable to initialize Rx hardware");
398 err = ngbe_dev_rxtx_start(dev);
400 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
404 err = hw->mac.check_link(hw, &speed, &link_up, 0);
407 dev->data->dev_link.link_status = link_up;
409 link_speeds = &dev->data->dev_conf.link_speeds;
410 if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG)
413 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
418 if (hw->mac.default_speeds & NGBE_LINK_SPEED_1GB_FULL)
419 allowed_speeds |= RTE_ETH_LINK_SPEED_1G;
420 if (hw->mac.default_speeds & NGBE_LINK_SPEED_100M_FULL)
421 allowed_speeds |= RTE_ETH_LINK_SPEED_100M;
422 if (hw->mac.default_speeds & NGBE_LINK_SPEED_10M_FULL)
423 allowed_speeds |= RTE_ETH_LINK_SPEED_10M;
425 if (*link_speeds & ~allowed_speeds) {
426 PMD_INIT_LOG(ERR, "Invalid link setting");
431 if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
432 speed = hw->mac.default_speeds;
434 if (*link_speeds & RTE_ETH_LINK_SPEED_1G)
435 speed |= NGBE_LINK_SPEED_1GB_FULL;
436 if (*link_speeds & RTE_ETH_LINK_SPEED_100M)
437 speed |= NGBE_LINK_SPEED_100M_FULL;
438 if (*link_speeds & RTE_ETH_LINK_SPEED_10M)
439 speed |= NGBE_LINK_SPEED_10M_FULL;
443 err = hw->mac.setup_link(hw, speed, link_up);
447 if (rte_intr_allow_others(intr_handle)) {
448 ngbe_dev_misc_interrupt_setup(dev);
449 /* check if lsc interrupt is enabled */
450 if (dev->data->dev_conf.intr_conf.lsc != 0)
451 ngbe_dev_lsc_interrupt_setup(dev, TRUE);
453 ngbe_dev_lsc_interrupt_setup(dev, FALSE);
454 ngbe_dev_macsec_interrupt_setup(dev);
455 ngbe_set_ivar_map(hw, -1, 1, NGBE_MISC_VEC_ID);
457 rte_intr_callback_unregister(intr_handle,
458 ngbe_dev_interrupt_handler, dev);
459 if (dev->data->dev_conf.intr_conf.lsc != 0)
461 "LSC won't enable because of no intr multiplex");
464 /* check if rxq interrupt is enabled */
465 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
466 rte_intr_dp_is_en(intr_handle))
467 ngbe_dev_rxq_interrupt_setup(dev);
469 /* enable UIO/VFIO intr/eventfd mapping */
470 rte_intr_enable(intr_handle);
472 /* resume enabled intr since HW reset */
473 ngbe_enable_intr(dev);
475 if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
476 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
477 /* gpio0 is used to power on/off control*/
478 wr32(hw, NGBE_GPIODATA, 0);
482 * Update link status right before return, because it may
483 * start link configuration process in a separate thread.
485 ngbe_dev_link_update(dev, 0);
490 PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
491 ngbe_dev_clear_queues(dev);
496 * Stop device: disable rx and tx functions to allow for reconfiguring.
499 ngbe_dev_stop(struct rte_eth_dev *dev)
501 struct rte_eth_link link;
502 struct ngbe_hw *hw = ngbe_dev_hw(dev);
503 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
504 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
506 if (hw->adapter_stopped)
509 PMD_INIT_FUNC_TRACE();
511 if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP ||
512 (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) {
513 /* gpio0 is used to power on/off control*/
514 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);
517 /* disable interrupts */
518 ngbe_disable_intr(hw);
521 ngbe_pf_reset_hw(hw);
522 hw->adapter_stopped = 0;
527 ngbe_dev_clear_queues(dev);
529 /* Clear recorded link status */
530 memset(&link, 0, sizeof(link));
531 rte_eth_linkstatus_set(dev, &link);
533 if (!rte_intr_allow_others(intr_handle))
534 /* resume to the default handler */
535 rte_intr_callback_register(intr_handle,
536 ngbe_dev_interrupt_handler,
539 /* Clean datapath event and queue/vec mapping */
540 rte_intr_efd_disable(intr_handle);
541 rte_intr_vec_list_free(intr_handle);
543 hw->adapter_stopped = true;
544 dev->data->dev_started = 0;
550 * Reset and stop device.
553 ngbe_dev_close(struct rte_eth_dev *dev)
555 struct ngbe_hw *hw = ngbe_dev_hw(dev);
556 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
557 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
561 PMD_INIT_FUNC_TRACE();
563 ngbe_pf_reset_hw(hw);
567 ngbe_dev_free_queues(dev);
569 /* reprogram the RAR[0] in case user changed it. */
570 ngbe_set_rar(hw, 0, hw->mac.addr, 0, true);
572 /* Unlock any pending hardware semaphore */
573 ngbe_swfw_lock_reset(hw);
575 /* disable uio intr before callback unregister */
576 rte_intr_disable(intr_handle);
579 ret = rte_intr_callback_unregister(intr_handle,
580 ngbe_dev_interrupt_handler, dev);
581 if (ret >= 0 || ret == -ENOENT) {
583 } else if (ret != -EAGAIN) {
585 "intr callback unregister failed: %d",
589 } while (retries++ < (10 + NGBE_LINK_UP_TIME));
591 rte_free(dev->data->mac_addrs);
592 dev->data->mac_addrs = NULL;
594 rte_free(dev->data->hash_mac_addrs);
595 dev->data->hash_mac_addrs = NULL;
604 ngbe_dev_reset(struct rte_eth_dev *dev)
608 ret = eth_ngbe_dev_uninit(dev);
612 ret = eth_ngbe_dev_init(dev, NULL);
618 ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
620 struct ngbe_hw *hw = ngbe_dev_hw(dev);
622 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
623 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
624 dev_info->min_rx_bufsize = 1024;
625 dev_info->max_rx_pktlen = 15872;
627 dev_info->default_rxconf = (struct rte_eth_rxconf) {
629 .pthresh = NGBE_DEFAULT_RX_PTHRESH,
630 .hthresh = NGBE_DEFAULT_RX_HTHRESH,
631 .wthresh = NGBE_DEFAULT_RX_WTHRESH,
633 .rx_free_thresh = NGBE_DEFAULT_RX_FREE_THRESH,
638 dev_info->default_txconf = (struct rte_eth_txconf) {
640 .pthresh = NGBE_DEFAULT_TX_PTHRESH,
641 .hthresh = NGBE_DEFAULT_TX_HTHRESH,
642 .wthresh = NGBE_DEFAULT_TX_WTHRESH,
644 .tx_free_thresh = NGBE_DEFAULT_TX_FREE_THRESH,
648 dev_info->rx_desc_lim = rx_desc_lim;
649 dev_info->tx_desc_lim = tx_desc_lim;
651 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_100M |
652 RTE_ETH_LINK_SPEED_10M;
654 /* Driver-preferred Rx/Tx parameters */
655 dev_info->default_rxportconf.burst_size = 32;
656 dev_info->default_txportconf.burst_size = 32;
657 dev_info->default_rxportconf.nb_queues = 1;
658 dev_info->default_txportconf.nb_queues = 1;
659 dev_info->default_rxportconf.ring_size = 256;
660 dev_info->default_txportconf.ring_size = 256;
666 ngbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
668 if (dev->rx_pkt_burst == ngbe_recv_pkts)
669 return ngbe_get_supported_ptypes();
674 /* return 0 means link status changed, -1 means not changed */
676 ngbe_dev_link_update_share(struct rte_eth_dev *dev,
677 int wait_to_complete)
679 struct ngbe_hw *hw = ngbe_dev_hw(dev);
680 struct rte_eth_link link;
681 u32 link_speed = NGBE_LINK_SPEED_UNKNOWN;
683 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
688 memset(&link, 0, sizeof(link));
689 link.link_status = RTE_ETH_LINK_DOWN;
690 link.link_speed = RTE_ETH_SPEED_NUM_NONE;
691 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
692 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
693 ~RTE_ETH_LINK_SPEED_AUTONEG);
695 hw->mac.get_link_status = true;
697 if (intr->flags & NGBE_FLAG_NEED_LINK_CONFIG)
698 return rte_eth_linkstatus_set(dev, &link);
700 /* check if it needs to wait to complete, if lsc interrupt is enabled */
701 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
704 err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
706 link.link_speed = RTE_ETH_SPEED_NUM_NONE;
707 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
708 return rte_eth_linkstatus_set(dev, &link);
712 return rte_eth_linkstatus_set(dev, &link);
714 intr->flags &= ~NGBE_FLAG_NEED_LINK_CONFIG;
715 link.link_status = RTE_ETH_LINK_UP;
716 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
718 switch (link_speed) {
720 case NGBE_LINK_SPEED_UNKNOWN:
721 link.link_speed = RTE_ETH_SPEED_NUM_NONE;
724 case NGBE_LINK_SPEED_10M_FULL:
725 link.link_speed = RTE_ETH_SPEED_NUM_10M;
729 case NGBE_LINK_SPEED_100M_FULL:
730 link.link_speed = RTE_ETH_SPEED_NUM_100M;
734 case NGBE_LINK_SPEED_1GB_FULL:
735 link.link_speed = RTE_ETH_SPEED_NUM_1G;
741 wr32m(hw, NGBE_LAN_SPEED, NGBE_LAN_SPEED_MASK, lan_speed);
742 if (link_speed & (NGBE_LINK_SPEED_1GB_FULL |
743 NGBE_LINK_SPEED_100M_FULL |
744 NGBE_LINK_SPEED_10M_FULL)) {
745 wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_SPEED_MASK,
746 NGBE_MACTXCFG_SPEED_1G | NGBE_MACTXCFG_TE);
750 return rte_eth_linkstatus_set(dev, &link);
754 ngbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
756 return ngbe_dev_link_update_share(dev, wait_to_complete);
760 * It clears the interrupt causes and enables the interrupt.
761 * It will be called once only during NIC initialized.
764 * Pointer to struct rte_eth_dev.
769 * - On success, zero.
770 * - On failure, a negative value.
773 ngbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
775 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
777 ngbe_dev_link_status_print(dev);
779 intr->mask_misc |= NGBE_ICRMISC_PHY;
780 intr->mask_misc |= NGBE_ICRMISC_GPIO;
782 intr->mask_misc &= ~NGBE_ICRMISC_PHY;
783 intr->mask_misc &= ~NGBE_ICRMISC_GPIO;
790 * It clears the interrupt causes and enables the interrupt.
791 * It will be called once only during NIC initialized.
794 * Pointer to struct rte_eth_dev.
797 * - On success, zero.
798 * - On failure, a negative value.
801 ngbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev)
803 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
806 mask = NGBE_ICR_MASK;
807 mask &= (1ULL << NGBE_MISC_VEC_ID);
809 intr->mask_misc |= NGBE_ICRMISC_GPIO;
815 * It clears the interrupt causes and enables the interrupt.
816 * It will be called once only during NIC initialized.
819 * Pointer to struct rte_eth_dev.
822 * - On success, zero.
823 * - On failure, a negative value.
826 ngbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
828 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
831 mask = NGBE_ICR_MASK;
832 mask &= ~((1ULL << NGBE_RX_VEC_START) - 1);
839 * It clears the interrupt causes and enables the interrupt.
840 * It will be called once only during NIC initialized.
843 * Pointer to struct rte_eth_dev.
846 * - On success, zero.
847 * - On failure, a negative value.
850 ngbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
852 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
854 intr->mask_misc |= NGBE_ICRMISC_LNKSEC;
860 * It reads ICR and sets flag for the link_update.
863 * Pointer to struct rte_eth_dev.
866 * - On success, zero.
867 * - On failure, a negative value.
870 ngbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
873 struct ngbe_hw *hw = ngbe_dev_hw(dev);
874 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
876 /* clear all cause mask */
877 ngbe_disable_intr(hw);
879 /* read-on-clear nic registers here */
880 eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_MISC];
881 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
885 /* set flag for async link update */
886 if (eicr & NGBE_ICRMISC_PHY)
887 intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE;
889 if (eicr & NGBE_ICRMISC_VFMBX)
890 intr->flags |= NGBE_FLAG_MAILBOX;
892 if (eicr & NGBE_ICRMISC_LNKSEC)
893 intr->flags |= NGBE_FLAG_MACSEC;
895 if (eicr & NGBE_ICRMISC_GPIO)
896 intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE;
902 * It gets and then prints the link status.
905 * Pointer to struct rte_eth_dev.
908 * - On success, zero.
909 * - On failure, a negative value.
912 ngbe_dev_link_status_print(struct rte_eth_dev *dev)
914 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
915 struct rte_eth_link link;
917 rte_eth_linkstatus_get(dev, &link);
919 if (link.link_status == RTE_ETH_LINK_UP) {
920 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
921 (int)(dev->data->port_id),
922 (unsigned int)link.link_speed,
923 link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ?
924 "full-duplex" : "half-duplex");
926 PMD_INIT_LOG(INFO, " Port %d: Link Down",
927 (int)(dev->data->port_id));
929 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
930 pci_dev->addr.domain,
933 pci_dev->addr.function);
937 * It executes link_update after knowing an interrupt occurred.
940 * Pointer to struct rte_eth_dev.
943 * - On success, zero.
944 * - On failure, a negative value.
947 ngbe_dev_interrupt_action(struct rte_eth_dev *dev)
949 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
952 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
954 if (intr->flags & NGBE_FLAG_NEED_LINK_UPDATE) {
955 struct rte_eth_link link;
957 /*get the link status before link update, for predicting later*/
958 rte_eth_linkstatus_get(dev, &link);
960 ngbe_dev_link_update(dev, 0);
963 if (link.link_status != RTE_ETH_LINK_UP)
964 /* handle it 1 sec later, wait it being stable */
965 timeout = NGBE_LINK_UP_CHECK_TIMEOUT;
968 /* handle it 4 sec later, wait it being stable */
969 timeout = NGBE_LINK_DOWN_CHECK_TIMEOUT;
971 ngbe_dev_link_status_print(dev);
972 if (rte_eal_alarm_set(timeout * 1000,
973 ngbe_dev_interrupt_delayed_handler,
975 PMD_DRV_LOG(ERR, "Error setting alarm");
977 /* remember original mask */
978 intr->mask_misc_orig = intr->mask_misc;
979 /* only disable lsc interrupt */
980 intr->mask_misc &= ~NGBE_ICRMISC_PHY;
982 intr->mask_orig = intr->mask;
983 /* only disable all misc interrupts */
984 intr->mask &= ~(1ULL << NGBE_MISC_VEC_ID);
988 PMD_DRV_LOG(DEBUG, "enable intr immediately");
989 ngbe_enable_intr(dev);
995 * Interrupt handler which shall be registered for alarm callback for delayed
996 * handling specific interrupt to wait for the stable nic state. As the
997 * NIC interrupt state is not stable for ngbe after link is just down,
998 * it needs to wait 4 seconds to get the stable status.
1001 * The address of parameter (struct rte_eth_dev *) registered before.
1004 ngbe_dev_interrupt_delayed_handler(void *param)
1006 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1007 struct ngbe_interrupt *intr = ngbe_dev_intr(dev);
1008 struct ngbe_hw *hw = ngbe_dev_hw(dev);
1011 ngbe_disable_intr(hw);
1013 eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_MISC];
1015 if (intr->flags & NGBE_FLAG_NEED_LINK_UPDATE) {
1016 ngbe_dev_link_update(dev, 0);
1017 intr->flags &= ~NGBE_FLAG_NEED_LINK_UPDATE;
1018 ngbe_dev_link_status_print(dev);
1019 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
1023 if (intr->flags & NGBE_FLAG_MACSEC) {
1024 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
1026 intr->flags &= ~NGBE_FLAG_MACSEC;
1029 /* restore original mask */
1030 intr->mask_misc = intr->mask_misc_orig;
1031 intr->mask_misc_orig = 0;
1032 intr->mask = intr->mask_orig;
1033 intr->mask_orig = 0;
1035 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
1036 ngbe_enable_intr(dev);
1040 * Interrupt handler triggered by NIC for handling
1041 * specific interrupt.
1044 * The address of parameter (struct rte_eth_dev *) registered before.
1047 ngbe_dev_interrupt_handler(void *param)
1049 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1051 ngbe_dev_interrupt_get_status(dev);
1052 ngbe_dev_interrupt_action(dev);
1056 * Set the IVAR registers, mapping interrupt causes to vectors
1058 * pointer to ngbe_hw struct
1060 * 0 for Rx, 1 for Tx, -1 for other causes
1062 * queue to map the corresponding interrupt to
1064 * the vector to map to the corresponding queue
1067 ngbe_set_ivar_map(struct ngbe_hw *hw, int8_t direction,
1068 uint8_t queue, uint8_t msix_vector)
1072 if (direction == -1) {
1074 msix_vector |= NGBE_IVARMISC_VLD;
1076 tmp = rd32(hw, NGBE_IVARMISC);
1077 tmp &= ~(0xFF << idx);
1078 tmp |= (msix_vector << idx);
1079 wr32(hw, NGBE_IVARMISC, tmp);
1081 /* rx or tx causes */
1082 /* Workround for ICR lost */
1083 idx = ((16 * (queue & 1)) + (8 * direction));
1084 tmp = rd32(hw, NGBE_IVAR(queue >> 1));
1085 tmp &= ~(0xFF << idx);
1086 tmp |= (msix_vector << idx);
1087 wr32(hw, NGBE_IVAR(queue >> 1), tmp);
1092 * Sets up the hardware to properly generate MSI-X interrupts
1094 * board private structure
1097 ngbe_configure_msix(struct rte_eth_dev *dev)
1099 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1100 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1101 struct ngbe_hw *hw = ngbe_dev_hw(dev);
1102 uint32_t queue_id, base = NGBE_MISC_VEC_ID;
1103 uint32_t vec = NGBE_MISC_VEC_ID;
1107 * Won't configure MSI-X register if no mapping is done
1108 * between intr vector and event fd
1109 * but if MSI-X has been enabled already, need to configure
1110 * auto clean, auto mask and throttling.
1112 gpie = rd32(hw, NGBE_GPIE);
1113 if (!rte_intr_dp_is_en(intr_handle) &&
1114 !(gpie & NGBE_GPIE_MSIX))
1117 if (rte_intr_allow_others(intr_handle)) {
1118 base = NGBE_RX_VEC_START;
1122 /* setup GPIE for MSI-X mode */
1123 gpie = rd32(hw, NGBE_GPIE);
1124 gpie |= NGBE_GPIE_MSIX;
1125 wr32(hw, NGBE_GPIE, gpie);
1127 /* Populate the IVAR table and set the ITR values to the
1128 * corresponding register.
1130 if (rte_intr_dp_is_en(intr_handle)) {
1131 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
1133 /* by default, 1:1 mapping */
1134 ngbe_set_ivar_map(hw, 0, queue_id, vec);
1135 rte_intr_vec_list_index_set(intr_handle,
1137 if (vec < base + rte_intr_nb_efd_get(intr_handle)
1142 ngbe_set_ivar_map(hw, -1, 1, NGBE_MISC_VEC_ID);
1144 wr32(hw, NGBE_ITR(NGBE_MISC_VEC_ID),
1145 NGBE_ITR_IVAL_1G(NGBE_QUEUE_ITR_INTERVAL_DEFAULT)
1149 static const struct eth_dev_ops ngbe_eth_dev_ops = {
1150 .dev_configure = ngbe_dev_configure,
1151 .dev_infos_get = ngbe_dev_info_get,
1152 .dev_start = ngbe_dev_start,
1153 .dev_stop = ngbe_dev_stop,
1154 .dev_close = ngbe_dev_close,
1155 .dev_reset = ngbe_dev_reset,
1156 .link_update = ngbe_dev_link_update,
1157 .dev_supported_ptypes_get = ngbe_dev_supported_ptypes_get,
1158 .rx_queue_start = ngbe_dev_rx_queue_start,
1159 .rx_queue_stop = ngbe_dev_rx_queue_stop,
1160 .tx_queue_start = ngbe_dev_tx_queue_start,
1161 .tx_queue_stop = ngbe_dev_tx_queue_stop,
1162 .rx_queue_setup = ngbe_dev_rx_queue_setup,
1163 .rx_queue_release = ngbe_dev_rx_queue_release,
1164 .tx_queue_setup = ngbe_dev_tx_queue_setup,
1165 .tx_queue_release = ngbe_dev_tx_queue_release,
1168 RTE_PMD_REGISTER_PCI(net_ngbe, rte_ngbe_pmd);
1169 RTE_PMD_REGISTER_PCI_TABLE(net_ngbe, pci_id_ngbe_map);
1170 RTE_PMD_REGISTER_KMOD_DEP(net_ngbe, "* igb_uio | uio_pci_generic | vfio-pci");
1172 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_init, init, NOTICE);
1173 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_driver, driver, NOTICE);
1175 #ifdef RTE_ETHDEV_DEBUG_RX
1176 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_rx, rx, DEBUG);
1178 #ifdef RTE_ETHDEV_DEBUG_TX
1179 RTE_LOG_REGISTER_SUFFIX(ngbe_logtype_tx, tx, DEBUG);