1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
9 #include <rte_ethdev.h>
10 #include <ethdev_driver.h>
11 #include <rte_malloc.h>
14 #include "ngbe_logs.h"
15 #include "base/ngbe.h"
16 #include "ngbe_ethdev.h"
17 #include "ngbe_rxtx.h"
19 /* Bit Mask to indicate what bits required for building Tx context */
20 static const u64 NGBE_TX_OFFLOAD_MASK = (RTE_MBUF_F_TX_IP_CKSUM |
21 RTE_MBUF_F_TX_OUTER_IPV6 |
22 RTE_MBUF_F_TX_OUTER_IPV4 |
26 RTE_MBUF_F_TX_L4_MASK |
27 RTE_MBUF_F_TX_TCP_SEG |
28 RTE_MBUF_F_TX_TUNNEL_MASK |
29 RTE_MBUF_F_TX_OUTER_IP_CKSUM);
30 #define NGBE_TX_OFFLOAD_NOTSUP_MASK \
31 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ NGBE_TX_OFFLOAD_MASK)
34 * Prefetch a cache line into all cache levels.
36 #define rte_ngbe_prefetch(p) rte_prefetch0(p)
38 /*********************************************************************
42 **********************************************************************/
45 * Check for descriptors with their DD bit set and free mbufs.
46 * Return the total number of buffers freed.
48 static __rte_always_inline int
49 ngbe_tx_free_bufs(struct ngbe_tx_queue *txq)
51 struct ngbe_tx_entry *txep;
54 struct rte_mbuf *m, *free[RTE_NGBE_TX_MAX_FREE_BUF_SZ];
56 /* check DD bit on threshold descriptor */
57 status = txq->tx_ring[txq->tx_next_dd].dw3;
58 if (!(status & rte_cpu_to_le_32(NGBE_TXD_DD))) {
59 if (txq->nb_tx_free >> 1 < txq->tx_free_thresh)
60 ngbe_set32_masked(txq->tdc_reg_addr,
61 NGBE_TXCFG_FLUSH, NGBE_TXCFG_FLUSH);
66 * first buffer to free from S/W ring is at index
67 * tx_next_dd - (tx_free_thresh-1)
69 txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_free_thresh - 1)];
70 for (i = 0; i < txq->tx_free_thresh; ++i, ++txep) {
71 /* free buffers one at a time */
72 m = rte_pktmbuf_prefree_seg(txep->mbuf);
75 if (unlikely(m == NULL))
78 if (nb_free >= RTE_NGBE_TX_MAX_FREE_BUF_SZ ||
79 (nb_free > 0 && m->pool != free[0]->pool)) {
80 rte_mempool_put_bulk(free[0]->pool,
81 (void **)free, nb_free);
89 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
91 /* buffers were freed, update counters */
92 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_free_thresh);
93 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_free_thresh);
94 if (txq->tx_next_dd >= txq->nb_tx_desc)
95 txq->tx_next_dd = (uint16_t)(txq->tx_free_thresh - 1);
97 return txq->tx_free_thresh;
100 /* Populate 4 descriptors with data from 4 mbufs */
102 tx4(volatile struct ngbe_tx_desc *txdp, struct rte_mbuf **pkts)
104 uint64_t buf_dma_addr;
108 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
109 buf_dma_addr = rte_mbuf_data_iova(*pkts);
110 pkt_len = (*pkts)->data_len;
112 /* write data to descriptor */
113 txdp->qw0 = rte_cpu_to_le_64(buf_dma_addr);
114 txdp->dw2 = cpu_to_le32(NGBE_TXD_FLAGS |
115 NGBE_TXD_DATLEN(pkt_len));
116 txdp->dw3 = cpu_to_le32(NGBE_TXD_PAYLEN(pkt_len));
118 rte_prefetch0(&(*pkts)->pool);
122 /* Populate 1 descriptor with data from 1 mbuf */
124 tx1(volatile struct ngbe_tx_desc *txdp, struct rte_mbuf **pkts)
126 uint64_t buf_dma_addr;
129 buf_dma_addr = rte_mbuf_data_iova(*pkts);
130 pkt_len = (*pkts)->data_len;
132 /* write data to descriptor */
133 txdp->qw0 = cpu_to_le64(buf_dma_addr);
134 txdp->dw2 = cpu_to_le32(NGBE_TXD_FLAGS |
135 NGBE_TXD_DATLEN(pkt_len));
136 txdp->dw3 = cpu_to_le32(NGBE_TXD_PAYLEN(pkt_len));
138 rte_prefetch0(&(*pkts)->pool);
142 * Fill H/W descriptor ring with mbuf data.
143 * Copy mbuf pointers to the S/W ring.
146 ngbe_tx_fill_hw_ring(struct ngbe_tx_queue *txq, struct rte_mbuf **pkts,
149 volatile struct ngbe_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
150 struct ngbe_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
151 const int N_PER_LOOP = 4;
152 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
153 int mainpart, leftover;
157 * Process most of the packets in chunks of N pkts. Any
158 * leftover packets will get processed one at a time.
160 mainpart = (nb_pkts & ((uint32_t)~N_PER_LOOP_MASK));
161 leftover = (nb_pkts & ((uint32_t)N_PER_LOOP_MASK));
162 for (i = 0; i < mainpart; i += N_PER_LOOP) {
163 /* Copy N mbuf pointers to the S/W ring */
164 for (j = 0; j < N_PER_LOOP; ++j)
165 (txep + i + j)->mbuf = *(pkts + i + j);
166 tx4(txdp + i, pkts + i);
169 if (unlikely(leftover > 0)) {
170 for (i = 0; i < leftover; ++i) {
171 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
172 tx1(txdp + mainpart + i, pkts + mainpart + i);
177 static inline uint16_t
178 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
181 struct ngbe_tx_queue *txq = (struct ngbe_tx_queue *)tx_queue;
185 * Begin scanning the H/W ring for done descriptors when the
186 * number of available descriptors drops below tx_free_thresh.
187 * For each done descriptor, free the associated buffer.
189 if (txq->nb_tx_free < txq->tx_free_thresh)
190 ngbe_tx_free_bufs(txq);
192 /* Only use descriptors that are available */
193 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
194 if (unlikely(nb_pkts == 0))
197 /* Use exactly nb_pkts descriptors */
198 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
201 * At this point, we know there are enough descriptors in the
202 * ring to transmit all the packets. This assumes that each
203 * mbuf contains a single segment, and that no new offloads
204 * are expected, which would require a new context descriptor.
208 * See if we're going to wrap-around. If so, handle the top
209 * of the descriptor ring first, then do the bottom. If not,
210 * the processing looks just like the "bottom" part anyway...
212 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
213 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
214 ngbe_tx_fill_hw_ring(txq, tx_pkts, n);
218 /* Fill H/W descriptor ring with mbuf data */
219 ngbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
220 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
223 * Check for wrap-around. This would only happen if we used
224 * up to the last descriptor in the ring, no more, no less.
226 if (txq->tx_tail >= txq->nb_tx_desc)
229 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
230 (uint16_t)txq->port_id, (uint16_t)txq->queue_id,
231 (uint16_t)txq->tx_tail, (uint16_t)nb_pkts);
233 /* update tail pointer */
235 ngbe_set32_relaxed(txq->tdt_reg_addr, txq->tx_tail);
241 ngbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
246 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
247 if (likely(nb_pkts <= RTE_PMD_NGBE_TX_MAX_BURST))
248 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
250 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
252 while (nb_pkts != 0) {
255 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_NGBE_TX_MAX_BURST);
256 ret = tx_xmit_pkts(tx_queue, &tx_pkts[nb_tx], n);
257 nb_tx = (uint16_t)(nb_tx + ret);
258 nb_pkts = (uint16_t)(nb_pkts - ret);
267 ngbe_set_xmit_ctx(struct ngbe_tx_queue *txq,
268 volatile struct ngbe_tx_ctx_desc *ctx_txd,
269 uint64_t ol_flags, union ngbe_tx_offload tx_offload)
271 union ngbe_tx_offload tx_offload_mask;
272 uint32_t type_tucmd_mlhl;
273 uint32_t mss_l4len_idx;
275 uint32_t vlan_macip_lens;
276 uint32_t tunnel_seed;
278 ctx_idx = txq->ctx_curr;
279 tx_offload_mask.data[0] = 0;
280 tx_offload_mask.data[1] = 0;
282 /* Specify which HW CTX to upload. */
283 mss_l4len_idx = NGBE_TXD_IDX(ctx_idx);
284 type_tucmd_mlhl = NGBE_TXD_CTXT;
286 tx_offload_mask.ptid |= ~0;
287 type_tucmd_mlhl |= NGBE_TXD_PTID(tx_offload.ptid);
289 /* check if TCP segmentation required for this packet */
290 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
291 tx_offload_mask.l2_len |= ~0;
292 tx_offload_mask.l3_len |= ~0;
293 tx_offload_mask.l4_len |= ~0;
294 tx_offload_mask.tso_segsz |= ~0;
295 mss_l4len_idx |= NGBE_TXD_MSS(tx_offload.tso_segsz);
296 mss_l4len_idx |= NGBE_TXD_L4LEN(tx_offload.l4_len);
297 } else { /* no TSO, check if hardware checksum is needed */
298 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
299 tx_offload_mask.l2_len |= ~0;
300 tx_offload_mask.l3_len |= ~0;
303 switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
304 case RTE_MBUF_F_TX_UDP_CKSUM:
306 NGBE_TXD_L4LEN(sizeof(struct rte_udp_hdr));
307 tx_offload_mask.l2_len |= ~0;
308 tx_offload_mask.l3_len |= ~0;
310 case RTE_MBUF_F_TX_TCP_CKSUM:
312 NGBE_TXD_L4LEN(sizeof(struct rte_tcp_hdr));
313 tx_offload_mask.l2_len |= ~0;
314 tx_offload_mask.l3_len |= ~0;
316 case RTE_MBUF_F_TX_SCTP_CKSUM:
318 NGBE_TXD_L4LEN(sizeof(struct rte_sctp_hdr));
319 tx_offload_mask.l2_len |= ~0;
320 tx_offload_mask.l3_len |= ~0;
327 vlan_macip_lens = NGBE_TXD_IPLEN(tx_offload.l3_len >> 1);
329 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
330 tx_offload_mask.outer_tun_len |= ~0;
331 tx_offload_mask.outer_l2_len |= ~0;
332 tx_offload_mask.outer_l3_len |= ~0;
333 tx_offload_mask.l2_len |= ~0;
334 tunnel_seed = NGBE_TXD_ETUNLEN(tx_offload.outer_tun_len >> 1);
335 tunnel_seed |= NGBE_TXD_EIPLEN(tx_offload.outer_l3_len >> 2);
337 switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
338 case RTE_MBUF_F_TX_TUNNEL_IPIP:
339 /* for non UDP / GRE tunneling, set to 0b */
342 PMD_TX_LOG(ERR, "Tunnel type not supported");
345 vlan_macip_lens |= NGBE_TXD_MACLEN(tx_offload.outer_l2_len);
348 vlan_macip_lens |= NGBE_TXD_MACLEN(tx_offload.l2_len);
351 if (ol_flags & RTE_MBUF_F_TX_VLAN) {
352 tx_offload_mask.vlan_tci |= ~0;
353 vlan_macip_lens |= NGBE_TXD_VLAN(tx_offload.vlan_tci);
356 txq->ctx_cache[ctx_idx].flags = ol_flags;
357 txq->ctx_cache[ctx_idx].tx_offload.data[0] =
358 tx_offload_mask.data[0] & tx_offload.data[0];
359 txq->ctx_cache[ctx_idx].tx_offload.data[1] =
360 tx_offload_mask.data[1] & tx_offload.data[1];
361 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
363 ctx_txd->dw0 = rte_cpu_to_le_32(vlan_macip_lens);
364 ctx_txd->dw1 = rte_cpu_to_le_32(tunnel_seed);
365 ctx_txd->dw2 = rte_cpu_to_le_32(type_tucmd_mlhl);
366 ctx_txd->dw3 = rte_cpu_to_le_32(mss_l4len_idx);
370 * Check which hardware context can be used. Use the existing match
371 * or create a new context descriptor.
373 static inline uint32_t
374 what_ctx_update(struct ngbe_tx_queue *txq, uint64_t flags,
375 union ngbe_tx_offload tx_offload)
377 /* If match with the current used context */
378 if (likely(txq->ctx_cache[txq->ctx_curr].flags == flags &&
379 (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
380 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
381 & tx_offload.data[0])) &&
382 (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
383 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
384 & tx_offload.data[1]))))
385 return txq->ctx_curr;
387 /* What if match with the next context */
389 if (likely(txq->ctx_cache[txq->ctx_curr].flags == flags &&
390 (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
391 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
392 & tx_offload.data[0])) &&
393 (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
394 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
395 & tx_offload.data[1]))))
396 return txq->ctx_curr;
398 /* Mismatch, use the previous context */
402 static inline uint32_t
403 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
407 if ((ol_flags & RTE_MBUF_F_TX_L4_MASK) != RTE_MBUF_F_TX_L4_NO_CKSUM) {
409 tmp |= NGBE_TXD_L4CS;
411 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
413 tmp |= NGBE_TXD_IPCS;
415 if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) {
417 tmp |= NGBE_TXD_EIPCS;
419 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
421 /* implies IPv4 cksum */
422 if (ol_flags & RTE_MBUF_F_TX_IPV4)
423 tmp |= NGBE_TXD_IPCS;
424 tmp |= NGBE_TXD_L4CS;
426 if (ol_flags & RTE_MBUF_F_TX_VLAN)
432 static inline uint32_t
433 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
435 uint32_t cmdtype = 0;
437 if (ol_flags & RTE_MBUF_F_TX_VLAN)
438 cmdtype |= NGBE_TXD_VLE;
439 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
440 cmdtype |= NGBE_TXD_TSE;
444 static inline uint8_t
445 tx_desc_ol_flags_to_ptid(uint64_t oflags, uint32_t ptype)
450 return ngbe_encode_ptype(ptype);
452 /* Only support flags in NGBE_TX_OFFLOAD_MASK */
453 tun = !!(oflags & RTE_MBUF_F_TX_TUNNEL_MASK);
456 ptype = RTE_PTYPE_L2_ETHER;
457 if (oflags & RTE_MBUF_F_TX_VLAN)
458 ptype |= RTE_PTYPE_L2_ETHER_VLAN;
461 if (oflags & (RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IP_CKSUM))
462 ptype |= RTE_PTYPE_L3_IPV4;
463 else if (oflags & (RTE_MBUF_F_TX_OUTER_IPV6))
464 ptype |= RTE_PTYPE_L3_IPV6;
466 if (oflags & (RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IP_CKSUM))
467 ptype |= (tun ? RTE_PTYPE_INNER_L3_IPV4 : RTE_PTYPE_L3_IPV4);
468 else if (oflags & (RTE_MBUF_F_TX_IPV6))
469 ptype |= (tun ? RTE_PTYPE_INNER_L3_IPV6 : RTE_PTYPE_L3_IPV6);
472 switch (oflags & (RTE_MBUF_F_TX_L4_MASK)) {
473 case RTE_MBUF_F_TX_TCP_CKSUM:
474 ptype |= (tun ? RTE_PTYPE_INNER_L4_TCP : RTE_PTYPE_L4_TCP);
476 case RTE_MBUF_F_TX_UDP_CKSUM:
477 ptype |= (tun ? RTE_PTYPE_INNER_L4_UDP : RTE_PTYPE_L4_UDP);
479 case RTE_MBUF_F_TX_SCTP_CKSUM:
480 ptype |= (tun ? RTE_PTYPE_INNER_L4_SCTP : RTE_PTYPE_L4_SCTP);
484 if (oflags & RTE_MBUF_F_TX_TCP_SEG)
485 ptype |= (tun ? RTE_PTYPE_INNER_L4_TCP : RTE_PTYPE_L4_TCP);
488 switch (oflags & RTE_MBUF_F_TX_TUNNEL_MASK) {
489 case RTE_MBUF_F_TX_TUNNEL_IPIP:
490 case RTE_MBUF_F_TX_TUNNEL_IP:
491 ptype |= RTE_PTYPE_L2_ETHER |
497 return ngbe_encode_ptype(ptype);
500 /* Reset transmit descriptors after they have been used */
502 ngbe_xmit_cleanup(struct ngbe_tx_queue *txq)
504 struct ngbe_tx_entry *sw_ring = txq->sw_ring;
505 volatile struct ngbe_tx_desc *txr = txq->tx_ring;
506 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
507 uint16_t nb_tx_desc = txq->nb_tx_desc;
508 uint16_t desc_to_clean_to;
509 uint16_t nb_tx_to_clean;
512 /* Determine the last descriptor needing to be cleaned */
513 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_free_thresh);
514 if (desc_to_clean_to >= nb_tx_desc)
515 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
517 /* Check to make sure the last descriptor to clean is done */
518 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
519 status = txr[desc_to_clean_to].dw3;
520 if (!(status & rte_cpu_to_le_32(NGBE_TXD_DD))) {
522 "Tx descriptor %4u is not done"
523 "(port=%d queue=%d)",
525 txq->port_id, txq->queue_id);
526 if (txq->nb_tx_free >> 1 < txq->tx_free_thresh)
527 ngbe_set32_masked(txq->tdc_reg_addr,
528 NGBE_TXCFG_FLUSH, NGBE_TXCFG_FLUSH);
529 /* Failed to clean any descriptors, better luck next time */
533 /* Figure out how many descriptors will be cleaned */
534 if (last_desc_cleaned > desc_to_clean_to)
535 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
538 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
542 "Cleaning %4u Tx descriptors: %4u to %4u (port=%d queue=%d)",
543 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
544 txq->port_id, txq->queue_id);
547 * The last descriptor to clean is done, so that means all the
548 * descriptors from the last descriptor that was cleaned
549 * up to the last descriptor with the RS bit set
550 * are done. Only reset the threshold descriptor.
552 txr[desc_to_clean_to].dw3 = 0;
554 /* Update the txq to reflect the last descriptor that was cleaned */
555 txq->last_desc_cleaned = desc_to_clean_to;
556 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
563 ngbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
566 struct ngbe_tx_queue *txq;
567 struct ngbe_tx_entry *sw_ring;
568 struct ngbe_tx_entry *txe, *txn;
569 volatile struct ngbe_tx_desc *txr;
570 volatile struct ngbe_tx_desc *txd;
571 struct rte_mbuf *tx_pkt;
572 struct rte_mbuf *m_seg;
573 uint64_t buf_dma_addr;
574 uint32_t olinfo_status;
575 uint32_t cmd_type_len;
586 union ngbe_tx_offload tx_offload;
588 tx_offload.data[0] = 0;
589 tx_offload.data[1] = 0;
591 sw_ring = txq->sw_ring;
593 tx_id = txq->tx_tail;
594 txe = &sw_ring[tx_id];
596 /* Determine if the descriptor ring needs to be cleaned. */
597 if (txq->nb_tx_free < txq->tx_free_thresh)
598 ngbe_xmit_cleanup(txq);
600 rte_prefetch0(&txe->mbuf->pool);
603 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
606 pkt_len = tx_pkt->pkt_len;
609 * Determine how many (if any) context descriptors
610 * are needed for offload functionality.
612 ol_flags = tx_pkt->ol_flags;
614 /* If hardware offload required */
615 tx_ol_req = ol_flags & NGBE_TX_OFFLOAD_MASK;
617 tx_offload.ptid = tx_desc_ol_flags_to_ptid(tx_ol_req,
618 tx_pkt->packet_type);
619 tx_offload.l2_len = tx_pkt->l2_len;
620 tx_offload.l3_len = tx_pkt->l3_len;
621 tx_offload.l4_len = tx_pkt->l4_len;
622 tx_offload.vlan_tci = tx_pkt->vlan_tci;
623 tx_offload.tso_segsz = tx_pkt->tso_segsz;
624 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
625 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
626 tx_offload.outer_tun_len = 0;
628 /* If new context need be built or reuse the exist ctx*/
629 ctx = what_ctx_update(txq, tx_ol_req, tx_offload);
630 /* Only allocate context descriptor if required */
631 new_ctx = (ctx == NGBE_CTX_NUM);
636 * Keep track of how many descriptors are used this loop
637 * This will always be the number of segments + the number of
638 * Context descriptors required to transmit the packet
640 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
643 * The number of descriptors that must be allocated for a
644 * packet is the number of segments of that packet, plus 1
645 * Context Descriptor for the hardware offload, if any.
646 * Determine the last Tx descriptor to allocate in the Tx ring
647 * for the packet, starting from the current position (tx_id)
650 tx_last = (uint16_t)(tx_id + nb_used - 1);
653 if (tx_last >= txq->nb_tx_desc)
654 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
656 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
657 " tx_first=%u tx_last=%u",
658 (uint16_t)txq->port_id,
659 (uint16_t)txq->queue_id,
665 * Make sure there are enough Tx descriptors available to
666 * transmit the entire packet.
667 * nb_used better be less than or equal to txq->tx_free_thresh
669 if (nb_used > txq->nb_tx_free) {
671 "Not enough free Tx descriptors "
672 "nb_used=%4u nb_free=%4u "
673 "(port=%d queue=%d)",
674 nb_used, txq->nb_tx_free,
675 txq->port_id, txq->queue_id);
677 if (ngbe_xmit_cleanup(txq) != 0) {
678 /* Could not clean any descriptors */
684 /* nb_used better be <= txq->tx_free_thresh */
685 if (unlikely(nb_used > txq->tx_free_thresh)) {
687 "The number of descriptors needed to "
688 "transmit the packet exceeds the "
689 "RS bit threshold. This will impact "
691 "nb_used=%4u nb_free=%4u "
692 "tx_free_thresh=%4u. "
693 "(port=%d queue=%d)",
694 nb_used, txq->nb_tx_free,
696 txq->port_id, txq->queue_id);
698 * Loop here until there are enough Tx
699 * descriptors or until the ring cannot be
702 while (nb_used > txq->nb_tx_free) {
703 if (ngbe_xmit_cleanup(txq) != 0) {
705 * Could not clean any
717 * By now there are enough free Tx descriptors to transmit
722 * Set common flags of all Tx Data Descriptors.
724 * The following bits must be set in the first Data Descriptor
725 * and are ignored in the other ones:
728 * The following bits must only be set in the last Data
732 cmd_type_len = NGBE_TXD_FCS;
736 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
737 /* when TSO is on, paylen in descriptor is the
738 * not the packet len but the tcp payload len
740 pkt_len -= (tx_offload.l2_len +
741 tx_offload.l3_len + tx_offload.l4_len);
743 (tx_pkt->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
744 ? tx_offload.outer_l2_len +
745 tx_offload.outer_l3_len : 0;
749 * Setup the Tx Context Descriptor if required
752 volatile struct ngbe_tx_ctx_desc *ctx_txd;
754 ctx_txd = (volatile struct ngbe_tx_ctx_desc *)
757 txn = &sw_ring[txe->next_id];
758 rte_prefetch0(&txn->mbuf->pool);
760 if (txe->mbuf != NULL) {
761 rte_pktmbuf_free_seg(txe->mbuf);
765 ngbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
768 txe->last_id = tx_last;
769 tx_id = txe->next_id;
774 * Setup the Tx Data Descriptor,
775 * This path will go through
776 * whatever new/reuse the context descriptor
778 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
780 tx_desc_cksum_flags_to_olinfo(ol_flags);
781 olinfo_status |= NGBE_TXD_IDX(ctx);
784 olinfo_status |= NGBE_TXD_PAYLEN(pkt_len);
789 txn = &sw_ring[txe->next_id];
790 rte_prefetch0(&txn->mbuf->pool);
792 if (txe->mbuf != NULL)
793 rte_pktmbuf_free_seg(txe->mbuf);
797 * Set up Transmit Data Descriptor.
799 slen = m_seg->data_len;
800 buf_dma_addr = rte_mbuf_data_iova(m_seg);
801 txd->qw0 = rte_cpu_to_le_64(buf_dma_addr);
802 txd->dw2 = rte_cpu_to_le_32(cmd_type_len | slen);
803 txd->dw3 = rte_cpu_to_le_32(olinfo_status);
804 txe->last_id = tx_last;
805 tx_id = txe->next_id;
808 } while (m_seg != NULL);
811 * The last packet data descriptor needs End Of Packet (EOP)
813 cmd_type_len |= NGBE_TXD_EOP;
814 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
816 txd->dw2 |= rte_cpu_to_le_32(cmd_type_len);
824 * Set the Transmit Descriptor Tail (TDT)
826 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
827 (uint16_t)txq->port_id, (uint16_t)txq->queue_id,
828 (uint16_t)tx_id, (uint16_t)nb_tx);
829 ngbe_set32_relaxed(txq->tdt_reg_addr, tx_id);
830 txq->tx_tail = tx_id;
835 /*********************************************************************
839 **********************************************************************/
841 ngbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
846 struct ngbe_tx_queue *txq = (struct ngbe_tx_queue *)tx_queue;
848 for (i = 0; i < nb_pkts; i++) {
850 ol_flags = m->ol_flags;
853 * Check if packet meets requirements for number of segments
855 * NOTE: for ngbe it's always (40 - WTHRESH) for both TSO and
859 if (m->nb_segs > NGBE_TX_MAX_SEG - txq->wthresh) {
864 if (ol_flags & NGBE_TX_OFFLOAD_NOTSUP_MASK) {
865 rte_errno = -ENOTSUP;
869 #ifdef RTE_ETHDEV_DEBUG_TX
870 ret = rte_validate_tx_offload(m);
876 ret = rte_net_intel_cksum_prepare(m);
886 /*********************************************************************
890 **********************************************************************/
891 static inline uint32_t
892 ngbe_rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint16_t ptid_mask)
894 uint16_t ptid = NGBE_RXD_PTID(pkt_info);
898 return ngbe_decode_ptype(ptid);
901 static inline uint64_t
902 ngbe_rxd_pkt_info_to_pkt_flags(uint32_t pkt_info)
904 static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
905 0, RTE_MBUF_F_RX_RSS_HASH, RTE_MBUF_F_RX_RSS_HASH, RTE_MBUF_F_RX_RSS_HASH,
906 0, RTE_MBUF_F_RX_RSS_HASH, 0, RTE_MBUF_F_RX_RSS_HASH,
907 RTE_MBUF_F_RX_RSS_HASH, 0, 0, 0,
908 0, 0, 0, RTE_MBUF_F_RX_FDIR,
910 return ip_rss_types_map[NGBE_RXD_RSSTYPE(pkt_info)];
913 static inline uint64_t
914 rx_desc_status_to_pkt_flags(uint32_t rx_status, uint64_t vlan_flags)
919 * Check if VLAN present only.
920 * Do not check whether L3/L4 rx checksum done by NIC or not,
921 * That can be found from rte_eth_rxmode.offloads flag
923 pkt_flags = (rx_status & NGBE_RXD_STAT_VLAN &&
924 vlan_flags & RTE_MBUF_F_RX_VLAN_STRIPPED)
930 static inline uint64_t
931 rx_desc_error_to_pkt_flags(uint32_t rx_status)
933 uint64_t pkt_flags = 0;
935 /* checksum offload can't be disabled */
936 if (rx_status & NGBE_RXD_STAT_IPCS)
937 pkt_flags |= (rx_status & NGBE_RXD_ERR_IPCS
938 ? RTE_MBUF_F_RX_IP_CKSUM_BAD : RTE_MBUF_F_RX_IP_CKSUM_GOOD);
940 if (rx_status & NGBE_RXD_STAT_L4CS)
941 pkt_flags |= (rx_status & NGBE_RXD_ERR_L4CS
942 ? RTE_MBUF_F_RX_L4_CKSUM_BAD : RTE_MBUF_F_RX_L4_CKSUM_GOOD);
944 if (rx_status & NGBE_RXD_STAT_EIPCS &&
945 rx_status & NGBE_RXD_ERR_EIPCS)
946 pkt_flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
952 * LOOK_AHEAD defines how many desc statuses to check beyond the
953 * current descriptor.
954 * It must be a pound define for optimal performance.
955 * Do not change the value of LOOK_AHEAD, as the ngbe_rx_scan_hw_ring
956 * function only works with LOOK_AHEAD=8.
959 #if (LOOK_AHEAD != 8)
960 #error "PMD NGBE: LOOK_AHEAD must be 8\n"
963 ngbe_rx_scan_hw_ring(struct ngbe_rx_queue *rxq)
965 volatile struct ngbe_rx_desc *rxdp;
966 struct ngbe_rx_entry *rxep;
971 uint32_t s[LOOK_AHEAD];
972 uint32_t pkt_info[LOOK_AHEAD];
976 /* get references to current descriptor and S/W ring entry */
977 rxdp = &rxq->rx_ring[rxq->rx_tail];
978 rxep = &rxq->sw_ring[rxq->rx_tail];
980 status = rxdp->qw1.lo.status;
981 /* check to make sure there is at least 1 packet to receive */
982 if (!(status & rte_cpu_to_le_32(NGBE_RXD_STAT_DD)))
986 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
987 * reference packets that are ready to be received.
989 for (i = 0; i < RTE_PMD_NGBE_RX_MAX_BURST;
990 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD) {
991 /* Read desc statuses backwards to avoid race condition */
992 for (j = 0; j < LOOK_AHEAD; j++)
993 s[j] = rte_le_to_cpu_32(rxdp[j].qw1.lo.status);
995 rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
997 /* Compute how many status bits were set */
998 for (nb_dd = 0; nb_dd < LOOK_AHEAD &&
999 (s[nb_dd] & NGBE_RXD_STAT_DD); nb_dd++)
1002 for (j = 0; j < nb_dd; j++)
1003 pkt_info[j] = rte_le_to_cpu_32(rxdp[j].qw0.dw0);
1007 /* Translate descriptor info to mbuf format */
1008 for (j = 0; j < nb_dd; ++j) {
1010 pkt_len = rte_le_to_cpu_16(rxdp[j].qw1.hi.len) -
1012 mb->data_len = pkt_len;
1013 mb->pkt_len = pkt_len;
1014 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].qw1.hi.tag);
1016 /* convert descriptor fields to rte mbuf flags */
1017 pkt_flags = rx_desc_status_to_pkt_flags(s[j],
1019 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1021 ngbe_rxd_pkt_info_to_pkt_flags(pkt_info[j]);
1022 mb->ol_flags = pkt_flags;
1024 ngbe_rxd_pkt_info_to_pkt_type(pkt_info[j],
1027 if (likely(pkt_flags & RTE_MBUF_F_RX_RSS_HASH))
1029 rte_le_to_cpu_32(rxdp[j].qw0.dw1);
1032 /* Move mbuf pointers from the S/W ring to the stage */
1033 for (j = 0; j < LOOK_AHEAD; ++j)
1034 rxq->rx_stage[i + j] = rxep[j].mbuf;
1036 /* stop if all requested packets could not be received */
1037 if (nb_dd != LOOK_AHEAD)
1041 /* clear software ring entries so we can cleanup correctly */
1042 for (i = 0; i < nb_rx; ++i)
1043 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1049 ngbe_rx_alloc_bufs(struct ngbe_rx_queue *rxq, bool reset_mbuf)
1051 volatile struct ngbe_rx_desc *rxdp;
1052 struct ngbe_rx_entry *rxep;
1053 struct rte_mbuf *mb;
1058 /* allocate buffers in bulk directly into the S/W ring */
1059 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1060 rxep = &rxq->sw_ring[alloc_idx];
1061 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1062 rxq->rx_free_thresh);
1063 if (unlikely(diag != 0))
1066 rxdp = &rxq->rx_ring[alloc_idx];
1067 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1068 /* populate the static rte mbuf fields */
1071 mb->port = rxq->port_id;
1073 rte_mbuf_refcnt_set(mb, 1);
1074 mb->data_off = RTE_PKTMBUF_HEADROOM;
1076 /* populate the descriptors */
1077 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1078 NGBE_RXD_HDRADDR(&rxdp[i], 0);
1079 NGBE_RXD_PKTADDR(&rxdp[i], dma_addr);
1082 /* update state of internal queue structure */
1083 rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1084 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1085 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1091 static inline uint16_t
1092 ngbe_rx_fill_from_stage(struct ngbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1095 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1098 /* how many packets are ready to return? */
1099 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1101 /* copy mbuf pointers to the application's packet list */
1102 for (i = 0; i < nb_pkts; ++i)
1103 rx_pkts[i] = stage[i];
1105 /* update internal queue state */
1106 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1107 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1112 static inline uint16_t
1113 ngbe_rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1116 struct ngbe_rx_queue *rxq = (struct ngbe_rx_queue *)rx_queue;
1117 struct rte_eth_dev *dev = &rte_eth_devices[rxq->port_id];
1120 /* Any previously recv'd pkts will be returned from the Rx stage */
1121 if (rxq->rx_nb_avail)
1122 return ngbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1124 /* Scan the H/W ring for packets to receive */
1125 nb_rx = (uint16_t)ngbe_rx_scan_hw_ring(rxq);
1127 /* update internal queue state */
1128 rxq->rx_next_avail = 0;
1129 rxq->rx_nb_avail = nb_rx;
1130 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1132 /* if required, allocate new buffers to replenish descriptors */
1133 if (rxq->rx_tail > rxq->rx_free_trigger) {
1134 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1136 if (ngbe_rx_alloc_bufs(rxq, true) != 0) {
1139 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1140 "queue_id=%u", (uint16_t)rxq->port_id,
1141 (uint16_t)rxq->queue_id);
1143 dev->data->rx_mbuf_alloc_failed +=
1144 rxq->rx_free_thresh;
1147 * Need to rewind any previous receives if we cannot
1148 * allocate new buffers to replenish the old ones.
1150 rxq->rx_nb_avail = 0;
1151 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1152 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1153 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1158 /* update tail pointer */
1160 ngbe_set32_relaxed(rxq->rdt_reg_addr, cur_free_trigger);
1163 if (rxq->rx_tail >= rxq->nb_rx_desc)
1166 /* received any packets this loop? */
1167 if (rxq->rx_nb_avail)
1168 return ngbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1173 /* split requests into chunks of size RTE_PMD_NGBE_RX_MAX_BURST */
1175 ngbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1180 if (unlikely(nb_pkts == 0))
1183 if (likely(nb_pkts <= RTE_PMD_NGBE_RX_MAX_BURST))
1184 return ngbe_rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1186 /* request is relatively large, chunk it up */
1191 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_NGBE_RX_MAX_BURST);
1192 ret = ngbe_rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1193 nb_rx = (uint16_t)(nb_rx + ret);
1194 nb_pkts = (uint16_t)(nb_pkts - ret);
1203 ngbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1206 struct ngbe_rx_queue *rxq;
1207 volatile struct ngbe_rx_desc *rx_ring;
1208 volatile struct ngbe_rx_desc *rxdp;
1209 struct ngbe_rx_entry *sw_ring;
1210 struct ngbe_rx_entry *rxe;
1211 struct rte_mbuf *rxm;
1212 struct rte_mbuf *nmb;
1213 struct ngbe_rx_desc rxd;
1226 rx_id = rxq->rx_tail;
1227 rx_ring = rxq->rx_ring;
1228 sw_ring = rxq->sw_ring;
1229 struct rte_eth_dev *dev = &rte_eth_devices[rxq->port_id];
1230 while (nb_rx < nb_pkts) {
1232 * The order of operations here is important as the DD status
1233 * bit must not be read after any other descriptor fields.
1234 * rx_ring and rxdp are pointing to volatile data so the order
1235 * of accesses cannot be reordered by the compiler. If they were
1236 * not volatile, they could be reordered which could lead to
1237 * using invalid descriptor fields when read from rxd.
1239 rxdp = &rx_ring[rx_id];
1240 staterr = rxdp->qw1.lo.status;
1241 if (!(staterr & rte_cpu_to_le_32(NGBE_RXD_STAT_DD)))
1248 * If the NGBE_RXD_STAT_EOP flag is not set, the Rx packet
1249 * is likely to be invalid and to be dropped by the various
1250 * validation checks performed by the network stack.
1252 * Allocate a new mbuf to replenish the RX ring descriptor.
1253 * If the allocation fails:
1254 * - arrange for that Rx descriptor to be the first one
1255 * being parsed the next time the receive function is
1256 * invoked [on the same queue].
1258 * - Stop parsing the Rx ring and return immediately.
1260 * This policy do not drop the packet received in the Rx
1261 * descriptor for which the allocation of a new mbuf failed.
1262 * Thus, it allows that packet to be later retrieved if
1263 * mbuf have been freed in the mean time.
1264 * As a side effect, holding Rx descriptors instead of
1265 * systematically giving them back to the NIC may lead to
1266 * Rx ring exhaustion situations.
1267 * However, the NIC can gracefully prevent such situations
1268 * to happen by sending specific "back-pressure" flow control
1269 * frames to its peer(s).
1272 "port_id=%u queue_id=%u rx_id=%u ext_err_stat=0x%08x pkt_len=%u",
1273 (uint16_t)rxq->port_id, (uint16_t)rxq->queue_id,
1274 (uint16_t)rx_id, (uint32_t)staterr,
1275 (uint16_t)rte_le_to_cpu_16(rxd.qw1.hi.len));
1277 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1280 "Rx mbuf alloc failed port_id=%u queue_id=%u",
1281 (uint16_t)rxq->port_id,
1282 (uint16_t)rxq->queue_id);
1283 dev->data->rx_mbuf_alloc_failed++;
1288 rxe = &sw_ring[rx_id];
1290 if (rx_id == rxq->nb_rx_desc)
1293 /* Prefetch next mbuf while processing current one. */
1294 rte_ngbe_prefetch(sw_ring[rx_id].mbuf);
1297 * When next Rx descriptor is on a cache-line boundary,
1298 * prefetch the next 4 Rx descriptors and the next 8 pointers
1301 if ((rx_id & 0x3) == 0) {
1302 rte_ngbe_prefetch(&rx_ring[rx_id]);
1303 rte_ngbe_prefetch(&sw_ring[rx_id]);
1308 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1309 NGBE_RXD_HDRADDR(rxdp, 0);
1310 NGBE_RXD_PKTADDR(rxdp, dma_addr);
1313 * Initialize the returned mbuf.
1314 * 1) setup generic mbuf fields:
1315 * - number of segments,
1318 * - Rx port identifier.
1319 * 2) integrate hardware offload data, if any:
1320 * - RSS flag & hash,
1321 * - IP checksum flag,
1322 * - VLAN TCI, if any,
1325 pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.qw1.hi.len) -
1327 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1328 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1331 rxm->pkt_len = pkt_len;
1332 rxm->data_len = pkt_len;
1333 rxm->port = rxq->port_id;
1335 pkt_info = rte_le_to_cpu_32(rxd.qw0.dw0);
1336 /* Only valid if RTE_MBUF_F_RX_VLAN set in pkt_flags */
1337 rxm->vlan_tci = rte_le_to_cpu_16(rxd.qw1.hi.tag);
1339 pkt_flags = rx_desc_status_to_pkt_flags(staterr,
1341 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1342 pkt_flags |= ngbe_rxd_pkt_info_to_pkt_flags(pkt_info);
1343 rxm->ol_flags = pkt_flags;
1344 rxm->packet_type = ngbe_rxd_pkt_info_to_pkt_type(pkt_info,
1347 if (likely(pkt_flags & RTE_MBUF_F_RX_RSS_HASH))
1348 rxm->hash.rss = rte_le_to_cpu_32(rxd.qw0.dw1);
1351 * Store the mbuf address into the next entry of the array
1352 * of returned packets.
1354 rx_pkts[nb_rx++] = rxm;
1356 rxq->rx_tail = rx_id;
1359 * If the number of free Rx descriptors is greater than the Rx free
1360 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1362 * Update the RDT with the value of the last processed Rx descriptor
1363 * minus 1, to guarantee that the RDT register is never equal to the
1364 * RDH register, which creates a "full" ring situation from the
1365 * hardware point of view...
1367 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1368 if (nb_hold > rxq->rx_free_thresh) {
1370 "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u nb_rx=%u",
1371 (uint16_t)rxq->port_id, (uint16_t)rxq->queue_id,
1372 (uint16_t)rx_id, (uint16_t)nb_hold,
1374 rx_id = (uint16_t)((rx_id == 0) ?
1375 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1376 ngbe_set32(rxq->rdt_reg_addr, rx_id);
1379 rxq->nb_rx_hold = nb_hold;
1384 * ngbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1386 * Fill the following info in the HEAD buffer of the Rx cluster:
1387 * - RX port identifier
1388 * - hardware offload data, if any:
1390 * - IP checksum flag
1391 * - VLAN TCI, if any
1393 * @head HEAD of the packet cluster
1394 * @desc HW descriptor to get data from
1395 * @rxq Pointer to the Rx queue
1398 ngbe_fill_cluster_head_buf(struct rte_mbuf *head, struct ngbe_rx_desc *desc,
1399 struct ngbe_rx_queue *rxq, uint32_t staterr)
1404 head->port = rxq->port_id;
1406 /* The vlan_tci field is only valid when RTE_MBUF_F_RX_VLAN is
1407 * set in the pkt_flags field.
1409 head->vlan_tci = rte_le_to_cpu_16(desc->qw1.hi.tag);
1410 pkt_info = rte_le_to_cpu_32(desc->qw0.dw0);
1411 pkt_flags = rx_desc_status_to_pkt_flags(staterr, rxq->vlan_flags);
1412 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1413 pkt_flags |= ngbe_rxd_pkt_info_to_pkt_flags(pkt_info);
1414 head->ol_flags = pkt_flags;
1415 head->packet_type = ngbe_rxd_pkt_info_to_pkt_type(pkt_info,
1418 if (likely(pkt_flags & RTE_MBUF_F_RX_RSS_HASH))
1419 head->hash.rss = rte_le_to_cpu_32(desc->qw0.dw1);
1423 * ngbe_recv_pkts_sc - receive handler for scatter case.
1425 * @rx_queue Rx queue handle
1426 * @rx_pkts table of received packets
1427 * @nb_pkts size of rx_pkts table
1428 * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1430 * Returns the number of received packets/clusters (according to the "bulk
1431 * receive" interface).
1433 static inline uint16_t
1434 ngbe_recv_pkts_sc(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
1437 struct ngbe_rx_queue *rxq = rx_queue;
1438 struct rte_eth_dev *dev = &rte_eth_devices[rxq->port_id];
1439 volatile struct ngbe_rx_desc *rx_ring = rxq->rx_ring;
1440 struct ngbe_rx_entry *sw_ring = rxq->sw_ring;
1441 struct ngbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
1442 uint16_t rx_id = rxq->rx_tail;
1444 uint16_t nb_hold = rxq->nb_rx_hold;
1445 uint16_t prev_id = rxq->rx_tail;
1447 while (nb_rx < nb_pkts) {
1449 struct ngbe_rx_entry *rxe;
1450 struct ngbe_scattered_rx_entry *sc_entry;
1451 struct ngbe_scattered_rx_entry *next_sc_entry = NULL;
1452 struct ngbe_rx_entry *next_rxe = NULL;
1453 struct rte_mbuf *first_seg;
1454 struct rte_mbuf *rxm;
1455 struct rte_mbuf *nmb = NULL;
1456 struct ngbe_rx_desc rxd;
1459 volatile struct ngbe_rx_desc *rxdp;
1463 rxdp = &rx_ring[rx_id];
1464 staterr = rte_le_to_cpu_32(rxdp->qw1.lo.status);
1466 if (!(staterr & NGBE_RXD_STAT_DD))
1471 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1472 "staterr=0x%x data_len=%u",
1473 rxq->port_id, rxq->queue_id, rx_id, staterr,
1474 rte_le_to_cpu_16(rxd.qw1.hi.len));
1477 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1479 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed "
1480 "port_id=%u queue_id=%u",
1481 rxq->port_id, rxq->queue_id);
1483 dev->data->rx_mbuf_alloc_failed++;
1486 } else if (nb_hold > rxq->rx_free_thresh) {
1487 uint16_t next_rdt = rxq->rx_free_trigger;
1489 if (!ngbe_rx_alloc_bufs(rxq, false)) {
1491 ngbe_set32_relaxed(rxq->rdt_reg_addr,
1493 nb_hold -= rxq->rx_free_thresh;
1495 PMD_RX_LOG(DEBUG, "Rx bulk alloc failed "
1496 "port_id=%u queue_id=%u",
1497 rxq->port_id, rxq->queue_id);
1499 dev->data->rx_mbuf_alloc_failed++;
1505 rxe = &sw_ring[rx_id];
1506 eop = staterr & NGBE_RXD_STAT_EOP;
1508 next_id = rx_id + 1;
1509 if (next_id == rxq->nb_rx_desc)
1512 /* Prefetch next mbuf while processing current one. */
1513 rte_ngbe_prefetch(sw_ring[next_id].mbuf);
1516 * When next Rx descriptor is on a cache-line boundary,
1517 * prefetch the next 4 RX descriptors and the next 4 pointers
1520 if ((next_id & 0x3) == 0) {
1521 rte_ngbe_prefetch(&rx_ring[next_id]);
1522 rte_ngbe_prefetch(&sw_ring[next_id]);
1529 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1531 * Update Rx descriptor with the physical address of the
1532 * new data buffer of the new allocated mbuf.
1536 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1537 NGBE_RXD_HDRADDR(rxdp, 0);
1538 NGBE_RXD_PKTADDR(rxdp, dma);
1544 * Set data length & data buffer address of mbuf.
1546 data_len = rte_le_to_cpu_16(rxd.qw1.hi.len);
1547 rxm->data_len = data_len;
1553 next_sc_entry = &sw_sc_ring[nextp_id];
1554 next_rxe = &sw_ring[nextp_id];
1555 rte_ngbe_prefetch(next_rxe);
1558 sc_entry = &sw_sc_ring[rx_id];
1559 first_seg = sc_entry->fbuf;
1560 sc_entry->fbuf = NULL;
1563 * If this is the first buffer of the received packet,
1564 * set the pointer to the first mbuf of the packet and
1565 * initialize its context.
1566 * Otherwise, update the total length and the number of segments
1567 * of the current scattered packet, and update the pointer to
1568 * the last mbuf of the current packet.
1570 if (first_seg == NULL) {
1572 first_seg->pkt_len = data_len;
1573 first_seg->nb_segs = 1;
1575 first_seg->pkt_len += data_len;
1576 first_seg->nb_segs++;
1583 * If this is not the last buffer of the received packet, update
1584 * the pointer to the first mbuf at the NEXTP entry in the
1585 * sw_sc_ring and continue to parse the Rx ring.
1587 if (!eop && next_rxe) {
1588 rxm->next = next_rxe->mbuf;
1589 next_sc_entry->fbuf = first_seg;
1593 /* Initialize the first mbuf of the returned packet */
1594 ngbe_fill_cluster_head_buf(first_seg, &rxd, rxq, staterr);
1596 /* Deal with the case, when HW CRC srip is disabled. */
1597 first_seg->pkt_len -= rxq->crc_len;
1598 if (unlikely(rxm->data_len <= rxq->crc_len)) {
1599 struct rte_mbuf *lp;
1601 for (lp = first_seg; lp->next != rxm; lp = lp->next)
1604 first_seg->nb_segs--;
1605 lp->data_len -= rxq->crc_len - rxm->data_len;
1607 rte_pktmbuf_free_seg(rxm);
1609 rxm->data_len -= rxq->crc_len;
1612 /* Prefetch data of first segment, if configured to do so. */
1613 rte_packet_prefetch((char *)first_seg->buf_addr +
1614 first_seg->data_off);
1617 * Store the mbuf address into the next entry of the array
1618 * of returned packets.
1620 rx_pkts[nb_rx++] = first_seg;
1624 * Record index of the next Rx descriptor to probe.
1626 rxq->rx_tail = rx_id;
1629 * If the number of free Rx descriptors is greater than the Rx free
1630 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1632 * Update the RDT with the value of the last processed Rx descriptor
1633 * minus 1, to guarantee that the RDT register is never equal to the
1634 * RDH register, which creates a "full" ring situation from the
1635 * hardware point of view...
1637 if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
1638 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1639 "nb_hold=%u nb_rx=%u",
1640 rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
1643 ngbe_set32_relaxed(rxq->rdt_reg_addr, prev_id);
1647 rxq->nb_rx_hold = nb_hold;
1652 ngbe_recv_pkts_sc_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1655 return ngbe_recv_pkts_sc(rx_queue, rx_pkts, nb_pkts, false);
1659 ngbe_recv_pkts_sc_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1662 return ngbe_recv_pkts_sc(rx_queue, rx_pkts, nb_pkts, true);
1665 /*********************************************************************
1667 * Queue management functions
1669 **********************************************************************/
1672 ngbe_tx_queue_release_mbufs(struct ngbe_tx_queue *txq)
1676 if (txq->sw_ring != NULL) {
1677 for (i = 0; i < txq->nb_tx_desc; i++) {
1678 if (txq->sw_ring[i].mbuf != NULL) {
1679 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1680 txq->sw_ring[i].mbuf = NULL;
1687 ngbe_tx_free_swring(struct ngbe_tx_queue *txq)
1690 rte_free(txq->sw_ring);
1694 ngbe_tx_queue_release(struct ngbe_tx_queue *txq)
1697 if (txq->ops != NULL) {
1698 txq->ops->release_mbufs(txq);
1699 txq->ops->free_swring(txq);
1706 ngbe_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1708 ngbe_tx_queue_release(dev->data->tx_queues[qid]);
1711 /* (Re)set dynamic ngbe_tx_queue fields to defaults */
1713 ngbe_reset_tx_queue(struct ngbe_tx_queue *txq)
1715 static const struct ngbe_tx_desc zeroed_desc = {0};
1716 struct ngbe_tx_entry *txe = txq->sw_ring;
1719 /* Zero out HW ring memory */
1720 for (i = 0; i < txq->nb_tx_desc; i++)
1721 txq->tx_ring[i] = zeroed_desc;
1723 /* Initialize SW ring entries */
1724 prev = (uint16_t)(txq->nb_tx_desc - 1);
1725 for (i = 0; i < txq->nb_tx_desc; i++) {
1726 /* the ring can also be modified by hardware */
1727 volatile struct ngbe_tx_desc *txd = &txq->tx_ring[i];
1729 txd->dw3 = rte_cpu_to_le_32(NGBE_TXD_DD);
1732 txe[prev].next_id = i;
1736 txq->tx_next_dd = (uint16_t)(txq->tx_free_thresh - 1);
1740 * Always allow 1 descriptor to be un-allocated to avoid
1741 * a H/W race condition
1743 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1744 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1746 memset((void *)&txq->ctx_cache, 0,
1747 NGBE_CTX_NUM * sizeof(struct ngbe_ctx_info));
1750 static const struct ngbe_txq_ops def_txq_ops = {
1751 .release_mbufs = ngbe_tx_queue_release_mbufs,
1752 .free_swring = ngbe_tx_free_swring,
1753 .reset = ngbe_reset_tx_queue,
1756 /* Takes an ethdev and a queue and sets up the tx function to be used based on
1757 * the queue parameters. Used in tx_queue_setup by primary process and then
1758 * in dev_init by secondary process when attaching to an existing ethdev.
1761 ngbe_set_tx_function(struct rte_eth_dev *dev, struct ngbe_tx_queue *txq)
1763 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1764 if (txq->offloads == 0 &&
1765 txq->tx_free_thresh >= RTE_PMD_NGBE_TX_MAX_BURST) {
1766 PMD_INIT_LOG(DEBUG, "Using simple tx code path");
1767 dev->tx_pkt_burst = ngbe_xmit_pkts_simple;
1768 dev->tx_pkt_prepare = NULL;
1770 PMD_INIT_LOG(DEBUG, "Using full-featured tx code path");
1772 " - offloads = 0x%" PRIx64,
1775 " - tx_free_thresh = %lu [RTE_PMD_NGBE_TX_MAX_BURST=%lu]",
1776 (unsigned long)txq->tx_free_thresh,
1777 (unsigned long)RTE_PMD_NGBE_TX_MAX_BURST);
1778 dev->tx_pkt_burst = ngbe_xmit_pkts;
1779 dev->tx_pkt_prepare = ngbe_prep_pkts;
1783 static const struct {
1784 eth_tx_burst_t pkt_burst;
1786 } ngbe_tx_burst_infos[] = {
1787 { ngbe_xmit_pkts_simple, "Scalar Simple"},
1788 { ngbe_xmit_pkts, "Scalar"},
1792 ngbe_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
1793 struct rte_eth_burst_mode *mode)
1795 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
1799 for (i = 0; i < RTE_DIM(ngbe_tx_burst_infos); ++i) {
1800 if (pkt_burst == ngbe_tx_burst_infos[i].pkt_burst) {
1801 snprintf(mode->info, sizeof(mode->info), "%s",
1802 ngbe_tx_burst_infos[i].info);
1812 ngbe_get_tx_port_offloads(struct rte_eth_dev *dev)
1814 uint64_t tx_offload_capa;
1815 struct ngbe_hw *hw = ngbe_dev_hw(dev);
1818 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
1819 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
1820 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
1821 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
1822 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
1823 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1824 RTE_ETH_TX_OFFLOAD_TCP_TSO |
1825 RTE_ETH_TX_OFFLOAD_UDP_TSO |
1826 RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO |
1827 RTE_ETH_TX_OFFLOAD_IP_TNL_TSO |
1828 RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO |
1829 RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
1832 tx_offload_capa |= RTE_ETH_TX_OFFLOAD_QINQ_INSERT;
1834 return tx_offload_capa;
1838 ngbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1841 unsigned int socket_id,
1842 const struct rte_eth_txconf *tx_conf)
1844 const struct rte_memzone *tz;
1845 struct ngbe_tx_queue *txq;
1847 uint16_t tx_free_thresh;
1850 PMD_INIT_FUNC_TRACE();
1851 hw = ngbe_dev_hw(dev);
1853 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1856 * The Tx descriptor ring will be cleaned after txq->tx_free_thresh
1857 * descriptors are used or if the number of descriptors required
1858 * to transmit a packet is greater than the number of free Tx
1860 * One descriptor in the Tx ring is used as a sentinel to avoid a
1861 * H/W race condition, hence the maximum threshold constraints.
1862 * When set to zero use default values.
1864 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1865 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1866 if (tx_free_thresh >= (nb_desc - 3)) {
1868 "tx_free_thresh must be less than the number of TX descriptors minus 3. (tx_free_thresh=%u port=%d queue=%d)",
1869 (unsigned int)tx_free_thresh,
1870 (int)dev->data->port_id, (int)queue_idx);
1874 if (nb_desc % tx_free_thresh != 0) {
1876 "tx_free_thresh must be a divisor of the number of Tx descriptors. (tx_free_thresh=%u port=%d queue=%d)",
1877 (unsigned int)tx_free_thresh,
1878 (int)dev->data->port_id, (int)queue_idx);
1882 /* Free memory prior to re-allocation if needed... */
1883 if (dev->data->tx_queues[queue_idx] != NULL) {
1884 ngbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1885 dev->data->tx_queues[queue_idx] = NULL;
1888 /* First allocate the Tx queue data structure */
1889 txq = rte_zmalloc_socket("ethdev Tx queue",
1890 sizeof(struct ngbe_tx_queue),
1891 RTE_CACHE_LINE_SIZE, socket_id);
1896 * Allocate Tx ring hardware descriptors. A memzone large enough to
1897 * handle the maximum ring size is allocated in order to allow for
1898 * resizing in later calls to the queue setup function.
1900 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1901 sizeof(struct ngbe_tx_desc) * NGBE_RING_DESC_MAX,
1902 NGBE_ALIGN, socket_id);
1904 ngbe_tx_queue_release(txq);
1908 txq->nb_tx_desc = nb_desc;
1909 txq->tx_free_thresh = tx_free_thresh;
1910 txq->pthresh = tx_conf->tx_thresh.pthresh;
1911 txq->hthresh = tx_conf->tx_thresh.hthresh;
1912 txq->wthresh = tx_conf->tx_thresh.wthresh;
1913 txq->queue_id = queue_idx;
1914 txq->reg_idx = queue_idx;
1915 txq->port_id = dev->data->port_id;
1916 txq->offloads = offloads;
1917 txq->ops = &def_txq_ops;
1918 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1920 txq->tdt_reg_addr = NGBE_REG_ADDR(hw, NGBE_TXWP(txq->reg_idx));
1921 txq->tdc_reg_addr = NGBE_REG_ADDR(hw, NGBE_TXCFG(txq->reg_idx));
1923 txq->tx_ring_phys_addr = TMZ_PADDR(tz);
1924 txq->tx_ring = (struct ngbe_tx_desc *)TMZ_VADDR(tz);
1926 /* Allocate software ring */
1927 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1928 sizeof(struct ngbe_tx_entry) * nb_desc,
1929 RTE_CACHE_LINE_SIZE, socket_id);
1930 if (txq->sw_ring == NULL) {
1931 ngbe_tx_queue_release(txq);
1935 "sw_ring=%p hw_ring=%p dma_addr=0x%" PRIx64,
1936 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1938 /* set up scalar Tx function as appropriate */
1939 ngbe_set_tx_function(dev, txq);
1941 txq->ops->reset(txq);
1943 dev->data->tx_queues[queue_idx] = txq;
1949 * ngbe_free_sc_cluster - free the not-yet-completed scattered cluster
1951 * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
1952 * in the sw_sc_ring is not set to NULL but rather points to the next
1953 * mbuf of this RSC aggregation (that has not been completed yet and still
1954 * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
1955 * will just free first "nb_segs" segments of the cluster explicitly by calling
1956 * an rte_pktmbuf_free_seg().
1958 * @m scattered cluster head
1961 ngbe_free_sc_cluster(struct rte_mbuf *m)
1963 uint16_t i, nb_segs = m->nb_segs;
1964 struct rte_mbuf *next_seg;
1966 for (i = 0; i < nb_segs; i++) {
1968 rte_pktmbuf_free_seg(m);
1974 ngbe_rx_queue_release_mbufs(struct ngbe_rx_queue *rxq)
1978 if (rxq->sw_ring != NULL) {
1979 for (i = 0; i < rxq->nb_rx_desc; i++) {
1980 if (rxq->sw_ring[i].mbuf != NULL) {
1981 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1982 rxq->sw_ring[i].mbuf = NULL;
1985 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1986 struct rte_mbuf *mb;
1988 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1989 rte_pktmbuf_free_seg(mb);
1991 rxq->rx_nb_avail = 0;
1994 if (rxq->sw_sc_ring != NULL)
1995 for (i = 0; i < rxq->nb_rx_desc; i++)
1996 if (rxq->sw_sc_ring[i].fbuf != NULL) {
1997 ngbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
1998 rxq->sw_sc_ring[i].fbuf = NULL;
2003 ngbe_rx_queue_release(struct ngbe_rx_queue *rxq)
2006 ngbe_rx_queue_release_mbufs(rxq);
2007 rte_free(rxq->sw_ring);
2008 rte_free(rxq->sw_sc_ring);
2014 ngbe_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2016 ngbe_rx_queue_release(dev->data->rx_queues[qid]);
2020 * Check if Rx Burst Bulk Alloc function can be used.
2022 * 0: the preconditions are satisfied and the bulk allocation function
2024 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2025 * function must be used.
2028 check_rx_burst_bulk_alloc_preconditions(struct ngbe_rx_queue *rxq)
2033 * Make sure the following pre-conditions are satisfied:
2034 * rxq->rx_free_thresh >= RTE_PMD_NGBE_RX_MAX_BURST
2035 * rxq->rx_free_thresh < rxq->nb_rx_desc
2036 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2037 * Scattered packets are not supported. This should be checked
2038 * outside of this function.
2040 if (rxq->rx_free_thresh < RTE_PMD_NGBE_RX_MAX_BURST) {
2042 "Rx Burst Bulk Alloc Preconditions: rxq->rx_free_thresh=%d, RTE_PMD_NGBE_RX_MAX_BURST=%d",
2043 rxq->rx_free_thresh, RTE_PMD_NGBE_RX_MAX_BURST);
2045 } else if (rxq->rx_free_thresh >= rxq->nb_rx_desc) {
2047 "Rx Burst Bulk Alloc Preconditions: rxq->rx_free_thresh=%d, rxq->nb_rx_desc=%d",
2048 rxq->rx_free_thresh, rxq->nb_rx_desc);
2050 } else if ((rxq->nb_rx_desc % rxq->rx_free_thresh) != 0) {
2052 "Rx Burst Bulk Alloc Preconditions: rxq->nb_rx_desc=%d, rxq->rx_free_thresh=%d",
2053 rxq->nb_rx_desc, rxq->rx_free_thresh);
2060 /* Reset dynamic ngbe_rx_queue fields back to defaults */
2062 ngbe_reset_rx_queue(struct ngbe_adapter *adapter, struct ngbe_rx_queue *rxq)
2064 static const struct ngbe_rx_desc zeroed_desc = {
2065 {{0}, {0} }, {{0}, {0} } };
2067 uint16_t len = rxq->nb_rx_desc;
2070 * By default, the Rx queue setup function allocates enough memory for
2071 * NGBE_RING_DESC_MAX. The Rx Burst bulk allocation function requires
2072 * extra memory at the end of the descriptor ring to be zero'd out.
2074 if (adapter->rx_bulk_alloc_allowed)
2075 /* zero out extra memory */
2076 len += RTE_PMD_NGBE_RX_MAX_BURST;
2079 * Zero out HW ring memory. Zero out extra memory at the end of
2080 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2081 * reads extra memory as zeros.
2083 for (i = 0; i < len; i++)
2084 rxq->rx_ring[i] = zeroed_desc;
2087 * initialize extra software ring entries. Space for these extra
2088 * entries is always allocated
2090 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2091 for (i = rxq->nb_rx_desc; i < len; ++i)
2092 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2094 rxq->rx_nb_avail = 0;
2095 rxq->rx_next_avail = 0;
2096 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2098 rxq->nb_rx_hold = 0;
2099 rxq->pkt_first_seg = NULL;
2100 rxq->pkt_last_seg = NULL;
2104 ngbe_get_rx_queue_offloads(struct rte_eth_dev *dev __rte_unused)
2106 return RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
2110 ngbe_get_rx_port_offloads(struct rte_eth_dev *dev)
2113 struct ngbe_hw *hw = ngbe_dev_hw(dev);
2115 offloads = RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
2116 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
2117 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
2118 RTE_ETH_RX_OFFLOAD_KEEP_CRC |
2119 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
2120 RTE_ETH_RX_OFFLOAD_SCATTER;
2123 offloads |= (RTE_ETH_RX_OFFLOAD_QINQ_STRIP |
2124 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND);
2130 ngbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2133 unsigned int socket_id,
2134 const struct rte_eth_rxconf *rx_conf,
2135 struct rte_mempool *mp)
2137 const struct rte_memzone *rz;
2138 struct ngbe_rx_queue *rxq;
2141 struct ngbe_adapter *adapter = ngbe_dev_adapter(dev);
2144 PMD_INIT_FUNC_TRACE();
2145 hw = ngbe_dev_hw(dev);
2147 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
2149 /* Free memory prior to re-allocation if needed... */
2150 if (dev->data->rx_queues[queue_idx] != NULL) {
2151 ngbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2152 dev->data->rx_queues[queue_idx] = NULL;
2155 /* First allocate the Rx queue data structure */
2156 rxq = rte_zmalloc_socket("ethdev RX queue",
2157 sizeof(struct ngbe_rx_queue),
2158 RTE_CACHE_LINE_SIZE, socket_id);
2162 rxq->nb_rx_desc = nb_desc;
2163 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2164 rxq->queue_id = queue_idx;
2165 rxq->reg_idx = queue_idx;
2166 rxq->port_id = dev->data->port_id;
2167 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
2168 rxq->crc_len = RTE_ETHER_CRC_LEN;
2171 rxq->drop_en = rx_conf->rx_drop_en;
2172 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2173 rxq->offloads = offloads;
2176 * Allocate Rx ring hardware descriptors. A memzone large enough to
2177 * handle the maximum ring size is allocated in order to allow for
2178 * resizing in later calls to the queue setup function.
2180 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2181 RX_RING_SZ, NGBE_ALIGN, socket_id);
2183 ngbe_rx_queue_release(rxq);
2188 * Zero init all the descriptors in the ring.
2190 memset(rz->addr, 0, RX_RING_SZ);
2192 rxq->rdt_reg_addr = NGBE_REG_ADDR(hw, NGBE_RXWP(rxq->reg_idx));
2193 rxq->rdh_reg_addr = NGBE_REG_ADDR(hw, NGBE_RXRP(rxq->reg_idx));
2195 rxq->rx_ring_phys_addr = TMZ_PADDR(rz);
2196 rxq->rx_ring = (struct ngbe_rx_desc *)TMZ_VADDR(rz);
2199 * Certain constraints must be met in order to use the bulk buffer
2200 * allocation Rx burst function. If any of Rx queues doesn't meet them
2201 * the feature should be disabled for the whole port.
2203 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2205 "queue[%d] doesn't meet Rx Bulk Alloc preconditions - canceling the feature for the whole port[%d]",
2206 rxq->queue_id, rxq->port_id);
2207 adapter->rx_bulk_alloc_allowed = false;
2211 * Allocate software ring. Allow for space at the end of the
2212 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2213 * function does not access an invalid memory region.
2216 if (adapter->rx_bulk_alloc_allowed)
2217 len += RTE_PMD_NGBE_RX_MAX_BURST;
2219 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2220 sizeof(struct ngbe_rx_entry) * len,
2221 RTE_CACHE_LINE_SIZE, socket_id);
2222 if (rxq->sw_ring == NULL) {
2223 ngbe_rx_queue_release(rxq);
2228 * Always allocate even if it's not going to be needed in order to
2229 * simplify the code.
2231 * This ring is used in Scattered Rx cases and Scattered Rx may
2232 * be requested in ngbe_dev_rx_init(), which is called later from
2236 rte_zmalloc_socket("rxq->sw_sc_ring",
2237 sizeof(struct ngbe_scattered_rx_entry) * len,
2238 RTE_CACHE_LINE_SIZE, socket_id);
2239 if (rxq->sw_sc_ring == NULL) {
2240 ngbe_rx_queue_release(rxq);
2245 "sw_ring=%p sw_sc_ring=%p hw_ring=%p dma_addr=0x%" PRIx64,
2246 rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
2247 rxq->rx_ring_phys_addr);
2249 dev->data->rx_queues[queue_idx] = rxq;
2251 ngbe_reset_rx_queue(adapter, rxq);
2257 ngbe_dev_clear_queues(struct rte_eth_dev *dev)
2260 struct ngbe_adapter *adapter = ngbe_dev_adapter(dev);
2262 PMD_INIT_FUNC_TRACE();
2264 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2265 struct ngbe_tx_queue *txq = dev->data->tx_queues[i];
2268 txq->ops->release_mbufs(txq);
2269 txq->ops->reset(txq);
2273 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2274 struct ngbe_rx_queue *rxq = dev->data->rx_queues[i];
2277 ngbe_rx_queue_release_mbufs(rxq);
2278 ngbe_reset_rx_queue(adapter, rxq);
2284 ngbe_dev_free_queues(struct rte_eth_dev *dev)
2288 PMD_INIT_FUNC_TRACE();
2290 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2291 ngbe_dev_rx_queue_release(dev, i);
2292 dev->data->rx_queues[i] = NULL;
2294 dev->data->nb_rx_queues = 0;
2296 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2297 ngbe_dev_tx_queue_release(dev, i);
2298 dev->data->tx_queues[i] = NULL;
2300 dev->data->nb_tx_queues = 0;
2304 * Receive Side Scaling (RSS)
2307 * The source and destination IP addresses of the IP header and the source
2308 * and destination ports of TCP/UDP headers, if any, of received packets are
2309 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2310 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2311 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2312 * RSS output index which is used as the Rx queue index where to store the
2314 * The following output is supplied in the Rx write-back descriptor:
2315 * - 32-bit result of the Microsoft RSS hash function,
2316 * - 4-bit RSS type field.
2320 * Used as the default key.
2322 static uint8_t rss_intel_key[40] = {
2323 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2324 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2325 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2326 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2327 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2331 ngbe_rss_disable(struct rte_eth_dev *dev)
2333 struct ngbe_hw *hw = ngbe_dev_hw(dev);
2335 wr32m(hw, NGBE_RACTL, NGBE_RACTL_RSSENA, 0);
2339 ngbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2340 struct rte_eth_rss_conf *rss_conf)
2342 struct ngbe_hw *hw = ngbe_dev_hw(dev);
2350 PMD_DRV_LOG(ERR, "RSS hash update is not supported on this "
2355 hash_key = rss_conf->rss_key;
2357 /* Fill in RSS hash key */
2358 for (i = 0; i < 10; i++) {
2359 rss_key = LS32(hash_key[(i * 4) + 0], 0, 0xFF);
2360 rss_key |= LS32(hash_key[(i * 4) + 1], 8, 0xFF);
2361 rss_key |= LS32(hash_key[(i * 4) + 2], 16, 0xFF);
2362 rss_key |= LS32(hash_key[(i * 4) + 3], 24, 0xFF);
2363 wr32a(hw, NGBE_REG_RSSKEY, i, rss_key);
2367 /* Set configured hashing protocols */
2368 rss_hf = rss_conf->rss_hf & NGBE_RSS_OFFLOAD_ALL;
2370 mrqc = rd32(hw, NGBE_RACTL);
2371 mrqc &= ~NGBE_RACTL_RSSMASK;
2372 if (rss_hf & RTE_ETH_RSS_IPV4)
2373 mrqc |= NGBE_RACTL_RSSIPV4;
2374 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP)
2375 mrqc |= NGBE_RACTL_RSSIPV4TCP;
2376 if (rss_hf & RTE_ETH_RSS_IPV6 ||
2377 rss_hf & RTE_ETH_RSS_IPV6_EX)
2378 mrqc |= NGBE_RACTL_RSSIPV6;
2379 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP ||
2380 rss_hf & RTE_ETH_RSS_IPV6_TCP_EX)
2381 mrqc |= NGBE_RACTL_RSSIPV6TCP;
2382 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP)
2383 mrqc |= NGBE_RACTL_RSSIPV4UDP;
2384 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP ||
2385 rss_hf & RTE_ETH_RSS_IPV6_UDP_EX)
2386 mrqc |= NGBE_RACTL_RSSIPV6UDP;
2389 mrqc |= NGBE_RACTL_RSSENA;
2391 mrqc &= ~NGBE_RACTL_RSSENA;
2393 wr32(hw, NGBE_RACTL, mrqc);
2399 ngbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2400 struct rte_eth_rss_conf *rss_conf)
2402 struct ngbe_hw *hw = ngbe_dev_hw(dev);
2409 hash_key = rss_conf->rss_key;
2411 /* Return RSS hash key */
2412 for (i = 0; i < 10; i++) {
2413 rss_key = rd32a(hw, NGBE_REG_RSSKEY, i);
2414 hash_key[(i * 4) + 0] = RS32(rss_key, 0, 0xFF);
2415 hash_key[(i * 4) + 1] = RS32(rss_key, 8, 0xFF);
2416 hash_key[(i * 4) + 2] = RS32(rss_key, 16, 0xFF);
2417 hash_key[(i * 4) + 3] = RS32(rss_key, 24, 0xFF);
2423 mrqc = rd32(hw, NGBE_RACTL);
2424 if (mrqc & NGBE_RACTL_RSSIPV4)
2425 rss_hf |= RTE_ETH_RSS_IPV4;
2426 if (mrqc & NGBE_RACTL_RSSIPV4TCP)
2427 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP;
2428 if (mrqc & NGBE_RACTL_RSSIPV6)
2429 rss_hf |= RTE_ETH_RSS_IPV6 |
2430 RTE_ETH_RSS_IPV6_EX;
2431 if (mrqc & NGBE_RACTL_RSSIPV6TCP)
2432 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP |
2433 RTE_ETH_RSS_IPV6_TCP_EX;
2434 if (mrqc & NGBE_RACTL_RSSIPV4UDP)
2435 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP;
2436 if (mrqc & NGBE_RACTL_RSSIPV6UDP)
2437 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP |
2438 RTE_ETH_RSS_IPV6_UDP_EX;
2439 if (!(mrqc & NGBE_RACTL_RSSENA))
2442 rss_hf &= NGBE_RSS_OFFLOAD_ALL;
2444 rss_conf->rss_hf = rss_hf;
2449 ngbe_rss_configure(struct rte_eth_dev *dev)
2451 struct rte_eth_rss_conf rss_conf;
2452 struct ngbe_adapter *adapter = ngbe_dev_adapter(dev);
2453 struct ngbe_hw *hw = ngbe_dev_hw(dev);
2458 PMD_INIT_FUNC_TRACE();
2461 * Fill in redirection table
2462 * The byte-swap is needed because NIC registers are in
2463 * little-endian order.
2465 if (adapter->rss_reta_updated == 0) {
2467 for (i = 0, j = 0; i < RTE_ETH_RSS_RETA_SIZE_128; i++, j++) {
2468 if (j == dev->data->nb_rx_queues)
2470 reta = (reta >> 8) | LS32(j, 24, 0xFF);
2472 wr32a(hw, NGBE_REG_RSSTBL, i >> 2, reta);
2476 * Configure the RSS key and the RSS protocols used to compute
2477 * the RSS hash of input packets.
2479 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2480 if (rss_conf.rss_key == NULL)
2481 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2482 ngbe_dev_rss_hash_update(dev, &rss_conf);
2485 void ngbe_configure_port(struct rte_eth_dev *dev)
2487 struct ngbe_hw *hw = ngbe_dev_hw(dev);
2489 uint16_t tpids[8] = {RTE_ETHER_TYPE_VLAN, RTE_ETHER_TYPE_QINQ,
2494 PMD_INIT_FUNC_TRACE();
2496 /* default outer vlan tpid */
2497 wr32(hw, NGBE_EXTAG,
2498 NGBE_EXTAG_ETAG(RTE_ETHER_TYPE_ETAG) |
2499 NGBE_EXTAG_VLAN(RTE_ETHER_TYPE_QINQ));
2501 /* default inner vlan tpid */
2502 wr32m(hw, NGBE_VLANCTL,
2503 NGBE_VLANCTL_TPID_MASK,
2504 NGBE_VLANCTL_TPID(RTE_ETHER_TYPE_VLAN));
2505 wr32m(hw, NGBE_DMATXCTRL,
2506 NGBE_DMATXCTRL_TPID_MASK,
2507 NGBE_DMATXCTRL_TPID(RTE_ETHER_TYPE_VLAN));
2509 /* default vlan tpid filters */
2510 for (i = 0; i < 8; i++) {
2511 wr32m(hw, NGBE_TAGTPID(i / 2),
2512 (i % 2 ? NGBE_TAGTPID_MSB_MASK
2513 : NGBE_TAGTPID_LSB_MASK),
2514 (i % 2 ? NGBE_TAGTPID_MSB(tpids[i])
2515 : NGBE_TAGTPID_LSB(tpids[i])));
2520 ngbe_alloc_rx_queue_mbufs(struct ngbe_rx_queue *rxq)
2522 struct ngbe_rx_entry *rxe = rxq->sw_ring;
2526 /* Initialize software ring entries */
2527 for (i = 0; i < rxq->nb_rx_desc; i++) {
2528 /* the ring can also be modified by hardware */
2529 volatile struct ngbe_rx_desc *rxd;
2530 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
2533 PMD_INIT_LOG(ERR, "Rx mbuf alloc failed queue_id=%u port_id=%u",
2534 (unsigned int)rxq->queue_id,
2535 (unsigned int)rxq->port_id);
2539 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2540 mbuf->port = rxq->port_id;
2543 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2544 rxd = &rxq->rx_ring[i];
2545 NGBE_RXD_HDRADDR(rxd, 0);
2546 NGBE_RXD_PKTADDR(rxd, dma_addr);
2554 ngbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
2556 switch (dev->data->dev_conf.rxmode.mq_mode) {
2557 case RTE_ETH_MQ_RX_RSS:
2558 ngbe_rss_configure(dev);
2561 case RTE_ETH_MQ_RX_NONE:
2563 /* if mq_mode is none, disable rss mode.*/
2564 ngbe_rss_disable(dev);
2572 ngbe_set_rx_function(struct rte_eth_dev *dev)
2574 struct ngbe_adapter *adapter = ngbe_dev_adapter(dev);
2576 if (dev->data->scattered_rx) {
2578 * Set the scattered callback: there are bulk and
2579 * single allocation versions.
2581 if (adapter->rx_bulk_alloc_allowed) {
2582 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2583 "allocation callback (port=%d).",
2584 dev->data->port_id);
2585 dev->rx_pkt_burst = ngbe_recv_pkts_sc_bulk_alloc;
2587 PMD_INIT_LOG(DEBUG, "Using Regular (non-vector, "
2588 "single allocation) "
2589 "Scattered Rx callback "
2591 dev->data->port_id);
2593 dev->rx_pkt_burst = ngbe_recv_pkts_sc_single_alloc;
2596 * Below we set "simple" callbacks according to port/queues parameters.
2597 * If parameters allow we are going to choose between the following
2600 * - Single buffer allocation (the simplest one)
2602 } else if (adapter->rx_bulk_alloc_allowed) {
2603 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2604 "satisfied. Rx Burst Bulk Alloc function "
2605 "will be used on port=%d.",
2606 dev->data->port_id);
2608 dev->rx_pkt_burst = ngbe_recv_pkts_bulk_alloc;
2610 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2611 "satisfied, or Scattered Rx is requested "
2613 dev->data->port_id);
2615 dev->rx_pkt_burst = ngbe_recv_pkts;
2619 static const struct {
2620 eth_rx_burst_t pkt_burst;
2622 } ngbe_rx_burst_infos[] = {
2623 { ngbe_recv_pkts_sc_single_alloc, "Scalar Scattered"},
2624 { ngbe_recv_pkts_sc_bulk_alloc, "Scalar Scattered Bulk Alloc"},
2625 { ngbe_recv_pkts_bulk_alloc, "Scalar Bulk Alloc"},
2626 { ngbe_recv_pkts, "Scalar"},
2630 ngbe_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2631 struct rte_eth_burst_mode *mode)
2633 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2637 for (i = 0; i < RTE_DIM(ngbe_rx_burst_infos); ++i) {
2638 if (pkt_burst == ngbe_rx_burst_infos[i].pkt_burst) {
2639 snprintf(mode->info, sizeof(mode->info), "%s",
2640 ngbe_rx_burst_infos[i].info);
2650 * Initializes Receive Unit.
2653 ngbe_dev_rx_init(struct rte_eth_dev *dev)
2656 struct ngbe_rx_queue *rxq;
2665 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
2667 PMD_INIT_FUNC_TRACE();
2668 hw = ngbe_dev_hw(dev);
2671 * Make sure receives are disabled while setting
2672 * up the Rx context (registers, descriptor rings, etc.).
2674 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, 0);
2675 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0);
2677 /* Enable receipt of broadcasted frames */
2678 fctrl = rd32(hw, NGBE_PSRCTL);
2679 fctrl |= NGBE_PSRCTL_BCA;
2680 wr32(hw, NGBE_PSRCTL, fctrl);
2683 * Configure CRC stripping, if any.
2685 hlreg0 = rd32(hw, NGBE_SECRXCTL);
2686 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
2687 hlreg0 &= ~NGBE_SECRXCTL_CRCSTRIP;
2689 hlreg0 |= NGBE_SECRXCTL_CRCSTRIP;
2690 hlreg0 &= ~NGBE_SECRXCTL_XDSA;
2691 wr32(hw, NGBE_SECRXCTL, hlreg0);
2694 * Configure jumbo frame support, if any.
2696 wr32m(hw, NGBE_FRMSZ, NGBE_FRMSZ_MAX_MASK,
2697 NGBE_FRMSZ_MAX(dev->data->mtu + NGBE_ETH_OVERHEAD));
2700 * If loopback mode is configured, set LPBK bit.
2702 hlreg0 = rd32(hw, NGBE_PSRCTL);
2703 if (hw->is_pf && dev->data->dev_conf.lpbk_mode)
2704 hlreg0 |= NGBE_PSRCTL_LBENA;
2706 hlreg0 &= ~NGBE_PSRCTL_LBENA;
2708 wr32(hw, NGBE_PSRCTL, hlreg0);
2711 * Assume no header split and no VLAN strip support
2712 * on any Rx queue first .
2714 rx_conf->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
2716 /* Setup Rx queues */
2717 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2718 rxq = dev->data->rx_queues[i];
2721 * Reset crc_len in case it was changed after queue setup by a
2722 * call to configure.
2724 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
2725 rxq->crc_len = RTE_ETHER_CRC_LEN;
2729 /* Setup the Base and Length of the Rx Descriptor Rings */
2730 bus_addr = rxq->rx_ring_phys_addr;
2731 wr32(hw, NGBE_RXBAL(rxq->reg_idx),
2732 (uint32_t)(bus_addr & BIT_MASK32));
2733 wr32(hw, NGBE_RXBAH(rxq->reg_idx),
2734 (uint32_t)(bus_addr >> 32));
2735 wr32(hw, NGBE_RXRP(rxq->reg_idx), 0);
2736 wr32(hw, NGBE_RXWP(rxq->reg_idx), 0);
2738 srrctl = NGBE_RXCFG_RNGLEN(rxq->nb_rx_desc);
2740 /* Set if packets are dropped when no descriptors available */
2742 srrctl |= NGBE_RXCFG_DROP;
2745 * Configure the Rx buffer size in the PKTLEN field of
2746 * the RXCFG register of the queue.
2747 * The value is in 1 KB resolution. Valid values can be from
2750 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
2751 RTE_PKTMBUF_HEADROOM);
2752 buf_size = ROUND_DOWN(buf_size, 0x1 << 10);
2753 srrctl |= NGBE_RXCFG_PKTLEN(buf_size);
2755 wr32(hw, NGBE_RXCFG(rxq->reg_idx), srrctl);
2757 /* It adds dual VLAN length for supporting dual VLAN */
2758 if (dev->data->mtu + NGBE_ETH_OVERHEAD +
2759 2 * NGBE_VLAN_TAG_SIZE > buf_size)
2760 dev->data->scattered_rx = 1;
2761 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
2762 rx_conf->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
2765 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_SCATTER)
2766 dev->data->scattered_rx = 1;
2769 * Device configured with multiple RX queues.
2771 ngbe_dev_mq_rx_configure(dev);
2774 * Setup the Checksum Register.
2775 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
2776 * Enable IP/L4 checksum computation by hardware if requested to do so.
2778 rxcsum = rd32(hw, NGBE_PSRCTL);
2779 rxcsum |= NGBE_PSRCTL_PCSD;
2780 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_CHECKSUM)
2781 rxcsum |= NGBE_PSRCTL_L4CSUM;
2783 rxcsum &= ~NGBE_PSRCTL_L4CSUM;
2785 wr32(hw, NGBE_PSRCTL, rxcsum);
2788 rdrxctl = rd32(hw, NGBE_SECRXCTL);
2789 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
2790 rdrxctl &= ~NGBE_SECRXCTL_CRCSTRIP;
2792 rdrxctl |= NGBE_SECRXCTL_CRCSTRIP;
2793 wr32(hw, NGBE_SECRXCTL, rdrxctl);
2796 ngbe_set_rx_function(dev);
2802 * Initializes Transmit Unit.
2805 ngbe_dev_tx_init(struct rte_eth_dev *dev)
2808 struct ngbe_tx_queue *txq;
2812 PMD_INIT_FUNC_TRACE();
2813 hw = ngbe_dev_hw(dev);
2815 wr32m(hw, NGBE_SECTXCTL, NGBE_SECTXCTL_ODSA, NGBE_SECTXCTL_ODSA);
2816 wr32m(hw, NGBE_SECTXCTL, NGBE_SECTXCTL_XDSA, 0);
2818 /* Setup the Base and Length of the Tx Descriptor Rings */
2819 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2820 txq = dev->data->tx_queues[i];
2822 bus_addr = txq->tx_ring_phys_addr;
2823 wr32(hw, NGBE_TXBAL(txq->reg_idx),
2824 (uint32_t)(bus_addr & BIT_MASK32));
2825 wr32(hw, NGBE_TXBAH(txq->reg_idx),
2826 (uint32_t)(bus_addr >> 32));
2827 wr32m(hw, NGBE_TXCFG(txq->reg_idx), NGBE_TXCFG_BUFLEN_MASK,
2828 NGBE_TXCFG_BUFLEN(txq->nb_tx_desc));
2829 /* Setup the HW Tx Head and TX Tail descriptor pointers */
2830 wr32(hw, NGBE_TXRP(txq->reg_idx), 0);
2831 wr32(hw, NGBE_TXWP(txq->reg_idx), 0);
2836 * Set up link loopback mode Tx->Rx.
2839 ngbe_setup_loopback_link(struct ngbe_hw *hw)
2841 PMD_INIT_FUNC_TRACE();
2843 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_LB, NGBE_MACRXCFG_LB);
2849 * Start Transmit and Receive Units.
2852 ngbe_dev_rxtx_start(struct rte_eth_dev *dev)
2855 struct ngbe_tx_queue *txq;
2856 struct ngbe_rx_queue *rxq;
2862 PMD_INIT_FUNC_TRACE();
2863 hw = ngbe_dev_hw(dev);
2865 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2866 txq = dev->data->tx_queues[i];
2867 /* Setup Transmit Threshold Registers */
2868 wr32m(hw, NGBE_TXCFG(txq->reg_idx),
2869 NGBE_TXCFG_HTHRESH_MASK |
2870 NGBE_TXCFG_WTHRESH_MASK,
2871 NGBE_TXCFG_HTHRESH(txq->hthresh) |
2872 NGBE_TXCFG_WTHRESH(txq->wthresh));
2875 dmatxctl = rd32(hw, NGBE_DMATXCTRL);
2876 dmatxctl |= NGBE_DMATXCTRL_ENA;
2877 wr32(hw, NGBE_DMATXCTRL, dmatxctl);
2879 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2880 txq = dev->data->tx_queues[i];
2881 if (txq->tx_deferred_start == 0) {
2882 ret = ngbe_dev_tx_queue_start(dev, i);
2888 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2889 rxq = dev->data->rx_queues[i];
2890 if (rxq->rx_deferred_start == 0) {
2891 ret = ngbe_dev_rx_queue_start(dev, i);
2897 /* Enable Receive engine */
2898 rxctrl = rd32(hw, NGBE_PBRXCTL);
2899 rxctrl |= NGBE_PBRXCTL_ENA;
2900 hw->mac.enable_rx_dma(hw, rxctrl);
2902 /* If loopback mode is enabled, set up the link accordingly */
2903 if (hw->is_pf && dev->data->dev_conf.lpbk_mode)
2904 ngbe_setup_loopback_link(hw);
2910 ngbe_dev_save_rx_queue(struct ngbe_hw *hw, uint16_t rx_queue_id)
2912 u32 *reg = &hw->q_rx_regs[rx_queue_id * 8];
2913 *(reg++) = rd32(hw, NGBE_RXBAL(rx_queue_id));
2914 *(reg++) = rd32(hw, NGBE_RXBAH(rx_queue_id));
2915 *(reg++) = rd32(hw, NGBE_RXCFG(rx_queue_id));
2919 ngbe_dev_store_rx_queue(struct ngbe_hw *hw, uint16_t rx_queue_id)
2921 u32 *reg = &hw->q_rx_regs[rx_queue_id * 8];
2922 wr32(hw, NGBE_RXBAL(rx_queue_id), *(reg++));
2923 wr32(hw, NGBE_RXBAH(rx_queue_id), *(reg++));
2924 wr32(hw, NGBE_RXCFG(rx_queue_id), *(reg++) & ~NGBE_RXCFG_ENA);
2928 ngbe_dev_save_tx_queue(struct ngbe_hw *hw, uint16_t tx_queue_id)
2930 u32 *reg = &hw->q_tx_regs[tx_queue_id * 8];
2931 *(reg++) = rd32(hw, NGBE_TXBAL(tx_queue_id));
2932 *(reg++) = rd32(hw, NGBE_TXBAH(tx_queue_id));
2933 *(reg++) = rd32(hw, NGBE_TXCFG(tx_queue_id));
2937 ngbe_dev_store_tx_queue(struct ngbe_hw *hw, uint16_t tx_queue_id)
2939 u32 *reg = &hw->q_tx_regs[tx_queue_id * 8];
2940 wr32(hw, NGBE_TXBAL(tx_queue_id), *(reg++));
2941 wr32(hw, NGBE_TXBAH(tx_queue_id), *(reg++));
2942 wr32(hw, NGBE_TXCFG(tx_queue_id), *(reg++) & ~NGBE_TXCFG_ENA);
2946 * Start Receive Units for specified queue.
2949 ngbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2951 struct ngbe_hw *hw = ngbe_dev_hw(dev);
2952 struct ngbe_rx_queue *rxq;
2956 PMD_INIT_FUNC_TRACE();
2958 rxq = dev->data->rx_queues[rx_queue_id];
2960 /* Allocate buffers for descriptor rings */
2961 if (ngbe_alloc_rx_queue_mbufs(rxq) != 0) {
2962 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
2966 rxdctl = rd32(hw, NGBE_RXCFG(rxq->reg_idx));
2967 rxdctl |= NGBE_RXCFG_ENA;
2968 wr32(hw, NGBE_RXCFG(rxq->reg_idx), rxdctl);
2970 /* Wait until Rx Enable ready */
2971 poll_ms = RTE_NGBE_REGISTER_POLL_WAIT_10_MS;
2974 rxdctl = rd32(hw, NGBE_RXCFG(rxq->reg_idx));
2975 } while (--poll_ms && !(rxdctl & NGBE_RXCFG_ENA));
2977 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", rx_queue_id);
2979 wr32(hw, NGBE_RXRP(rxq->reg_idx), 0);
2980 wr32(hw, NGBE_RXWP(rxq->reg_idx), rxq->nb_rx_desc - 1);
2981 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2987 * Stop Receive Units for specified queue.
2990 ngbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2992 struct ngbe_hw *hw = ngbe_dev_hw(dev);
2993 struct ngbe_adapter *adapter = ngbe_dev_adapter(dev);
2994 struct ngbe_rx_queue *rxq;
2998 PMD_INIT_FUNC_TRACE();
3000 rxq = dev->data->rx_queues[rx_queue_id];
3002 ngbe_dev_save_rx_queue(hw, rxq->reg_idx);
3003 wr32m(hw, NGBE_RXCFG(rxq->reg_idx), NGBE_RXCFG_ENA, 0);
3005 /* Wait until Rx Enable bit clear */
3006 poll_ms = RTE_NGBE_REGISTER_POLL_WAIT_10_MS;
3009 rxdctl = rd32(hw, NGBE_RXCFG(rxq->reg_idx));
3010 } while (--poll_ms && (rxdctl & NGBE_RXCFG_ENA));
3012 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d", rx_queue_id);
3014 rte_delay_us(RTE_NGBE_WAIT_100_US);
3015 ngbe_dev_store_rx_queue(hw, rxq->reg_idx);
3017 ngbe_rx_queue_release_mbufs(rxq);
3018 ngbe_reset_rx_queue(adapter, rxq);
3019 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
3025 * Start Transmit Units for specified queue.
3028 ngbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3030 struct ngbe_hw *hw = ngbe_dev_hw(dev);
3031 struct ngbe_tx_queue *txq;
3035 PMD_INIT_FUNC_TRACE();
3037 txq = dev->data->tx_queues[tx_queue_id];
3038 wr32m(hw, NGBE_TXCFG(txq->reg_idx), NGBE_TXCFG_ENA, NGBE_TXCFG_ENA);
3040 /* Wait until Tx Enable ready */
3041 poll_ms = RTE_NGBE_REGISTER_POLL_WAIT_10_MS;
3044 txdctl = rd32(hw, NGBE_TXCFG(txq->reg_idx));
3045 } while (--poll_ms && !(txdctl & NGBE_TXCFG_ENA));
3047 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d",
3051 wr32(hw, NGBE_TXWP(txq->reg_idx), txq->tx_tail);
3052 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
3058 * Stop Transmit Units for specified queue.
3061 ngbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3063 struct ngbe_hw *hw = ngbe_dev_hw(dev);
3064 struct ngbe_tx_queue *txq;
3066 uint32_t txtdh, txtdt;
3069 PMD_INIT_FUNC_TRACE();
3071 txq = dev->data->tx_queues[tx_queue_id];
3073 /* Wait until Tx queue is empty */
3074 poll_ms = RTE_NGBE_REGISTER_POLL_WAIT_10_MS;
3076 rte_delay_us(RTE_NGBE_WAIT_100_US);
3077 txtdh = rd32(hw, NGBE_TXRP(txq->reg_idx));
3078 txtdt = rd32(hw, NGBE_TXWP(txq->reg_idx));
3079 } while (--poll_ms && (txtdh != txtdt));
3081 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty when stopping.",
3084 ngbe_dev_save_tx_queue(hw, txq->reg_idx);
3085 wr32m(hw, NGBE_TXCFG(txq->reg_idx), NGBE_TXCFG_ENA, 0);
3087 /* Wait until Tx Enable bit clear */
3088 poll_ms = RTE_NGBE_REGISTER_POLL_WAIT_10_MS;
3091 txdctl = rd32(hw, NGBE_TXCFG(txq->reg_idx));
3092 } while (--poll_ms && (txdctl & NGBE_TXCFG_ENA));
3094 PMD_INIT_LOG(ERR, "Could not disable Tx Queue %d",
3097 rte_delay_us(RTE_NGBE_WAIT_100_US);
3098 ngbe_dev_store_tx_queue(hw, txq->reg_idx);
3100 if (txq->ops != NULL) {
3101 txq->ops->release_mbufs(txq);
3102 txq->ops->reset(txq);
3104 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;