4 * Copyright (C) Cavium Inc. 2017. All rights reserved.
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7 * modification, are permitted provided that the following conditions
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17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
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21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include "octeontx_pkivf.h"
40 octeontx_pki_port_open(int port)
42 struct octeontx_mbox_hdr hdr;
45 hdr.coproc = OCTEONTX_PKI_COPROC;
46 hdr.msg = MBOX_PKI_PORT_OPEN;
49 res = octeontx_ssovf_mbox_send(&hdr, NULL, 0, NULL, 0);
56 octeontx_pki_port_hash_config(int port, pki_hash_cfg_t *hash_cfg)
58 struct octeontx_mbox_hdr hdr;
61 mbox_pki_hash_cfg_t h_cfg = *(mbox_pki_hash_cfg_t *)hash_cfg;
62 int len = sizeof(mbox_pki_hash_cfg_t);
64 hdr.coproc = OCTEONTX_PKI_COPROC;
65 hdr.msg = MBOX_PKI_PORT_HASH_CONFIG;
68 res = octeontx_ssovf_mbox_send(&hdr, &h_cfg, len, NULL, 0);
76 octeontx_pki_port_pktbuf_config(int port, pki_pktbuf_cfg_t *buf_cfg)
78 struct octeontx_mbox_hdr hdr;
81 mbox_pki_pktbuf_cfg_t b_cfg = *(mbox_pki_pktbuf_cfg_t *)buf_cfg;
82 int len = sizeof(mbox_pki_pktbuf_cfg_t);
84 hdr.coproc = OCTEONTX_PKI_COPROC;
85 hdr.msg = MBOX_PKI_PORT_PKTBUF_CONFIG;
88 res = octeontx_ssovf_mbox_send(&hdr, &b_cfg, len, NULL, 0);
95 octeontx_pki_port_create_qos(int port, pki_qos_cfg_t *qos_cfg)
97 struct octeontx_mbox_hdr hdr;
100 mbox_pki_qos_cfg_t q_cfg = *(mbox_pki_qos_cfg_t *)qos_cfg;
101 int len = sizeof(mbox_pki_qos_cfg_t);
103 hdr.coproc = OCTEONTX_PKI_COPROC;
104 hdr.msg = MBOX_PKI_PORT_CREATE_QOS;
107 res = octeontx_ssovf_mbox_send(&hdr, &q_cfg, len, NULL, 0);
116 octeontx_pki_port_errchk_config(int port, pki_errchk_cfg_t *cfg)
118 struct octeontx_mbox_hdr hdr;
121 mbox_pki_errcheck_cfg_t e_cfg;
122 e_cfg = *((mbox_pki_errcheck_cfg_t *)(cfg));
123 int len = sizeof(mbox_pki_errcheck_cfg_t);
125 hdr.coproc = OCTEONTX_PKI_COPROC;
126 hdr.msg = MBOX_PKI_PORT_ERRCHK_CONFIG;
129 res = octeontx_ssovf_mbox_send(&hdr, &e_cfg, len, NULL, 0);
136 #define PCI_VENDOR_ID_CAVIUM 0x177D
137 #define PCI_DEVICE_ID_OCTEONTX_PKI_VF 0xA0DD
139 /* PKIVF pcie device */
141 pkivf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
143 RTE_SET_USED(pci_drv);
144 RTE_SET_USED(pci_dev);
146 /* For secondary processes, the primary has done all the work */
147 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
153 static const struct rte_pci_id pci_pkivf_map[] = {
155 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
156 PCI_DEVICE_ID_OCTEONTX_PKI_VF)
163 static struct rte_pci_driver pci_pkivf = {
164 .id_table = pci_pkivf_map,
165 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
166 .probe = pkivf_probe,
169 RTE_PMD_REGISTER_PCI(octeontx_pkivf, pci_pkivf);