1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Cavium, Inc
5 #ifndef __OCTEONTX_ETHDEV_H__
6 #define __OCTEONTX_ETHDEV_H__
10 #include <rte_common.h>
11 #include <rte_ethdev_driver.h>
12 #include <rte_eventdev.h>
13 #include <rte_mempool.h>
14 #include <rte_memory.h>
16 #include <octeontx_fpavf.h>
18 #include "base/octeontx_bgx.h"
19 #include "base/octeontx_pki_var.h"
20 #include "base/octeontx_pkivf.h"
21 #include "base/octeontx_pkovf.h"
22 #include "base/octeontx_io.h"
24 #define OCTEONTX_PMD net_octeontx
25 #define OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT 12
26 #define OCTEONTX_VDEV_NR_PORT_ARG ("nr_port")
27 #define OCTEONTX_MAX_NAME_LEN 32
29 #define OCTEONTX_MAX_BGX_PORTS 4
30 #define OCTEONTX_MAX_LMAC_PER_BGX 4
32 #define OCCTX_RX_NB_SEG_MAX 6
34 /* VLAN tag inserted by OCCTX_TX_VTAG_ACTION.
35 * In Tx space is always reserved for this in FRS.
37 #define OCCTX_MAX_VTAG_INS 2
38 #define OCCTX_MAX_VTAG_ACT_SIZE (4 * OCCTX_MAX_VTAG_INS)
40 /* HW config of frame size doesn't include FCS */
41 #define OCCTX_MAX_HW_FRS 9212
42 #define OCCTX_MIN_HW_FRS 60
44 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
45 #define OCCTX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
46 OCCTX_MAX_VTAG_ACT_SIZE)
48 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
49 #define OCCTX_MAX_FRS \
50 (OCCTX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - OCCTX_MAX_VTAG_ACT_SIZE)
52 #define OCCTX_MIN_FRS (OCCTX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
54 #define OCCTX_MAX_MTU (OCCTX_MAX_FRS - OCCTX_L2_OVERHEAD)
56 #define OCTEONTX_RX_OFFLOADS (DEV_RX_OFFLOAD_CHECKSUM | \
57 DEV_RX_OFFLOAD_SCATTER | \
58 DEV_RX_OFFLOAD_JUMBO_FRAME)
60 #define OCTEONTX_TX_OFFLOADS (DEV_TX_OFFLOAD_MT_LOCKFREE | \
61 DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
62 DEV_TX_OFFLOAD_MULTI_SEGS)
64 static inline struct octeontx_nic *
65 octeontx_pmd_priv(struct rte_eth_dev *dev)
67 return dev->data->dev_private;
71 rte_octeontx_pchan_map[OCTEONTX_MAX_BGX_PORTS][OCTEONTX_MAX_LMAC_PER_BGX];
73 /* Octeontx ethdev nic */
75 struct rte_eth_dev *dev;
88 uint16_t num_tx_queues;
96 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
97 /* Rx port parameters */
99 bool classifier_enable;
106 uint64_t rx_offloads;
107 uint16_t rx_offload_flags;
108 uint64_t tx_offloads;
109 uint16_t tx_offload_flags;
110 } __rte_cache_aligned;
112 struct octeontx_txq {
115 struct rte_eth_dev *eth_dev;
116 } __rte_cache_aligned;
118 struct octeontx_rxq {
122 struct rte_eth_dev *eth_dev;
125 struct rte_mempool *pool;
126 } __rte_cache_aligned;
129 octeontx_set_tx_function(struct rte_eth_dev *dev);
130 #endif /* __OCTEONTX_ETHDEV_H__ */