net/dpaa: support FMCless mode
[dpdk.git] / drivers / net / octeontx / octeontx_ethdev.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2017 Cavium, Inc
3  */
4
5 #ifndef __OCTEONTX_ETHDEV_H__
6 #define __OCTEONTX_ETHDEV_H__
7
8 #include <stdbool.h>
9
10 #include <rte_common.h>
11 #include <rte_ethdev_driver.h>
12 #include <rte_eventdev.h>
13 #include <rte_mempool.h>
14 #include <rte_memory.h>
15
16 #include <octeontx_fpavf.h>
17
18 #include "base/octeontx_bgx.h"
19 #include "base/octeontx_pki_var.h"
20 #include "base/octeontx_pkivf.h"
21 #include "base/octeontx_pkovf.h"
22 #include "base/octeontx_io.h"
23
24 #define OCTEONTX_PMD                            net_octeontx
25 #define OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT       12
26 #define OCTEONTX_VDEV_NR_PORT_ARG               ("nr_port")
27 #define OCTEONTX_MAX_NAME_LEN                   32
28
29 #define OCTEONTX_MAX_BGX_PORTS                  4
30 #define OCTEONTX_MAX_LMAC_PER_BGX               4
31
32 #define OCCTX_RX_NB_SEG_MAX                     6
33 #define OCCTX_INTR_POLL_INTERVAL_MS             1000
34 /* VLAN tag inserted by OCCTX_TX_VTAG_ACTION.
35  * In Tx space is always reserved for this in FRS.
36  */
37 #define OCCTX_MAX_VTAG_INS              2
38 #define OCCTX_MAX_VTAG_ACT_SIZE         (4 * OCCTX_MAX_VTAG_INS)
39
40 /* HW config of frame size doesn't include FCS */
41 #define OCCTX_MAX_HW_FRS                9212
42 #define OCCTX_MIN_HW_FRS                60
43
44 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
45 #define OCCTX_L2_OVERHEAD       (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
46                                  OCCTX_MAX_VTAG_ACT_SIZE)
47
48 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
49 #define OCCTX_MAX_FRS   \
50         (OCCTX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - OCCTX_MAX_VTAG_ACT_SIZE)
51
52 #define OCCTX_MIN_FRS           (OCCTX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
53
54 #define OCCTX_MAX_MTU           (OCCTX_MAX_FRS - OCCTX_L2_OVERHEAD)
55
56 #define OCTEONTX_RX_OFFLOADS            (                                  \
57                                          DEV_RX_OFFLOAD_CHECKSUM         | \
58                                          DEV_RX_OFFLOAD_SCTP_CKSUM       | \
59                                          DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
60                                          DEV_RX_OFFLOAD_SCATTER          | \
61                                          DEV_RX_OFFLOAD_SCATTER          | \
62                                          DEV_RX_OFFLOAD_JUMBO_FRAME      | \
63                                          DEV_RX_OFFLOAD_VLAN_FILTER)
64
65 #define OCTEONTX_TX_OFFLOADS            (                                  \
66                                          DEV_TX_OFFLOAD_MBUF_FAST_FREE   | \
67                                          DEV_TX_OFFLOAD_MT_LOCKFREE      | \
68                                          DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
69                                          DEV_TX_OFFLOAD_OUTER_UDP_CKSUM  | \
70                                          DEV_TX_OFFLOAD_IPV4_CKSUM       | \
71                                          DEV_TX_OFFLOAD_TCP_CKSUM        | \
72                                          DEV_TX_OFFLOAD_UDP_CKSUM        | \
73                                          DEV_TX_OFFLOAD_SCTP_CKSUM       | \
74                                          DEV_TX_OFFLOAD_MULTI_SEGS)
75
76 static inline struct octeontx_nic *
77 octeontx_pmd_priv(struct rte_eth_dev *dev)
78 {
79         return dev->data->dev_private;
80 }
81
82 extern uint16_t
83 rte_octeontx_pchan_map[OCTEONTX_MAX_BGX_PORTS][OCTEONTX_MAX_LMAC_PER_BGX];
84
85 struct vlan_entry {
86         TAILQ_ENTRY(vlan_entry) next;
87         uint16_t vlan_id;
88 };
89
90 TAILQ_HEAD(octeontx_vlan_filter_tbl, vlan_entry);
91
92 struct octeontx_vlan_info {
93         struct octeontx_vlan_filter_tbl fltr_tbl;
94         uint8_t filter_on;
95 };
96
97 struct octeontx_fc_info {
98         enum rte_eth_fc_mode mode;  /**< Link flow control mode */
99         enum rte_eth_fc_mode def_mode;
100         uint16_t high_water;
101         uint16_t low_water;
102         uint16_t def_highmark;
103         uint16_t def_lowmark;
104         uint32_t rx_fifosz;
105 };
106
107 /* Octeontx ethdev nic */
108 struct octeontx_nic {
109         struct rte_eth_dev *dev;
110         int node;
111         int port_id;
112         int port_ena;
113         int base_ichan;
114         int num_ichans;
115         int base_ochan;
116         int num_ochans;
117         uint8_t evdev;
118         uint8_t bpen;
119         uint8_t fcs_strip;
120         uint8_t bcast_mode;
121         uint8_t mcast_mode;
122         uint16_t num_tx_queues;
123         uint64_t hwcap;
124         uint8_t pko_vfid;
125         uint8_t link_up;
126         uint8_t duplex;
127         uint8_t speed;
128         uint16_t bgx_mtu;
129         uint16_t mtu;
130         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
131         /* Rx port parameters */
132         struct {
133                 bool classifier_enable;
134                 bool hash_enable;
135                 bool initialized;
136         } pki;
137
138         uint16_t ev_queues;
139         uint16_t ev_ports;
140         uint64_t rx_offloads;
141         uint16_t rx_offload_flags;
142         uint64_t tx_offloads;
143         uint16_t tx_offload_flags;
144         struct octeontx_vlan_info vlan_info;
145         int print_flag;
146         struct octeontx_fc_info fc;
147 } __rte_cache_aligned;
148
149 struct octeontx_txq {
150         uint16_t queue_id;
151         octeontx_dq_t dq;
152         struct rte_eth_dev *eth_dev;
153 } __rte_cache_aligned;
154
155 struct octeontx_rxq {
156         uint16_t queue_id;
157         uint16_t port_id;
158         uint8_t evdev;
159         struct rte_eth_dev *eth_dev;
160         uint16_t ev_queues;
161         uint16_t ev_ports;
162         struct rte_mempool *pool;
163 } __rte_cache_aligned;
164
165 void
166 octeontx_set_tx_function(struct rte_eth_dev *dev);
167
168 /* VLAN */
169 int octeontx_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx);
170 int octeontx_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx);
171 int octeontx_dev_vlan_offload_init(struct rte_eth_dev *dev);
172 int octeontx_dev_vlan_offload_fini(struct rte_eth_dev *eth_dev);
173 int octeontx_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
174 int octeontx_dev_vlan_filter_set(struct rte_eth_dev *dev,
175                                  uint16_t vlan_id, int on);
176 int octeontx_dev_set_link_up(struct rte_eth_dev *eth_dev);
177 int octeontx_dev_set_link_down(struct rte_eth_dev *eth_dev);
178
179 /* Flow control */
180 int octeontx_dev_flow_ctrl_init(struct rte_eth_dev *dev);
181 int octeontx_dev_flow_ctrl_fini(struct rte_eth_dev *dev);
182 int octeontx_dev_flow_ctrl_get(struct rte_eth_dev *dev,
183                                struct rte_eth_fc_conf *fc_conf);
184 int octeontx_dev_flow_ctrl_set(struct rte_eth_dev *dev,
185                                struct rte_eth_fc_conf *fc_conf);
186
187 #endif /* __OCTEONTX_ETHDEV_H__ */