drivers/net/octeontx/octeontx_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Cavium, Inc
   3  */
   4
   5 #ifndef __OCTEONTX_ETHDEV_H__
   6 #define __OCTEONTX_ETHDEV_H__
   7
   8 #include <stdbool.h>
   9
  10 #include <rte_common.h>
  11 #include <ethdev_driver.h>
  12 #include <rte_eventdev.h>
  13 #include <rte_mempool.h>
  14 #include <rte_memory.h>
  15
  16 #include <octeontx_fpavf.h>
  17
  18 #include "base/octeontx_bgx.h"
  19 #include "base/octeontx_pki_var.h"
  20 #include "base/octeontx_pkivf.h"
  21 #include "base/octeontx_pkovf.h"
  22 #include "base/octeontx_io.h"
  23
  24 #define OCTEONTX_PMD                            net_octeontx
  25 #define OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT       12
  26 #define OCTEONTX_VDEV_NR_PORT_ARG               ("nr_port")
  27 #define OCTEONTX_MAX_NAME_LEN                   32
  28
  29 #define OCTEONTX_MAX_BGX_PORTS                  4
  30 #define OCTEONTX_MAX_LMAC_PER_BGX               4
  31
  32 #define OCCTX_RX_NB_SEG_MAX                     6
  33 #define OCCTX_INTR_POLL_INTERVAL_MS             1000
  34 /* VLAN tag inserted by OCCTX_TX_VTAG_ACTION.
  35  * In Tx space is always reserved for this in FRS.
  36  */
  37 #define OCCTX_MAX_VTAG_INS              2
  38 #define OCCTX_MAX_VTAG_ACT_SIZE         (4 * OCCTX_MAX_VTAG_INS)
  39
  40 /* HW config of frame size doesn't include FCS */
  41 #define OCCTX_MAX_HW_FRS                9212
  42 #define OCCTX_MIN_HW_FRS                60
  43
  44 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
  45 #define OCCTX_L2_OVERHEAD       (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
  46                                  OCCTX_MAX_VTAG_ACT_SIZE)
  47 #define OCCTX_L2_MAX_LEN        (RTE_ETHER_MTU + OCCTX_L2_OVERHEAD)
  48
  49 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
  50 #define OCCTX_MAX_FRS   \
  51         (OCCTX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - OCCTX_MAX_VTAG_ACT_SIZE)
  52
  53 #define OCCTX_MIN_FRS           (OCCTX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
  54
  55 #define OCCTX_MAX_MTU           (OCCTX_MAX_FRS - OCCTX_L2_OVERHEAD)
  56
  57 #define OCTEONTX_RX_OFFLOADS            (                                  \
  58                                          DEV_RX_OFFLOAD_CHECKSUM         | \
  59                                          DEV_RX_OFFLOAD_SCTP_CKSUM       | \
  60                                          DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
  61                                          DEV_RX_OFFLOAD_SCATTER          | \
  62                                          DEV_RX_OFFLOAD_SCATTER          | \
  63                                          DEV_RX_OFFLOAD_JUMBO_FRAME      | \
  64                                          DEV_RX_OFFLOAD_VLAN_FILTER)
  65
  66 #define OCTEONTX_TX_OFFLOADS            (                                  \
  67                                          DEV_TX_OFFLOAD_MBUF_FAST_FREE   | \
  68                                          DEV_TX_OFFLOAD_MT_LOCKFREE      | \
  69                                          DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
  70                                          DEV_TX_OFFLOAD_OUTER_UDP_CKSUM  | \
  71                                          DEV_TX_OFFLOAD_IPV4_CKSUM       | \
  72                                          DEV_TX_OFFLOAD_TCP_CKSUM        | \
  73                                          DEV_TX_OFFLOAD_UDP_CKSUM        | \
  74                                          DEV_TX_OFFLOAD_SCTP_CKSUM       | \
  75                                          DEV_TX_OFFLOAD_MULTI_SEGS)
  76
  77 static inline struct octeontx_nic *
  78 octeontx_pmd_priv(struct rte_eth_dev *dev)
  79 {
  80         return dev->data->dev_private;
  81 }
  82
  83 extern uint16_t
  84 rte_octeontx_pchan_map[OCTEONTX_MAX_BGX_PORTS][OCTEONTX_MAX_LMAC_PER_BGX];
  85
  86 struct vlan_entry {
  87         TAILQ_ENTRY(vlan_entry) next;
  88         uint16_t vlan_id;
  89 };
  90
  91 TAILQ_HEAD(octeontx_vlan_filter_tbl, vlan_entry);
  92
  93 struct octeontx_vlan_info {
  94         struct octeontx_vlan_filter_tbl fltr_tbl;
  95         uint8_t filter_on;
  96 };
  97
  98 struct octeontx_fc_info {
  99         enum rte_eth_fc_mode mode;  /**< Link flow control mode */
 100         enum rte_eth_fc_mode def_mode;
 101         uint16_t high_water;
 102         uint16_t low_water;
 103         uint16_t def_highmark;
 104         uint16_t def_lowmark;
 105         uint32_t rx_fifosz;
 106 };
 107
 108 /* Octeontx ethdev nic */
 109 struct octeontx_nic {
 110         struct rte_eth_dev *dev;
 111         int node;
 112         int port_id;
 113         int port_ena;
 114         int base_ichan;
 115         int num_ichans;
 116         int base_ochan;
 117         int num_ochans;
 118         uint8_t evdev;
 119         uint8_t bpen;
 120         uint8_t fcs_strip;
 121         uint8_t bcast_mode;
 122         uint8_t mcast_mode;
 123         uint16_t num_tx_queues;
 124         uint64_t hwcap;
 125         uint8_t pko_vfid;
 126         uint8_t link_up;
 127         uint8_t duplex;
 128         uint8_t speed;
 129         uint16_t bgx_mtu;
 130         uint16_t mtu;
 131         uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
 132         /* Rx port parameters */
 133         struct {
 134                 bool classifier_enable;
 135                 bool hash_enable;
 136                 bool initialized;
 137         } pki;
 138
 139         uint16_t ev_queues;
 140         uint16_t ev_ports;
 141         uint64_t rx_offloads;
 142         uint16_t rx_offload_flags;
 143         uint64_t tx_offloads;
 144         uint16_t tx_offload_flags;
 145         struct octeontx_vlan_info vlan_info;
 146         int print_flag;
 147         struct octeontx_fc_info fc;
 148 } __rte_cache_aligned;
 149
 150 struct octeontx_txq {
 151         uint16_t queue_id;
 152         octeontx_dq_t dq;
 153         struct rte_eth_dev *eth_dev;
 154 } __rte_cache_aligned;
 155
 156 struct octeontx_rxq {
 157         uint16_t queue_id;
 158         uint16_t port_id;
 159         uint8_t evdev;
 160         struct rte_eth_dev *eth_dev;
 161         uint16_t ev_queues;
 162         uint16_t ev_ports;
 163         struct rte_mempool *pool;
 164 } __rte_cache_aligned;
 165
 166 void
 167 octeontx_set_tx_function(struct rte_eth_dev *dev);
 168
 169 /* VLAN */
 170 int octeontx_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx);
 171 int octeontx_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx);
 172 int octeontx_dev_vlan_offload_init(struct rte_eth_dev *dev);
 173 int octeontx_dev_vlan_offload_fini(struct rte_eth_dev *eth_dev);
 174 int octeontx_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 175 int octeontx_dev_vlan_filter_set(struct rte_eth_dev *dev,
 176                                  uint16_t vlan_id, int on);
 177 int octeontx_dev_set_link_up(struct rte_eth_dev *eth_dev);
 178 int octeontx_dev_set_link_down(struct rte_eth_dev *eth_dev);
 179
 180 /* Flow control */
 181 int octeontx_dev_flow_ctrl_init(struct rte_eth_dev *dev);
 182 int octeontx_dev_flow_ctrl_fini(struct rte_eth_dev *dev);
 183 int octeontx_dev_flow_ctrl_get(struct rte_eth_dev *dev,
 184                                struct rte_eth_fc_conf *fc_conf);
 185 int octeontx_dev_flow_ctrl_set(struct rte_eth_dev *dev,
 186                                struct rte_eth_fc_conf *fc_conf);
 187
 188 #endif /* __OCTEONTX_ETHDEV_H__ */