1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_ethdev_pci.h>
7 #include <rte_malloc.h>
9 #include "otx2_ethdev.h"
12 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
14 RTE_SET_USED(eth_dev);
20 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
22 RTE_SET_USED(eth_dev);
23 RTE_SET_USED(mbox_close);
29 nix_remove(struct rte_pci_device *pci_dev)
31 struct rte_eth_dev *eth_dev;
34 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
37 rc = otx2_eth_dev_uninit(eth_dev, true);
41 rte_eth_dev_pci_release(eth_dev);
44 /* Nothing to be done for secondary processes */
45 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
52 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
56 RTE_SET_USED(pci_drv);
58 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
61 /* On error on secondary, recheck if port exists in primary or
62 * in mid of detach state.
64 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
65 if (!rte_eth_dev_allocated(pci_dev->device.name))
70 static const struct rte_pci_id pci_nix_map[] = {
72 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
75 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
78 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
79 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
86 static struct rte_pci_driver pci_nix = {
87 .id_table = pci_nix_map,
88 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA |
94 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
95 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
96 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");