1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <ethdev_pci.h>
9 #include <rte_malloc.h>
11 #include <rte_mbuf_pool_ops.h>
12 #include <rte_mempool.h>
14 #include "otx2_ethdev.h"
15 #include "otx2_ethdev_sec.h"
17 static inline uint64_t
18 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
20 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
22 if (otx2_dev_is_vf(dev) ||
23 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
24 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
29 static inline uint64_t
30 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
32 uint64_t capa = NIX_TX_OFFLOAD_CAPA;
34 /* TSO not supported for earlier chip revisions */
35 if (otx2_dev_is_96xx_A0(dev) || otx2_dev_is_95xx_Ax(dev))
36 capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
37 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
38 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
39 DEV_TX_OFFLOAD_GRE_TNL_TSO);
43 static const struct otx2_dev_ops otx2_dev_ops = {
44 .link_status_update = otx2_eth_dev_link_status_update,
45 .ptp_info_update = otx2_eth_dev_ptp_info_update
49 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
51 struct otx2_mbox *mbox = dev->mbox;
52 struct nix_lf_alloc_req *req;
53 struct nix_lf_alloc_rsp *rsp;
56 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
60 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
61 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
62 req->xqe_sz = NIX_XQESZ_W16;
63 req->rss_sz = dev->rss_info.rss_size;
64 req->rss_grps = NIX_RSS_GRPS;
65 req->npa_func = otx2_npa_pf_func_get();
66 req->sso_func = otx2_sso_pf_func_get();
67 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
68 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
69 DEV_RX_OFFLOAD_UDP_CKSUM)) {
70 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
71 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
73 req->rx_cfg |= (BIT_ULL(32 /* DROP_RE */) |
74 BIT_ULL(33 /* Outer L2 Length */) |
75 BIT_ULL(38 /* Inner L4 UDP Length */) |
76 BIT_ULL(39 /* Inner L3 Length */) |
77 BIT_ULL(40 /* Outer L4 UDP Length */) |
78 BIT_ULL(41 /* Outer L3 Length */));
80 if (dev->rss_tag_as_xor == 0)
81 req->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER;
83 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
87 dev->sqb_size = rsp->sqb_size;
88 dev->tx_chan_base = rsp->tx_chan_base;
89 dev->rx_chan_base = rsp->rx_chan_base;
90 dev->rx_chan_cnt = rsp->rx_chan_cnt;
91 dev->tx_chan_cnt = rsp->tx_chan_cnt;
92 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
93 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
94 dev->lf_tx_stats = rsp->lf_tx_stats;
95 dev->lf_rx_stats = rsp->lf_rx_stats;
96 dev->cints = rsp->cints;
97 dev->qints = rsp->qints;
98 dev->npc_flow.channel = dev->rx_chan_base;
99 dev->ptp_en = rsp->hw_rx_tstamp_en;
105 nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)
107 struct otx2_mbox *mbox = dev->mbox;
108 struct npc_set_pkind *req;
109 struct msg_resp *rsp;
112 if (dev->npc_flow.switch_header_type == 0)
115 /* Notify AF about higig2 config */
116 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
117 req->mode = dev->npc_flow.switch_header_type;
118 if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B) {
119 req->mode = OTX2_PRIV_FLAGS_CUSTOM;
120 req->pkind = NPC_RX_CHLEN90B_PKIND;
121 } else if (dev->npc_flow.switch_header_type ==
122 OTX2_PRIV_FLAGS_CH_LEN_24B) {
123 req->mode = OTX2_PRIV_FLAGS_CUSTOM;
124 req->pkind = NPC_RX_CHLEN24B_PKIND;
125 } else if (dev->npc_flow.switch_header_type ==
126 OTX2_PRIV_FLAGS_EXDSA) {
127 req->mode = OTX2_PRIV_FLAGS_CUSTOM;
128 req->pkind = NPC_RX_EXDSA_PKIND;
129 } else if (dev->npc_flow.switch_header_type ==
130 OTX2_PRIV_FLAGS_VLAN_EXDSA) {
131 req->mode = OTX2_PRIV_FLAGS_CUSTOM;
132 req->pkind = NPC_RX_VLAN_EXDSA_PKIND;
136 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
138 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
141 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
142 req->mode = dev->npc_flow.switch_header_type;
143 if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B ||
144 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_24B)
145 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
148 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
150 return otx2_mbox_process_msg(mbox, (void *)&rsp);
154 nix_lf_free(struct otx2_eth_dev *dev)
156 struct otx2_mbox *mbox = dev->mbox;
157 struct nix_lf_free_req *req;
158 struct ndc_sync_op *ndc_req;
161 /* Sync NDC-NIX for LF */
162 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
163 ndc_req->nix_lf_tx_sync = 1;
164 ndc_req->nix_lf_rx_sync = 1;
165 rc = otx2_mbox_process(mbox);
167 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
169 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
170 /* Let AF driver free all this nix lf's
171 * NPC entries allocated using NPC MBOX.
175 return otx2_mbox_process(mbox);
179 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
181 struct otx2_mbox *mbox = dev->mbox;
183 if (otx2_dev_is_vf_or_sdp(dev))
186 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
188 return otx2_mbox_process(mbox);
192 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
194 struct otx2_mbox *mbox = dev->mbox;
196 if (otx2_dev_is_vf_or_sdp(dev))
199 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
201 return otx2_mbox_process(mbox);
205 npc_rx_enable(struct otx2_eth_dev *dev)
207 struct otx2_mbox *mbox = dev->mbox;
209 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
211 return otx2_mbox_process(mbox);
215 npc_rx_disable(struct otx2_eth_dev *dev)
217 struct otx2_mbox *mbox = dev->mbox;
219 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
221 return otx2_mbox_process(mbox);
225 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
227 struct otx2_mbox *mbox = dev->mbox;
229 if (otx2_dev_is_vf_or_sdp(dev))
232 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
234 return otx2_mbox_process(mbox);
238 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
240 struct otx2_mbox *mbox = dev->mbox;
242 if (en && otx2_dev_is_vf_or_sdp(dev))
246 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
248 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
250 return otx2_mbox_process(mbox);
254 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
256 struct otx2_mbox *mbox = dev->mbox;
258 if (otx2_dev_is_vf_or_sdp(dev))
261 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
263 return otx2_mbox_process(mbox);
267 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
273 static inline uint32_t
274 nix_qsize_to_val(enum nix_q_size_e qsize)
276 return (16UL << (qsize * 2));
279 static inline enum nix_q_size_e
280 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
284 if (otx2_ethdev_fixup_is_min_4k_q(dev))
289 for (; i < nix_q_size_max; i++)
290 if (val <= nix_qsize_to_val(i))
293 if (i >= nix_q_size_max)
294 i = nix_q_size_max - 1;
300 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
301 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
303 struct otx2_mbox *mbox = dev->mbox;
304 const struct rte_memzone *rz;
305 uint32_t ring_size, cq_size;
306 struct nix_aq_enq_req *aq;
311 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
312 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
313 NIX_CQ_ALIGN, dev->node);
315 otx2_err("Failed to allocate mem for cq hw ring");
318 memset(rz->addr, 0, rz->len);
319 rxq->desc = (uintptr_t)rz->addr;
320 rxq->qmask = cq_size - 1;
322 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
324 aq->ctype = NIX_AQ_CTYPE_CQ;
325 aq->op = NIX_AQ_INSTOP_INIT;
329 aq->cq.qsize = rxq->qsize;
330 aq->cq.base = rz->iova;
331 aq->cq.avg_level = 0xff;
332 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
333 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
335 /* Many to one reduction */
336 aq->cq.qint_idx = qid % dev->qints;
337 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
338 aq->cq.cint_idx = qid;
340 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
341 const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
342 uint16_t min_rx_drop;
344 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
345 aq->cq.drop = min_rx_drop;
347 rxq->cq_drop = min_rx_drop;
349 rxq->cq_drop = NIX_CQ_THRESH_LEVEL;
350 aq->cq.drop = rxq->cq_drop;
354 /* TX pause frames enable flowctrl on RX side */
355 if (dev->fc_info.tx_pause) {
356 /* Single bpid is allocated for all rx channels for now */
357 aq->cq.bpid = dev->fc_info.bpid[0];
358 aq->cq.bp = rxq->cq_drop;
362 rc = otx2_mbox_process(mbox);
364 otx2_err("Failed to init cq context");
368 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
370 aq->ctype = NIX_AQ_CTYPE_RQ;
371 aq->op = NIX_AQ_INSTOP_INIT;
375 if (rxq->offloads & DEV_RX_OFFLOAD_SECURITY)
376 aq->rq.ipsech_ena = 1;
378 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
380 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
381 first_skip = (sizeof(struct rte_mbuf));
382 first_skip += RTE_PKTMBUF_HEADROOM;
383 first_skip += rte_pktmbuf_priv_size(mp);
384 rxq->data_off = first_skip;
386 first_skip /= 8; /* Expressed in number of dwords */
387 aq->rq.first_skip = first_skip;
388 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
389 aq->rq.flow_tagw = 32; /* 32-bits */
390 aq->rq.lpb_sizem1 = mp->elt_size / 8;
391 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
393 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
394 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
395 aq->rq.rq_int_ena = 0;
396 /* Many to one reduction */
397 aq->rq.qint_idx = qid % dev->qints;
399 aq->rq.xqe_drop_ena = 1;
401 rc = otx2_mbox_process(mbox);
403 otx2_err("Failed to init rq context");
407 if (dev->lock_rx_ctx) {
408 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
410 aq->ctype = NIX_AQ_CTYPE_CQ;
411 aq->op = NIX_AQ_INSTOP_LOCK;
413 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
415 /* The shared memory buffer can be full.
418 otx2_mbox_msg_send(mbox, 0);
419 rc = otx2_mbox_wait_for_rsp(mbox, 0);
421 otx2_err("Failed to LOCK cq context");
425 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
427 otx2_err("Failed to LOCK rq context");
432 aq->ctype = NIX_AQ_CTYPE_RQ;
433 aq->op = NIX_AQ_INSTOP_LOCK;
434 rc = otx2_mbox_process(mbox);
436 otx2_err("Failed to LOCK rq context");
445 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
446 struct otx2_eth_rxq *rxq, const bool enb)
448 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
449 struct otx2_mbox *mbox = dev->mbox;
450 struct nix_aq_enq_req *aq;
452 /* Pkts will be dropped silently if RQ is disabled */
453 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
455 aq->ctype = NIX_AQ_CTYPE_RQ;
456 aq->op = NIX_AQ_INSTOP_WRITE;
459 aq->rq_mask.ena = ~(aq->rq_mask.ena);
461 return otx2_mbox_process(mbox);
465 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
467 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
468 struct otx2_mbox *mbox = dev->mbox;
469 struct nix_aq_enq_req *aq;
472 /* RQ is already disabled */
474 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
476 aq->ctype = NIX_AQ_CTYPE_CQ;
477 aq->op = NIX_AQ_INSTOP_WRITE;
480 aq->cq_mask.ena = ~(aq->cq_mask.ena);
482 rc = otx2_mbox_process(mbox);
484 otx2_err("Failed to disable cq context");
488 if (dev->lock_rx_ctx) {
489 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
491 aq->ctype = NIX_AQ_CTYPE_CQ;
492 aq->op = NIX_AQ_INSTOP_UNLOCK;
494 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
496 /* The shared memory buffer can be full.
499 otx2_mbox_msg_send(mbox, 0);
500 rc = otx2_mbox_wait_for_rsp(mbox, 0);
502 otx2_err("Failed to UNLOCK cq context");
506 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
508 otx2_err("Failed to UNLOCK rq context");
513 aq->ctype = NIX_AQ_CTYPE_RQ;
514 aq->op = NIX_AQ_INSTOP_UNLOCK;
515 rc = otx2_mbox_process(mbox);
517 otx2_err("Failed to UNLOCK rq context");
526 nix_get_data_off(struct otx2_eth_dev *dev)
528 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
532 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
534 struct rte_mbuf mb_def;
537 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
538 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
539 offsetof(struct rte_mbuf, data_off) != 2);
540 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
541 offsetof(struct rte_mbuf, data_off) != 4);
542 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
543 offsetof(struct rte_mbuf, data_off) != 6);
545 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
546 mb_def.port = port_id;
547 rte_mbuf_refcnt_set(&mb_def, 1);
549 /* Prevent compiler reordering: rearm_data covers previous fields */
550 rte_compiler_barrier();
551 tmp = (uint64_t *)&mb_def.rearm_data;
557 otx2_nix_rx_queue_release(void *rx_queue)
559 struct otx2_eth_rxq *rxq = rx_queue;
564 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
565 nix_cq_rq_uninit(rxq->eth_dev, rxq);
570 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
571 uint16_t nb_desc, unsigned int socket,
572 const struct rte_eth_rxconf *rx_conf,
573 struct rte_mempool *mp)
575 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
576 struct rte_mempool_ops *ops;
577 struct otx2_eth_rxq *rxq;
578 const char *platform_ops;
579 enum nix_q_size_e qsize;
585 /* Compile time check to make sure all fast path elements in a CL */
586 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
589 if (rx_conf->rx_deferred_start == 1) {
590 otx2_err("Deferred Rx start is not supported");
594 platform_ops = rte_mbuf_platform_mempool_ops();
595 /* This driver needs octeontx2_npa mempool ops to work */
596 ops = rte_mempool_get_ops(mp->ops_index);
597 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
598 otx2_err("mempool ops should be of octeontx2_npa type");
602 if (mp->pool_id == 0) {
603 otx2_err("Invalid pool_id");
607 /* Free memory prior to re-allocation if needed */
608 if (eth_dev->data->rx_queues[rq] != NULL) {
609 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
610 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
611 rte_eth_dma_zone_free(eth_dev, "cq", rq);
612 eth_dev->data->rx_queues[rq] = NULL;
615 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
616 dev->rx_offloads |= offloads;
618 /* Find the CQ queue size */
619 qsize = nix_qsize_clampup_get(dev, nb_desc);
620 /* Allocate rxq memory */
621 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
623 otx2_err("Failed to allocate rq=%d", rq);
628 rxq->eth_dev = eth_dev;
630 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
631 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
632 rxq->wdata = (uint64_t)rq << 32;
633 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
634 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
635 eth_dev->data->port_id);
636 rxq->offloads = offloads;
638 rxq->qlen = nix_qsize_to_val(qsize);
640 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
641 rxq->tstamp = &dev->tstamp;
643 /* Alloc completion queue */
644 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
646 otx2_err("Failed to allocate rxq=%u", rq);
650 rxq->qconf.socket_id = socket;
651 rxq->qconf.nb_desc = nb_desc;
652 rxq->qconf.mempool = mp;
653 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
655 nix_rx_queue_reset(rxq);
656 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
657 rq, mp->name, qsize, nb_desc, rxq->qlen);
659 eth_dev->data->rx_queues[rq] = rxq;
660 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
662 /* Calculating delta and freq mult between PTP HI clock and tsc.
663 * These are needed in deriving raw clock value from tsc counter.
664 * read_clock eth op returns raw clock value.
666 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
667 otx2_ethdev_is_ptp_en(dev)) {
668 rc = otx2_nix_raw_clock_tsc_conv(dev);
670 otx2_err("Failed to calculate delta and freq mult");
675 /* Setup scatter mode if needed by jumbo */
676 otx2_nix_enable_mseg_on_jumbo(rxq);
681 otx2_nix_rx_queue_release(rxq);
686 static inline uint8_t
687 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
690 * Maximum three segments can be supported with W8, Choose
691 * NIX_MAXSQESZ_W16 for multi segment offload.
693 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
694 return NIX_MAXSQESZ_W16;
696 return NIX_MAXSQESZ_W8;
700 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
702 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
703 struct rte_eth_dev_data *data = eth_dev->data;
704 struct rte_eth_conf *conf = &data->dev_conf;
705 struct rte_eth_rxmode *rxmode = &conf->rxmode;
708 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
709 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
710 flags |= NIX_RX_OFFLOAD_RSS_F;
712 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
713 DEV_RX_OFFLOAD_UDP_CKSUM))
714 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
716 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
717 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
718 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
720 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
721 flags |= NIX_RX_MULTI_SEG_F;
723 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
724 DEV_RX_OFFLOAD_QINQ_STRIP))
725 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
727 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
728 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
730 if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
731 flags |= NIX_RX_OFFLOAD_SECURITY_F;
733 if (!dev->ptype_disable)
734 flags |= NIX_RX_OFFLOAD_PTYPE_F;
740 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
742 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
743 uint64_t conf = dev->tx_offloads;
746 /* Fastpath is dependent on these enums */
747 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
748 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
749 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
750 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
751 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
752 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
753 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
754 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
755 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
756 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
757 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
758 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
759 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
760 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
761 offsetof(struct rte_mbuf, buf_iova) + 8);
762 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
763 offsetof(struct rte_mbuf, buf_iova) + 16);
764 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
765 offsetof(struct rte_mbuf, ol_flags) + 12);
766 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
767 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
769 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
770 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
771 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
773 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
774 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
775 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
777 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
778 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
779 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
780 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
781 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
783 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
784 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
786 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
787 flags |= NIX_TX_MULTI_SEG_F;
789 /* Enable Inner checksum for TSO */
790 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
791 flags |= (NIX_TX_OFFLOAD_TSO_F |
792 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
794 /* Enable Inner and Outer checksum for Tunnel TSO */
795 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
796 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
797 DEV_TX_OFFLOAD_GRE_TNL_TSO))
798 flags |= (NIX_TX_OFFLOAD_TSO_F |
799 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
800 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
802 if (conf & DEV_TX_OFFLOAD_SECURITY)
803 flags |= NIX_TX_OFFLOAD_SECURITY_F;
805 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
806 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
812 nix_sqb_lock(struct rte_mempool *mp)
814 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
815 struct npa_aq_enq_req *req;
818 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
819 req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
820 req->ctype = NPA_AQ_CTYPE_AURA;
821 req->op = NPA_AQ_INSTOP_LOCK;
823 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
825 /* The shared memory buffer can be full.
828 otx2_mbox_msg_send(npa_lf->mbox, 0);
829 rc = otx2_mbox_wait_for_rsp(npa_lf->mbox, 0);
831 otx2_err("Failed to LOCK AURA context");
835 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
837 otx2_err("Failed to LOCK POOL context");
842 req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
843 req->ctype = NPA_AQ_CTYPE_POOL;
844 req->op = NPA_AQ_INSTOP_LOCK;
846 rc = otx2_mbox_process(npa_lf->mbox);
848 otx2_err("Unable to lock POOL in NDC");
856 nix_sqb_unlock(struct rte_mempool *mp)
858 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
859 struct npa_aq_enq_req *req;
862 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
863 req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
864 req->ctype = NPA_AQ_CTYPE_AURA;
865 req->op = NPA_AQ_INSTOP_UNLOCK;
867 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
869 /* The shared memory buffer can be full.
872 otx2_mbox_msg_send(npa_lf->mbox, 0);
873 rc = otx2_mbox_wait_for_rsp(npa_lf->mbox, 0);
875 otx2_err("Failed to UNLOCK AURA context");
879 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
881 otx2_err("Failed to UNLOCK POOL context");
885 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
886 req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
887 req->ctype = NPA_AQ_CTYPE_POOL;
888 req->op = NPA_AQ_INSTOP_UNLOCK;
890 rc = otx2_mbox_process(npa_lf->mbox);
892 otx2_err("Unable to UNLOCK AURA in NDC");
900 otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq)
902 struct rte_pktmbuf_pool_private *mbp_priv;
903 struct rte_eth_dev *eth_dev;
904 struct otx2_eth_dev *dev;
907 eth_dev = rxq->eth_dev;
908 dev = otx2_eth_pmd_priv(eth_dev);
910 /* Get rx buffer size */
911 mbp_priv = rte_mempool_get_priv(rxq->pool);
912 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
914 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buffsz) {
915 dev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER;
916 dev->tx_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
918 /* Setting up the rx[tx]_offload_flags due to change
919 * in rx[tx]_offloads.
921 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
922 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
927 nix_sq_init(struct otx2_eth_txq *txq)
929 struct otx2_eth_dev *dev = txq->dev;
930 struct otx2_mbox *mbox = dev->mbox;
931 struct nix_aq_enq_req *sq;
936 if (txq->sqb_pool->pool_id == 0)
939 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
941 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
945 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
947 sq->ctype = NIX_AQ_CTYPE_SQ;
948 sq->op = NIX_AQ_INSTOP_INIT;
949 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
952 sq->sq.smq_rr_quantum = rr_quantum;
953 sq->sq.default_chan = dev->tx_chan_base;
954 sq->sq.sqe_stype = NIX_STYPE_STF;
956 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
957 sq->sq.sqe_stype = NIX_STYPE_STP;
959 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
960 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
961 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
962 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
963 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
965 /* Many to one reduction */
966 sq->sq.qint_idx = txq->sq % dev->qints;
968 rc = otx2_mbox_process(mbox);
972 if (dev->lock_tx_ctx) {
973 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
975 sq->ctype = NIX_AQ_CTYPE_SQ;
976 sq->op = NIX_AQ_INSTOP_LOCK;
978 rc = otx2_mbox_process(mbox);
985 nix_sq_uninit(struct otx2_eth_txq *txq)
987 struct otx2_eth_dev *dev = txq->dev;
988 struct otx2_mbox *mbox = dev->mbox;
989 struct ndc_sync_op *ndc_req;
990 struct nix_aq_enq_rsp *rsp;
991 struct nix_aq_enq_req *aq;
992 uint16_t sqes_per_sqb;
996 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
998 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
1000 aq->ctype = NIX_AQ_CTYPE_SQ;
1001 aq->op = NIX_AQ_INSTOP_READ;
1003 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1007 /* Check if sq is already cleaned up */
1012 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
1014 aq->ctype = NIX_AQ_CTYPE_SQ;
1015 aq->op = NIX_AQ_INSTOP_WRITE;
1017 aq->sq_mask.ena = ~aq->sq_mask.ena;
1020 rc = otx2_mbox_process(mbox);
1024 if (dev->lock_tx_ctx) {
1026 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
1028 aq->ctype = NIX_AQ_CTYPE_SQ;
1029 aq->op = NIX_AQ_INSTOP_UNLOCK;
1031 rc = otx2_mbox_process(mbox);
1035 nix_sqb_unlock(txq->sqb_pool);
1038 /* Read SQ and free sqb's */
1039 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
1041 aq->ctype = NIX_AQ_CTYPE_SQ;
1042 aq->op = NIX_AQ_INSTOP_READ;
1044 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1048 if (aq->sq.smq_pend)
1049 otx2_err("SQ has pending sqe's");
1051 count = aq->sq.sqb_count;
1052 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
1053 /* Free SQB's that are used */
1054 sqb_buf = (void *)rsp->sq.head_sqb;
1058 next_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)
1059 ((sqes_per_sqb - 1) *
1060 nix_sq_max_sqe_sz(txq)));
1061 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
1067 /* Free next to use sqb */
1068 if (rsp->sq.next_sqb)
1069 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
1072 /* Sync NDC-NIX-TX for LF */
1073 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
1074 ndc_req->nix_lf_tx_sync = 1;
1075 rc = otx2_mbox_process(mbox);
1077 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
1083 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
1085 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
1086 struct npa_aq_enq_req *aura_req;
1088 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
1089 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
1090 aura_req->ctype = NPA_AQ_CTYPE_AURA;
1091 aura_req->op = NPA_AQ_INSTOP_WRITE;
1093 aura_req->aura.limit = nb_sqb_bufs;
1094 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
1096 return otx2_mbox_process(npa_lf->mbox);
1100 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
1102 struct otx2_eth_dev *dev = txq->dev;
1103 uint16_t sqes_per_sqb, nb_sqb_bufs;
1104 char name[RTE_MEMPOOL_NAMESIZE];
1105 struct rte_mempool_objsz sz;
1106 struct npa_aura_s *aura;
1107 uint32_t tmp, blk_sz;
1109 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
1110 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
1111 blk_sz = dev->sqb_size;
1113 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
1114 sqes_per_sqb = (dev->sqb_size / 8) / 16;
1116 sqes_per_sqb = (dev->sqb_size / 8) / 8;
1118 nb_sqb_bufs = nb_desc / sqes_per_sqb;
1119 /* Clamp up to devarg passed SQB count */
1120 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,
1121 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
1123 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
1125 MEMPOOL_F_NO_SPREAD);
1126 txq->nb_sqb_bufs = nb_sqb_bufs;
1127 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
1128 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
1129 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
1130 txq->nb_sqb_bufs_adj =
1131 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
1133 if (txq->sqb_pool == NULL) {
1134 otx2_err("Failed to allocate sqe mempool");
1138 memset(aura, 0, sizeof(*aura));
1140 aura->fc_addr = txq->fc_iova;
1141 aura->fc_hyst_bits = 0; /* Store count on all updates */
1142 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
1143 otx2_err("Failed to set ops for sqe mempool");
1146 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
1147 otx2_err("Failed to populate sqe mempool");
1151 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
1152 if (dev->sqb_size != sz.elt_size) {
1153 otx2_err("sqe pool block size is not expected %d != %d",
1154 dev->sqb_size, tmp);
1158 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
1159 if (dev->lock_tx_ctx)
1160 nix_sqb_lock(txq->sqb_pool);
1168 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
1170 struct nix_send_ext_s *send_hdr_ext;
1171 struct nix_send_hdr_s *send_hdr;
1172 struct nix_send_mem_s *send_mem;
1173 union nix_send_sg_s *sg;
1175 /* Initialize the fields based on basic single segment packet */
1176 memset(&txq->cmd, 0, sizeof(txq->cmd));
1178 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
1179 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
1180 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
1181 send_hdr->w0.sizem1 = 2;
1183 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
1184 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
1185 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
1186 /* Default: one seg packet would have:
1187 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
1190 send_hdr->w0.sizem1 = 3;
1191 send_hdr_ext->w0.tstmp = 1;
1193 /* To calculate the offset for send_mem,
1194 * send_hdr->w0.sizem1 * 2
1196 send_mem = (struct nix_send_mem_s *)(txq->cmd +
1197 (send_hdr->w0.sizem1 << 1));
1198 send_mem->subdc = NIX_SUBDC_MEM;
1199 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
1200 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
1202 sg = (union nix_send_sg_s *)&txq->cmd[4];
1204 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
1205 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
1206 send_hdr->w0.sizem1 = 1;
1207 sg = (union nix_send_sg_s *)&txq->cmd[2];
1210 send_hdr->w0.sq = txq->sq;
1211 sg->subdc = NIX_SUBDC_SG;
1213 sg->ld_type = NIX_SENDLDTYPE_LDD;
1219 otx2_nix_tx_queue_release(void *_txq)
1221 struct otx2_eth_txq *txq = _txq;
1222 struct rte_eth_dev *eth_dev;
1227 eth_dev = txq->dev->eth_dev;
1229 otx2_nix_dbg("Releasing txq %u", txq->sq);
1231 /* Flush and disable tm */
1232 otx2_nix_sq_flush_pre(txq, eth_dev->data->dev_started);
1234 /* Free sqb's and disable sq */
1237 if (txq->sqb_pool) {
1238 rte_mempool_free(txq->sqb_pool);
1239 txq->sqb_pool = NULL;
1241 otx2_nix_sq_flush_post(txq);
1247 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
1248 uint16_t nb_desc, unsigned int socket_id,
1249 const struct rte_eth_txconf *tx_conf)
1251 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1252 const struct rte_memzone *fc;
1253 struct otx2_eth_txq *txq;
1259 /* Compile time check to make sure all fast path elements in a CL */
1260 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
1262 if (tx_conf->tx_deferred_start) {
1263 otx2_err("Tx deferred start is not supported");
1267 /* Free memory prior to re-allocation if needed. */
1268 if (eth_dev->data->tx_queues[sq] != NULL) {
1269 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
1270 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
1271 eth_dev->data->tx_queues[sq] = NULL;
1274 /* Find the expected offloads for this queue */
1275 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
1277 /* Allocating tx queue data structure */
1278 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
1279 OTX2_ALIGN, socket_id);
1281 otx2_err("Failed to alloc txq=%d", sq);
1287 txq->sqb_pool = NULL;
1288 txq->offloads = offloads;
1289 dev->tx_offloads |= offloads;
1292 * Allocate memory for flow control updates from HW.
1293 * Alloc one cache line, so that fits all FC_STYPE modes.
1295 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
1296 OTX2_ALIGN + sizeof(struct npa_aura_s),
1297 OTX2_ALIGN, dev->node);
1299 otx2_err("Failed to allocate mem for fcmem");
1303 txq->fc_iova = fc->iova;
1304 txq->fc_mem = fc->addr;
1306 /* Initialize the aura sqb pool */
1307 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
1309 otx2_err("Failed to alloc sqe pool rc=%d", rc);
1313 /* Initialize the SQ */
1314 rc = nix_sq_init(txq);
1316 otx2_err("Failed to init sq=%d context", sq);
1320 txq->fc_cache_pkts = 0;
1321 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
1322 /* Evenly distribute LMT slot for each sq */
1323 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1325 txq->qconf.socket_id = socket_id;
1326 txq->qconf.nb_desc = nb_desc;
1327 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1329 otx2_nix_form_default_desc(txq);
1331 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1332 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1333 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1334 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1335 eth_dev->data->tx_queues[sq] = txq;
1336 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1340 otx2_nix_tx_queue_release(txq);
1346 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1348 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1349 struct otx2_eth_qconf *tx_qconf = NULL;
1350 struct otx2_eth_qconf *rx_qconf = NULL;
1351 struct otx2_eth_txq **txq;
1352 struct otx2_eth_rxq **rxq;
1353 int i, nb_rxq, nb_txq;
1355 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1356 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1358 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1359 if (tx_qconf == NULL) {
1360 otx2_err("Failed to allocate memory for tx_qconf");
1364 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1365 if (rx_qconf == NULL) {
1366 otx2_err("Failed to allocate memory for rx_qconf");
1370 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1371 for (i = 0; i < nb_txq; i++) {
1372 if (txq[i] == NULL) {
1373 tx_qconf[i].valid = false;
1374 otx2_info("txq[%d] is already released", i);
1377 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1378 tx_qconf[i].valid = true;
1379 otx2_nix_tx_queue_release(txq[i]);
1380 eth_dev->data->tx_queues[i] = NULL;
1383 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1384 for (i = 0; i < nb_rxq; i++) {
1385 if (rxq[i] == NULL) {
1386 rx_qconf[i].valid = false;
1387 otx2_info("rxq[%d] is already released", i);
1390 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1391 rx_qconf[i].valid = true;
1392 otx2_nix_rx_queue_release(rxq[i]);
1393 eth_dev->data->rx_queues[i] = NULL;
1396 dev->tx_qconf = tx_qconf;
1397 dev->rx_qconf = rx_qconf;
1408 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1410 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1411 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1412 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1413 struct otx2_eth_txq **txq;
1414 struct otx2_eth_rxq **rxq;
1415 int rc, i, nb_rxq, nb_txq;
1417 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1418 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1421 /* Setup tx & rx queues with previous configuration so
1422 * that the queues can be functional in cases like ports
1423 * are started without re configuring queues.
1425 * Usual re config sequence is like below:
1426 * port_configure() {
1431 * queue_configure() {
1438 * In some application's control path, queue_configure() would
1439 * NOT be invoked for TXQs/RXQs in port_configure().
1440 * In such cases, queues can be functional after start as the
1441 * queues are already setup in port_configure().
1443 for (i = 0; i < nb_txq; i++) {
1444 if (!tx_qconf[i].valid)
1446 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1447 tx_qconf[i].socket_id,
1448 &tx_qconf[i].conf.tx);
1450 otx2_err("Failed to setup tx queue rc=%d", rc);
1451 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1452 for (i -= 1; i >= 0; i--)
1453 otx2_nix_tx_queue_release(txq[i]);
1458 free(tx_qconf); tx_qconf = NULL;
1460 for (i = 0; i < nb_rxq; i++) {
1461 if (!rx_qconf[i].valid)
1463 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1464 rx_qconf[i].socket_id,
1465 &rx_qconf[i].conf.rx,
1466 rx_qconf[i].mempool);
1468 otx2_err("Failed to setup rx queue rc=%d", rc);
1469 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1470 for (i -= 1; i >= 0; i--)
1471 otx2_nix_rx_queue_release(rxq[i]);
1472 goto release_tx_queues;
1476 free(rx_qconf); rx_qconf = NULL;
1481 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1482 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1483 otx2_nix_tx_queue_release(txq[i]);
1494 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1496 RTE_SET_USED(queue);
1497 RTE_SET_USED(mbufs);
1504 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1506 /* These dummy functions are required for supporting
1507 * some applications which reconfigure queues without
1508 * stopping tx burst and rx burst threads(eg kni app)
1509 * When the queues context is saved, txq/rxqs are released
1510 * which caused app crash since rx/tx burst is still
1511 * on different lcores
1513 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1514 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1519 nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)
1521 volatile struct nix_lso_format *field;
1523 /* Format works only with TCP packet marked by OL3/OL4 */
1524 field = (volatile struct nix_lso_format *)&req->fields[0];
1525 req->field_mask = NIX_LSO_FIELD_MASK;
1526 /* Outer IPv4/IPv6 */
1527 field->layer = NIX_TXLAYER_OL3;
1528 field->offset = v4 ? 2 : 4;
1529 field->sizem1 = 1; /* 2B */
1530 field->alg = NIX_LSOALG_ADD_PAYLEN;
1534 field->layer = NIX_TXLAYER_OL3;
1537 /* Incremented linearly per segment */
1538 field->alg = NIX_LSOALG_ADD_SEGNUM;
1542 /* TCP sequence number update */
1543 field->layer = NIX_TXLAYER_OL4;
1545 field->sizem1 = 3; /* 4 bytes */
1546 field->alg = NIX_LSOALG_ADD_OFFSET;
1548 /* TCP flags field */
1549 field->layer = NIX_TXLAYER_OL4;
1552 field->alg = NIX_LSOALG_TCP_FLAGS;
1557 nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req,
1558 bool outer_v4, bool inner_v4)
1560 volatile struct nix_lso_format *field;
1562 field = (volatile struct nix_lso_format *)&req->fields[0];
1563 req->field_mask = NIX_LSO_FIELD_MASK;
1564 /* Outer IPv4/IPv6 len */
1565 field->layer = NIX_TXLAYER_OL3;
1566 field->offset = outer_v4 ? 2 : 4;
1567 field->sizem1 = 1; /* 2B */
1568 field->alg = NIX_LSOALG_ADD_PAYLEN;
1572 field->layer = NIX_TXLAYER_OL3;
1575 /* Incremented linearly per segment */
1576 field->alg = NIX_LSOALG_ADD_SEGNUM;
1580 /* Outer UDP length */
1581 field->layer = NIX_TXLAYER_OL4;
1584 field->alg = NIX_LSOALG_ADD_PAYLEN;
1587 /* Inner IPv4/IPv6 */
1588 field->layer = NIX_TXLAYER_IL3;
1589 field->offset = inner_v4 ? 2 : 4;
1590 field->sizem1 = 1; /* 2B */
1591 field->alg = NIX_LSOALG_ADD_PAYLEN;
1595 field->layer = NIX_TXLAYER_IL3;
1598 /* Incremented linearly per segment */
1599 field->alg = NIX_LSOALG_ADD_SEGNUM;
1603 /* TCP sequence number update */
1604 field->layer = NIX_TXLAYER_IL4;
1606 field->sizem1 = 3; /* 4 bytes */
1607 field->alg = NIX_LSOALG_ADD_OFFSET;
1610 /* TCP flags field */
1611 field->layer = NIX_TXLAYER_IL4;
1614 field->alg = NIX_LSOALG_TCP_FLAGS;
1619 nix_lso_tun_tcp(struct nix_lso_format_cfg *req,
1620 bool outer_v4, bool inner_v4)
1622 volatile struct nix_lso_format *field;
1624 field = (volatile struct nix_lso_format *)&req->fields[0];
1625 req->field_mask = NIX_LSO_FIELD_MASK;
1626 /* Outer IPv4/IPv6 len */
1627 field->layer = NIX_TXLAYER_OL3;
1628 field->offset = outer_v4 ? 2 : 4;
1629 field->sizem1 = 1; /* 2B */
1630 field->alg = NIX_LSOALG_ADD_PAYLEN;
1634 field->layer = NIX_TXLAYER_OL3;
1637 /* Incremented linearly per segment */
1638 field->alg = NIX_LSOALG_ADD_SEGNUM;
1642 /* Inner IPv4/IPv6 */
1643 field->layer = NIX_TXLAYER_IL3;
1644 field->offset = inner_v4 ? 2 : 4;
1645 field->sizem1 = 1; /* 2B */
1646 field->alg = NIX_LSOALG_ADD_PAYLEN;
1650 field->layer = NIX_TXLAYER_IL3;
1653 /* Incremented linearly per segment */
1654 field->alg = NIX_LSOALG_ADD_SEGNUM;
1658 /* TCP sequence number update */
1659 field->layer = NIX_TXLAYER_IL4;
1661 field->sizem1 = 3; /* 4 bytes */
1662 field->alg = NIX_LSOALG_ADD_OFFSET;
1665 /* TCP flags field */
1666 field->layer = NIX_TXLAYER_IL4;
1669 field->alg = NIX_LSOALG_TCP_FLAGS;
1674 nix_setup_lso_formats(struct otx2_eth_dev *dev)
1676 struct otx2_mbox *mbox = dev->mbox;
1677 struct nix_lso_format_cfg_rsp *rsp;
1678 struct nix_lso_format_cfg *req;
1682 /* Skip if TSO was not requested */
1683 if (!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))
1688 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1689 nix_lso_tcp(req, true);
1690 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1694 base = rsp->lso_format_idx;
1695 if (base != NIX_LSO_FORMAT_IDX_TSOV4)
1697 dev->lso_base_idx = base;
1698 otx2_nix_dbg("tcpv4 lso fmt=%u", base);
1704 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1705 nix_lso_tcp(req, false);
1706 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1710 if (rsp->lso_format_idx != base + 1)
1712 otx2_nix_dbg("tcpv6 lso fmt=%u\n", base + 1);
1715 * IPv4/UDP/TUN HDR/IPv4/TCP LSO
1717 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1718 nix_lso_udp_tun_tcp(req, true, true);
1719 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1723 if (rsp->lso_format_idx != base + 2)
1725 otx2_nix_dbg("udp tun v4v4 fmt=%u\n", base + 2);
1728 * IPv4/UDP/TUN HDR/IPv6/TCP LSO
1730 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1731 nix_lso_udp_tun_tcp(req, true, false);
1732 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1736 if (rsp->lso_format_idx != base + 3)
1738 otx2_nix_dbg("udp tun v4v6 fmt=%u\n", base + 3);
1741 * IPv6/UDP/TUN HDR/IPv4/TCP LSO
1743 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1744 nix_lso_udp_tun_tcp(req, false, true);
1745 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1749 if (rsp->lso_format_idx != base + 4)
1751 otx2_nix_dbg("udp tun v6v4 fmt=%u\n", base + 4);
1754 * IPv6/UDP/TUN HDR/IPv6/TCP LSO
1756 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1757 nix_lso_udp_tun_tcp(req, false, false);
1758 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1761 if (rsp->lso_format_idx != base + 5)
1763 otx2_nix_dbg("udp tun v6v6 fmt=%u\n", base + 5);
1766 * IPv4/TUN HDR/IPv4/TCP LSO
1768 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1769 nix_lso_tun_tcp(req, true, true);
1770 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1774 if (rsp->lso_format_idx != base + 6)
1776 otx2_nix_dbg("tun v4v4 fmt=%u\n", base + 6);
1779 * IPv4/TUN HDR/IPv6/TCP LSO
1781 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1782 nix_lso_tun_tcp(req, true, false);
1783 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1787 if (rsp->lso_format_idx != base + 7)
1789 otx2_nix_dbg("tun v4v6 fmt=%u\n", base + 7);
1792 * IPv6/TUN HDR/IPv4/TCP LSO
1794 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1795 nix_lso_tun_tcp(req, false, true);
1796 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1800 if (rsp->lso_format_idx != base + 8)
1802 otx2_nix_dbg("tun v6v4 fmt=%u\n", base + 8);
1805 * IPv6/TUN HDR/IPv6/TCP LSO
1807 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1808 nix_lso_tun_tcp(req, false, false);
1809 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1812 if (rsp->lso_format_idx != base + 9)
1814 otx2_nix_dbg("tun v6v6 fmt=%u\n", base + 9);
1819 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1821 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1822 struct rte_eth_dev_data *data = eth_dev->data;
1823 struct rte_eth_conf *conf = &data->dev_conf;
1824 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1825 struct rte_eth_txmode *txmode = &conf->txmode;
1826 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1827 struct rte_ether_addr *ea;
1828 uint8_t nb_rxq, nb_txq;
1834 if (rte_eal_has_hugepages() == 0) {
1835 otx2_err("Huge page is not configured");
1836 goto fail_configure;
1839 if (conf->dcb_capability_en == 1) {
1840 otx2_err("dcb enable is not supported");
1841 goto fail_configure;
1844 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1845 otx2_err("Flow director is not supported");
1846 goto fail_configure;
1849 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1850 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1851 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1852 goto fail_configure;
1855 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1856 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1857 goto fail_configure;
1860 if (otx2_dev_is_Ax(dev) &&
1861 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1862 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1863 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1864 otx2_err("Outer IP and SCTP checksum unsupported");
1865 goto fail_configure;
1868 /* Free the resources allocated from the previous configure */
1869 if (dev->configured == 1) {
1870 otx2_eth_sec_fini(eth_dev);
1871 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1872 otx2_nix_vlan_fini(eth_dev);
1873 otx2_nix_mc_addr_list_uninstall(eth_dev);
1874 otx2_flow_free_all_resources(dev);
1875 oxt2_nix_unregister_queue_irqs(eth_dev);
1876 if (eth_dev->data->dev_conf.intr_conf.rxq)
1877 oxt2_nix_unregister_cq_irqs(eth_dev);
1878 nix_set_nop_rxtx_function(eth_dev);
1879 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1881 goto fail_configure;
1882 otx2_nix_tm_fini(eth_dev);
1886 dev->rx_offloads = rxmode->offloads;
1887 dev->tx_offloads = txmode->offloads;
1888 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1889 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1890 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1892 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1893 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1895 /* Alloc a nix lf */
1896 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1898 otx2_err("Failed to init nix_lf rc=%d", rc);
1902 otx2_nix_err_intr_enb_dis(eth_dev, true);
1903 otx2_nix_ras_intr_enb_dis(eth_dev, true);
1906 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
1907 otx2_err("Both PTP and switch header enabled");
1911 rc = nix_lf_switch_header_type_enable(dev, true);
1913 otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
1917 rc = nix_setup_lso_formats(dev);
1919 otx2_err("failed to setup nix lso format fields, rc=%d", rc);
1924 rc = otx2_nix_rss_config(eth_dev);
1926 otx2_err("Failed to configure rss rc=%d", rc);
1930 /* Init the default TM scheduler hierarchy */
1931 rc = otx2_nix_tm_init_default(eth_dev);
1933 otx2_err("Failed to init traffic manager rc=%d", rc);
1937 rc = otx2_nix_vlan_offload_init(eth_dev);
1939 otx2_err("Failed to init vlan offload rc=%d", rc);
1943 /* Register queue IRQs */
1944 rc = oxt2_nix_register_queue_irqs(eth_dev);
1946 otx2_err("Failed to register queue interrupts rc=%d", rc);
1950 /* Register cq IRQs */
1951 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1952 if (eth_dev->data->nb_rx_queues > dev->cints) {
1953 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1957 /* Rx interrupt feature cannot work with vector mode because,
1958 * vector mode doesn't process packets unless min 4 pkts are
1959 * received, while cq interrupts are generated even for 1 pkt
1962 dev->scalar_ena = true;
1964 rc = oxt2_nix_register_cq_irqs(eth_dev);
1966 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1971 /* Configure loop back mode */
1972 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1974 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1978 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1980 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1984 /* Enable security */
1985 rc = otx2_eth_sec_init(eth_dev);
1989 rc = otx2_nix_flow_ctrl_init(eth_dev);
1991 otx2_err("Failed to init flow ctrl mode %d", rc);
1995 rc = otx2_nix_mc_addr_list_install(eth_dev);
1997 otx2_err("Failed to install mc address list rc=%d", rc);
2002 * Restore queue config when reconfigure followed by
2003 * reconfigure and no queue configure invoked from application case.
2005 if (dev->configured == 1) {
2006 rc = nix_restore_queue_cfg(eth_dev);
2008 goto uninstall_mc_list;
2011 /* Update the mac address */
2012 ea = eth_dev->data->mac_addrs;
2013 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2014 if (rte_is_zero_ether_addr(ea))
2015 rte_eth_random_addr((uint8_t *)ea);
2017 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
2019 /* Apply new link configurations if changed */
2020 rc = otx2_apply_link_speed(eth_dev);
2022 otx2_err("Failed to set link configuration");
2023 goto uninstall_mc_list;
2026 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
2027 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
2028 " rx_flags=0x%x tx_flags=0x%x",
2029 eth_dev->data->port_id, ea_fmt, nb_rxq,
2030 nb_txq, dev->rx_offloads, dev->tx_offloads,
2031 dev->rx_offload_flags, dev->tx_offload_flags);
2034 dev->configured = 1;
2035 dev->configured_nb_rx_qs = data->nb_rx_queues;
2036 dev->configured_nb_tx_qs = data->nb_tx_queues;
2040 otx2_nix_mc_addr_list_uninstall(eth_dev);
2042 otx2_eth_sec_fini(eth_dev);
2044 oxt2_nix_unregister_cq_irqs(eth_dev);
2046 oxt2_nix_unregister_queue_irqs(eth_dev);
2048 otx2_nix_vlan_fini(eth_dev);
2050 otx2_nix_tm_fini(eth_dev);
2054 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
2055 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
2057 dev->configured = 0;
2062 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
2064 struct rte_eth_dev_data *data = eth_dev->data;
2065 struct otx2_eth_txq *txq;
2068 txq = eth_dev->data->tx_queues[qidx];
2070 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
2073 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
2075 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
2080 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
2087 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
2089 struct rte_eth_dev_data *data = eth_dev->data;
2090 struct otx2_eth_txq *txq;
2093 txq = eth_dev->data->tx_queues[qidx];
2095 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
2098 txq->fc_cache_pkts = 0;
2100 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
2102 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
2107 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
2114 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
2116 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
2117 struct rte_eth_dev_data *data = eth_dev->data;
2120 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
2123 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
2125 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
2129 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
2136 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
2138 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
2139 struct rte_eth_dev_data *data = eth_dev->data;
2142 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
2145 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
2147 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
2151 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
2158 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
2160 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2161 struct rte_mbuf *rx_pkts[32];
2162 struct otx2_eth_rxq *rxq;
2163 int count, i, j, rc;
2165 nix_lf_switch_header_type_enable(dev, false);
2166 nix_cgx_stop_link_event(dev);
2167 npc_rx_disable(dev);
2169 /* Stop rx queues and free up pkts pending */
2170 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2171 rc = otx2_nix_rx_queue_stop(eth_dev, i);
2175 rxq = eth_dev->data->rx_queues[i];
2176 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
2178 for (j = 0; j < count; j++)
2179 rte_pktmbuf_free(rx_pkts[j]);
2180 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
2184 /* Stop tx queues */
2185 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
2186 otx2_nix_tx_queue_stop(eth_dev, i);
2192 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
2194 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2197 /* MTU recalculate should be avoided here if PTP is enabled by PF, as
2198 * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
2201 if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
2202 rc = otx2_nix_recalc_mtu(eth_dev);
2207 /* Start rx queues */
2208 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2209 rc = otx2_nix_rx_queue_start(eth_dev, i);
2214 /* Start tx queues */
2215 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2216 rc = otx2_nix_tx_queue_start(eth_dev, i);
2221 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
2223 otx2_err("Failed to update flow ctrl mode %d", rc);
2227 /* Enable PTP if it was requested by the app or if it is already
2228 * enabled in PF owning this VF
2230 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
2231 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
2232 otx2_ethdev_is_ptp_en(dev))
2233 otx2_nix_timesync_enable(eth_dev);
2235 otx2_nix_timesync_disable(eth_dev);
2237 /* Update VF about data off shifted by 8 bytes if PTP already
2238 * enabled in PF owning this VF
2240 if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
2241 otx2_nix_ptp_enable_vf(eth_dev);
2243 if (dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F) {
2244 rc = rte_mbuf_dyn_rx_timestamp_register(
2245 &dev->tstamp.tstamp_dynfield_offset,
2246 &dev->tstamp.rx_tstamp_dynflag);
2248 otx2_err("Failed to register Rx timestamp field/flag");
2253 rc = npc_rx_enable(dev);
2255 otx2_err("Failed to enable NPC rx %d", rc);
2259 otx2_nix_toggle_flag_link_cfg(dev, true);
2261 rc = nix_cgx_start_link_event(dev);
2263 otx2_err("Failed to start cgx link event %d", rc);
2267 otx2_nix_toggle_flag_link_cfg(dev, false);
2268 otx2_eth_set_tx_function(eth_dev);
2269 otx2_eth_set_rx_function(eth_dev);
2274 npc_rx_disable(dev);
2275 otx2_nix_toggle_flag_link_cfg(dev, false);
2279 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
2280 static int otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
2282 /* Initialize and register driver with DPDK Application */
2283 static const struct eth_dev_ops otx2_eth_dev_ops = {
2284 .dev_infos_get = otx2_nix_info_get,
2285 .dev_configure = otx2_nix_configure,
2286 .link_update = otx2_nix_link_update,
2287 .tx_queue_setup = otx2_nix_tx_queue_setup,
2288 .tx_queue_release = otx2_nix_tx_queue_release,
2289 .tm_ops_get = otx2_nix_tm_ops_get,
2290 .rx_queue_setup = otx2_nix_rx_queue_setup,
2291 .rx_queue_release = otx2_nix_rx_queue_release,
2292 .dev_start = otx2_nix_dev_start,
2293 .dev_stop = otx2_nix_dev_stop,
2294 .dev_close = otx2_nix_dev_close,
2295 .tx_queue_start = otx2_nix_tx_queue_start,
2296 .tx_queue_stop = otx2_nix_tx_queue_stop,
2297 .rx_queue_start = otx2_nix_rx_queue_start,
2298 .rx_queue_stop = otx2_nix_rx_queue_stop,
2299 .dev_set_link_up = otx2_nix_dev_set_link_up,
2300 .dev_set_link_down = otx2_nix_dev_set_link_down,
2301 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
2302 .dev_ptypes_set = otx2_nix_ptypes_set,
2303 .dev_reset = otx2_nix_dev_reset,
2304 .stats_get = otx2_nix_dev_stats_get,
2305 .stats_reset = otx2_nix_dev_stats_reset,
2306 .get_reg = otx2_nix_dev_get_reg,
2307 .mtu_set = otx2_nix_mtu_set,
2308 .mac_addr_add = otx2_nix_mac_addr_add,
2309 .mac_addr_remove = otx2_nix_mac_addr_del,
2310 .mac_addr_set = otx2_nix_mac_addr_set,
2311 .set_mc_addr_list = otx2_nix_set_mc_addr_list,
2312 .promiscuous_enable = otx2_nix_promisc_enable,
2313 .promiscuous_disable = otx2_nix_promisc_disable,
2314 .allmulticast_enable = otx2_nix_allmulticast_enable,
2315 .allmulticast_disable = otx2_nix_allmulticast_disable,
2316 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
2317 .reta_update = otx2_nix_dev_reta_update,
2318 .reta_query = otx2_nix_dev_reta_query,
2319 .rss_hash_update = otx2_nix_rss_hash_update,
2320 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
2321 .xstats_get = otx2_nix_xstats_get,
2322 .xstats_get_names = otx2_nix_xstats_get_names,
2323 .xstats_reset = otx2_nix_xstats_reset,
2324 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
2325 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
2326 .rxq_info_get = otx2_nix_rxq_info_get,
2327 .txq_info_get = otx2_nix_txq_info_get,
2328 .rx_burst_mode_get = otx2_rx_burst_mode_get,
2329 .tx_burst_mode_get = otx2_tx_burst_mode_get,
2330 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
2331 .set_queue_rate_limit = otx2_nix_tm_set_queue_rate_limit,
2332 .pool_ops_supported = otx2_nix_pool_ops_supported,
2333 .flow_ops_get = otx2_nix_dev_flow_ops_get,
2334 .get_module_info = otx2_nix_get_module_info,
2335 .get_module_eeprom = otx2_nix_get_module_eeprom,
2336 .fw_version_get = otx2_nix_fw_version_get,
2337 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
2338 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
2339 .timesync_enable = otx2_nix_timesync_enable,
2340 .timesync_disable = otx2_nix_timesync_disable,
2341 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
2342 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
2343 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
2344 .timesync_read_time = otx2_nix_timesync_read_time,
2345 .timesync_write_time = otx2_nix_timesync_write_time,
2346 .vlan_offload_set = otx2_nix_vlan_offload_set,
2347 .vlan_filter_set = otx2_nix_vlan_filter_set,
2348 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
2349 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
2350 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
2351 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
2352 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
2353 .read_clock = otx2_nix_read_clock,
2357 nix_lf_attach(struct otx2_eth_dev *dev)
2359 struct otx2_mbox *mbox = dev->mbox;
2360 struct rsrc_attach_req *req;
2362 /* Attach NIX(lf) */
2363 req = otx2_mbox_alloc_msg_attach_resources(mbox);
2367 return otx2_mbox_process(mbox);
2371 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
2373 struct otx2_mbox *mbox = dev->mbox;
2374 struct msix_offset_rsp *msix_rsp;
2377 /* Get NPA and NIX MSIX vector offsets */
2378 otx2_mbox_alloc_msg_msix_offset(mbox);
2380 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
2382 dev->nix_msixoff = msix_rsp->nix_msixoff;
2388 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
2390 struct rsrc_detach_req *req;
2392 req = otx2_mbox_alloc_msg_detach_resources(mbox);
2394 /* Detach all except npa lf */
2395 req->partial = true;
2402 return otx2_mbox_process(mbox);
2406 otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
2408 if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
2409 pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2414 static inline uint64_t
2415 nix_get_blkaddr(struct otx2_eth_dev *dev)
2419 /* Reading the discovery register to know which NIX is the LF
2422 reg = otx2_read64(dev->bar2 +
2423 RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_NIX0));
2425 return reg & 0x1FFULL ? RVU_BLOCK_ADDR_NIX0 : RVU_BLOCK_ADDR_NIX1;
2429 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
2431 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2432 struct rte_pci_device *pci_dev;
2433 int rc, max_entries;
2435 eth_dev->dev_ops = &otx2_eth_dev_ops;
2436 eth_dev->rx_descriptor_done = otx2_nix_rx_descriptor_done;
2437 eth_dev->rx_queue_count = otx2_nix_rx_queue_count;
2438 eth_dev->rx_descriptor_status = otx2_nix_rx_descriptor_status;
2439 eth_dev->tx_descriptor_status = otx2_nix_tx_descriptor_status;
2441 /* For secondary processes, the primary has done all the work */
2442 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2443 /* Setup callbacks for secondary process */
2444 otx2_eth_set_tx_function(eth_dev);
2445 otx2_eth_set_rx_function(eth_dev);
2449 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2451 rte_eth_copy_pci_info(eth_dev, pci_dev);
2452 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2454 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
2455 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
2456 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
2458 /* Parse devargs string */
2459 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
2461 otx2_err("Failed to parse devargs rc=%d", rc);
2465 if (!dev->mbox_active) {
2466 /* Initialize the base otx2_dev object
2467 * only if already present
2469 rc = otx2_dev_init(pci_dev, dev);
2471 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
2475 if (otx2_eth_dev_is_sdp(pci_dev))
2476 dev->sdp_link = true;
2478 dev->sdp_link = false;
2479 /* Device generic callbacks */
2480 dev->ops = &otx2_dev_ops;
2481 dev->eth_dev = eth_dev;
2483 /* Grab the NPA LF if required */
2484 rc = otx2_npa_lf_init(pci_dev, dev);
2486 goto otx2_dev_uninit;
2488 dev->configured = 0;
2489 dev->drv_inited = true;
2490 dev->ptype_disable = 0;
2491 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
2494 rc = nix_lf_attach(dev);
2496 goto otx2_npa_uninit;
2498 dev->base = dev->bar2 + (nix_get_blkaddr(dev) << 20);
2500 /* Get NIX MSIX offset */
2501 rc = nix_lf_get_msix_offset(dev);
2503 goto otx2_npa_uninit;
2505 /* Register LF irq handlers */
2506 rc = otx2_nix_register_irqs(eth_dev);
2510 /* Get maximum number of supported MAC entries */
2511 max_entries = otx2_cgx_mac_max_entries_get(dev);
2512 if (max_entries < 0) {
2513 otx2_err("Failed to get max entries for mac addr");
2515 goto unregister_irq;
2518 /* For VFs, returned max_entries will be 0. But to keep default MAC
2519 * address, one entry must be allocated. So setting up to 1.
2521 if (max_entries == 0)
2524 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
2525 RTE_ETHER_ADDR_LEN, 0);
2526 if (eth_dev->data->mac_addrs == NULL) {
2527 otx2_err("Failed to allocate memory for mac addr");
2529 goto unregister_irq;
2532 dev->max_mac_entries = max_entries;
2534 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
2536 goto free_mac_addrs;
2538 /* Update the mac address */
2539 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2541 /* Also sync same MAC address to CGX table */
2542 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
2544 /* Initialize the tm data structures */
2545 otx2_nix_tm_conf_init(eth_dev);
2547 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
2548 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
2550 if (otx2_dev_is_96xx_A0(dev) ||
2551 otx2_dev_is_95xx_Ax(dev)) {
2552 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
2553 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
2556 /* Create security ctx */
2557 rc = otx2_eth_sec_ctx_create(eth_dev);
2559 goto free_mac_addrs;
2560 dev->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
2561 dev->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
2563 /* Initialize rte-flow */
2564 rc = otx2_flow_init(dev);
2566 goto sec_ctx_destroy;
2568 otx2_nix_mc_filter_init(dev);
2570 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
2571 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
2572 eth_dev->data->port_id, dev->pf, dev->vf,
2573 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
2574 dev->rx_offload_capa, dev->tx_offload_capa);
2578 otx2_eth_sec_ctx_destroy(eth_dev);
2580 rte_free(eth_dev->data->mac_addrs);
2582 otx2_nix_unregister_irqs(eth_dev);
2584 otx2_eth_dev_lf_detach(dev->mbox);
2588 otx2_dev_fini(pci_dev, dev);
2590 otx2_err("Failed to init nix eth_dev rc=%d", rc);
2595 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
2597 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2598 struct rte_pci_device *pci_dev;
2601 /* Nothing to be done for secondary processes */
2602 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2605 /* Clear the flag since we are closing down */
2606 dev->configured = 0;
2608 /* Disable nix bpid config */
2609 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
2611 npc_rx_disable(dev);
2613 /* Disable vlan offloads */
2614 otx2_nix_vlan_fini(eth_dev);
2616 /* Disable other rte_flow entries */
2617 otx2_flow_fini(dev);
2619 /* Free multicast filter list */
2620 otx2_nix_mc_filter_fini(dev);
2622 /* Disable PTP if already enabled */
2623 if (otx2_ethdev_is_ptp_en(dev))
2624 otx2_nix_timesync_disable(eth_dev);
2626 nix_cgx_stop_link_event(dev);
2629 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2630 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
2631 eth_dev->data->tx_queues[i] = NULL;
2633 eth_dev->data->nb_tx_queues = 0;
2635 /* Free up RQ's and CQ's */
2636 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2637 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
2638 eth_dev->data->rx_queues[i] = NULL;
2640 eth_dev->data->nb_rx_queues = 0;
2642 /* Free tm resources */
2643 rc = otx2_nix_tm_fini(eth_dev);
2645 otx2_err("Failed to cleanup tm, rc=%d", rc);
2647 /* Unregister queue irqs */
2648 oxt2_nix_unregister_queue_irqs(eth_dev);
2650 /* Unregister cq irqs */
2651 if (eth_dev->data->dev_conf.intr_conf.rxq)
2652 oxt2_nix_unregister_cq_irqs(eth_dev);
2654 rc = nix_lf_free(dev);
2656 otx2_err("Failed to free nix lf, rc=%d", rc);
2658 rc = otx2_npa_lf_fini();
2660 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
2662 /* Disable security */
2663 otx2_eth_sec_fini(eth_dev);
2665 /* Destroy security ctx */
2666 otx2_eth_sec_ctx_destroy(eth_dev);
2668 rte_free(eth_dev->data->mac_addrs);
2669 eth_dev->data->mac_addrs = NULL;
2670 dev->drv_inited = false;
2672 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2673 otx2_nix_unregister_irqs(eth_dev);
2675 rc = otx2_eth_dev_lf_detach(dev->mbox);
2677 otx2_err("Failed to detach resources, rc=%d", rc);
2679 /* Check if mbox close is needed */
2683 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
2684 /* Will be freed later by PMD */
2685 eth_dev->data->dev_private = NULL;
2689 otx2_dev_fini(pci_dev, dev);
2694 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
2696 otx2_eth_dev_uninit(eth_dev, true);
2701 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
2705 rc = otx2_eth_dev_uninit(eth_dev, false);
2709 return otx2_eth_dev_init(eth_dev);
2713 nix_remove(struct rte_pci_device *pci_dev)
2715 struct rte_eth_dev *eth_dev;
2716 struct otx2_idev_cfg *idev;
2717 struct otx2_dev *otx2_dev;
2720 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
2722 /* Cleanup eth dev */
2723 rc = otx2_eth_dev_uninit(eth_dev, true);
2727 rte_eth_dev_release_port(eth_dev);
2730 /* Nothing to be done for secondary processes */
2731 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2734 /* Check for common resources */
2735 idev = otx2_intra_dev_get_cfg();
2736 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
2739 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
2741 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
2744 /* Safe to cleanup mbox as no more users */
2745 otx2_dev_fini(pci_dev, otx2_dev);
2750 otx2_info("%s: common resource in use by other devices", pci_dev->name);
2755 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2759 RTE_SET_USED(pci_drv);
2761 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2764 /* On error on secondary, recheck if port exists in primary or
2765 * in mid of detach state.
2767 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2768 if (!rte_eth_dev_allocated(pci_dev->device.name))
2773 static const struct rte_pci_id pci_nix_map[] = {
2775 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2778 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2781 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2782 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2785 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2786 PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
2789 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2790 PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2797 static struct rte_pci_driver pci_nix = {
2798 .id_table = pci_nix_map,
2799 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2800 RTE_PCI_DRV_INTR_LSC,
2802 .remove = nix_remove,
2805 RTE_PMD_REGISTER_PCI(OCTEONTX2_PMD, pci_nix);
2806 RTE_PMD_REGISTER_PCI_TABLE(OCTEONTX2_PMD, pci_nix_map);
2807 RTE_PMD_REGISTER_KMOD_DEP(OCTEONTX2_PMD, "vfio-pci");