1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_ethdev_pci.h>
9 #include <rte_malloc.h>
11 #include <rte_mbuf_pool_ops.h>
12 #include <rte_mempool.h>
14 #include "otx2_ethdev.h"
16 static inline uint64_t
17 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
19 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
21 if (otx2_dev_is_vf(dev) ||
22 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
23 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
28 static inline uint64_t
29 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
31 uint64_t capa = NIX_TX_OFFLOAD_CAPA;
33 /* TSO not supported for earlier chip revisions */
34 if (otx2_dev_is_96xx_A0(dev) || otx2_dev_is_95xx_Ax(dev))
35 capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
36 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
37 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
38 DEV_TX_OFFLOAD_GRE_TNL_TSO);
42 static const struct otx2_dev_ops otx2_dev_ops = {
43 .link_status_update = otx2_eth_dev_link_status_update,
44 .ptp_info_update = otx2_eth_dev_ptp_info_update
48 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
50 struct otx2_mbox *mbox = dev->mbox;
51 struct nix_lf_alloc_req *req;
52 struct nix_lf_alloc_rsp *rsp;
55 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
59 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
60 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
61 req->xqe_sz = NIX_XQESZ_W16;
62 req->rss_sz = dev->rss_info.rss_size;
63 req->rss_grps = NIX_RSS_GRPS;
64 req->npa_func = otx2_npa_pf_func_get();
65 req->sso_func = otx2_sso_pf_func_get();
66 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
67 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
68 DEV_RX_OFFLOAD_UDP_CKSUM)) {
69 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
70 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
72 req->rx_cfg |= BIT_ULL(32 /* DROP_RE */);
73 if (dev->rss_tag_as_xor == 0)
74 req->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER;
76 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
80 dev->sqb_size = rsp->sqb_size;
81 dev->tx_chan_base = rsp->tx_chan_base;
82 dev->rx_chan_base = rsp->rx_chan_base;
83 dev->rx_chan_cnt = rsp->rx_chan_cnt;
84 dev->tx_chan_cnt = rsp->tx_chan_cnt;
85 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
86 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
87 dev->lf_tx_stats = rsp->lf_tx_stats;
88 dev->lf_rx_stats = rsp->lf_rx_stats;
89 dev->cints = rsp->cints;
90 dev->qints = rsp->qints;
91 dev->npc_flow.channel = dev->rx_chan_base;
92 dev->ptp_en = rsp->hw_rx_tstamp_en;
98 nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)
100 struct otx2_mbox *mbox = dev->mbox;
101 struct npc_set_pkind *req;
102 struct msg_resp *rsp;
105 if (dev->npc_flow.switch_header_type == 0)
108 /* Notify AF about higig2 config */
109 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
110 req->mode = dev->npc_flow.switch_header_type;
112 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
114 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
117 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
118 req->mode = dev->npc_flow.switch_header_type;
120 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
122 return otx2_mbox_process_msg(mbox, (void *)&rsp);
126 nix_lf_free(struct otx2_eth_dev *dev)
128 struct otx2_mbox *mbox = dev->mbox;
129 struct nix_lf_free_req *req;
130 struct ndc_sync_op *ndc_req;
133 /* Sync NDC-NIX for LF */
134 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
135 ndc_req->nix_lf_tx_sync = 1;
136 ndc_req->nix_lf_rx_sync = 1;
137 rc = otx2_mbox_process(mbox);
139 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
141 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
142 /* Let AF driver free all this nix lf's
143 * NPC entries allocated using NPC MBOX.
147 return otx2_mbox_process(mbox);
151 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
153 struct otx2_mbox *mbox = dev->mbox;
155 if (otx2_dev_is_vf_or_sdp(dev))
158 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
160 return otx2_mbox_process(mbox);
164 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
166 struct otx2_mbox *mbox = dev->mbox;
168 if (otx2_dev_is_vf_or_sdp(dev))
171 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
173 return otx2_mbox_process(mbox);
177 npc_rx_enable(struct otx2_eth_dev *dev)
179 struct otx2_mbox *mbox = dev->mbox;
181 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
183 return otx2_mbox_process(mbox);
187 npc_rx_disable(struct otx2_eth_dev *dev)
189 struct otx2_mbox *mbox = dev->mbox;
191 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
193 return otx2_mbox_process(mbox);
197 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
199 struct otx2_mbox *mbox = dev->mbox;
201 if (otx2_dev_is_vf_or_sdp(dev))
204 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
206 return otx2_mbox_process(mbox);
210 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
212 struct otx2_mbox *mbox = dev->mbox;
214 if (en && otx2_dev_is_vf_or_sdp(dev))
218 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
220 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
222 return otx2_mbox_process(mbox);
226 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
228 struct otx2_mbox *mbox = dev->mbox;
230 if (otx2_dev_is_vf_or_sdp(dev))
233 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
235 return otx2_mbox_process(mbox);
239 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
245 static inline uint32_t
246 nix_qsize_to_val(enum nix_q_size_e qsize)
248 return (16UL << (qsize * 2));
251 static inline enum nix_q_size_e
252 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
256 if (otx2_ethdev_fixup_is_min_4k_q(dev))
261 for (; i < nix_q_size_max; i++)
262 if (val <= nix_qsize_to_val(i))
265 if (i >= nix_q_size_max)
266 i = nix_q_size_max - 1;
272 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
273 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
275 struct otx2_mbox *mbox = dev->mbox;
276 const struct rte_memzone *rz;
277 uint32_t ring_size, cq_size;
278 struct nix_aq_enq_req *aq;
283 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
284 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
285 NIX_CQ_ALIGN, dev->node);
287 otx2_err("Failed to allocate mem for cq hw ring");
291 memset(rz->addr, 0, rz->len);
292 rxq->desc = (uintptr_t)rz->addr;
293 rxq->qmask = cq_size - 1;
295 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
297 aq->ctype = NIX_AQ_CTYPE_CQ;
298 aq->op = NIX_AQ_INSTOP_INIT;
302 aq->cq.qsize = rxq->qsize;
303 aq->cq.base = rz->iova;
304 aq->cq.avg_level = 0xff;
305 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
306 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
308 /* Many to one reduction */
309 aq->cq.qint_idx = qid % dev->qints;
310 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
311 aq->cq.cint_idx = qid;
313 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
314 const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
315 uint16_t min_rx_drop;
317 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
318 aq->cq.drop = min_rx_drop;
320 rxq->cq_drop = min_rx_drop;
322 rxq->cq_drop = NIX_CQ_THRESH_LEVEL;
323 aq->cq.drop = rxq->cq_drop;
327 /* TX pause frames enable flowctrl on RX side */
328 if (dev->fc_info.tx_pause) {
329 /* Single bpid is allocated for all rx channels for now */
330 aq->cq.bpid = dev->fc_info.bpid[0];
331 aq->cq.bp = rxq->cq_drop;
335 rc = otx2_mbox_process(mbox);
337 otx2_err("Failed to init cq context");
341 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
343 aq->ctype = NIX_AQ_CTYPE_RQ;
344 aq->op = NIX_AQ_INSTOP_INIT;
347 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
349 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
350 first_skip = (sizeof(struct rte_mbuf));
351 first_skip += RTE_PKTMBUF_HEADROOM;
352 first_skip += rte_pktmbuf_priv_size(mp);
353 rxq->data_off = first_skip;
355 first_skip /= 8; /* Expressed in number of dwords */
356 aq->rq.first_skip = first_skip;
357 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
358 aq->rq.flow_tagw = 32; /* 32-bits */
359 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
360 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
361 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
362 aq->rq.lpb_sizem1 /= 8;
363 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
365 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
366 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
367 aq->rq.rq_int_ena = 0;
368 /* Many to one reduction */
369 aq->rq.qint_idx = qid % dev->qints;
371 aq->rq.xqe_drop_ena = 1;
373 rc = otx2_mbox_process(mbox);
375 otx2_err("Failed to init rq context");
385 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
386 struct otx2_eth_rxq *rxq, const bool enb)
388 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
389 struct otx2_mbox *mbox = dev->mbox;
390 struct nix_aq_enq_req *aq;
392 /* Pkts will be dropped silently if RQ is disabled */
393 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
395 aq->ctype = NIX_AQ_CTYPE_RQ;
396 aq->op = NIX_AQ_INSTOP_WRITE;
399 aq->rq_mask.ena = ~(aq->rq_mask.ena);
401 return otx2_mbox_process(mbox);
405 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
407 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
408 struct otx2_mbox *mbox = dev->mbox;
409 struct nix_aq_enq_req *aq;
412 /* RQ is already disabled */
414 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
416 aq->ctype = NIX_AQ_CTYPE_CQ;
417 aq->op = NIX_AQ_INSTOP_WRITE;
420 aq->cq_mask.ena = ~(aq->cq_mask.ena);
422 rc = otx2_mbox_process(mbox);
424 otx2_err("Failed to disable cq context");
432 nix_get_data_off(struct otx2_eth_dev *dev)
434 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
438 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
440 struct rte_mbuf mb_def;
443 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
444 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
445 offsetof(struct rte_mbuf, data_off) != 2);
446 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
447 offsetof(struct rte_mbuf, data_off) != 4);
448 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
449 offsetof(struct rte_mbuf, data_off) != 6);
451 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
452 mb_def.port = port_id;
453 rte_mbuf_refcnt_set(&mb_def, 1);
455 /* Prevent compiler reordering: rearm_data covers previous fields */
456 rte_compiler_barrier();
457 tmp = (uint64_t *)&mb_def.rearm_data;
463 otx2_nix_rx_queue_release(void *rx_queue)
465 struct otx2_eth_rxq *rxq = rx_queue;
470 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
471 nix_cq_rq_uninit(rxq->eth_dev, rxq);
476 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
477 uint16_t nb_desc, unsigned int socket,
478 const struct rte_eth_rxconf *rx_conf,
479 struct rte_mempool *mp)
481 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
482 struct rte_mempool_ops *ops;
483 struct otx2_eth_rxq *rxq;
484 const char *platform_ops;
485 enum nix_q_size_e qsize;
491 /* Compile time check to make sure all fast path elements in a CL */
492 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
495 if (rx_conf->rx_deferred_start == 1) {
496 otx2_err("Deferred Rx start is not supported");
500 platform_ops = rte_mbuf_platform_mempool_ops();
501 /* This driver needs octeontx2_npa mempool ops to work */
502 ops = rte_mempool_get_ops(mp->ops_index);
503 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
504 otx2_err("mempool ops should be of octeontx2_npa type");
508 if (mp->pool_id == 0) {
509 otx2_err("Invalid pool_id");
513 /* Free memory prior to re-allocation if needed */
514 if (eth_dev->data->rx_queues[rq] != NULL) {
515 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
516 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
517 eth_dev->data->rx_queues[rq] = NULL;
520 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
521 dev->rx_offloads |= offloads;
523 /* Find the CQ queue size */
524 qsize = nix_qsize_clampup_get(dev, nb_desc);
525 /* Allocate rxq memory */
526 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
528 otx2_err("Failed to allocate rq=%d", rq);
533 rxq->eth_dev = eth_dev;
535 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
536 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
537 rxq->wdata = (uint64_t)rq << 32;
538 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
539 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
540 eth_dev->data->port_id);
541 rxq->offloads = offloads;
543 rxq->qlen = nix_qsize_to_val(qsize);
545 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
546 rxq->tstamp = &dev->tstamp;
548 /* Alloc completion queue */
549 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
551 otx2_err("Failed to allocate rxq=%u", rq);
555 rxq->qconf.socket_id = socket;
556 rxq->qconf.nb_desc = nb_desc;
557 rxq->qconf.mempool = mp;
558 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
560 nix_rx_queue_reset(rxq);
561 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
562 rq, mp->name, qsize, nb_desc, rxq->qlen);
564 eth_dev->data->rx_queues[rq] = rxq;
565 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
567 /* Calculating delta and freq mult between PTP HI clock and tsc.
568 * These are needed in deriving raw clock value from tsc counter.
569 * read_clock eth op returns raw clock value.
571 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
572 otx2_ethdev_is_ptp_en(dev)) {
573 rc = otx2_nix_raw_clock_tsc_conv(dev);
575 otx2_err("Failed to calculate delta and freq mult");
583 otx2_nix_rx_queue_release(rxq);
588 static inline uint8_t
589 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
592 * Maximum three segments can be supported with W8, Choose
593 * NIX_MAXSQESZ_W16 for multi segment offload.
595 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
596 return NIX_MAXSQESZ_W16;
598 return NIX_MAXSQESZ_W8;
602 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
604 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
605 struct rte_eth_dev_data *data = eth_dev->data;
606 struct rte_eth_conf *conf = &data->dev_conf;
607 struct rte_eth_rxmode *rxmode = &conf->rxmode;
610 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
611 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
612 flags |= NIX_RX_OFFLOAD_RSS_F;
614 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
615 DEV_RX_OFFLOAD_UDP_CKSUM))
616 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
618 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
619 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
620 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
622 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
623 flags |= NIX_RX_MULTI_SEG_F;
625 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
626 DEV_RX_OFFLOAD_QINQ_STRIP))
627 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
629 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
630 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
632 if (!dev->ptype_disable)
633 flags |= NIX_RX_OFFLOAD_PTYPE_F;
639 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
641 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
642 uint64_t conf = dev->tx_offloads;
645 /* Fastpath is dependent on these enums */
646 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
647 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
648 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
649 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
650 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
651 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
652 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
653 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
654 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
655 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
656 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
657 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
658 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
659 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
660 offsetof(struct rte_mbuf, buf_iova) + 8);
661 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
662 offsetof(struct rte_mbuf, buf_iova) + 16);
663 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
664 offsetof(struct rte_mbuf, ol_flags) + 12);
665 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
666 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
668 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
669 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
670 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
672 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
673 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
674 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
676 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
677 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
678 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
679 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
680 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
682 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
683 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
685 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
686 flags |= NIX_TX_MULTI_SEG_F;
688 /* Enable Inner checksum for TSO */
689 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
690 flags |= (NIX_TX_OFFLOAD_TSO_F |
691 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
693 /* Enable Inner and Outer checksum for Tunnel TSO */
694 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
695 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
696 DEV_TX_OFFLOAD_GRE_TNL_TSO))
697 flags |= (NIX_TX_OFFLOAD_TSO_F |
698 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
699 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
701 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
702 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
708 nix_sq_init(struct otx2_eth_txq *txq)
710 struct otx2_eth_dev *dev = txq->dev;
711 struct otx2_mbox *mbox = dev->mbox;
712 struct nix_aq_enq_req *sq;
717 if (txq->sqb_pool->pool_id == 0)
720 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
722 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
726 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
728 sq->ctype = NIX_AQ_CTYPE_SQ;
729 sq->op = NIX_AQ_INSTOP_INIT;
730 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
733 sq->sq.smq_rr_quantum = rr_quantum;
734 sq->sq.default_chan = dev->tx_chan_base;
735 sq->sq.sqe_stype = NIX_STYPE_STF;
737 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
738 sq->sq.sqe_stype = NIX_STYPE_STP;
740 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
741 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
742 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
743 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
744 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
746 /* Many to one reduction */
747 sq->sq.qint_idx = txq->sq % dev->qints;
749 return otx2_mbox_process(mbox);
753 nix_sq_uninit(struct otx2_eth_txq *txq)
755 struct otx2_eth_dev *dev = txq->dev;
756 struct otx2_mbox *mbox = dev->mbox;
757 struct ndc_sync_op *ndc_req;
758 struct nix_aq_enq_rsp *rsp;
759 struct nix_aq_enq_req *aq;
760 uint16_t sqes_per_sqb;
764 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
766 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
768 aq->ctype = NIX_AQ_CTYPE_SQ;
769 aq->op = NIX_AQ_INSTOP_READ;
771 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
775 /* Check if sq is already cleaned up */
780 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
782 aq->ctype = NIX_AQ_CTYPE_SQ;
783 aq->op = NIX_AQ_INSTOP_WRITE;
785 aq->sq_mask.ena = ~aq->sq_mask.ena;
788 rc = otx2_mbox_process(mbox);
792 /* Read SQ and free sqb's */
793 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
795 aq->ctype = NIX_AQ_CTYPE_SQ;
796 aq->op = NIX_AQ_INSTOP_READ;
798 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
803 otx2_err("SQ has pending sqe's");
805 count = aq->sq.sqb_count;
806 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
807 /* Free SQB's that are used */
808 sqb_buf = (void *)rsp->sq.head_sqb;
812 next_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)
813 ((sqes_per_sqb - 1) *
814 nix_sq_max_sqe_sz(txq)));
815 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
821 /* Free next to use sqb */
822 if (rsp->sq.next_sqb)
823 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
826 /* Sync NDC-NIX-TX for LF */
827 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
828 ndc_req->nix_lf_tx_sync = 1;
829 rc = otx2_mbox_process(mbox);
831 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
837 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
839 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
840 struct npa_aq_enq_req *aura_req;
842 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
843 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
844 aura_req->ctype = NPA_AQ_CTYPE_AURA;
845 aura_req->op = NPA_AQ_INSTOP_WRITE;
847 aura_req->aura.limit = nb_sqb_bufs;
848 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
850 return otx2_mbox_process(npa_lf->mbox);
854 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
856 struct otx2_eth_dev *dev = txq->dev;
857 uint16_t sqes_per_sqb, nb_sqb_bufs;
858 char name[RTE_MEMPOOL_NAMESIZE];
859 struct rte_mempool_objsz sz;
860 struct npa_aura_s *aura;
861 uint32_t tmp, blk_sz;
863 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
864 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
865 blk_sz = dev->sqb_size;
867 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
868 sqes_per_sqb = (dev->sqb_size / 8) / 16;
870 sqes_per_sqb = (dev->sqb_size / 8) / 8;
872 nb_sqb_bufs = nb_desc / sqes_per_sqb;
873 /* Clamp up to devarg passed SQB count */
874 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,
875 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
877 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
879 MEMPOOL_F_NO_SPREAD);
880 txq->nb_sqb_bufs = nb_sqb_bufs;
881 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
882 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
883 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
884 txq->nb_sqb_bufs_adj =
885 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
887 if (txq->sqb_pool == NULL) {
888 otx2_err("Failed to allocate sqe mempool");
892 memset(aura, 0, sizeof(*aura));
894 aura->fc_addr = txq->fc_iova;
895 aura->fc_hyst_bits = 0; /* Store count on all updates */
896 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
897 otx2_err("Failed to set ops for sqe mempool");
900 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
901 otx2_err("Failed to populate sqe mempool");
905 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
906 if (dev->sqb_size != sz.elt_size) {
907 otx2_err("sqe pool block size is not expected %d != %d",
912 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
920 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
922 struct nix_send_ext_s *send_hdr_ext;
923 struct nix_send_hdr_s *send_hdr;
924 struct nix_send_mem_s *send_mem;
925 union nix_send_sg_s *sg;
927 /* Initialize the fields based on basic single segment packet */
928 memset(&txq->cmd, 0, sizeof(txq->cmd));
930 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
931 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
932 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
933 send_hdr->w0.sizem1 = 2;
935 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
936 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
937 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
938 /* Default: one seg packet would have:
939 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
942 send_hdr->w0.sizem1 = 3;
943 send_hdr_ext->w0.tstmp = 1;
945 /* To calculate the offset for send_mem,
946 * send_hdr->w0.sizem1 * 2
948 send_mem = (struct nix_send_mem_s *)(txq->cmd +
949 (send_hdr->w0.sizem1 << 1));
950 send_mem->subdc = NIX_SUBDC_MEM;
951 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
952 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
954 sg = (union nix_send_sg_s *)&txq->cmd[4];
956 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
957 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
958 send_hdr->w0.sizem1 = 1;
959 sg = (union nix_send_sg_s *)&txq->cmd[2];
962 send_hdr->w0.sq = txq->sq;
963 sg->subdc = NIX_SUBDC_SG;
965 sg->ld_type = NIX_SENDLDTYPE_LDD;
971 otx2_nix_tx_queue_release(void *_txq)
973 struct otx2_eth_txq *txq = _txq;
974 struct rte_eth_dev *eth_dev;
979 eth_dev = txq->dev->eth_dev;
981 otx2_nix_dbg("Releasing txq %u", txq->sq);
983 /* Flush and disable tm */
984 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
986 /* Free sqb's and disable sq */
990 rte_mempool_free(txq->sqb_pool);
991 txq->sqb_pool = NULL;
998 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
999 uint16_t nb_desc, unsigned int socket_id,
1000 const struct rte_eth_txconf *tx_conf)
1002 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1003 const struct rte_memzone *fc;
1004 struct otx2_eth_txq *txq;
1010 /* Compile time check to make sure all fast path elements in a CL */
1011 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
1013 if (tx_conf->tx_deferred_start) {
1014 otx2_err("Tx deferred start is not supported");
1018 /* Free memory prior to re-allocation if needed. */
1019 if (eth_dev->data->tx_queues[sq] != NULL) {
1020 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
1021 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
1022 eth_dev->data->tx_queues[sq] = NULL;
1025 /* Find the expected offloads for this queue */
1026 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
1028 /* Allocating tx queue data structure */
1029 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
1030 OTX2_ALIGN, socket_id);
1032 otx2_err("Failed to alloc txq=%d", sq);
1038 txq->sqb_pool = NULL;
1039 txq->offloads = offloads;
1040 dev->tx_offloads |= offloads;
1043 * Allocate memory for flow control updates from HW.
1044 * Alloc one cache line, so that fits all FC_STYPE modes.
1046 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
1047 OTX2_ALIGN + sizeof(struct npa_aura_s),
1048 OTX2_ALIGN, dev->node);
1050 otx2_err("Failed to allocate mem for fcmem");
1054 txq->fc_iova = fc->iova;
1055 txq->fc_mem = fc->addr;
1057 /* Initialize the aura sqb pool */
1058 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
1060 otx2_err("Failed to alloc sqe pool rc=%d", rc);
1064 /* Initialize the SQ */
1065 rc = nix_sq_init(txq);
1067 otx2_err("Failed to init sq=%d context", sq);
1071 txq->fc_cache_pkts = 0;
1072 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
1073 /* Evenly distribute LMT slot for each sq */
1074 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1076 txq->qconf.socket_id = socket_id;
1077 txq->qconf.nb_desc = nb_desc;
1078 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1080 otx2_nix_form_default_desc(txq);
1082 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1083 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1084 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1085 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1086 eth_dev->data->tx_queues[sq] = txq;
1087 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1091 otx2_nix_tx_queue_release(txq);
1097 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1099 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1100 struct otx2_eth_qconf *tx_qconf = NULL;
1101 struct otx2_eth_qconf *rx_qconf = NULL;
1102 struct otx2_eth_txq **txq;
1103 struct otx2_eth_rxq **rxq;
1104 int i, nb_rxq, nb_txq;
1106 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1107 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1109 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1110 if (tx_qconf == NULL) {
1111 otx2_err("Failed to allocate memory for tx_qconf");
1115 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1116 if (rx_qconf == NULL) {
1117 otx2_err("Failed to allocate memory for rx_qconf");
1121 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1122 for (i = 0; i < nb_txq; i++) {
1123 if (txq[i] == NULL) {
1124 otx2_err("txq[%d] is already released", i);
1127 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1128 otx2_nix_tx_queue_release(txq[i]);
1129 eth_dev->data->tx_queues[i] = NULL;
1132 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1133 for (i = 0; i < nb_rxq; i++) {
1134 if (rxq[i] == NULL) {
1135 otx2_err("rxq[%d] is already released", i);
1138 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1139 otx2_nix_rx_queue_release(rxq[i]);
1140 eth_dev->data->rx_queues[i] = NULL;
1143 dev->tx_qconf = tx_qconf;
1144 dev->rx_qconf = rx_qconf;
1157 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1159 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1160 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1161 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1162 struct otx2_eth_txq **txq;
1163 struct otx2_eth_rxq **rxq;
1164 int rc, i, nb_rxq, nb_txq;
1166 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1167 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1170 /* Setup tx & rx queues with previous configuration so
1171 * that the queues can be functional in cases like ports
1172 * are started without re configuring queues.
1174 * Usual re config sequence is like below:
1175 * port_configure() {
1180 * queue_configure() {
1187 * In some application's control path, queue_configure() would
1188 * NOT be invoked for TXQs/RXQs in port_configure().
1189 * In such cases, queues can be functional after start as the
1190 * queues are already setup in port_configure().
1192 for (i = 0; i < nb_txq; i++) {
1193 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1194 tx_qconf[i].socket_id,
1195 &tx_qconf[i].conf.tx);
1197 otx2_err("Failed to setup tx queue rc=%d", rc);
1198 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1199 for (i -= 1; i >= 0; i--)
1200 otx2_nix_tx_queue_release(txq[i]);
1205 free(tx_qconf); tx_qconf = NULL;
1207 for (i = 0; i < nb_rxq; i++) {
1208 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1209 rx_qconf[i].socket_id,
1210 &rx_qconf[i].conf.rx,
1211 rx_qconf[i].mempool);
1213 otx2_err("Failed to setup rx queue rc=%d", rc);
1214 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1215 for (i -= 1; i >= 0; i--)
1216 otx2_nix_rx_queue_release(rxq[i]);
1217 goto release_tx_queues;
1221 free(rx_qconf); rx_qconf = NULL;
1226 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1227 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1228 otx2_nix_tx_queue_release(txq[i]);
1239 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1241 RTE_SET_USED(queue);
1242 RTE_SET_USED(mbufs);
1249 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1251 /* These dummy functions are required for supporting
1252 * some applications which reconfigure queues without
1253 * stopping tx burst and rx burst threads(eg kni app)
1254 * When the queues context is saved, txq/rxqs are released
1255 * which caused app crash since rx/tx burst is still
1256 * on different lcores
1258 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1259 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1264 nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)
1266 volatile struct nix_lso_format *field;
1268 /* Format works only with TCP packet marked by OL3/OL4 */
1269 field = (volatile struct nix_lso_format *)&req->fields[0];
1270 req->field_mask = NIX_LSO_FIELD_MASK;
1271 /* Outer IPv4/IPv6 */
1272 field->layer = NIX_TXLAYER_OL3;
1273 field->offset = v4 ? 2 : 4;
1274 field->sizem1 = 1; /* 2B */
1275 field->alg = NIX_LSOALG_ADD_PAYLEN;
1279 field->layer = NIX_TXLAYER_OL3;
1282 /* Incremented linearly per segment */
1283 field->alg = NIX_LSOALG_ADD_SEGNUM;
1287 /* TCP sequence number update */
1288 field->layer = NIX_TXLAYER_OL4;
1290 field->sizem1 = 3; /* 4 bytes */
1291 field->alg = NIX_LSOALG_ADD_OFFSET;
1293 /* TCP flags field */
1294 field->layer = NIX_TXLAYER_OL4;
1297 field->alg = NIX_LSOALG_TCP_FLAGS;
1302 nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req,
1303 bool outer_v4, bool inner_v4)
1305 volatile struct nix_lso_format *field;
1307 field = (volatile struct nix_lso_format *)&req->fields[0];
1308 req->field_mask = NIX_LSO_FIELD_MASK;
1309 /* Outer IPv4/IPv6 len */
1310 field->layer = NIX_TXLAYER_OL3;
1311 field->offset = outer_v4 ? 2 : 4;
1312 field->sizem1 = 1; /* 2B */
1313 field->alg = NIX_LSOALG_ADD_PAYLEN;
1317 field->layer = NIX_TXLAYER_OL3;
1320 /* Incremented linearly per segment */
1321 field->alg = NIX_LSOALG_ADD_SEGNUM;
1325 /* Outer UDP length */
1326 field->layer = NIX_TXLAYER_OL4;
1329 field->alg = NIX_LSOALG_ADD_PAYLEN;
1332 /* Inner IPv4/IPv6 */
1333 field->layer = NIX_TXLAYER_IL3;
1334 field->offset = inner_v4 ? 2 : 4;
1335 field->sizem1 = 1; /* 2B */
1336 field->alg = NIX_LSOALG_ADD_PAYLEN;
1340 field->layer = NIX_TXLAYER_IL3;
1343 /* Incremented linearly per segment */
1344 field->alg = NIX_LSOALG_ADD_SEGNUM;
1348 /* TCP sequence number update */
1349 field->layer = NIX_TXLAYER_IL4;
1351 field->sizem1 = 3; /* 4 bytes */
1352 field->alg = NIX_LSOALG_ADD_OFFSET;
1355 /* TCP flags field */
1356 field->layer = NIX_TXLAYER_IL4;
1359 field->alg = NIX_LSOALG_TCP_FLAGS;
1364 nix_lso_tun_tcp(struct nix_lso_format_cfg *req,
1365 bool outer_v4, bool inner_v4)
1367 volatile struct nix_lso_format *field;
1369 field = (volatile struct nix_lso_format *)&req->fields[0];
1370 req->field_mask = NIX_LSO_FIELD_MASK;
1371 /* Outer IPv4/IPv6 len */
1372 field->layer = NIX_TXLAYER_OL3;
1373 field->offset = outer_v4 ? 2 : 4;
1374 field->sizem1 = 1; /* 2B */
1375 field->alg = NIX_LSOALG_ADD_PAYLEN;
1379 field->layer = NIX_TXLAYER_OL3;
1382 /* Incremented linearly per segment */
1383 field->alg = NIX_LSOALG_ADD_SEGNUM;
1387 /* Inner IPv4/IPv6 */
1388 field->layer = NIX_TXLAYER_IL3;
1389 field->offset = inner_v4 ? 2 : 4;
1390 field->sizem1 = 1; /* 2B */
1391 field->alg = NIX_LSOALG_ADD_PAYLEN;
1395 field->layer = NIX_TXLAYER_IL3;
1398 /* Incremented linearly per segment */
1399 field->alg = NIX_LSOALG_ADD_SEGNUM;
1403 /* TCP sequence number update */
1404 field->layer = NIX_TXLAYER_IL4;
1406 field->sizem1 = 3; /* 4 bytes */
1407 field->alg = NIX_LSOALG_ADD_OFFSET;
1410 /* TCP flags field */
1411 field->layer = NIX_TXLAYER_IL4;
1414 field->alg = NIX_LSOALG_TCP_FLAGS;
1419 nix_setup_lso_formats(struct otx2_eth_dev *dev)
1421 struct otx2_mbox *mbox = dev->mbox;
1422 struct nix_lso_format_cfg_rsp *rsp;
1423 struct nix_lso_format_cfg *req;
1427 /* Skip if TSO was not requested */
1428 if (!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))
1433 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1434 nix_lso_tcp(req, true);
1435 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1439 base = rsp->lso_format_idx;
1440 if (base != NIX_LSO_FORMAT_IDX_TSOV4)
1442 dev->lso_base_idx = base;
1443 otx2_nix_dbg("tcpv4 lso fmt=%u", base);
1449 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1450 nix_lso_tcp(req, false);
1451 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1455 if (rsp->lso_format_idx != base + 1)
1457 otx2_nix_dbg("tcpv6 lso fmt=%u\n", base + 1);
1460 * IPv4/UDP/TUN HDR/IPv4/TCP LSO
1462 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1463 nix_lso_udp_tun_tcp(req, true, true);
1464 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1468 if (rsp->lso_format_idx != base + 2)
1470 otx2_nix_dbg("udp tun v4v4 fmt=%u\n", base + 2);
1473 * IPv4/UDP/TUN HDR/IPv6/TCP LSO
1475 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1476 nix_lso_udp_tun_tcp(req, true, false);
1477 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1481 if (rsp->lso_format_idx != base + 3)
1483 otx2_nix_dbg("udp tun v4v6 fmt=%u\n", base + 3);
1486 * IPv6/UDP/TUN HDR/IPv4/TCP LSO
1488 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1489 nix_lso_udp_tun_tcp(req, false, true);
1490 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1494 if (rsp->lso_format_idx != base + 4)
1496 otx2_nix_dbg("udp tun v6v4 fmt=%u\n", base + 4);
1499 * IPv6/UDP/TUN HDR/IPv6/TCP LSO
1501 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1502 nix_lso_udp_tun_tcp(req, false, false);
1503 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1506 if (rsp->lso_format_idx != base + 5)
1508 otx2_nix_dbg("udp tun v6v6 fmt=%u\n", base + 5);
1511 * IPv4/TUN HDR/IPv4/TCP LSO
1513 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1514 nix_lso_tun_tcp(req, true, true);
1515 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1519 if (rsp->lso_format_idx != base + 6)
1521 otx2_nix_dbg("tun v4v4 fmt=%u\n", base + 6);
1524 * IPv4/TUN HDR/IPv6/TCP LSO
1526 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1527 nix_lso_tun_tcp(req, true, false);
1528 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1532 if (rsp->lso_format_idx != base + 7)
1534 otx2_nix_dbg("tun v4v6 fmt=%u\n", base + 7);
1537 * IPv6/TUN HDR/IPv4/TCP LSO
1539 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1540 nix_lso_tun_tcp(req, false, true);
1541 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1545 if (rsp->lso_format_idx != base + 8)
1547 otx2_nix_dbg("tun v6v4 fmt=%u\n", base + 8);
1550 * IPv6/TUN HDR/IPv6/TCP LSO
1552 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1553 nix_lso_tun_tcp(req, false, false);
1554 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1557 if (rsp->lso_format_idx != base + 9)
1559 otx2_nix_dbg("tun v6v6 fmt=%u\n", base + 9);
1564 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1566 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1567 struct rte_eth_dev_data *data = eth_dev->data;
1568 struct rte_eth_conf *conf = &data->dev_conf;
1569 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1570 struct rte_eth_txmode *txmode = &conf->txmode;
1571 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1572 struct rte_ether_addr *ea;
1573 uint8_t nb_rxq, nb_txq;
1579 if (rte_eal_has_hugepages() == 0) {
1580 otx2_err("Huge page is not configured");
1581 goto fail_configure;
1584 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1585 otx2_err("Setting link speed/duplex not supported");
1586 goto fail_configure;
1589 if (conf->dcb_capability_en == 1) {
1590 otx2_err("dcb enable is not supported");
1591 goto fail_configure;
1594 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1595 otx2_err("Flow director is not supported");
1596 goto fail_configure;
1599 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1600 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1601 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1602 goto fail_configure;
1605 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1606 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1607 goto fail_configure;
1610 if (otx2_dev_is_Ax(dev) &&
1611 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1612 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1613 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1614 otx2_err("Outer IP and SCTP checksum unsupported");
1615 goto fail_configure;
1618 /* Free the resources allocated from the previous configure */
1619 if (dev->configured == 1) {
1620 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1621 otx2_nix_vlan_fini(eth_dev);
1622 otx2_nix_mc_addr_list_uninstall(eth_dev);
1623 otx2_flow_free_all_resources(dev);
1624 oxt2_nix_unregister_queue_irqs(eth_dev);
1625 if (eth_dev->data->dev_conf.intr_conf.rxq)
1626 oxt2_nix_unregister_cq_irqs(eth_dev);
1627 nix_set_nop_rxtx_function(eth_dev);
1628 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1630 goto fail_configure;
1631 otx2_nix_tm_fini(eth_dev);
1635 dev->rx_offloads = rxmode->offloads;
1636 dev->tx_offloads = txmode->offloads;
1637 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1638 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1639 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1641 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1642 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1644 /* Alloc a nix lf */
1645 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1647 otx2_err("Failed to init nix_lf rc=%d", rc);
1652 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
1653 otx2_err("Both PTP and switch header enabled");
1657 rc = nix_lf_switch_header_type_enable(dev, true);
1659 otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
1663 rc = nix_setup_lso_formats(dev);
1665 otx2_err("failed to setup nix lso format fields, rc=%d", rc);
1670 rc = otx2_nix_rss_config(eth_dev);
1672 otx2_err("Failed to configure rss rc=%d", rc);
1676 /* Init the default TM scheduler hierarchy */
1677 rc = otx2_nix_tm_init_default(eth_dev);
1679 otx2_err("Failed to init traffic manager rc=%d", rc);
1683 rc = otx2_nix_vlan_offload_init(eth_dev);
1685 otx2_err("Failed to init vlan offload rc=%d", rc);
1689 /* Register queue IRQs */
1690 rc = oxt2_nix_register_queue_irqs(eth_dev);
1692 otx2_err("Failed to register queue interrupts rc=%d", rc);
1696 /* Register cq IRQs */
1697 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1698 if (eth_dev->data->nb_rx_queues > dev->cints) {
1699 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1703 /* Rx interrupt feature cannot work with vector mode because,
1704 * vector mode doesn't process packets unless min 4 pkts are
1705 * received, while cq interrupts are generated even for 1 pkt
1708 dev->scalar_ena = true;
1710 rc = oxt2_nix_register_cq_irqs(eth_dev);
1712 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1717 /* Configure loop back mode */
1718 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1720 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1724 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1726 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1730 rc = otx2_nix_mc_addr_list_install(eth_dev);
1732 otx2_err("Failed to install mc address list rc=%d", rc);
1737 * Restore queue config when reconfigure followed by
1738 * reconfigure and no queue configure invoked from application case.
1740 if (dev->configured == 1) {
1741 rc = nix_restore_queue_cfg(eth_dev);
1743 goto uninstall_mc_list;
1746 /* Update the mac address */
1747 ea = eth_dev->data->mac_addrs;
1748 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1749 if (rte_is_zero_ether_addr(ea))
1750 rte_eth_random_addr((uint8_t *)ea);
1752 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1754 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1755 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1756 " rx_flags=0x%x tx_flags=0x%x",
1757 eth_dev->data->port_id, ea_fmt, nb_rxq,
1758 nb_txq, dev->rx_offloads, dev->tx_offloads,
1759 dev->rx_offload_flags, dev->tx_offload_flags);
1762 dev->configured = 1;
1763 dev->configured_nb_rx_qs = data->nb_rx_queues;
1764 dev->configured_nb_tx_qs = data->nb_tx_queues;
1768 otx2_nix_mc_addr_list_uninstall(eth_dev);
1770 oxt2_nix_unregister_cq_irqs(eth_dev);
1772 oxt2_nix_unregister_queue_irqs(eth_dev);
1774 otx2_nix_vlan_fini(eth_dev);
1776 otx2_nix_tm_fini(eth_dev);
1780 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
1781 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
1783 dev->configured = 0;
1788 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1790 struct rte_eth_dev_data *data = eth_dev->data;
1791 struct otx2_eth_txq *txq;
1794 txq = eth_dev->data->tx_queues[qidx];
1796 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1799 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1801 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1806 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1813 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1815 struct rte_eth_dev_data *data = eth_dev->data;
1816 struct otx2_eth_txq *txq;
1819 txq = eth_dev->data->tx_queues[qidx];
1821 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1824 txq->fc_cache_pkts = 0;
1826 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1828 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1833 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1840 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1842 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1843 struct rte_eth_dev_data *data = eth_dev->data;
1846 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1849 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1851 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1855 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1862 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1864 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1865 struct rte_eth_dev_data *data = eth_dev->data;
1868 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1871 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1873 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1877 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1884 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
1886 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1887 struct rte_mbuf *rx_pkts[32];
1888 struct otx2_eth_rxq *rxq;
1889 int count, i, j, rc;
1891 nix_lf_switch_header_type_enable(dev, false);
1892 nix_cgx_stop_link_event(dev);
1893 npc_rx_disable(dev);
1895 /* Stop rx queues and free up pkts pending */
1896 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1897 rc = otx2_nix_rx_queue_stop(eth_dev, i);
1901 rxq = eth_dev->data->rx_queues[i];
1902 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1904 for (j = 0; j < count; j++)
1905 rte_pktmbuf_free(rx_pkts[j]);
1906 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1910 /* Stop tx queues */
1911 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1912 otx2_nix_tx_queue_stop(eth_dev, i);
1916 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
1918 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1921 /* MTU recalculate should be avoided here if PTP is enabled by PF, as
1922 * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
1925 if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
1926 rc = otx2_nix_recalc_mtu(eth_dev);
1931 /* Start rx queues */
1932 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1933 rc = otx2_nix_rx_queue_start(eth_dev, i);
1938 /* Start tx queues */
1939 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1940 rc = otx2_nix_tx_queue_start(eth_dev, i);
1945 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
1947 otx2_err("Failed to update flow ctrl mode %d", rc);
1951 /* Enable PTP if it was requested by the app or if it is already
1952 * enabled in PF owning this VF
1954 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
1955 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
1956 otx2_ethdev_is_ptp_en(dev))
1957 otx2_nix_timesync_enable(eth_dev);
1959 otx2_nix_timesync_disable(eth_dev);
1961 /* Update VF about data off shifted by 8 bytes if PTP already
1962 * enabled in PF owning this VF
1964 if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
1965 otx2_nix_ptp_enable_vf(eth_dev);
1967 rc = npc_rx_enable(dev);
1969 otx2_err("Failed to enable NPC rx %d", rc);
1973 otx2_nix_toggle_flag_link_cfg(dev, true);
1975 rc = nix_cgx_start_link_event(dev);
1977 otx2_err("Failed to start cgx link event %d", rc);
1981 otx2_nix_toggle_flag_link_cfg(dev, false);
1982 otx2_eth_set_tx_function(eth_dev);
1983 otx2_eth_set_rx_function(eth_dev);
1988 npc_rx_disable(dev);
1989 otx2_nix_toggle_flag_link_cfg(dev, false);
1993 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
1994 static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
1996 /* Initialize and register driver with DPDK Application */
1997 static const struct eth_dev_ops otx2_eth_dev_ops = {
1998 .dev_infos_get = otx2_nix_info_get,
1999 .dev_configure = otx2_nix_configure,
2000 .link_update = otx2_nix_link_update,
2001 .tx_queue_setup = otx2_nix_tx_queue_setup,
2002 .tx_queue_release = otx2_nix_tx_queue_release,
2003 .rx_queue_setup = otx2_nix_rx_queue_setup,
2004 .rx_queue_release = otx2_nix_rx_queue_release,
2005 .dev_start = otx2_nix_dev_start,
2006 .dev_stop = otx2_nix_dev_stop,
2007 .dev_close = otx2_nix_dev_close,
2008 .tx_queue_start = otx2_nix_tx_queue_start,
2009 .tx_queue_stop = otx2_nix_tx_queue_stop,
2010 .rx_queue_start = otx2_nix_rx_queue_start,
2011 .rx_queue_stop = otx2_nix_rx_queue_stop,
2012 .dev_set_link_up = otx2_nix_dev_set_link_up,
2013 .dev_set_link_down = otx2_nix_dev_set_link_down,
2014 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
2015 .dev_ptypes_set = otx2_nix_ptypes_set,
2016 .dev_reset = otx2_nix_dev_reset,
2017 .stats_get = otx2_nix_dev_stats_get,
2018 .stats_reset = otx2_nix_dev_stats_reset,
2019 .get_reg = otx2_nix_dev_get_reg,
2020 .mtu_set = otx2_nix_mtu_set,
2021 .mac_addr_add = otx2_nix_mac_addr_add,
2022 .mac_addr_remove = otx2_nix_mac_addr_del,
2023 .mac_addr_set = otx2_nix_mac_addr_set,
2024 .set_mc_addr_list = otx2_nix_set_mc_addr_list,
2025 .promiscuous_enable = otx2_nix_promisc_enable,
2026 .promiscuous_disable = otx2_nix_promisc_disable,
2027 .allmulticast_enable = otx2_nix_allmulticast_enable,
2028 .allmulticast_disable = otx2_nix_allmulticast_disable,
2029 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
2030 .reta_update = otx2_nix_dev_reta_update,
2031 .reta_query = otx2_nix_dev_reta_query,
2032 .rss_hash_update = otx2_nix_rss_hash_update,
2033 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
2034 .xstats_get = otx2_nix_xstats_get,
2035 .xstats_get_names = otx2_nix_xstats_get_names,
2036 .xstats_reset = otx2_nix_xstats_reset,
2037 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
2038 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
2039 .rxq_info_get = otx2_nix_rxq_info_get,
2040 .txq_info_get = otx2_nix_txq_info_get,
2041 .rx_burst_mode_get = otx2_rx_burst_mode_get,
2042 .tx_burst_mode_get = otx2_tx_burst_mode_get,
2043 .rx_queue_count = otx2_nix_rx_queue_count,
2044 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
2045 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
2046 .tx_descriptor_status = otx2_nix_tx_descriptor_status,
2047 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
2048 .pool_ops_supported = otx2_nix_pool_ops_supported,
2049 .filter_ctrl = otx2_nix_dev_filter_ctrl,
2050 .get_module_info = otx2_nix_get_module_info,
2051 .get_module_eeprom = otx2_nix_get_module_eeprom,
2052 .fw_version_get = otx2_nix_fw_version_get,
2053 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
2054 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
2055 .timesync_enable = otx2_nix_timesync_enable,
2056 .timesync_disable = otx2_nix_timesync_disable,
2057 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
2058 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
2059 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
2060 .timesync_read_time = otx2_nix_timesync_read_time,
2061 .timesync_write_time = otx2_nix_timesync_write_time,
2062 .vlan_offload_set = otx2_nix_vlan_offload_set,
2063 .vlan_filter_set = otx2_nix_vlan_filter_set,
2064 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
2065 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
2066 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
2067 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
2068 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
2069 .read_clock = otx2_nix_read_clock,
2073 nix_lf_attach(struct otx2_eth_dev *dev)
2075 struct otx2_mbox *mbox = dev->mbox;
2076 struct rsrc_attach_req *req;
2078 /* Attach NIX(lf) */
2079 req = otx2_mbox_alloc_msg_attach_resources(mbox);
2083 return otx2_mbox_process(mbox);
2087 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
2089 struct otx2_mbox *mbox = dev->mbox;
2090 struct msix_offset_rsp *msix_rsp;
2093 /* Get NPA and NIX MSIX vector offsets */
2094 otx2_mbox_alloc_msg_msix_offset(mbox);
2096 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
2098 dev->nix_msixoff = msix_rsp->nix_msixoff;
2104 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
2106 struct rsrc_detach_req *req;
2108 req = otx2_mbox_alloc_msg_detach_resources(mbox);
2110 /* Detach all except npa lf */
2111 req->partial = true;
2118 return otx2_mbox_process(mbox);
2122 otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
2124 if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
2125 pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2131 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
2133 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2134 struct rte_pci_device *pci_dev;
2135 int rc, max_entries;
2137 eth_dev->dev_ops = &otx2_eth_dev_ops;
2139 /* For secondary processes, the primary has done all the work */
2140 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2141 /* Setup callbacks for secondary process */
2142 otx2_eth_set_tx_function(eth_dev);
2143 otx2_eth_set_rx_function(eth_dev);
2147 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2149 rte_eth_copy_pci_info(eth_dev, pci_dev);
2150 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2152 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
2153 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
2154 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
2156 /* Parse devargs string */
2157 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
2159 otx2_err("Failed to parse devargs rc=%d", rc);
2163 if (!dev->mbox_active) {
2164 /* Initialize the base otx2_dev object
2165 * only if already present
2167 rc = otx2_dev_init(pci_dev, dev);
2169 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
2173 if (otx2_eth_dev_is_sdp(pci_dev))
2174 dev->sdp_link = true;
2176 dev->sdp_link = false;
2177 /* Device generic callbacks */
2178 dev->ops = &otx2_dev_ops;
2179 dev->eth_dev = eth_dev;
2181 /* Grab the NPA LF if required */
2182 rc = otx2_npa_lf_init(pci_dev, dev);
2184 goto otx2_dev_uninit;
2186 dev->configured = 0;
2187 dev->drv_inited = true;
2188 dev->ptype_disable = 0;
2189 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
2190 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
2193 rc = nix_lf_attach(dev);
2195 goto otx2_npa_uninit;
2197 /* Get NIX MSIX offset */
2198 rc = nix_lf_get_msix_offset(dev);
2200 goto otx2_npa_uninit;
2202 /* Register LF irq handlers */
2203 rc = otx2_nix_register_irqs(eth_dev);
2207 /* Get maximum number of supported MAC entries */
2208 max_entries = otx2_cgx_mac_max_entries_get(dev);
2209 if (max_entries < 0) {
2210 otx2_err("Failed to get max entries for mac addr");
2212 goto unregister_irq;
2215 /* For VFs, returned max_entries will be 0. But to keep default MAC
2216 * address, one entry must be allocated. So setting up to 1.
2218 if (max_entries == 0)
2221 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
2222 RTE_ETHER_ADDR_LEN, 0);
2223 if (eth_dev->data->mac_addrs == NULL) {
2224 otx2_err("Failed to allocate memory for mac addr");
2226 goto unregister_irq;
2229 dev->max_mac_entries = max_entries;
2231 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
2233 goto free_mac_addrs;
2235 /* Update the mac address */
2236 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2238 /* Also sync same MAC address to CGX table */
2239 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
2241 /* Initialize the tm data structures */
2242 otx2_nix_tm_conf_init(eth_dev);
2244 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
2245 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
2247 if (otx2_dev_is_96xx_A0(dev) ||
2248 otx2_dev_is_95xx_Ax(dev)) {
2249 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
2250 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
2253 /* Initialize rte-flow */
2254 rc = otx2_flow_init(dev);
2256 goto free_mac_addrs;
2258 otx2_nix_mc_filter_init(dev);
2260 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
2261 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
2262 eth_dev->data->port_id, dev->pf, dev->vf,
2263 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
2264 dev->rx_offload_capa, dev->tx_offload_capa);
2268 rte_free(eth_dev->data->mac_addrs);
2270 otx2_nix_unregister_irqs(eth_dev);
2272 otx2_eth_dev_lf_detach(dev->mbox);
2276 otx2_dev_fini(pci_dev, dev);
2278 otx2_err("Failed to init nix eth_dev rc=%d", rc);
2283 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
2285 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2286 struct rte_pci_device *pci_dev;
2289 /* Nothing to be done for secondary processes */
2290 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2293 /* Clear the flag since we are closing down */
2294 dev->configured = 0;
2296 /* Disable nix bpid config */
2297 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
2299 npc_rx_disable(dev);
2301 /* Disable vlan offloads */
2302 otx2_nix_vlan_fini(eth_dev);
2304 /* Disable other rte_flow entries */
2305 otx2_flow_fini(dev);
2307 /* Free multicast filter list */
2308 otx2_nix_mc_filter_fini(dev);
2310 /* Disable PTP if already enabled */
2311 if (otx2_ethdev_is_ptp_en(dev))
2312 otx2_nix_timesync_disable(eth_dev);
2314 nix_cgx_stop_link_event(dev);
2317 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2318 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
2319 eth_dev->data->tx_queues[i] = NULL;
2321 eth_dev->data->nb_tx_queues = 0;
2323 /* Free up RQ's and CQ's */
2324 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2325 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
2326 eth_dev->data->rx_queues[i] = NULL;
2328 eth_dev->data->nb_rx_queues = 0;
2330 /* Free tm resources */
2331 rc = otx2_nix_tm_fini(eth_dev);
2333 otx2_err("Failed to cleanup tm, rc=%d", rc);
2335 /* Unregister queue irqs */
2336 oxt2_nix_unregister_queue_irqs(eth_dev);
2338 /* Unregister cq irqs */
2339 if (eth_dev->data->dev_conf.intr_conf.rxq)
2340 oxt2_nix_unregister_cq_irqs(eth_dev);
2342 rc = nix_lf_free(dev);
2344 otx2_err("Failed to free nix lf, rc=%d", rc);
2346 rc = otx2_npa_lf_fini();
2348 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
2350 rte_free(eth_dev->data->mac_addrs);
2351 eth_dev->data->mac_addrs = NULL;
2352 dev->drv_inited = false;
2354 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2355 otx2_nix_unregister_irqs(eth_dev);
2357 rc = otx2_eth_dev_lf_detach(dev->mbox);
2359 otx2_err("Failed to detach resources, rc=%d", rc);
2361 /* Check if mbox close is needed */
2365 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
2366 /* Will be freed later by PMD */
2367 eth_dev->data->dev_private = NULL;
2371 otx2_dev_fini(pci_dev, dev);
2376 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
2378 otx2_eth_dev_uninit(eth_dev, true);
2382 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
2386 rc = otx2_eth_dev_uninit(eth_dev, false);
2390 return otx2_eth_dev_init(eth_dev);
2394 nix_remove(struct rte_pci_device *pci_dev)
2396 struct rte_eth_dev *eth_dev;
2397 struct otx2_idev_cfg *idev;
2398 struct otx2_dev *otx2_dev;
2401 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
2403 /* Cleanup eth dev */
2404 rc = otx2_eth_dev_uninit(eth_dev, true);
2408 rte_eth_dev_pci_release(eth_dev);
2411 /* Nothing to be done for secondary processes */
2412 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2415 /* Check for common resources */
2416 idev = otx2_intra_dev_get_cfg();
2417 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
2420 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
2422 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
2425 /* Safe to cleanup mbox as no more users */
2426 otx2_dev_fini(pci_dev, otx2_dev);
2431 otx2_info("%s: common resource in use by other devices", pci_dev->name);
2436 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2440 RTE_SET_USED(pci_drv);
2442 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2445 /* On error on secondary, recheck if port exists in primary or
2446 * in mid of detach state.
2448 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2449 if (!rte_eth_dev_allocated(pci_dev->device.name))
2454 static const struct rte_pci_id pci_nix_map[] = {
2456 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2459 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2462 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2463 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2466 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2467 PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
2470 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2471 PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2478 static struct rte_pci_driver pci_nix = {
2479 .id_table = pci_nix_map,
2480 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2481 RTE_PCI_DRV_INTR_LSC,
2483 .remove = nix_remove,
2486 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2487 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2488 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");