1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include <rte_ethdev_pci.h>
10 #include <rte_malloc.h>
12 #include <rte_mbuf_pool_ops.h>
13 #include <rte_mempool.h>
15 #include "otx2_ethdev.h"
18 otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev)
20 RTE_SET_USED(eth_dev);
24 otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)
26 RTE_SET_USED(eth_dev);
29 static inline uint64_t
30 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
32 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
34 if (otx2_dev_is_vf(dev))
35 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
40 static inline uint64_t
41 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
45 return NIX_TX_OFFLOAD_CAPA;
48 static const struct otx2_dev_ops otx2_dev_ops = {
49 .link_status_update = otx2_eth_dev_link_status_update,
53 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
55 struct otx2_mbox *mbox = dev->mbox;
56 struct nix_lf_alloc_req *req;
57 struct nix_lf_alloc_rsp *rsp;
60 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
64 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
65 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
66 req->xqe_sz = NIX_XQESZ_W16;
67 req->rss_sz = dev->rss_info.rss_size;
68 req->rss_grps = NIX_RSS_GRPS;
69 req->npa_func = otx2_npa_pf_func_get();
70 req->sso_func = otx2_sso_pf_func_get();
71 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
72 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
73 DEV_RX_OFFLOAD_UDP_CKSUM)) {
74 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
75 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
78 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
82 dev->sqb_size = rsp->sqb_size;
83 dev->tx_chan_base = rsp->tx_chan_base;
84 dev->rx_chan_base = rsp->rx_chan_base;
85 dev->rx_chan_cnt = rsp->rx_chan_cnt;
86 dev->tx_chan_cnt = rsp->tx_chan_cnt;
87 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
88 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
89 dev->lf_tx_stats = rsp->lf_tx_stats;
90 dev->lf_rx_stats = rsp->lf_rx_stats;
91 dev->cints = rsp->cints;
92 dev->qints = rsp->qints;
93 dev->npc_flow.channel = dev->rx_chan_base;
99 nix_lf_free(struct otx2_eth_dev *dev)
101 struct otx2_mbox *mbox = dev->mbox;
102 struct nix_lf_free_req *req;
103 struct ndc_sync_op *ndc_req;
106 /* Sync NDC-NIX for LF */
107 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
108 ndc_req->nix_lf_tx_sync = 1;
109 ndc_req->nix_lf_rx_sync = 1;
110 rc = otx2_mbox_process(mbox);
112 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
114 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
115 /* Let AF driver free all this nix lf's
116 * NPC entries allocated using NPC MBOX.
120 return otx2_mbox_process(mbox);
124 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
126 struct otx2_mbox *mbox = dev->mbox;
128 if (otx2_dev_is_vf(dev))
131 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
133 return otx2_mbox_process(mbox);
137 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
139 struct otx2_mbox *mbox = dev->mbox;
141 if (otx2_dev_is_vf(dev))
144 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
146 return otx2_mbox_process(mbox);
150 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
156 static inline uint32_t
157 nix_qsize_to_val(enum nix_q_size_e qsize)
159 return (16UL << (qsize * 2));
162 static inline enum nix_q_size_e
163 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
167 if (otx2_ethdev_fixup_is_min_4k_q(dev))
172 for (; i < nix_q_size_max; i++)
173 if (val <= nix_qsize_to_val(i))
176 if (i >= nix_q_size_max)
177 i = nix_q_size_max - 1;
183 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
184 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
186 struct otx2_mbox *mbox = dev->mbox;
187 const struct rte_memzone *rz;
188 uint32_t ring_size, cq_size;
189 struct nix_aq_enq_req *aq;
194 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
195 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
196 NIX_CQ_ALIGN, dev->node);
198 otx2_err("Failed to allocate mem for cq hw ring");
202 memset(rz->addr, 0, rz->len);
203 rxq->desc = (uintptr_t)rz->addr;
204 rxq->qmask = cq_size - 1;
206 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
208 aq->ctype = NIX_AQ_CTYPE_CQ;
209 aq->op = NIX_AQ_INSTOP_INIT;
213 aq->cq.qsize = rxq->qsize;
214 aq->cq.base = rz->iova;
215 aq->cq.avg_level = 0xff;
216 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
217 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
219 /* TX pause frames enable flowctrl on RX side */
220 if (dev->fc_info.tx_pause) {
221 /* Single bpid is allocated for all rx channels for now */
222 aq->cq.bpid = dev->fc_info.bpid[0];
223 aq->cq.bp = NIX_CQ_BP_LEVEL;
227 /* Many to one reduction */
228 aq->cq.qint_idx = qid % dev->qints;
230 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
231 uint16_t min_rx_drop;
232 const float rx_cq_skid = 1024 * 256;
234 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
235 aq->cq.drop = min_rx_drop;
239 rc = otx2_mbox_process(mbox);
241 otx2_err("Failed to init cq context");
245 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
247 aq->ctype = NIX_AQ_CTYPE_RQ;
248 aq->op = NIX_AQ_INSTOP_INIT;
251 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
253 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
254 first_skip = (sizeof(struct rte_mbuf));
255 first_skip += RTE_PKTMBUF_HEADROOM;
256 first_skip += rte_pktmbuf_priv_size(mp);
257 rxq->data_off = first_skip;
259 first_skip /= 8; /* Expressed in number of dwords */
260 aq->rq.first_skip = first_skip;
261 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
262 aq->rq.flow_tagw = 32; /* 32-bits */
263 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
264 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
265 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
266 aq->rq.lpb_sizem1 /= 8;
267 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
269 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
270 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
271 aq->rq.rq_int_ena = 0;
272 /* Many to one reduction */
273 aq->rq.qint_idx = qid % dev->qints;
275 if (otx2_ethdev_fixup_is_limit_cq_full(dev))
276 aq->rq.xqe_drop_ena = 1;
278 rc = otx2_mbox_process(mbox);
280 otx2_err("Failed to init rq context");
290 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
291 struct otx2_eth_rxq *rxq, const bool enb)
293 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
294 struct otx2_mbox *mbox = dev->mbox;
295 struct nix_aq_enq_req *aq;
297 /* Pkts will be dropped silently if RQ is disabled */
298 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
300 aq->ctype = NIX_AQ_CTYPE_RQ;
301 aq->op = NIX_AQ_INSTOP_WRITE;
304 aq->rq_mask.ena = ~(aq->rq_mask.ena);
306 return otx2_mbox_process(mbox);
310 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
312 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
313 struct otx2_mbox *mbox = dev->mbox;
314 struct nix_aq_enq_req *aq;
317 /* RQ is already disabled */
319 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
321 aq->ctype = NIX_AQ_CTYPE_CQ;
322 aq->op = NIX_AQ_INSTOP_WRITE;
325 aq->cq_mask.ena = ~(aq->cq_mask.ena);
327 rc = otx2_mbox_process(mbox);
329 otx2_err("Failed to disable cq context");
337 nix_get_data_off(struct otx2_eth_dev *dev)
345 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
347 struct rte_mbuf mb_def;
350 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
351 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
352 offsetof(struct rte_mbuf, data_off) != 2);
353 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
354 offsetof(struct rte_mbuf, data_off) != 4);
355 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
356 offsetof(struct rte_mbuf, data_off) != 6);
358 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
359 mb_def.port = port_id;
360 rte_mbuf_refcnt_set(&mb_def, 1);
362 /* Prevent compiler reordering: rearm_data covers previous fields */
363 rte_compiler_barrier();
364 tmp = (uint64_t *)&mb_def.rearm_data;
370 otx2_nix_rx_queue_release(void *rx_queue)
372 struct otx2_eth_rxq *rxq = rx_queue;
377 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
378 nix_cq_rq_uninit(rxq->eth_dev, rxq);
383 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
384 uint16_t nb_desc, unsigned int socket,
385 const struct rte_eth_rxconf *rx_conf,
386 struct rte_mempool *mp)
388 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
389 struct rte_mempool_ops *ops;
390 struct otx2_eth_rxq *rxq;
391 const char *platform_ops;
392 enum nix_q_size_e qsize;
398 /* Compile time check to make sure all fast path elements in a CL */
399 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
402 if (rx_conf->rx_deferred_start == 1) {
403 otx2_err("Deferred Rx start is not supported");
407 platform_ops = rte_mbuf_platform_mempool_ops();
408 /* This driver needs octeontx2_npa mempool ops to work */
409 ops = rte_mempool_get_ops(mp->ops_index);
410 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
411 otx2_err("mempool ops should be of octeontx2_npa type");
415 if (mp->pool_id == 0) {
416 otx2_err("Invalid pool_id");
420 /* Free memory prior to re-allocation if needed */
421 if (eth_dev->data->rx_queues[rq] != NULL) {
422 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
423 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
424 eth_dev->data->rx_queues[rq] = NULL;
427 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
428 dev->rx_offloads |= offloads;
430 /* Find the CQ queue size */
431 qsize = nix_qsize_clampup_get(dev, nb_desc);
432 /* Allocate rxq memory */
433 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
435 otx2_err("Failed to allocate rq=%d", rq);
440 rxq->eth_dev = eth_dev;
442 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
443 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
444 rxq->wdata = (uint64_t)rq << 32;
445 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
446 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
447 eth_dev->data->port_id);
448 rxq->offloads = offloads;
450 rxq->qlen = nix_qsize_to_val(qsize);
452 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
454 /* Alloc completion queue */
455 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
457 otx2_err("Failed to allocate rxq=%u", rq);
461 rxq->qconf.socket_id = socket;
462 rxq->qconf.nb_desc = nb_desc;
463 rxq->qconf.mempool = mp;
464 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
466 nix_rx_queue_reset(rxq);
467 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
468 rq, mp->name, qsize, nb_desc, rxq->qlen);
470 eth_dev->data->rx_queues[rq] = rxq;
471 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
475 otx2_nix_rx_queue_release(rxq);
480 static inline uint8_t
481 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
484 * Maximum three segments can be supported with W8, Choose
485 * NIX_MAXSQESZ_W16 for multi segment offload.
487 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
488 return NIX_MAXSQESZ_W16;
490 return NIX_MAXSQESZ_W8;
494 nix_sq_init(struct otx2_eth_txq *txq)
496 struct otx2_eth_dev *dev = txq->dev;
497 struct otx2_mbox *mbox = dev->mbox;
498 struct nix_aq_enq_req *sq;
503 if (txq->sqb_pool->pool_id == 0)
506 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
508 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
512 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
514 sq->ctype = NIX_AQ_CTYPE_SQ;
515 sq->op = NIX_AQ_INSTOP_INIT;
516 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
519 sq->sq.smq_rr_quantum = rr_quantum;
520 sq->sq.default_chan = dev->tx_chan_base;
521 sq->sq.sqe_stype = NIX_STYPE_STF;
523 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
524 sq->sq.sqe_stype = NIX_STYPE_STP;
526 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
527 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
528 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
529 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
530 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
532 /* Many to one reduction */
533 sq->sq.qint_idx = txq->sq % dev->qints;
535 return otx2_mbox_process(mbox);
539 nix_sq_uninit(struct otx2_eth_txq *txq)
541 struct otx2_eth_dev *dev = txq->dev;
542 struct otx2_mbox *mbox = dev->mbox;
543 struct ndc_sync_op *ndc_req;
544 struct nix_aq_enq_rsp *rsp;
545 struct nix_aq_enq_req *aq;
546 uint16_t sqes_per_sqb;
550 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
552 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
554 aq->ctype = NIX_AQ_CTYPE_SQ;
555 aq->op = NIX_AQ_INSTOP_READ;
557 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
561 /* Check if sq is already cleaned up */
566 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
568 aq->ctype = NIX_AQ_CTYPE_SQ;
569 aq->op = NIX_AQ_INSTOP_WRITE;
571 aq->sq_mask.ena = ~aq->sq_mask.ena;
574 rc = otx2_mbox_process(mbox);
578 /* Read SQ and free sqb's */
579 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
581 aq->ctype = NIX_AQ_CTYPE_SQ;
582 aq->op = NIX_AQ_INSTOP_READ;
584 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
589 otx2_err("SQ has pending sqe's");
591 count = aq->sq.sqb_count;
592 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
593 /* Free SQB's that are used */
594 sqb_buf = (void *)rsp->sq.head_sqb;
598 next_sqb = *(void **)((uintptr_t)sqb_buf + ((sqes_per_sqb - 1) *
599 nix_sq_max_sqe_sz(txq)));
600 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
606 /* Free next to use sqb */
607 if (rsp->sq.next_sqb)
608 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
611 /* Sync NDC-NIX-TX for LF */
612 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
613 ndc_req->nix_lf_tx_sync = 1;
614 rc = otx2_mbox_process(mbox);
616 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
622 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
624 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
625 struct npa_aq_enq_req *aura_req;
627 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
628 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
629 aura_req->ctype = NPA_AQ_CTYPE_AURA;
630 aura_req->op = NPA_AQ_INSTOP_WRITE;
632 aura_req->aura.limit = nb_sqb_bufs;
633 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
635 return otx2_mbox_process(npa_lf->mbox);
639 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
641 struct otx2_eth_dev *dev = txq->dev;
642 uint16_t sqes_per_sqb, nb_sqb_bufs;
643 char name[RTE_MEMPOOL_NAMESIZE];
644 struct rte_mempool_objsz sz;
645 struct npa_aura_s *aura;
646 uint32_t tmp, blk_sz;
648 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
649 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
650 blk_sz = dev->sqb_size;
652 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
653 sqes_per_sqb = (dev->sqb_size / 8) / 16;
655 sqes_per_sqb = (dev->sqb_size / 8) / 8;
657 nb_sqb_bufs = nb_desc / sqes_per_sqb;
658 /* Clamp up to devarg passed SQB count */
659 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_MIN_SQB,
660 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
662 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
664 MEMPOOL_F_NO_SPREAD);
665 txq->nb_sqb_bufs = nb_sqb_bufs;
666 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
667 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
668 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
669 txq->nb_sqb_bufs_adj =
670 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
672 if (txq->sqb_pool == NULL) {
673 otx2_err("Failed to allocate sqe mempool");
677 memset(aura, 0, sizeof(*aura));
679 aura->fc_addr = txq->fc_iova;
680 aura->fc_hyst_bits = 0; /* Store count on all updates */
681 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
682 otx2_err("Failed to set ops for sqe mempool");
685 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
686 otx2_err("Failed to populate sqe mempool");
690 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
691 if (dev->sqb_size != sz.elt_size) {
692 otx2_err("sqe pool block size is not expected %d != %d",
697 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
705 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
707 struct nix_send_ext_s *send_hdr_ext;
708 struct nix_send_hdr_s *send_hdr;
709 struct nix_send_mem_s *send_mem;
710 union nix_send_sg_s *sg;
712 /* Initialize the fields based on basic single segment packet */
713 memset(&txq->cmd, 0, sizeof(txq->cmd));
715 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
716 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
717 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
718 send_hdr->w0.sizem1 = 2;
720 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
721 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
722 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
723 /* Default: one seg packet would have:
724 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
727 send_hdr->w0.sizem1 = 3;
728 send_hdr_ext->w0.tstmp = 1;
730 /* To calculate the offset for send_mem,
731 * send_hdr->w0.sizem1 * 2
733 send_mem = (struct nix_send_mem_s *)(txq->cmd +
734 (send_hdr->w0.sizem1 << 1));
735 send_mem->subdc = NIX_SUBDC_MEM;
737 send_mem->wmem = 0x1;
738 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
740 sg = (union nix_send_sg_s *)&txq->cmd[4];
742 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
743 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
744 send_hdr->w0.sizem1 = 1;
745 sg = (union nix_send_sg_s *)&txq->cmd[2];
748 send_hdr->w0.sq = txq->sq;
749 sg->subdc = NIX_SUBDC_SG;
751 sg->ld_type = NIX_SENDLDTYPE_LDD;
757 otx2_nix_tx_queue_release(void *_txq)
759 struct otx2_eth_txq *txq = _txq;
760 struct rte_eth_dev *eth_dev;
765 eth_dev = txq->dev->eth_dev;
767 otx2_nix_dbg("Releasing txq %u", txq->sq);
769 /* Flush and disable tm */
770 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
772 /* Free sqb's and disable sq */
776 rte_mempool_free(txq->sqb_pool);
777 txq->sqb_pool = NULL;
784 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
785 uint16_t nb_desc, unsigned int socket_id,
786 const struct rte_eth_txconf *tx_conf)
788 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
789 const struct rte_memzone *fc;
790 struct otx2_eth_txq *txq;
796 /* Compile time check to make sure all fast path elements in a CL */
797 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
799 if (tx_conf->tx_deferred_start) {
800 otx2_err("Tx deferred start is not supported");
804 /* Free memory prior to re-allocation if needed. */
805 if (eth_dev->data->tx_queues[sq] != NULL) {
806 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
807 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
808 eth_dev->data->tx_queues[sq] = NULL;
811 /* Find the expected offloads for this queue */
812 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
814 /* Allocating tx queue data structure */
815 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
816 OTX2_ALIGN, socket_id);
818 otx2_err("Failed to alloc txq=%d", sq);
824 txq->sqb_pool = NULL;
825 txq->offloads = offloads;
826 dev->tx_offloads |= offloads;
829 * Allocate memory for flow control updates from HW.
830 * Alloc one cache line, so that fits all FC_STYPE modes.
832 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
833 OTX2_ALIGN + sizeof(struct npa_aura_s),
834 OTX2_ALIGN, dev->node);
836 otx2_err("Failed to allocate mem for fcmem");
840 txq->fc_iova = fc->iova;
841 txq->fc_mem = fc->addr;
843 /* Initialize the aura sqb pool */
844 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
846 otx2_err("Failed to alloc sqe pool rc=%d", rc);
850 /* Initialize the SQ */
851 rc = nix_sq_init(txq);
853 otx2_err("Failed to init sq=%d context", sq);
857 txq->fc_cache_pkts = 0;
858 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
859 /* Evenly distribute LMT slot for each sq */
860 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
862 txq->qconf.socket_id = socket_id;
863 txq->qconf.nb_desc = nb_desc;
864 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
866 otx2_nix_form_default_desc(txq);
868 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
869 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
870 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
871 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
872 eth_dev->data->tx_queues[sq] = txq;
873 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
877 otx2_nix_tx_queue_release(txq);
883 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
885 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
886 struct otx2_eth_qconf *tx_qconf = NULL;
887 struct otx2_eth_qconf *rx_qconf = NULL;
888 struct otx2_eth_txq **txq;
889 struct otx2_eth_rxq **rxq;
890 int i, nb_rxq, nb_txq;
892 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
893 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
895 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
896 if (tx_qconf == NULL) {
897 otx2_err("Failed to allocate memory for tx_qconf");
901 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
902 if (rx_qconf == NULL) {
903 otx2_err("Failed to allocate memory for rx_qconf");
907 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
908 for (i = 0; i < nb_txq; i++) {
909 if (txq[i] == NULL) {
910 otx2_err("txq[%d] is already released", i);
913 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
914 otx2_nix_tx_queue_release(txq[i]);
915 eth_dev->data->tx_queues[i] = NULL;
918 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
919 for (i = 0; i < nb_rxq; i++) {
920 if (rxq[i] == NULL) {
921 otx2_err("rxq[%d] is already released", i);
924 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
925 otx2_nix_rx_queue_release(rxq[i]);
926 eth_dev->data->rx_queues[i] = NULL;
929 dev->tx_qconf = tx_qconf;
930 dev->rx_qconf = rx_qconf;
943 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
945 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
946 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
947 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
948 struct otx2_eth_txq **txq;
949 struct otx2_eth_rxq **rxq;
950 int rc, i, nb_rxq, nb_txq;
952 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
953 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
956 /* Setup tx & rx queues with previous configuration so
957 * that the queues can be functional in cases like ports
958 * are started without re configuring queues.
960 * Usual re config sequence is like below:
966 * queue_configure() {
973 * In some application's control path, queue_configure() would
974 * NOT be invoked for TXQs/RXQs in port_configure().
975 * In such cases, queues can be functional after start as the
976 * queues are already setup in port_configure().
978 for (i = 0; i < nb_txq; i++) {
979 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
980 tx_qconf[i].socket_id,
981 &tx_qconf[i].conf.tx);
983 otx2_err("Failed to setup tx queue rc=%d", rc);
984 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
985 for (i -= 1; i >= 0; i--)
986 otx2_nix_tx_queue_release(txq[i]);
991 free(tx_qconf); tx_qconf = NULL;
993 for (i = 0; i < nb_rxq; i++) {
994 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
995 rx_qconf[i].socket_id,
996 &rx_qconf[i].conf.rx,
997 rx_qconf[i].mempool);
999 otx2_err("Failed to setup rx queue rc=%d", rc);
1000 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1001 for (i -= 1; i >= 0; i--)
1002 otx2_nix_rx_queue_release(rxq[i]);
1003 goto release_tx_queues;
1007 free(rx_qconf); rx_qconf = NULL;
1012 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1013 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1014 otx2_nix_tx_queue_release(txq[i]);
1025 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1027 RTE_SET_USED(queue);
1028 RTE_SET_USED(mbufs);
1035 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1037 /* These dummy functions are required for supporting
1038 * some applications which reconfigure queues without
1039 * stopping tx burst and rx burst threads(eg kni app)
1040 * When the queues context is saved, txq/rxqs are released
1041 * which caused app crash since rx/tx burst is still
1042 * on different lcores
1044 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1045 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1050 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1052 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1053 struct rte_eth_dev_data *data = eth_dev->data;
1054 struct rte_eth_conf *conf = &data->dev_conf;
1055 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1056 struct rte_eth_txmode *txmode = &conf->txmode;
1057 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1058 struct rte_ether_addr *ea;
1059 uint8_t nb_rxq, nb_txq;
1065 if (rte_eal_has_hugepages() == 0) {
1066 otx2_err("Huge page is not configured");
1070 if (rte_eal_iova_mode() != RTE_IOVA_VA) {
1071 otx2_err("iova mode should be va");
1075 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1076 otx2_err("Setting link speed/duplex not supported");
1080 if (conf->dcb_capability_en == 1) {
1081 otx2_err("dcb enable is not supported");
1085 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1086 otx2_err("Flow director is not supported");
1090 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1091 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1092 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1096 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1097 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1101 /* Free the resources allocated from the previous configure */
1102 if (dev->configured == 1) {
1103 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1104 oxt2_nix_unregister_queue_irqs(eth_dev);
1105 nix_set_nop_rxtx_function(eth_dev);
1106 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1109 otx2_nix_tm_fini(eth_dev);
1113 if (otx2_dev_is_A0(dev) &&
1114 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1115 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1116 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1117 otx2_err("Outer IP and SCTP checksum unsupported");
1122 dev->rx_offloads = rxmode->offloads;
1123 dev->tx_offloads = txmode->offloads;
1124 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1126 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1127 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1129 /* Alloc a nix lf */
1130 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1132 otx2_err("Failed to init nix_lf rc=%d", rc);
1137 rc = otx2_nix_rss_config(eth_dev);
1139 otx2_err("Failed to configure rss rc=%d", rc);
1143 /* Init the default TM scheduler hierarchy */
1144 rc = otx2_nix_tm_init_default(eth_dev);
1146 otx2_err("Failed to init traffic manager rc=%d", rc);
1150 /* Register queue IRQs */
1151 rc = oxt2_nix_register_queue_irqs(eth_dev);
1153 otx2_err("Failed to register queue interrupts rc=%d", rc);
1157 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1159 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1164 * Restore queue config when reconfigure followed by
1165 * reconfigure and no queue configure invoked from application case.
1167 if (dev->configured == 1) {
1168 rc = nix_restore_queue_cfg(eth_dev);
1173 /* Update the mac address */
1174 ea = eth_dev->data->mac_addrs;
1175 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1176 if (rte_is_zero_ether_addr(ea))
1177 rte_eth_random_addr((uint8_t *)ea);
1179 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1181 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1182 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1183 " rx_flags=0x%x tx_flags=0x%x",
1184 eth_dev->data->port_id, ea_fmt, nb_rxq,
1185 nb_txq, dev->rx_offloads, dev->tx_offloads,
1186 dev->rx_offload_flags, dev->tx_offload_flags);
1189 dev->configured = 1;
1190 dev->configured_nb_rx_qs = data->nb_rx_queues;
1191 dev->configured_nb_tx_qs = data->nb_tx_queues;
1195 rc = nix_lf_free(dev);
1201 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1203 struct rte_eth_dev_data *data = eth_dev->data;
1204 struct otx2_eth_txq *txq;
1207 txq = eth_dev->data->tx_queues[qidx];
1209 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1212 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1214 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1219 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1226 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1228 struct rte_eth_dev_data *data = eth_dev->data;
1229 struct otx2_eth_txq *txq;
1232 txq = eth_dev->data->tx_queues[qidx];
1234 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1237 txq->fc_cache_pkts = 0;
1239 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1241 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1246 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1253 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1255 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1256 struct rte_eth_dev_data *data = eth_dev->data;
1259 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1262 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1264 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1268 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1275 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1277 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1278 struct rte_eth_dev_data *data = eth_dev->data;
1281 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1284 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1286 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1290 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1296 /* Initialize and register driver with DPDK Application */
1297 static const struct eth_dev_ops otx2_eth_dev_ops = {
1298 .dev_infos_get = otx2_nix_info_get,
1299 .dev_configure = otx2_nix_configure,
1300 .link_update = otx2_nix_link_update,
1301 .tx_queue_setup = otx2_nix_tx_queue_setup,
1302 .tx_queue_release = otx2_nix_tx_queue_release,
1303 .rx_queue_setup = otx2_nix_rx_queue_setup,
1304 .rx_queue_release = otx2_nix_rx_queue_release,
1305 .tx_queue_start = otx2_nix_tx_queue_start,
1306 .tx_queue_stop = otx2_nix_tx_queue_stop,
1307 .rx_queue_start = otx2_nix_rx_queue_start,
1308 .rx_queue_stop = otx2_nix_rx_queue_stop,
1309 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
1310 .stats_get = otx2_nix_dev_stats_get,
1311 .stats_reset = otx2_nix_dev_stats_reset,
1312 .get_reg = otx2_nix_dev_get_reg,
1313 .mac_addr_add = otx2_nix_mac_addr_add,
1314 .mac_addr_remove = otx2_nix_mac_addr_del,
1315 .mac_addr_set = otx2_nix_mac_addr_set,
1316 .promiscuous_enable = otx2_nix_promisc_enable,
1317 .promiscuous_disable = otx2_nix_promisc_disable,
1318 .allmulticast_enable = otx2_nix_allmulticast_enable,
1319 .allmulticast_disable = otx2_nix_allmulticast_disable,
1320 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
1321 .reta_update = otx2_nix_dev_reta_update,
1322 .reta_query = otx2_nix_dev_reta_query,
1323 .rss_hash_update = otx2_nix_rss_hash_update,
1324 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
1325 .xstats_get = otx2_nix_xstats_get,
1326 .xstats_get_names = otx2_nix_xstats_get_names,
1327 .xstats_reset = otx2_nix_xstats_reset,
1328 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
1329 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
1330 .rxq_info_get = otx2_nix_rxq_info_get,
1331 .txq_info_get = otx2_nix_txq_info_get,
1332 .rx_queue_count = otx2_nix_rx_queue_count,
1333 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
1334 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
1335 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
1336 .pool_ops_supported = otx2_nix_pool_ops_supported,
1337 .get_module_info = otx2_nix_get_module_info,
1338 .get_module_eeprom = otx2_nix_get_module_eeprom,
1339 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
1340 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
1344 nix_lf_attach(struct otx2_eth_dev *dev)
1346 struct otx2_mbox *mbox = dev->mbox;
1347 struct rsrc_attach_req *req;
1349 /* Attach NIX(lf) */
1350 req = otx2_mbox_alloc_msg_attach_resources(mbox);
1354 return otx2_mbox_process(mbox);
1358 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
1360 struct otx2_mbox *mbox = dev->mbox;
1361 struct msix_offset_rsp *msix_rsp;
1364 /* Get NPA and NIX MSIX vector offsets */
1365 otx2_mbox_alloc_msg_msix_offset(mbox);
1367 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
1369 dev->nix_msixoff = msix_rsp->nix_msixoff;
1375 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
1377 struct rsrc_detach_req *req;
1379 req = otx2_mbox_alloc_msg_detach_resources(mbox);
1381 /* Detach all except npa lf */
1382 req->partial = true;
1389 return otx2_mbox_process(mbox);
1393 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
1395 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1396 struct rte_pci_device *pci_dev;
1397 int rc, max_entries;
1399 eth_dev->dev_ops = &otx2_eth_dev_ops;
1401 /* For secondary processes, the primary has done all the work */
1402 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1403 /* Setup callbacks for secondary process */
1404 otx2_eth_set_tx_function(eth_dev);
1405 otx2_eth_set_rx_function(eth_dev);
1409 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1411 rte_eth_copy_pci_info(eth_dev, pci_dev);
1412 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1414 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
1415 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
1416 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
1418 /* Parse devargs string */
1419 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1421 otx2_err("Failed to parse devargs rc=%d", rc);
1425 if (!dev->mbox_active) {
1426 /* Initialize the base otx2_dev object
1427 * only if already present
1429 rc = otx2_dev_init(pci_dev, dev);
1431 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1435 /* Device generic callbacks */
1436 dev->ops = &otx2_dev_ops;
1437 dev->eth_dev = eth_dev;
1439 /* Grab the NPA LF if required */
1440 rc = otx2_npa_lf_init(pci_dev, dev);
1442 goto otx2_dev_uninit;
1444 dev->configured = 0;
1445 dev->drv_inited = true;
1446 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
1447 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
1450 rc = nix_lf_attach(dev);
1452 goto otx2_npa_uninit;
1454 /* Get NIX MSIX offset */
1455 rc = nix_lf_get_msix_offset(dev);
1457 goto otx2_npa_uninit;
1459 /* Register LF irq handlers */
1460 rc = otx2_nix_register_irqs(eth_dev);
1464 /* Get maximum number of supported MAC entries */
1465 max_entries = otx2_cgx_mac_max_entries_get(dev);
1466 if (max_entries < 0) {
1467 otx2_err("Failed to get max entries for mac addr");
1469 goto unregister_irq;
1472 /* For VFs, returned max_entries will be 0. But to keep default MAC
1473 * address, one entry must be allocated. So setting up to 1.
1475 if (max_entries == 0)
1478 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
1479 RTE_ETHER_ADDR_LEN, 0);
1480 if (eth_dev->data->mac_addrs == NULL) {
1481 otx2_err("Failed to allocate memory for mac addr");
1483 goto unregister_irq;
1486 dev->max_mac_entries = max_entries;
1488 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
1490 goto free_mac_addrs;
1492 /* Update the mac address */
1493 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1495 /* Also sync same MAC address to CGX table */
1496 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
1498 /* Initialize the tm data structures */
1499 otx2_nix_tm_conf_init(eth_dev);
1501 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1502 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1504 if (otx2_dev_is_A0(dev)) {
1505 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
1506 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
1509 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
1510 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1511 eth_dev->data->port_id, dev->pf, dev->vf,
1512 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
1513 dev->rx_offload_capa, dev->tx_offload_capa);
1517 rte_free(eth_dev->data->mac_addrs);
1519 otx2_nix_unregister_irqs(eth_dev);
1521 otx2_eth_dev_lf_detach(dev->mbox);
1525 otx2_dev_fini(pci_dev, dev);
1527 otx2_err("Failed to init nix eth_dev rc=%d", rc);
1532 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
1534 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1535 struct rte_pci_device *pci_dev;
1538 /* Nothing to be done for secondary processes */
1539 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1542 /* Disable nix bpid config */
1543 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1546 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1547 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
1548 eth_dev->data->tx_queues[i] = NULL;
1550 eth_dev->data->nb_tx_queues = 0;
1552 /* Free up RQ's and CQ's */
1553 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1554 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
1555 eth_dev->data->rx_queues[i] = NULL;
1557 eth_dev->data->nb_rx_queues = 0;
1559 /* Free tm resources */
1560 rc = otx2_nix_tm_fini(eth_dev);
1562 otx2_err("Failed to cleanup tm, rc=%d", rc);
1564 /* Unregister queue irqs */
1565 oxt2_nix_unregister_queue_irqs(eth_dev);
1567 rc = nix_lf_free(dev);
1569 otx2_err("Failed to free nix lf, rc=%d", rc);
1571 rc = otx2_npa_lf_fini();
1573 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
1575 rte_free(eth_dev->data->mac_addrs);
1576 eth_dev->data->mac_addrs = NULL;
1577 dev->drv_inited = false;
1579 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1580 otx2_nix_unregister_irqs(eth_dev);
1582 rc = otx2_eth_dev_lf_detach(dev->mbox);
1584 otx2_err("Failed to detach resources, rc=%d", rc);
1586 /* Check if mbox close is needed */
1590 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
1591 /* Will be freed later by PMD */
1592 eth_dev->data->dev_private = NULL;
1596 otx2_dev_fini(pci_dev, dev);
1601 nix_remove(struct rte_pci_device *pci_dev)
1603 struct rte_eth_dev *eth_dev;
1604 struct otx2_idev_cfg *idev;
1605 struct otx2_dev *otx2_dev;
1608 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1610 /* Cleanup eth dev */
1611 rc = otx2_eth_dev_uninit(eth_dev, true);
1615 rte_eth_dev_pci_release(eth_dev);
1618 /* Nothing to be done for secondary processes */
1619 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1622 /* Check for common resources */
1623 idev = otx2_intra_dev_get_cfg();
1624 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
1627 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
1629 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
1632 /* Safe to cleanup mbox as no more users */
1633 otx2_dev_fini(pci_dev, otx2_dev);
1638 otx2_info("%s: common resource in use by other devices", pci_dev->name);
1643 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1647 RTE_SET_USED(pci_drv);
1649 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
1652 /* On error on secondary, recheck if port exists in primary or
1653 * in mid of detach state.
1655 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1656 if (!rte_eth_dev_allocated(pci_dev->device.name))
1661 static const struct rte_pci_id pci_nix_map[] = {
1663 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
1666 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
1669 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1670 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
1677 static struct rte_pci_driver pci_nix = {
1678 .id_table = pci_nix_map,
1679 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA |
1680 RTE_PCI_DRV_INTR_LSC,
1682 .remove = nix_remove,
1685 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
1686 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
1687 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");