1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_ethdev_pci.h>
9 #include <rte_malloc.h>
11 #include <rte_mbuf_pool_ops.h>
12 #include <rte_mempool.h>
14 #include "otx2_ethdev.h"
16 static inline uint64_t
17 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
19 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
21 if (otx2_dev_is_vf(dev) ||
22 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
23 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
28 static inline uint64_t
29 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
31 uint64_t capa = NIX_TX_OFFLOAD_CAPA;
33 /* TSO not supported for earlier chip revisions */
34 if (otx2_dev_is_96xx_A0(dev) || otx2_dev_is_95xx_Ax(dev))
35 capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
36 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
37 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
38 DEV_TX_OFFLOAD_GRE_TNL_TSO);
42 static const struct otx2_dev_ops otx2_dev_ops = {
43 .link_status_update = otx2_eth_dev_link_status_update,
44 .ptp_info_update = otx2_eth_dev_ptp_info_update
48 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
50 struct otx2_mbox *mbox = dev->mbox;
51 struct nix_lf_alloc_req *req;
52 struct nix_lf_alloc_rsp *rsp;
55 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
59 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
60 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
61 req->xqe_sz = NIX_XQESZ_W16;
62 req->rss_sz = dev->rss_info.rss_size;
63 req->rss_grps = NIX_RSS_GRPS;
64 req->npa_func = otx2_npa_pf_func_get();
65 req->sso_func = otx2_sso_pf_func_get();
66 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
67 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
68 DEV_RX_OFFLOAD_UDP_CKSUM)) {
69 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
70 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
72 req->rx_cfg |= BIT_ULL(32 /* DROP_RE */);
74 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
78 dev->sqb_size = rsp->sqb_size;
79 dev->tx_chan_base = rsp->tx_chan_base;
80 dev->rx_chan_base = rsp->rx_chan_base;
81 dev->rx_chan_cnt = rsp->rx_chan_cnt;
82 dev->tx_chan_cnt = rsp->tx_chan_cnt;
83 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
84 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
85 dev->lf_tx_stats = rsp->lf_tx_stats;
86 dev->lf_rx_stats = rsp->lf_rx_stats;
87 dev->cints = rsp->cints;
88 dev->qints = rsp->qints;
89 dev->npc_flow.channel = dev->rx_chan_base;
90 dev->ptp_en = rsp->hw_rx_tstamp_en;
96 nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev)
98 struct otx2_mbox *mbox = dev->mbox;
99 struct npc_set_pkind *req;
100 struct msg_resp *rsp;
103 if (dev->npc_flow.switch_header_type == 0)
106 /* Notify AF about higig2 config */
107 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
108 req->mode = dev->npc_flow.switch_header_type;
110 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
113 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
114 req->mode = dev->npc_flow.switch_header_type;
116 return otx2_mbox_process_msg(mbox, (void *)&rsp);
120 nix_lf_free(struct otx2_eth_dev *dev)
122 struct otx2_mbox *mbox = dev->mbox;
123 struct nix_lf_free_req *req;
124 struct ndc_sync_op *ndc_req;
127 /* Sync NDC-NIX for LF */
128 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
129 ndc_req->nix_lf_tx_sync = 1;
130 ndc_req->nix_lf_rx_sync = 1;
131 rc = otx2_mbox_process(mbox);
133 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
135 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
136 /* Let AF driver free all this nix lf's
137 * NPC entries allocated using NPC MBOX.
141 return otx2_mbox_process(mbox);
145 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
147 struct otx2_mbox *mbox = dev->mbox;
149 if (otx2_dev_is_vf_or_sdp(dev))
152 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
154 return otx2_mbox_process(mbox);
158 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
160 struct otx2_mbox *mbox = dev->mbox;
162 if (otx2_dev_is_vf_or_sdp(dev))
165 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
167 return otx2_mbox_process(mbox);
171 npc_rx_enable(struct otx2_eth_dev *dev)
173 struct otx2_mbox *mbox = dev->mbox;
175 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
177 return otx2_mbox_process(mbox);
181 npc_rx_disable(struct otx2_eth_dev *dev)
183 struct otx2_mbox *mbox = dev->mbox;
185 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
187 return otx2_mbox_process(mbox);
191 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
193 struct otx2_mbox *mbox = dev->mbox;
195 if (otx2_dev_is_vf_or_sdp(dev))
198 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
200 return otx2_mbox_process(mbox);
204 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
206 struct otx2_mbox *mbox = dev->mbox;
208 if (en && otx2_dev_is_vf_or_sdp(dev))
212 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
214 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
216 return otx2_mbox_process(mbox);
220 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
222 struct otx2_mbox *mbox = dev->mbox;
224 if (otx2_dev_is_vf_or_sdp(dev))
227 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
229 return otx2_mbox_process(mbox);
233 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
239 static inline uint32_t
240 nix_qsize_to_val(enum nix_q_size_e qsize)
242 return (16UL << (qsize * 2));
245 static inline enum nix_q_size_e
246 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
250 if (otx2_ethdev_fixup_is_min_4k_q(dev))
255 for (; i < nix_q_size_max; i++)
256 if (val <= nix_qsize_to_val(i))
259 if (i >= nix_q_size_max)
260 i = nix_q_size_max - 1;
266 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
267 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
269 struct otx2_mbox *mbox = dev->mbox;
270 const struct rte_memzone *rz;
271 uint32_t ring_size, cq_size;
272 struct nix_aq_enq_req *aq;
277 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
278 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
279 NIX_CQ_ALIGN, dev->node);
281 otx2_err("Failed to allocate mem for cq hw ring");
285 memset(rz->addr, 0, rz->len);
286 rxq->desc = (uintptr_t)rz->addr;
287 rxq->qmask = cq_size - 1;
289 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
291 aq->ctype = NIX_AQ_CTYPE_CQ;
292 aq->op = NIX_AQ_INSTOP_INIT;
296 aq->cq.qsize = rxq->qsize;
297 aq->cq.base = rz->iova;
298 aq->cq.avg_level = 0xff;
299 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
300 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
302 /* Many to one reduction */
303 aq->cq.qint_idx = qid % dev->qints;
304 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
305 aq->cq.cint_idx = qid;
307 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
308 const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
309 uint16_t min_rx_drop;
311 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
312 aq->cq.drop = min_rx_drop;
314 rxq->cq_drop = min_rx_drop;
316 rxq->cq_drop = NIX_CQ_THRESH_LEVEL;
317 aq->cq.drop = rxq->cq_drop;
321 /* TX pause frames enable flowctrl on RX side */
322 if (dev->fc_info.tx_pause) {
323 /* Single bpid is allocated for all rx channels for now */
324 aq->cq.bpid = dev->fc_info.bpid[0];
325 aq->cq.bp = rxq->cq_drop;
329 rc = otx2_mbox_process(mbox);
331 otx2_err("Failed to init cq context");
335 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
337 aq->ctype = NIX_AQ_CTYPE_RQ;
338 aq->op = NIX_AQ_INSTOP_INIT;
341 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
343 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
344 first_skip = (sizeof(struct rte_mbuf));
345 first_skip += RTE_PKTMBUF_HEADROOM;
346 first_skip += rte_pktmbuf_priv_size(mp);
347 rxq->data_off = first_skip;
349 first_skip /= 8; /* Expressed in number of dwords */
350 aq->rq.first_skip = first_skip;
351 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
352 aq->rq.flow_tagw = 32; /* 32-bits */
353 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
354 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
355 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
356 aq->rq.lpb_sizem1 /= 8;
357 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
359 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
360 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
361 aq->rq.rq_int_ena = 0;
362 /* Many to one reduction */
363 aq->rq.qint_idx = qid % dev->qints;
365 aq->rq.xqe_drop_ena = 1;
367 rc = otx2_mbox_process(mbox);
369 otx2_err("Failed to init rq context");
379 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
380 struct otx2_eth_rxq *rxq, const bool enb)
382 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
383 struct otx2_mbox *mbox = dev->mbox;
384 struct nix_aq_enq_req *aq;
386 /* Pkts will be dropped silently if RQ is disabled */
387 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
389 aq->ctype = NIX_AQ_CTYPE_RQ;
390 aq->op = NIX_AQ_INSTOP_WRITE;
393 aq->rq_mask.ena = ~(aq->rq_mask.ena);
395 return otx2_mbox_process(mbox);
399 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
401 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
402 struct otx2_mbox *mbox = dev->mbox;
403 struct nix_aq_enq_req *aq;
406 /* RQ is already disabled */
408 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
410 aq->ctype = NIX_AQ_CTYPE_CQ;
411 aq->op = NIX_AQ_INSTOP_WRITE;
414 aq->cq_mask.ena = ~(aq->cq_mask.ena);
416 rc = otx2_mbox_process(mbox);
418 otx2_err("Failed to disable cq context");
426 nix_get_data_off(struct otx2_eth_dev *dev)
428 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
432 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
434 struct rte_mbuf mb_def;
437 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
438 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
439 offsetof(struct rte_mbuf, data_off) != 2);
440 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
441 offsetof(struct rte_mbuf, data_off) != 4);
442 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
443 offsetof(struct rte_mbuf, data_off) != 6);
445 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
446 mb_def.port = port_id;
447 rte_mbuf_refcnt_set(&mb_def, 1);
449 /* Prevent compiler reordering: rearm_data covers previous fields */
450 rte_compiler_barrier();
451 tmp = (uint64_t *)&mb_def.rearm_data;
457 otx2_nix_rx_queue_release(void *rx_queue)
459 struct otx2_eth_rxq *rxq = rx_queue;
464 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
465 nix_cq_rq_uninit(rxq->eth_dev, rxq);
470 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
471 uint16_t nb_desc, unsigned int socket,
472 const struct rte_eth_rxconf *rx_conf,
473 struct rte_mempool *mp)
475 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
476 struct rte_mempool_ops *ops;
477 struct otx2_eth_rxq *rxq;
478 const char *platform_ops;
479 enum nix_q_size_e qsize;
485 /* Compile time check to make sure all fast path elements in a CL */
486 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
489 if (rx_conf->rx_deferred_start == 1) {
490 otx2_err("Deferred Rx start is not supported");
494 platform_ops = rte_mbuf_platform_mempool_ops();
495 /* This driver needs octeontx2_npa mempool ops to work */
496 ops = rte_mempool_get_ops(mp->ops_index);
497 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
498 otx2_err("mempool ops should be of octeontx2_npa type");
502 if (mp->pool_id == 0) {
503 otx2_err("Invalid pool_id");
507 /* Free memory prior to re-allocation if needed */
508 if (eth_dev->data->rx_queues[rq] != NULL) {
509 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
510 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
511 eth_dev->data->rx_queues[rq] = NULL;
514 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
515 dev->rx_offloads |= offloads;
517 /* Find the CQ queue size */
518 qsize = nix_qsize_clampup_get(dev, nb_desc);
519 /* Allocate rxq memory */
520 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
522 otx2_err("Failed to allocate rq=%d", rq);
527 rxq->eth_dev = eth_dev;
529 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
530 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
531 rxq->wdata = (uint64_t)rq << 32;
532 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
533 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
534 eth_dev->data->port_id);
535 rxq->offloads = offloads;
537 rxq->qlen = nix_qsize_to_val(qsize);
539 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
540 rxq->tstamp = &dev->tstamp;
542 /* Alloc completion queue */
543 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
545 otx2_err("Failed to allocate rxq=%u", rq);
549 rxq->qconf.socket_id = socket;
550 rxq->qconf.nb_desc = nb_desc;
551 rxq->qconf.mempool = mp;
552 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
554 nix_rx_queue_reset(rxq);
555 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
556 rq, mp->name, qsize, nb_desc, rxq->qlen);
558 eth_dev->data->rx_queues[rq] = rxq;
559 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
561 /* Calculating delta and freq mult between PTP HI clock and tsc.
562 * These are needed in deriving raw clock value from tsc counter.
563 * read_clock eth op returns raw clock value.
565 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
566 otx2_ethdev_is_ptp_en(dev)) {
567 rc = otx2_nix_raw_clock_tsc_conv(dev);
569 otx2_err("Failed to calculate delta and freq mult");
577 otx2_nix_rx_queue_release(rxq);
582 static inline uint8_t
583 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
586 * Maximum three segments can be supported with W8, Choose
587 * NIX_MAXSQESZ_W16 for multi segment offload.
589 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
590 return NIX_MAXSQESZ_W16;
592 return NIX_MAXSQESZ_W8;
596 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
598 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
599 struct rte_eth_dev_data *data = eth_dev->data;
600 struct rte_eth_conf *conf = &data->dev_conf;
601 struct rte_eth_rxmode *rxmode = &conf->rxmode;
604 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
605 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
606 flags |= NIX_RX_OFFLOAD_RSS_F;
608 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
609 DEV_RX_OFFLOAD_UDP_CKSUM))
610 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
612 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
613 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
614 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
616 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
617 flags |= NIX_RX_MULTI_SEG_F;
619 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
620 DEV_RX_OFFLOAD_QINQ_STRIP))
621 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
623 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
624 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
626 if (!dev->ptype_disable)
627 flags |= NIX_RX_OFFLOAD_PTYPE_F;
633 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
635 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
636 uint64_t conf = dev->tx_offloads;
639 /* Fastpath is dependent on these enums */
640 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
641 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
642 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
643 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
644 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
645 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
646 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
647 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
648 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
649 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
650 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
651 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
652 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
653 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
654 offsetof(struct rte_mbuf, buf_iova) + 8);
655 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
656 offsetof(struct rte_mbuf, buf_iova) + 16);
657 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
658 offsetof(struct rte_mbuf, ol_flags) + 12);
659 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
660 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
662 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
663 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
664 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
666 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
667 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
668 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
670 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
671 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
672 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
673 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
674 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
676 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
677 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
679 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
680 flags |= NIX_TX_MULTI_SEG_F;
682 /* Enable Inner checksum for TSO */
683 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
684 flags |= (NIX_TX_OFFLOAD_TSO_F |
685 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
687 /* Enable Inner and Outer checksum for Tunnel TSO */
688 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
689 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
690 DEV_TX_OFFLOAD_GRE_TNL_TSO))
691 flags |= (NIX_TX_OFFLOAD_TSO_F |
692 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
693 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
695 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
696 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
702 nix_sq_init(struct otx2_eth_txq *txq)
704 struct otx2_eth_dev *dev = txq->dev;
705 struct otx2_mbox *mbox = dev->mbox;
706 struct nix_aq_enq_req *sq;
711 if (txq->sqb_pool->pool_id == 0)
714 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
716 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
720 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
722 sq->ctype = NIX_AQ_CTYPE_SQ;
723 sq->op = NIX_AQ_INSTOP_INIT;
724 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
727 sq->sq.smq_rr_quantum = rr_quantum;
728 sq->sq.default_chan = dev->tx_chan_base;
729 sq->sq.sqe_stype = NIX_STYPE_STF;
731 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
732 sq->sq.sqe_stype = NIX_STYPE_STP;
734 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
735 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
736 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
737 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
738 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
740 /* Many to one reduction */
741 sq->sq.qint_idx = txq->sq % dev->qints;
743 return otx2_mbox_process(mbox);
747 nix_sq_uninit(struct otx2_eth_txq *txq)
749 struct otx2_eth_dev *dev = txq->dev;
750 struct otx2_mbox *mbox = dev->mbox;
751 struct ndc_sync_op *ndc_req;
752 struct nix_aq_enq_rsp *rsp;
753 struct nix_aq_enq_req *aq;
754 uint16_t sqes_per_sqb;
758 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
760 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
762 aq->ctype = NIX_AQ_CTYPE_SQ;
763 aq->op = NIX_AQ_INSTOP_READ;
765 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
769 /* Check if sq is already cleaned up */
774 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
776 aq->ctype = NIX_AQ_CTYPE_SQ;
777 aq->op = NIX_AQ_INSTOP_WRITE;
779 aq->sq_mask.ena = ~aq->sq_mask.ena;
782 rc = otx2_mbox_process(mbox);
786 /* Read SQ and free sqb's */
787 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
789 aq->ctype = NIX_AQ_CTYPE_SQ;
790 aq->op = NIX_AQ_INSTOP_READ;
792 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
797 otx2_err("SQ has pending sqe's");
799 count = aq->sq.sqb_count;
800 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
801 /* Free SQB's that are used */
802 sqb_buf = (void *)rsp->sq.head_sqb;
806 next_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)
807 ((sqes_per_sqb - 1) *
808 nix_sq_max_sqe_sz(txq)));
809 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
815 /* Free next to use sqb */
816 if (rsp->sq.next_sqb)
817 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
820 /* Sync NDC-NIX-TX for LF */
821 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
822 ndc_req->nix_lf_tx_sync = 1;
823 rc = otx2_mbox_process(mbox);
825 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
831 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
833 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
834 struct npa_aq_enq_req *aura_req;
836 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
837 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
838 aura_req->ctype = NPA_AQ_CTYPE_AURA;
839 aura_req->op = NPA_AQ_INSTOP_WRITE;
841 aura_req->aura.limit = nb_sqb_bufs;
842 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
844 return otx2_mbox_process(npa_lf->mbox);
848 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
850 struct otx2_eth_dev *dev = txq->dev;
851 uint16_t sqes_per_sqb, nb_sqb_bufs;
852 char name[RTE_MEMPOOL_NAMESIZE];
853 struct rte_mempool_objsz sz;
854 struct npa_aura_s *aura;
855 uint32_t tmp, blk_sz;
857 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
858 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
859 blk_sz = dev->sqb_size;
861 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
862 sqes_per_sqb = (dev->sqb_size / 8) / 16;
864 sqes_per_sqb = (dev->sqb_size / 8) / 8;
866 nb_sqb_bufs = nb_desc / sqes_per_sqb;
867 /* Clamp up to devarg passed SQB count */
868 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,
869 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
871 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
873 MEMPOOL_F_NO_SPREAD);
874 txq->nb_sqb_bufs = nb_sqb_bufs;
875 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
876 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
877 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
878 txq->nb_sqb_bufs_adj =
879 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
881 if (txq->sqb_pool == NULL) {
882 otx2_err("Failed to allocate sqe mempool");
886 memset(aura, 0, sizeof(*aura));
888 aura->fc_addr = txq->fc_iova;
889 aura->fc_hyst_bits = 0; /* Store count on all updates */
890 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
891 otx2_err("Failed to set ops for sqe mempool");
894 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
895 otx2_err("Failed to populate sqe mempool");
899 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
900 if (dev->sqb_size != sz.elt_size) {
901 otx2_err("sqe pool block size is not expected %d != %d",
906 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
914 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
916 struct nix_send_ext_s *send_hdr_ext;
917 struct nix_send_hdr_s *send_hdr;
918 struct nix_send_mem_s *send_mem;
919 union nix_send_sg_s *sg;
921 /* Initialize the fields based on basic single segment packet */
922 memset(&txq->cmd, 0, sizeof(txq->cmd));
924 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
925 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
926 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
927 send_hdr->w0.sizem1 = 2;
929 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
930 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
931 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
932 /* Default: one seg packet would have:
933 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
936 send_hdr->w0.sizem1 = 3;
937 send_hdr_ext->w0.tstmp = 1;
939 /* To calculate the offset for send_mem,
940 * send_hdr->w0.sizem1 * 2
942 send_mem = (struct nix_send_mem_s *)(txq->cmd +
943 (send_hdr->w0.sizem1 << 1));
944 send_mem->subdc = NIX_SUBDC_MEM;
945 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
946 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
948 sg = (union nix_send_sg_s *)&txq->cmd[4];
950 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
951 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
952 send_hdr->w0.sizem1 = 1;
953 sg = (union nix_send_sg_s *)&txq->cmd[2];
956 send_hdr->w0.sq = txq->sq;
957 sg->subdc = NIX_SUBDC_SG;
959 sg->ld_type = NIX_SENDLDTYPE_LDD;
965 otx2_nix_tx_queue_release(void *_txq)
967 struct otx2_eth_txq *txq = _txq;
968 struct rte_eth_dev *eth_dev;
973 eth_dev = txq->dev->eth_dev;
975 otx2_nix_dbg("Releasing txq %u", txq->sq);
977 /* Flush and disable tm */
978 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
980 /* Free sqb's and disable sq */
984 rte_mempool_free(txq->sqb_pool);
985 txq->sqb_pool = NULL;
992 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
993 uint16_t nb_desc, unsigned int socket_id,
994 const struct rte_eth_txconf *tx_conf)
996 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
997 const struct rte_memzone *fc;
998 struct otx2_eth_txq *txq;
1004 /* Compile time check to make sure all fast path elements in a CL */
1005 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
1007 if (tx_conf->tx_deferred_start) {
1008 otx2_err("Tx deferred start is not supported");
1012 /* Free memory prior to re-allocation if needed. */
1013 if (eth_dev->data->tx_queues[sq] != NULL) {
1014 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
1015 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
1016 eth_dev->data->tx_queues[sq] = NULL;
1019 /* Find the expected offloads for this queue */
1020 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
1022 /* Allocating tx queue data structure */
1023 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
1024 OTX2_ALIGN, socket_id);
1026 otx2_err("Failed to alloc txq=%d", sq);
1032 txq->sqb_pool = NULL;
1033 txq->offloads = offloads;
1034 dev->tx_offloads |= offloads;
1037 * Allocate memory for flow control updates from HW.
1038 * Alloc one cache line, so that fits all FC_STYPE modes.
1040 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
1041 OTX2_ALIGN + sizeof(struct npa_aura_s),
1042 OTX2_ALIGN, dev->node);
1044 otx2_err("Failed to allocate mem for fcmem");
1048 txq->fc_iova = fc->iova;
1049 txq->fc_mem = fc->addr;
1051 /* Initialize the aura sqb pool */
1052 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
1054 otx2_err("Failed to alloc sqe pool rc=%d", rc);
1058 /* Initialize the SQ */
1059 rc = nix_sq_init(txq);
1061 otx2_err("Failed to init sq=%d context", sq);
1065 txq->fc_cache_pkts = 0;
1066 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
1067 /* Evenly distribute LMT slot for each sq */
1068 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1070 txq->qconf.socket_id = socket_id;
1071 txq->qconf.nb_desc = nb_desc;
1072 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1074 otx2_nix_form_default_desc(txq);
1076 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1077 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1078 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1079 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1080 eth_dev->data->tx_queues[sq] = txq;
1081 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1085 otx2_nix_tx_queue_release(txq);
1091 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1093 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1094 struct otx2_eth_qconf *tx_qconf = NULL;
1095 struct otx2_eth_qconf *rx_qconf = NULL;
1096 struct otx2_eth_txq **txq;
1097 struct otx2_eth_rxq **rxq;
1098 int i, nb_rxq, nb_txq;
1100 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1101 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1103 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1104 if (tx_qconf == NULL) {
1105 otx2_err("Failed to allocate memory for tx_qconf");
1109 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1110 if (rx_qconf == NULL) {
1111 otx2_err("Failed to allocate memory for rx_qconf");
1115 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1116 for (i = 0; i < nb_txq; i++) {
1117 if (txq[i] == NULL) {
1118 otx2_err("txq[%d] is already released", i);
1121 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1122 otx2_nix_tx_queue_release(txq[i]);
1123 eth_dev->data->tx_queues[i] = NULL;
1126 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1127 for (i = 0; i < nb_rxq; i++) {
1128 if (rxq[i] == NULL) {
1129 otx2_err("rxq[%d] is already released", i);
1132 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1133 otx2_nix_rx_queue_release(rxq[i]);
1134 eth_dev->data->rx_queues[i] = NULL;
1137 dev->tx_qconf = tx_qconf;
1138 dev->rx_qconf = rx_qconf;
1151 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1153 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1154 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1155 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1156 struct otx2_eth_txq **txq;
1157 struct otx2_eth_rxq **rxq;
1158 int rc, i, nb_rxq, nb_txq;
1160 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1161 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1164 /* Setup tx & rx queues with previous configuration so
1165 * that the queues can be functional in cases like ports
1166 * are started without re configuring queues.
1168 * Usual re config sequence is like below:
1169 * port_configure() {
1174 * queue_configure() {
1181 * In some application's control path, queue_configure() would
1182 * NOT be invoked for TXQs/RXQs in port_configure().
1183 * In such cases, queues can be functional after start as the
1184 * queues are already setup in port_configure().
1186 for (i = 0; i < nb_txq; i++) {
1187 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1188 tx_qconf[i].socket_id,
1189 &tx_qconf[i].conf.tx);
1191 otx2_err("Failed to setup tx queue rc=%d", rc);
1192 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1193 for (i -= 1; i >= 0; i--)
1194 otx2_nix_tx_queue_release(txq[i]);
1199 free(tx_qconf); tx_qconf = NULL;
1201 for (i = 0; i < nb_rxq; i++) {
1202 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1203 rx_qconf[i].socket_id,
1204 &rx_qconf[i].conf.rx,
1205 rx_qconf[i].mempool);
1207 otx2_err("Failed to setup rx queue rc=%d", rc);
1208 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1209 for (i -= 1; i >= 0; i--)
1210 otx2_nix_rx_queue_release(rxq[i]);
1211 goto release_tx_queues;
1215 free(rx_qconf); rx_qconf = NULL;
1220 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1221 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1222 otx2_nix_tx_queue_release(txq[i]);
1233 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1235 RTE_SET_USED(queue);
1236 RTE_SET_USED(mbufs);
1243 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1245 /* These dummy functions are required for supporting
1246 * some applications which reconfigure queues without
1247 * stopping tx burst and rx burst threads(eg kni app)
1248 * When the queues context is saved, txq/rxqs are released
1249 * which caused app crash since rx/tx burst is still
1250 * on different lcores
1252 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1253 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1258 nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)
1260 volatile struct nix_lso_format *field;
1262 /* Format works only with TCP packet marked by OL3/OL4 */
1263 field = (volatile struct nix_lso_format *)&req->fields[0];
1264 req->field_mask = NIX_LSO_FIELD_MASK;
1265 /* Outer IPv4/IPv6 */
1266 field->layer = NIX_TXLAYER_OL3;
1267 field->offset = v4 ? 2 : 4;
1268 field->sizem1 = 1; /* 2B */
1269 field->alg = NIX_LSOALG_ADD_PAYLEN;
1273 field->layer = NIX_TXLAYER_OL3;
1276 /* Incremented linearly per segment */
1277 field->alg = NIX_LSOALG_ADD_SEGNUM;
1281 /* TCP sequence number update */
1282 field->layer = NIX_TXLAYER_OL4;
1284 field->sizem1 = 3; /* 4 bytes */
1285 field->alg = NIX_LSOALG_ADD_OFFSET;
1287 /* TCP flags field */
1288 field->layer = NIX_TXLAYER_OL4;
1291 field->alg = NIX_LSOALG_TCP_FLAGS;
1296 nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req,
1297 bool outer_v4, bool inner_v4)
1299 volatile struct nix_lso_format *field;
1301 field = (volatile struct nix_lso_format *)&req->fields[0];
1302 req->field_mask = NIX_LSO_FIELD_MASK;
1303 /* Outer IPv4/IPv6 len */
1304 field->layer = NIX_TXLAYER_OL3;
1305 field->offset = outer_v4 ? 2 : 4;
1306 field->sizem1 = 1; /* 2B */
1307 field->alg = NIX_LSOALG_ADD_PAYLEN;
1311 field->layer = NIX_TXLAYER_OL3;
1314 /* Incremented linearly per segment */
1315 field->alg = NIX_LSOALG_ADD_SEGNUM;
1319 /* Outer UDP length */
1320 field->layer = NIX_TXLAYER_OL4;
1323 field->alg = NIX_LSOALG_ADD_PAYLEN;
1326 /* Inner IPv4/IPv6 */
1327 field->layer = NIX_TXLAYER_IL3;
1328 field->offset = inner_v4 ? 2 : 4;
1329 field->sizem1 = 1; /* 2B */
1330 field->alg = NIX_LSOALG_ADD_PAYLEN;
1334 field->layer = NIX_TXLAYER_IL3;
1337 /* Incremented linearly per segment */
1338 field->alg = NIX_LSOALG_ADD_SEGNUM;
1342 /* TCP sequence number update */
1343 field->layer = NIX_TXLAYER_IL4;
1345 field->sizem1 = 3; /* 4 bytes */
1346 field->alg = NIX_LSOALG_ADD_OFFSET;
1349 /* TCP flags field */
1350 field->layer = NIX_TXLAYER_IL4;
1353 field->alg = NIX_LSOALG_TCP_FLAGS;
1358 nix_lso_tun_tcp(struct nix_lso_format_cfg *req,
1359 bool outer_v4, bool inner_v4)
1361 volatile struct nix_lso_format *field;
1363 field = (volatile struct nix_lso_format *)&req->fields[0];
1364 req->field_mask = NIX_LSO_FIELD_MASK;
1365 /* Outer IPv4/IPv6 len */
1366 field->layer = NIX_TXLAYER_OL3;
1367 field->offset = outer_v4 ? 2 : 4;
1368 field->sizem1 = 1; /* 2B */
1369 field->alg = NIX_LSOALG_ADD_PAYLEN;
1373 field->layer = NIX_TXLAYER_OL3;
1376 /* Incremented linearly per segment */
1377 field->alg = NIX_LSOALG_ADD_SEGNUM;
1381 /* Inner IPv4/IPv6 */
1382 field->layer = NIX_TXLAYER_IL3;
1383 field->offset = inner_v4 ? 2 : 4;
1384 field->sizem1 = 1; /* 2B */
1385 field->alg = NIX_LSOALG_ADD_PAYLEN;
1389 field->layer = NIX_TXLAYER_IL3;
1392 /* Incremented linearly per segment */
1393 field->alg = NIX_LSOALG_ADD_SEGNUM;
1397 /* TCP sequence number update */
1398 field->layer = NIX_TXLAYER_IL4;
1400 field->sizem1 = 3; /* 4 bytes */
1401 field->alg = NIX_LSOALG_ADD_OFFSET;
1404 /* TCP flags field */
1405 field->layer = NIX_TXLAYER_IL4;
1408 field->alg = NIX_LSOALG_TCP_FLAGS;
1413 nix_setup_lso_formats(struct otx2_eth_dev *dev)
1415 struct otx2_mbox *mbox = dev->mbox;
1416 struct nix_lso_format_cfg_rsp *rsp;
1417 struct nix_lso_format_cfg *req;
1421 /* Skip if TSO was not requested */
1422 if (!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))
1427 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1428 nix_lso_tcp(req, true);
1429 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1433 base = rsp->lso_format_idx;
1434 if (base != NIX_LSO_FORMAT_IDX_TSOV4)
1436 dev->lso_base_idx = base;
1437 otx2_nix_dbg("tcpv4 lso fmt=%u", base);
1443 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1444 nix_lso_tcp(req, false);
1445 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1449 if (rsp->lso_format_idx != base + 1)
1451 otx2_nix_dbg("tcpv6 lso fmt=%u\n", base + 1);
1454 * IPv4/UDP/TUN HDR/IPv4/TCP LSO
1456 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1457 nix_lso_udp_tun_tcp(req, true, true);
1458 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1462 if (rsp->lso_format_idx != base + 2)
1464 otx2_nix_dbg("udp tun v4v4 fmt=%u\n", base + 2);
1467 * IPv4/UDP/TUN HDR/IPv6/TCP LSO
1469 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1470 nix_lso_udp_tun_tcp(req, true, false);
1471 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1475 if (rsp->lso_format_idx != base + 3)
1477 otx2_nix_dbg("udp tun v4v6 fmt=%u\n", base + 3);
1480 * IPv6/UDP/TUN HDR/IPv4/TCP LSO
1482 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1483 nix_lso_udp_tun_tcp(req, false, true);
1484 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1488 if (rsp->lso_format_idx != base + 4)
1490 otx2_nix_dbg("udp tun v6v4 fmt=%u\n", base + 4);
1493 * IPv6/UDP/TUN HDR/IPv6/TCP LSO
1495 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1496 nix_lso_udp_tun_tcp(req, false, false);
1497 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1500 if (rsp->lso_format_idx != base + 5)
1502 otx2_nix_dbg("udp tun v6v6 fmt=%u\n", base + 5);
1505 * IPv4/TUN HDR/IPv4/TCP LSO
1507 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1508 nix_lso_tun_tcp(req, true, true);
1509 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1513 if (rsp->lso_format_idx != base + 6)
1515 otx2_nix_dbg("tun v4v4 fmt=%u\n", base + 6);
1518 * IPv4/TUN HDR/IPv6/TCP LSO
1520 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1521 nix_lso_tun_tcp(req, true, false);
1522 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1526 if (rsp->lso_format_idx != base + 7)
1528 otx2_nix_dbg("tun v4v6 fmt=%u\n", base + 7);
1531 * IPv6/TUN HDR/IPv4/TCP LSO
1533 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1534 nix_lso_tun_tcp(req, false, true);
1535 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1539 if (rsp->lso_format_idx != base + 8)
1541 otx2_nix_dbg("tun v6v4 fmt=%u\n", base + 8);
1544 * IPv6/TUN HDR/IPv6/TCP LSO
1546 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1547 nix_lso_tun_tcp(req, false, false);
1548 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1551 if (rsp->lso_format_idx != base + 9)
1553 otx2_nix_dbg("tun v6v6 fmt=%u\n", base + 9);
1558 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1560 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1561 struct rte_eth_dev_data *data = eth_dev->data;
1562 struct rte_eth_conf *conf = &data->dev_conf;
1563 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1564 struct rte_eth_txmode *txmode = &conf->txmode;
1565 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1566 struct rte_ether_addr *ea;
1567 uint8_t nb_rxq, nb_txq;
1573 if (rte_eal_has_hugepages() == 0) {
1574 otx2_err("Huge page is not configured");
1575 goto fail_configure;
1578 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1579 otx2_err("Setting link speed/duplex not supported");
1580 goto fail_configure;
1583 if (conf->dcb_capability_en == 1) {
1584 otx2_err("dcb enable is not supported");
1585 goto fail_configure;
1588 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1589 otx2_err("Flow director is not supported");
1590 goto fail_configure;
1593 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1594 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1595 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1596 goto fail_configure;
1599 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1600 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1601 goto fail_configure;
1604 if (otx2_dev_is_Ax(dev) &&
1605 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1606 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1607 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1608 otx2_err("Outer IP and SCTP checksum unsupported");
1609 goto fail_configure;
1612 /* Free the resources allocated from the previous configure */
1613 if (dev->configured == 1) {
1614 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1615 otx2_nix_vlan_fini(eth_dev);
1616 otx2_nix_mc_addr_list_uninstall(eth_dev);
1617 otx2_flow_free_all_resources(dev);
1618 oxt2_nix_unregister_queue_irqs(eth_dev);
1619 if (eth_dev->data->dev_conf.intr_conf.rxq)
1620 oxt2_nix_unregister_cq_irqs(eth_dev);
1621 nix_set_nop_rxtx_function(eth_dev);
1622 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1624 goto fail_configure;
1625 otx2_nix_tm_fini(eth_dev);
1629 dev->rx_offloads = rxmode->offloads;
1630 dev->tx_offloads = txmode->offloads;
1631 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1632 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1633 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1635 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1636 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1638 /* Alloc a nix lf */
1639 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1641 otx2_err("Failed to init nix_lf rc=%d", rc);
1646 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
1647 otx2_err("Both PTP and switch header enabled");
1651 rc = nix_lf_switch_header_type_enable(dev);
1653 otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
1657 rc = nix_setup_lso_formats(dev);
1659 otx2_err("failed to setup nix lso format fields, rc=%d", rc);
1664 rc = otx2_nix_rss_config(eth_dev);
1666 otx2_err("Failed to configure rss rc=%d", rc);
1670 /* Init the default TM scheduler hierarchy */
1671 rc = otx2_nix_tm_init_default(eth_dev);
1673 otx2_err("Failed to init traffic manager rc=%d", rc);
1677 rc = otx2_nix_vlan_offload_init(eth_dev);
1679 otx2_err("Failed to init vlan offload rc=%d", rc);
1683 /* Register queue IRQs */
1684 rc = oxt2_nix_register_queue_irqs(eth_dev);
1686 otx2_err("Failed to register queue interrupts rc=%d", rc);
1690 /* Register cq IRQs */
1691 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1692 if (eth_dev->data->nb_rx_queues > dev->cints) {
1693 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1697 /* Rx interrupt feature cannot work with vector mode because,
1698 * vector mode doesn't process packets unless min 4 pkts are
1699 * received, while cq interrupts are generated even for 1 pkt
1702 dev->scalar_ena = true;
1704 rc = oxt2_nix_register_cq_irqs(eth_dev);
1706 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1711 /* Configure loop back mode */
1712 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1714 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1718 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1720 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1724 rc = otx2_nix_mc_addr_list_install(eth_dev);
1726 otx2_err("Failed to install mc address list rc=%d", rc);
1731 * Restore queue config when reconfigure followed by
1732 * reconfigure and no queue configure invoked from application case.
1734 if (dev->configured == 1) {
1735 rc = nix_restore_queue_cfg(eth_dev);
1737 goto uninstall_mc_list;
1740 /* Update the mac address */
1741 ea = eth_dev->data->mac_addrs;
1742 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1743 if (rte_is_zero_ether_addr(ea))
1744 rte_eth_random_addr((uint8_t *)ea);
1746 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1748 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1749 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1750 " rx_flags=0x%x tx_flags=0x%x",
1751 eth_dev->data->port_id, ea_fmt, nb_rxq,
1752 nb_txq, dev->rx_offloads, dev->tx_offloads,
1753 dev->rx_offload_flags, dev->tx_offload_flags);
1756 dev->configured = 1;
1757 dev->configured_nb_rx_qs = data->nb_rx_queues;
1758 dev->configured_nb_tx_qs = data->nb_tx_queues;
1762 otx2_nix_mc_addr_list_uninstall(eth_dev);
1764 oxt2_nix_unregister_cq_irqs(eth_dev);
1766 oxt2_nix_unregister_queue_irqs(eth_dev);
1768 otx2_nix_vlan_fini(eth_dev);
1770 otx2_nix_tm_fini(eth_dev);
1774 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
1775 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
1777 dev->configured = 0;
1782 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1784 struct rte_eth_dev_data *data = eth_dev->data;
1785 struct otx2_eth_txq *txq;
1788 txq = eth_dev->data->tx_queues[qidx];
1790 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1793 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1795 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1800 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1807 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1809 struct rte_eth_dev_data *data = eth_dev->data;
1810 struct otx2_eth_txq *txq;
1813 txq = eth_dev->data->tx_queues[qidx];
1815 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1818 txq->fc_cache_pkts = 0;
1820 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1822 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1827 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1834 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1836 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1837 struct rte_eth_dev_data *data = eth_dev->data;
1840 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1843 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1845 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1849 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1856 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1858 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1859 struct rte_eth_dev_data *data = eth_dev->data;
1862 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1865 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1867 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1871 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1878 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
1880 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1881 struct rte_mbuf *rx_pkts[32];
1882 struct otx2_eth_rxq *rxq;
1883 int count, i, j, rc;
1885 nix_cgx_stop_link_event(dev);
1886 npc_rx_disable(dev);
1888 /* Stop rx queues and free up pkts pending */
1889 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1890 rc = otx2_nix_rx_queue_stop(eth_dev, i);
1894 rxq = eth_dev->data->rx_queues[i];
1895 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1897 for (j = 0; j < count; j++)
1898 rte_pktmbuf_free(rx_pkts[j]);
1899 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1903 /* Stop tx queues */
1904 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1905 otx2_nix_tx_queue_stop(eth_dev, i);
1909 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
1911 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1914 /* MTU recalculate should be avoided here if PTP is enabled by PF, as
1915 * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
1918 if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
1919 rc = otx2_nix_recalc_mtu(eth_dev);
1924 /* Start rx queues */
1925 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1926 rc = otx2_nix_rx_queue_start(eth_dev, i);
1931 /* Start tx queues */
1932 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1933 rc = otx2_nix_tx_queue_start(eth_dev, i);
1938 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
1940 otx2_err("Failed to update flow ctrl mode %d", rc);
1944 /* Enable PTP if it was requested by the app or if it is already
1945 * enabled in PF owning this VF
1947 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
1948 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
1949 otx2_ethdev_is_ptp_en(dev))
1950 otx2_nix_timesync_enable(eth_dev);
1952 otx2_nix_timesync_disable(eth_dev);
1954 /* Update VF about data off shifted by 8 bytes if PTP already
1955 * enabled in PF owning this VF
1957 if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
1958 otx2_nix_ptp_enable_vf(eth_dev);
1960 rc = npc_rx_enable(dev);
1962 otx2_err("Failed to enable NPC rx %d", rc);
1966 otx2_nix_toggle_flag_link_cfg(dev, true);
1968 rc = nix_cgx_start_link_event(dev);
1970 otx2_err("Failed to start cgx link event %d", rc);
1974 otx2_nix_toggle_flag_link_cfg(dev, false);
1975 otx2_eth_set_tx_function(eth_dev);
1976 otx2_eth_set_rx_function(eth_dev);
1981 npc_rx_disable(dev);
1982 otx2_nix_toggle_flag_link_cfg(dev, false);
1986 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
1987 static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
1989 /* Initialize and register driver with DPDK Application */
1990 static const struct eth_dev_ops otx2_eth_dev_ops = {
1991 .dev_infos_get = otx2_nix_info_get,
1992 .dev_configure = otx2_nix_configure,
1993 .link_update = otx2_nix_link_update,
1994 .tx_queue_setup = otx2_nix_tx_queue_setup,
1995 .tx_queue_release = otx2_nix_tx_queue_release,
1996 .rx_queue_setup = otx2_nix_rx_queue_setup,
1997 .rx_queue_release = otx2_nix_rx_queue_release,
1998 .dev_start = otx2_nix_dev_start,
1999 .dev_stop = otx2_nix_dev_stop,
2000 .dev_close = otx2_nix_dev_close,
2001 .tx_queue_start = otx2_nix_tx_queue_start,
2002 .tx_queue_stop = otx2_nix_tx_queue_stop,
2003 .rx_queue_start = otx2_nix_rx_queue_start,
2004 .rx_queue_stop = otx2_nix_rx_queue_stop,
2005 .dev_set_link_up = otx2_nix_dev_set_link_up,
2006 .dev_set_link_down = otx2_nix_dev_set_link_down,
2007 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
2008 .dev_ptypes_set = otx2_nix_ptypes_set,
2009 .dev_reset = otx2_nix_dev_reset,
2010 .stats_get = otx2_nix_dev_stats_get,
2011 .stats_reset = otx2_nix_dev_stats_reset,
2012 .get_reg = otx2_nix_dev_get_reg,
2013 .mtu_set = otx2_nix_mtu_set,
2014 .mac_addr_add = otx2_nix_mac_addr_add,
2015 .mac_addr_remove = otx2_nix_mac_addr_del,
2016 .mac_addr_set = otx2_nix_mac_addr_set,
2017 .set_mc_addr_list = otx2_nix_set_mc_addr_list,
2018 .promiscuous_enable = otx2_nix_promisc_enable,
2019 .promiscuous_disable = otx2_nix_promisc_disable,
2020 .allmulticast_enable = otx2_nix_allmulticast_enable,
2021 .allmulticast_disable = otx2_nix_allmulticast_disable,
2022 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
2023 .reta_update = otx2_nix_dev_reta_update,
2024 .reta_query = otx2_nix_dev_reta_query,
2025 .rss_hash_update = otx2_nix_rss_hash_update,
2026 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
2027 .xstats_get = otx2_nix_xstats_get,
2028 .xstats_get_names = otx2_nix_xstats_get_names,
2029 .xstats_reset = otx2_nix_xstats_reset,
2030 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
2031 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
2032 .rxq_info_get = otx2_nix_rxq_info_get,
2033 .txq_info_get = otx2_nix_txq_info_get,
2034 .rx_burst_mode_get = otx2_rx_burst_mode_get,
2035 .tx_burst_mode_get = otx2_tx_burst_mode_get,
2036 .rx_queue_count = otx2_nix_rx_queue_count,
2037 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
2038 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
2039 .tx_descriptor_status = otx2_nix_tx_descriptor_status,
2040 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
2041 .pool_ops_supported = otx2_nix_pool_ops_supported,
2042 .filter_ctrl = otx2_nix_dev_filter_ctrl,
2043 .get_module_info = otx2_nix_get_module_info,
2044 .get_module_eeprom = otx2_nix_get_module_eeprom,
2045 .fw_version_get = otx2_nix_fw_version_get,
2046 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
2047 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
2048 .timesync_enable = otx2_nix_timesync_enable,
2049 .timesync_disable = otx2_nix_timesync_disable,
2050 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
2051 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
2052 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
2053 .timesync_read_time = otx2_nix_timesync_read_time,
2054 .timesync_write_time = otx2_nix_timesync_write_time,
2055 .vlan_offload_set = otx2_nix_vlan_offload_set,
2056 .vlan_filter_set = otx2_nix_vlan_filter_set,
2057 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
2058 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
2059 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
2060 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
2061 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
2062 .read_clock = otx2_nix_read_clock,
2066 nix_lf_attach(struct otx2_eth_dev *dev)
2068 struct otx2_mbox *mbox = dev->mbox;
2069 struct rsrc_attach_req *req;
2071 /* Attach NIX(lf) */
2072 req = otx2_mbox_alloc_msg_attach_resources(mbox);
2076 return otx2_mbox_process(mbox);
2080 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
2082 struct otx2_mbox *mbox = dev->mbox;
2083 struct msix_offset_rsp *msix_rsp;
2086 /* Get NPA and NIX MSIX vector offsets */
2087 otx2_mbox_alloc_msg_msix_offset(mbox);
2089 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
2091 dev->nix_msixoff = msix_rsp->nix_msixoff;
2097 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
2099 struct rsrc_detach_req *req;
2101 req = otx2_mbox_alloc_msg_detach_resources(mbox);
2103 /* Detach all except npa lf */
2104 req->partial = true;
2111 return otx2_mbox_process(mbox);
2115 otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
2117 if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
2118 pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2124 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
2126 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2127 struct rte_pci_device *pci_dev;
2128 int rc, max_entries;
2130 eth_dev->dev_ops = &otx2_eth_dev_ops;
2132 /* For secondary processes, the primary has done all the work */
2133 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2134 /* Setup callbacks for secondary process */
2135 otx2_eth_set_tx_function(eth_dev);
2136 otx2_eth_set_rx_function(eth_dev);
2140 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2142 rte_eth_copy_pci_info(eth_dev, pci_dev);
2143 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2145 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
2146 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
2147 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
2149 /* Parse devargs string */
2150 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
2152 otx2_err("Failed to parse devargs rc=%d", rc);
2156 if (!dev->mbox_active) {
2157 /* Initialize the base otx2_dev object
2158 * only if already present
2160 rc = otx2_dev_init(pci_dev, dev);
2162 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
2166 if (otx2_eth_dev_is_sdp(pci_dev))
2167 dev->sdp_link = true;
2169 dev->sdp_link = false;
2170 /* Device generic callbacks */
2171 dev->ops = &otx2_dev_ops;
2172 dev->eth_dev = eth_dev;
2174 /* Grab the NPA LF if required */
2175 rc = otx2_npa_lf_init(pci_dev, dev);
2177 goto otx2_dev_uninit;
2179 dev->configured = 0;
2180 dev->drv_inited = true;
2181 dev->ptype_disable = 0;
2182 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
2183 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
2186 rc = nix_lf_attach(dev);
2188 goto otx2_npa_uninit;
2190 /* Get NIX MSIX offset */
2191 rc = nix_lf_get_msix_offset(dev);
2193 goto otx2_npa_uninit;
2195 /* Register LF irq handlers */
2196 rc = otx2_nix_register_irqs(eth_dev);
2200 /* Get maximum number of supported MAC entries */
2201 max_entries = otx2_cgx_mac_max_entries_get(dev);
2202 if (max_entries < 0) {
2203 otx2_err("Failed to get max entries for mac addr");
2205 goto unregister_irq;
2208 /* For VFs, returned max_entries will be 0. But to keep default MAC
2209 * address, one entry must be allocated. So setting up to 1.
2211 if (max_entries == 0)
2214 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
2215 RTE_ETHER_ADDR_LEN, 0);
2216 if (eth_dev->data->mac_addrs == NULL) {
2217 otx2_err("Failed to allocate memory for mac addr");
2219 goto unregister_irq;
2222 dev->max_mac_entries = max_entries;
2224 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
2226 goto free_mac_addrs;
2228 /* Update the mac address */
2229 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2231 /* Also sync same MAC address to CGX table */
2232 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
2234 /* Initialize the tm data structures */
2235 otx2_nix_tm_conf_init(eth_dev);
2237 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
2238 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
2240 if (otx2_dev_is_96xx_A0(dev) ||
2241 otx2_dev_is_95xx_Ax(dev)) {
2242 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
2243 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
2246 /* Initialize rte-flow */
2247 rc = otx2_flow_init(dev);
2249 goto free_mac_addrs;
2251 otx2_nix_mc_filter_init(dev);
2253 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
2254 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
2255 eth_dev->data->port_id, dev->pf, dev->vf,
2256 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
2257 dev->rx_offload_capa, dev->tx_offload_capa);
2261 rte_free(eth_dev->data->mac_addrs);
2263 otx2_nix_unregister_irqs(eth_dev);
2265 otx2_eth_dev_lf_detach(dev->mbox);
2269 otx2_dev_fini(pci_dev, dev);
2271 otx2_err("Failed to init nix eth_dev rc=%d", rc);
2276 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
2278 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2279 struct rte_pci_device *pci_dev;
2282 /* Nothing to be done for secondary processes */
2283 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2286 /* Clear the flag since we are closing down */
2287 dev->configured = 0;
2289 /* Disable nix bpid config */
2290 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
2292 npc_rx_disable(dev);
2294 /* Disable vlan offloads */
2295 otx2_nix_vlan_fini(eth_dev);
2297 /* Disable other rte_flow entries */
2298 otx2_flow_fini(dev);
2300 /* Free multicast filter list */
2301 otx2_nix_mc_filter_fini(dev);
2303 /* Disable PTP if already enabled */
2304 if (otx2_ethdev_is_ptp_en(dev))
2305 otx2_nix_timesync_disable(eth_dev);
2307 nix_cgx_stop_link_event(dev);
2310 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2311 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
2312 eth_dev->data->tx_queues[i] = NULL;
2314 eth_dev->data->nb_tx_queues = 0;
2316 /* Free up RQ's and CQ's */
2317 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2318 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
2319 eth_dev->data->rx_queues[i] = NULL;
2321 eth_dev->data->nb_rx_queues = 0;
2323 /* Free tm resources */
2324 rc = otx2_nix_tm_fini(eth_dev);
2326 otx2_err("Failed to cleanup tm, rc=%d", rc);
2328 /* Unregister queue irqs */
2329 oxt2_nix_unregister_queue_irqs(eth_dev);
2331 /* Unregister cq irqs */
2332 if (eth_dev->data->dev_conf.intr_conf.rxq)
2333 oxt2_nix_unregister_cq_irqs(eth_dev);
2335 rc = nix_lf_free(dev);
2337 otx2_err("Failed to free nix lf, rc=%d", rc);
2339 rc = otx2_npa_lf_fini();
2341 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
2343 rte_free(eth_dev->data->mac_addrs);
2344 eth_dev->data->mac_addrs = NULL;
2345 dev->drv_inited = false;
2347 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2348 otx2_nix_unregister_irqs(eth_dev);
2350 rc = otx2_eth_dev_lf_detach(dev->mbox);
2352 otx2_err("Failed to detach resources, rc=%d", rc);
2354 /* Check if mbox close is needed */
2358 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
2359 /* Will be freed later by PMD */
2360 eth_dev->data->dev_private = NULL;
2364 otx2_dev_fini(pci_dev, dev);
2369 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
2371 otx2_eth_dev_uninit(eth_dev, true);
2375 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
2379 rc = otx2_eth_dev_uninit(eth_dev, false);
2383 return otx2_eth_dev_init(eth_dev);
2387 nix_remove(struct rte_pci_device *pci_dev)
2389 struct rte_eth_dev *eth_dev;
2390 struct otx2_idev_cfg *idev;
2391 struct otx2_dev *otx2_dev;
2394 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
2396 /* Cleanup eth dev */
2397 rc = otx2_eth_dev_uninit(eth_dev, true);
2401 rte_eth_dev_pci_release(eth_dev);
2404 /* Nothing to be done for secondary processes */
2405 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2408 /* Check for common resources */
2409 idev = otx2_intra_dev_get_cfg();
2410 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
2413 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
2415 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
2418 /* Safe to cleanup mbox as no more users */
2419 otx2_dev_fini(pci_dev, otx2_dev);
2424 otx2_info("%s: common resource in use by other devices", pci_dev->name);
2429 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2433 RTE_SET_USED(pci_drv);
2435 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2438 /* On error on secondary, recheck if port exists in primary or
2439 * in mid of detach state.
2441 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2442 if (!rte_eth_dev_allocated(pci_dev->device.name))
2447 static const struct rte_pci_id pci_nix_map[] = {
2449 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2452 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2455 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2456 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2459 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2460 PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
2463 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2464 PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2471 static struct rte_pci_driver pci_nix = {
2472 .id_table = pci_nix_map,
2473 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2474 RTE_PCI_DRV_INTR_LSC,
2476 .remove = nix_remove,
2479 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2480 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2481 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");